Lecture 6

Digital System Design
Digital System Design
Lecture 7
ASM and ASMD charts
ASM and ASMD charts
5/16/2010 Engr.Anees Ullah 1
Why ASMs?
Why ASMs?
• State
State‐transition graphs (STGs) indicate the
t a s t o g ap s (S Gs) d cate t e
transitions that result from inputs that are
applied when a state machine is in a particular
state, but STGs do not directly display the
b d d l d l h
evolution of states under the application of input
data.
data
• Complex digital systems are difficult to describe
with Finite State Machines.
with Finite State Machines.
• ASMs are similar to Flowcharts but they have a
g
timing information.
FSMs Vs ASMs
FSMs Vs ASMs
• An ASM chart focuses on the activity of the
y
machine, rather than on the contents of all the
storage elements. Sometimes it is more
convenient and even essential to describe the
convenient, and even essential, to describe the
state of a machine by the activity that
unfolds during its operation, rather than the data
that are produced by the machine.
For example, instead of describing a 16‐bit
counter by its contents we can view it as a
counter by its contents we can view it as a
datapath unit and describe its activity (e.g.,
g, g, )
counting, waiting, etc.).
Fundamental ASM elements
Fundamental ASM elements
Vehicle Speed Controller
Vehicle Speed Controller
Vehicle Speed Contoller
Vehicle Speed Contoller
• Outputs
Outputs of Moore Machines are inside the
of Moore Machines are inside the
state box.
• Mealy output are shown by conditional boxes.
Mealy output are shown by conditional boxes
• The decision boxes along a path in ASM chart
i l
imply a priority decoding.
i i d di
Algorithmic State Machines and Data
path (ASMD) charts
h( ) h
• The
The digital design Recipe
digital design Recipe
Digital design = Controller + Data path
• ASM chart when linked to the operations of a
ASM chart when linked to the operations of a
data path.
• The chart is modified by annotating each of its
The chart is modified by annotating each of its
paths to indicate the concurrent register
operations that occur in the associated data
operations that occur in the associated data
path unit when the state of the controller
makes a transition along the path.
ASMD charts
ASMD charts
• Register
Register operations that occur concurrently
operations that occur concurrently
with state transitions are annotated on a path
of the chart rather than in conditional boxes
of the chart, rather than in conditional boxes
on the path, or in state boxes, because these
registers are not part of the controller
registers are not part of the controller.
2‐ Stage Pipelined Register
2 Stage Pipelined Register
ASMD chart of 2‐Stage Pipelined
Register
Up Down Counter
Up Down Counter
• Suppose
Suppose a 3
a 3‐bit
bit counter has the features that
counter has the features that
it can count up or down or hold the count.
Up Down Counter
Up Down Counter
Up Down Counter
Up Down Counter
Verilog Code for Up Down Counter
Code for Up Down Counter
module Up_DownImplicit1 (count, up_dwn, clock, rese_);
output [2: 0] count;
input [1: 0] up_dwn;
i
input clock, reset_;
t l k t
reg [2: 0] count;
always @ (negedge
y @ ( g g clock or negedgeg g reset_))
if (reset_ ==0) count <= 3'bO; else
if (up_dwn == 2'bOO II up_dwn == 2'b11) count <= count; else
if (up_dwn == 2'b01) count <= count + 1; else
if (up_dwn == 2'b10) count <= count ‐1;
end module
end module
Ring Counter
Ring Counter
Verilog for Ring Counter
for Ring Counter
module ring
odu e g_cou counter
te (cou
(count, enable, clock, reset);
t, e ab e, c oc , eset);
output [7: 0] count;
input enable, reset, clock;
input enable, reset, clock;
reg [7: 0] count;
always @ (posedge reset or posedge
always @ (posedge reset or posedge clock)
clock)
if (reset == 1'b1) count <= 8'bOOOO_0001;
else
else
if (enable == 1'b1) count <= {count[6: 0], count[7]};
endmodule
Modified 3 bit Up Down Counter
Modified 3 bit Up Down Counter
Modified 3 bit Up Down counter
Modified 3 bit Up Down counter
Shift Register
Shift Register
Verilog for Shift Register
for Shift Register
module ShifUeg4 (Data_out, Data_in, clock, reset);
output Data_out;
input Data_in, clock, reset;
reg [3: 0] Data_reg;
[3: 0] Data reg;
assign Data_out = Data_reg[O];
always @ (negedge reset or posedge clock)
begin
if (reset == 1'bO) Data_reg <= 4'bO;
else Data reg <<= {Data_in, Data_reg[3:1]};
else Data_reg {Data in, Data reg[3:1]};
end
endmodule
Parallel load Register
Parallel load Register
Verilog for Parallel load Register
for Parallel load Register
module PaUoad_reg4 (Data_out, Data_in, load, clock, reset);
input [3: 0] Data_in;
input load, clock, reset;
output [3: 0] Data
p [ ] _out; ;
reg Data_out;
begin
begin
if (reset == 1'b1) Data_out <= 4'bO;
else if (load == 1'b1) Data_out <= Data_in;
end
end
endmodule
Barrel Shifter
Barrel Shifter
Verilog for Barrel Shifter
for Barrel Shifter
module barrel_shifter (Data_out, Data_in, load, clock, reset);
output [7: 0] Data_out;
input load, clock, reset;
reg [7: 0] Data_out;
begin
if (reset == 1'b1) Data_out <= 8'bO;
else if (load == 1'b1) Data_out <= Data_in;
else Data_out <= {Data
{ _out[6: 0], Data
[ ], _out[7]};
[ ]};
end
endmodule
Universal Shift Register
Universal Shift Register
Verilog for Universal Shift Register
module Universal_Shift
d l i l Shif Reg (Data_Out, MSB_Out, LSB_Out, Data_in, MSB_in,
( O S O S O i S i
LSB_in, s1, so, clk, rst);
output [3: 0] Data_Out;
output MSB_Out, LSB_Out;
input MSB_in, LSB_ln;
input 51, sO, clk, rst;
reg Data_Out;
Data Out;
assign MSB_Out = Data_Out[3];
assign LSB_Out = Data_Out[O];
always @ (posedge clk) begin
if (rst) Data_Out <= 0;
else case ({s1, sO})
0: Data_Out <= Data_Out;
1: Data Out <<= {MSB_in, Data_Out[3:1]};
1: Data_Out {MSB in, Data Out[3:1]};
2: Data_Out <= {Data_Out[2: 0], LSB_in};
3: Data_Out <= Data_in;
endcase
end d
endmodule
Register File
Register File
Verilog for Register File
for Register File
module Register_File (Data_Out_1, Data_Out_2, Data_in, Read_Addr_1,
Read_Addr_2, Write_Addr, Write_Enable, Clock); )
output [31: 0] Data _ Out_1, Data _ Out_2;
input [4: 0] Read Addr 1 Read Addr 2 Write Addr;
input [4: 0] Read_Addr_1, Read_Addr_2, Write_Addr;
input Write_Enable, Clock;
reg [31: 0] Reg_File [31: 0]; //32bit x32 word memory declaration
assign Data Out 1 = Reg File[Read Addr 1];
assign Data_Out_1 = Reg_File[Read_Addr_1];
assign Data_Out_2 = Reg_File[Read_Addr_2];
always @ (posedge Clock) begin
if (Write
( _Enable) Reg
) g_File [[Write_Addr] <= Data
] _in;
;
end
endmodule
Data path + FSM
Data path + FSM
4 bit Synchronous Binary Counter
4 bit Synchronous Binary Counter
STG
ASM
ASMD
Verilog Code: Top Level Module
Code: Top Level Module
module Binaryy_Counter_Part_RTL ((count, enable,
, ,
clk, rst);
parameter size = 4;
output [size ‐1: 0] count;
input enable;
i
input clk, rst;
t lk t
wire enable_DP;
Control Unit MO (enable_DP, enable, clk, rst);
Control_Unit MO (enable DP enable clk rst);
Datapath_Unit M1 (count.,enable_DP, clk, rst);
endmodule
Control Unit Module
Control Unit Module
module Control_Unit
module Control Unit (enable_DP, enable, clk,
(enable DP enable clk
rst);
output enable DP;
output enable _ DP;
input enable;
input clk, rst; // Not needed
wire enable_DP = enable; // pass through
; // p g
endmodule
Data path Module
module Datapath_Unit (count, enable, clk, rst);
parameter size = 4;
output [size‐1:
output [size 1: 0] count;
0] count;
input enable;
input clk, rst;
reg count;
count;
wire [size‐1: 0] next_count;
always @ (posedge elk)
if (rst == 1) count <= 0;
if (rst == 1) count <= 0;
else if (enable == 1) count <= next_count(count);
function [size‐1: 0] next_count;
input [size‐1: 0] count;
input [size‐1: 0] count;
begin
next_count = count + 1;
end
end
endfunction
endmodule
Reading Assingment
Reading Assingment
• 5.14, 5.15, 5.16, 7.1, 7.2
5 14 5 15 5 16 7 1 7 2

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