Basic Gates Program

1.
BASIC GATES PROGRAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BASGAT1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
ynot : out STD_LOGIC;
yor : out STD_LOGIC;
yand : out STD_LOGIC;
ynor : out STD_LOGIC;
ynand : out STD_LOGIC;
yxor : out STD_LOGIC;
yxnor : out STD_LOGIC);
end BASGAT1;
architecture Behavioral of BASGAT1 is
begin
ynot <= not a;

yor<=a or b;
yand <= a and b;
ynor <= a nor b;
ynand <= a nand b;
yxor <= a xor b;
yxnor <= a xnor b;
end Behavioral;
2. FULL ADDER
library IEEE;
entity FA1 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
1
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end FA1;
architecture Behavioral of FA1 is
begin
sum <= x xor y xor cin; --calculates the sum bit
cout <= (x and y) or (y and cin) or (cin and x);
end Behavioral;
3. FULL SUBTRACTER
library IEEE;
entity FS1 is
y : in STD_LOGIC;
bin : in STD_LOGIC;
diff : out STD_LOGIC;
bout : out STD_LOGIC);
end FS1;
architecture Behavioral of FS1 is
begin
diff<= x xor y xor bin;

bout<= ((not x) and (y or bin)) or (y and bin);
end Behavioral;
4. FOUR BIT PARALLEL ADDER
library IEEE;
entity FA41 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
2
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
end FA41;
architecture Behavioral of FA41 is

-- this is a structural description of a 4 bit full adder
component FA
port(x,y,cin: in STD_LOGIC;
sum,cout: out STD_LOGIC);
end component;
signal t: STD_LOGIC_VECTOR(2 downto 0);
begin
FA0 : FA port map(a(0),b(0),cin,sum(0),t(0));

FA1 : FA port map(a(1),b(1),t(0),sum(1),t(1));
FA2 : FA port map(a(2),b(2),t(1),sum(2),t(2));
FA3 : FA port map(a(3),b(3),t(2),sum(3),cout);
end Behavioral;
--COMPONENT FOR THE PROGRAM OF A 4 BIT FULL ADDER

library IEEE;
entity FA is
y : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
end FA;
architecture Behavioral of FA is
begin
sum <= x xor y xor cin;

cout <= (x and y) or (y and cin) or (cin and x);
end Behavioral;
3
5. FOUR BIT PARALLEL SUBTRACTOR
library IEEE;
entity FS41 is
bin : in STD_LOGIC;
diff : out STD_LOGIC_VECTOR (3 downto 0);
bout : out STD_LOGIC);
end FS41;
architecture Behavioral of FS41 is

--component for the structural description
component FS
port(x,y,borrowin: in STD_LOGIC;
d,borrowout: out STD_LOGIC);
end component;

begin
FS0 : FS port map(a(0),b(0),bin,diff(0),t(0));

FS1 : FS port map(a(1),b(1),t(0),diff(1),t(1));
FS2 : FS port map(a(2),b(2),t(1),diff(2),t(2));
FS3 : FS port map(a(3),b(3),t(2),diff(3),bout);
end Behavioral;
library IEEE;
----COMPONENT FOR THE FULL SUBTRACTOR--
entity FS is
y : in STD_LOGIC;
borrowin : in STD_LOGIC;
d : out STD_LOGIC;
borrowout : out STD_LOGIC);
end FS;
architecture Behavioral of FS is
4
begin
d<= x xor y xor borrowin;
borrowout<= ((not x) and (y or borrowin)) or (y and borrowin);
end Behavioral;
6. 4:1 MULTIPLEXER
library IEEE;
entity MUX411 is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
sel: in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end MUX411;
architecture Behavioral of MUX411 is
begin
with sel select --selected assignment statement.. it is concurrent statement

y<= x(0) when "00",
x(1) when "01",
x(2) when "10",
x(3) when "11",
'0' when others;
end Behavioral;
7. 8:1 MULTIPLEXER
--Code for the 8:1 MUX using a process statement

library IEEE;
entity MUX811 is
Port ( x : in STD_LOGIC_VECTOR (7 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC);
end MUX811;
5
architecture Behavioral of MUX811 is
begin
process(sel)
begin
case sel is
when "000"=> y<= x(0);
when "001"=> y<= x(1);
when "010"=> y<= x(2);
when "011"=> y<= x(3);
when "100"=> y<= x(4);
when "101"=> y<= x(5);
when "110"=> y<= x(6);
when "111"=> y<= x(7);
when OTHERS=> NULL;
end case;
end process;
end Behavioral;
8. J K FLIP FLOP
--Code and Simulate a JK Flip Flop with asynchronous clear and preset i/p with
--a positive edge triggered flip flops
library IEEE;
entity JKFF1 is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
pr : in STD_LOGIC;
q : inout STD_LOGIC;
nq : out STD_LOGIC);
end JKFF1;
architecture Behavioral of JKFF1 is
begin
process(clk,clr,pr)
begin
if clr='1' then
q<= '0';
elsif pr='1' then
q<= '1';
6
elsif clk='1' and clk' event then
q<= (j and not q) or (not k and q);
end if;
end process;
nq<= not q;
end Behavioral;
9. D FLIP FLOP
library IEEE;
entity DFF1 is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
end DFF1;
architecture Behavioral of DFF1 is
begin
process(clk,clr)
begin
if clr='1' then
q<='0';
q<=d;
end if;
end process;
nq<= not q;
end Behavioral;
10. T FLIP FLOP
library IEEE;
entity TFF1 is
Port ( T : in STD_LOGIC;
clk : in STD_LOGIC;
7
clr : in STD_LOGIC;
end TFF1;
architecture Behavioral of TFF1 is
begin
process(clr,clk)
begin
if clr='1' then
q<='0';
q<= t xor q;
end if;
end process;
nq<= not q;
end Behavioral;
11. 3 BIT BINARY COUNTER WITH ASYNCRONOUS CLEAR INPUT
library IEEE;
entity BCNT31 is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (2 downto 0));
end BCNT31;
architecture Behavioral of BCNT31 is
begin
process(CLR,CLK)
begin
if CLR='1' then
Q<="000";
elsif CLK='1' and CLK' event then
Q<=Q+1;
end if;
end process;
end Behavioral;
12. SHIFT REGISTER
8
--A shift register which shifts the data towards right or left depending on the value of
--sh=1 or 0 respectively. Also it should have the facility to load the data
library IEEE;
entity SHIFT1 is
Port ( data : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
w : in STD_LOGIC;
sh : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end SHIFT1;
architecture Behavioral of SHIFT1 is
begin
process (clk,load)
begin
if load='1' then
q<= data;
if sh='1' then --right shift operation
q(0)<= q(1);
q(1)<= q(2);
q(2)<= q(3);
q(3)<= w;
elsif sh='0' then -- left shift operation
q(3)<= q(2);
q(2)<= q(1);
q(1)<= q(0);
q(0)<= w;
end if;
end if;
end process;
end Behavioral;
13. DECADE COUNTER
--Wirte the VHDL description of a DECADE counter that counts from 1 to 10

library IEEE;
9
entity DECNT1 is
Port ( CLK : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (3 downto 0):="0000");
end DECNT1;
architecture Behavioral of DECNT1 is
begin
process(CLK)
begin
if CLK='1' and CLK' event then
if Q="1010" then
Q<= "0000";
else
Q<= Q+1;
end if;
end if;
end process;
end Behavioral;
14. 4 BIT UP DOWN DECADE COUNTER
--Give the description of the 4 bit binary UP DOWN Decade counter to count from
-- 0 to 10 and 10 to 0 based on the control signal
library IEEE;
entity UDCNTR1 is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
con : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0):="0000");
end UDCNTR1;
architecture Behavioral of UDCNTR1 is
begin
process(clk, clr)
begin
if clr ='1' then
q<= "0000";
10
if con='0' then --up counting
if q="1010" then
q<="0000";
else
q<=q+1;
end if;
elsif con='1' then --down counting
if q="0000" then
q<="1010";
else
q<=q-1;
end if;
end if;
end if;
end process;
end Behavioral;
15. 4:2 PRIORITY ENCODER
--Code and simulate a 4:2 priority encoder. It should have the capability to indicate
--an invalid o/p when all the i/p are zero.
library IEEE;
entity PE421 is
Port ( w : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC;
y : out STD_LOGIC_VECTOR (1 downto 0));
end PE421;
architecture Behavioral of PE421 is
begin
--conditional assignment operator
y<= "11" when w(3)='1' else
"10" when w(2)='1' else
"01" when w(1)='1' else
"00"; --when w(0) =1
z<= '0' when w="0000" else '1';
end Behavioral;
16. 2:4 DECODER
11
-- Code and Simulate a 2:4 decoder with an enable input
library IEEE;
entity DEC241 is
Port ( Enable : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR (1 downto 0);
end DEC241;
architecture Behavioral of DEC241 is

begin
t<= Enable & Sel;
with t select --selected assignment statement
y<= "0001" when "100",
"0010" when "101",
"0100" when "110",
"1000" when "111",
"0000" when others;
end Behavioral;
17. 2:4 DEMULTIPLEXER
--Give a VHDL description of a 2:4 demultiplexer
library IEEE;
entity DEMUX1 is
end DEMUX1;
architecture Behavioral of DEMUX1 is
begin
process(sel)
12
begin
case sel is
when "00"=> y(0) <= d;
when "01"=> y(1) <= d;
when "10"=> y(2) <= d;
when "11"=> y(3) <= d;
when OTHERS=> NULL;
end case;
end process;
end Behavioral;
--Give a VHDL description of a 2:4 demultiplexer without using the process statement
library IEEE;
entity DEMUX1 is
end DEMUX1;
architecture Behavioral of DEMUX1 is
begin
y <= "000"&d when sel="00" else --conditional assignment
"00" &d&'0' when sel="01" else
'0'&d&"00" when sel="10" else
d & "000" when sel="11";
end Behavioral;
18. MEALY STATE MACHINE PROGRAM
 Design a Mealy network to design a sequence detector. The input is arriving

serially and the detector has to detect the sequence “1101”
library IEEE;
entity SEQ1 is
clk : in STD_LOGIC;
13
z : out STD_LOGIC :='0');
end SEQ1;
architecture Behavioral of SEQ1 is

type state_type is(A,B,C,D);
signal ps,ns:state_type;
begin
p1: process(ps,x)
begin
case ps is
when A=>
if x='1' then ns<= B;
else ns<=A;
end if;
when B=>
if x='1' then ns<=C;
else ns<=A;
end if;
when C=>
if x='1' then ns<=C;
else ns<=D;
end if;
when D=>
if x='1' then
z<='1';
ns<=B;
else
z<='0';
ns<=A;
end if;
when OTHERS=> z<='0';
end case;
end process p1;
p2: process(clk)
begin
if clk ='1' and clk' event then
ps<= ns;
end if;
end process p2;
end Behavioral;
14
19. MOORE BCD COUNTER
library IEEE;
entity MORBCD1 is
count : out STD_LOGIC_VECTOR (3 downto 0));
end MORBCD1;
architecture Behavioral of MORBCD1 is

Type state_type is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
signal ps,ns : state_type;
begin
process(clk)
begin
if clk='1' and clk' event then
ps<=ns;
end if;
end process;
process(ps)
begin
case ps is
when S0=> count <= "0000"; ns<=S1;
when S1=> count <= "0001"; ns<=S2;
when S2=> count <= "0010"; ns<=S3;
when S3=> count <= "0011"; ns<=S4;
when S4=> count <= "0100"; ns<=S5;
when S5=> count <= "0101"; ns<=S6;
when S6=> count <= "0110"; ns<=S7;
when S7=> count <= "0111"; ns<=S8;
when S8=> count <= "1000"; ns<=S9;
when S9=> count <= "1001"; ns<=S0;
when OTHERS => NULL;
end case;
end process;
end Behavioral;
20. 4 BIT COMPARATOR
library IEEE;
15
entity COMP1 is
alb : out STD_LOGIC;
aeb : out STD_LOGIC;
agb : out STD_LOGIC);
end COMP1;
architecture Behavioral of COMP1 is
begin
process(a,b)
begin
if a<b then
alb<= '1';
else
alb<= '0';
end if;
if a=b then
aeb<= '1';
else
aeb<='0';
end if;
if a>b then
agb<= '1';
else
agb<= '0';
end if;
end process;
end Behavioral;
21. BINARY TO GREY CODE CONVERTER
library IEEE;
entity BINGR1 is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
g : out STD_LOGIC_VECTOR (3 downto 0));
end BINGR1;
16
architecture Behavioral of BINGR1 is
begin
g(3)<= b(3);
g(2)<= b(3) xor b(2);
g(1)<= b(2) xor b(1);
g(0)<= b(1) xor b(0);
end Behavioral;
22. COUNTER 74163/192/193
--Code and simulate a 4 bit counter 74163 whose control signals are as described below
--o/p is cleared when clrn=0 and others are don't cares
--parallel load takes place when clrn=1 and ldn=0 and others dont cares
--there is no change in the state if clrn=1,ldn=1 and pt=0
--count increments only when all signals are high.
library IEEE;
entity COUNTER1 is
Port ( p : in STD_LOGIC;
t : in STD_LOGIC;
ldn : in STD_LOGIC;
clrn : in STD_LOGIC;
clk : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0);
cout: out STD_LOGIC;
d : in STD_LOGIC_VECTOR (3 downto 0));
end COUNTER1;
architecture Behavioral of COUNTER1 is
begin
cout<= q(3) and q(2) and q(1)and q(0) and t;
process(clk)
begin
if clk='1' and clk' event then
if clrn='0' then q<="0000";
elsif ldn='0' then q<= d;
elsif (p and t)='1' then q<= q+1;
end if;
end if;
end process;
17
end Behavioral;
23. 32 BIT ALU
-- Write a VHDL model for a 32 bit ALU. The ALU should perform the following:-
-- Use a combinational logic to calculate an o/p based on the 4 bit op code input
-- ALU should pass the result to the out bus when enable line is high and tristate when
low
-- ALU should decode the 4 bit code according to the table(refer syllabus book)
library IEEE;
entity ALU321 is
enable: in STD_LOGIC;
opcode : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (31 downto 0):=(others=>'0'));
end ALU321;
architecture Behavioral of ALU321 is
begin
process(enable,opcode)
begin
if enable='1' then
case opcode is
when "0001" => y <= a+b;
when "0010" => y <= a-b;
when "0011" => y <= not a;
when "0100" => y <= a*b;
when "0101" => y <= a and b;
when "0110" => y <= a or b;
when "0111" => y <= a nand b;
when "1000" => y <= a xor b;
end case;
elsif enable='0' then
y<=(others => '0');
end if;
end process;
end Behavioral;
18
24. KEYBOARD ENCODER
library IEEE;
entity KEYBOARD1 is
Port ( rl : in STD_LOGIC_VECTOR (3 downto 0);
sc : out STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0);
d : out STD_LOGIC_VECTOR (3 downto 0);
clr: in STD_LOGIC;
clk : in STD_LOGIC);
end KEYBOARD1;
architecture Behavioral of KEYBOARD1 is

signal clkdiv:STD_LOGIC_VECTOR(11 downto 0);
signal dclk: STD_LOGIC;
signal cnt2: STD_LOGIC_VECTOR(1 downto 0); -- for giving various values to the scan
lines
signal trl: STD_LOGIC_VECTOR(3 downto 0);
signal tsc: STD_LOGIC_VECTOR(3 downto 0);
signal tseg: STD_LOGIC_VECTOR(6 downto 0);
begin
p1: process(clk,clr) -- clk division as the clock frequency is very high

begin
if clr='1' then
clkdiv<=(others=>'0');
clkdiv<= clkdiv +1;
end if;
end process p1;
dclk<= clkdiv(11);
p2: process(dclk)
begin
if dclk='1' and dclk' event then
cnt2 <= cnt2 +1;
end if;
end process p2;
p3: process(cnt2) -- energising the scan lines at the right instants

begin
19
case cnt2 is
when "00"=> tsc <= "0001";
when "01"=> tsc <= "0010";
when "10"=> tsc <= "0100";
when "11"=> tsc <= "1000";
when OTHERS=> NULL;
end case;
end process p3;
sc<=tsc;
trl<= rl;
p4: process(tsc,trl)
begin
case tsc is
when "0001"=>
case trl is
when "0001"=> tseg <= "1111110"; --display 0
when "1000"=> tseg <= "1001110"; --display c
when OTHERS => tseg <= "0000000";
end case;
when "0010"=>
case trl is
when "1000"=> tseg <= "0111101"; --display D
end case;
when "0100"=>
case trl is
when "0100"=> tseg <= "1110111"; --display A
when "1000"=> tseg <= "1001111"; --display E
end case;
when "1000"=>
case trl is
when "0100"=> tseg <= "0011111"; --display B
when "1000"=> tseg <= "1000111"; --display F
20
end case;
when OTHERS=> NULL;
end case;
end process p4;
D<= "1110"; --activating the particular LED display
seg<= tseg;
end Behavioral;
25. BCD COUNTER ON THE 7 SEGMENT DISPLAY
--Write a VHDL code to show a BCD counter on the 7 segment display
library IEEE;
entity CNTDIS1 is
clr : in STD_LOGIC;
d : out STD_LOGIC_VECTOR (3 downto 0));
end CNTDIS1;
architecture Behavioral of CNTDIS1 is

signal clkdiv: STD_LOGIC_VECTOR(20 downto 0);
signal q: STD_LOGIC_VECTOR(3 downto 0);
signal tseg: STD_LOGIC_VECTOR(6 downto 0);
begin
p1:process(clk,clr)
begin
if clr='1' then
clkdiv<= clkdiv+1;
end if;
end process p1;
dclk<= clkdiv(20);
p2: process(dclk,clr)
begin
if clr='1' or q="1010" then
21
q<="0000";
elsif dclk='1' and dclk' event then
q<= q+1;
end if;
end process p2;
p3:process(q)
begin
case q is
when "0000"=> tseg <= "1111110";
when "0001"=> tseg <= "0110000";
when "0010"=> tseg <= "1101101";
when "0011"=> tseg <= "1111001";
when "0100"=> tseg <= "0110011";
when "0101"=> tseg <= "1011011";
when "0110"=> tseg <= "1011111";
when "0111"=> tseg <= "1110000";
when "1000"=> tseg <= "1111111";
when "1001"=> tseg <= "1110011";
end case;
end process p3;
d<= "1110";
seg<= tseg;
end Behavioral;
26. DECADE COUNTER ON THE 7 SEGMENT DISPLAY
--Code a VHDL Module for a double decade counter
library IEEE;
entity DOUBDEC1 is
clr : in STD_LOGIC;
d : out STD_LOGIC_VECTOR (3 downto 0));
end DOUBDEC1;
architecture Behavioral of DOUBDEC1 is

22
signal fclk: STD_LOGIC; -- for activating the LED device
signal tseg1, tseg2 : STD_LOGIC_VECTOR(6 downto 0);
signal q1,q2: STD_LOGIC_VECTOR(3 downto 0); -- counting
begin
p1: process (clk)
begin
if clr='1' then
clkdiv<= clkdiv+1;
end if;
end process;
dclk<= clkdiv(19);
p2: process(dclk,clr)
begin
if clr='1' or q2="1010" then
q1<= "0000";
q2<= "0000";
q1<=q1+1;
if q1="1001" then
q2<=q2+1;
q1<="0000";
end if;
end if;
end process p2;
p3: process(q1,q2)
begin
case q1 is
when "0000"=> tseg1 <= "1111110";
when "0001"=> tseg1 <= "0110000";
when "0010"=> tseg1 <= "1101101";
when "0011"=> tseg1 <= "1111001";
when "0100"=> tseg1 <= "0110011";
when "0101"=> tseg1 <= "1011011";
when "0110"=> tseg1 <= "1011111";
when "0111"=> tseg1 <= "1110000";
when "1000"=> tseg1 <= "1111111";
when "1001"=> tseg1 <= "1110011";
end case;
case q2 is
23
when "0000"=> tseg2 <= "1111110";
when "0001"=> tseg2 <= "0110000";
when "0010"=> tseg2 <= "1101101";
when "0011"=> tseg2 <= "1111001";
when "0100"=> tseg2 <= "0110011";
when "0101"=> tseg2 <= "1011011";
when "0110"=> tseg2 <= "1011111";
when "0111"=> tseg2 <= "1110000";
when "1000"=> tseg2 <= "1111111";
when "1001"=> tseg2 <= "1110011";
end case;
end process p3;
fclk<= clkdiv(5);
p4: process(fclk)
begin
if fclk='1' then
d<= "1101";
seg<= tseg1;
elsif fclk='0' then
d<="1110";
seg<= tseg2;
end if;
end process;
end Behavioral;
27. STEPPER MOTOR
library IEEE;
entity MOTOR1 is
Port ( dout : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
spd : in STD_LOGIC_VECTOR (1 downto 0); --to vary the speeds
dir : in STD_LOGIC); -- to change the direction: 0--> clk wise and 1--> anti clk
wise
end MOTOR1;
architecture Behavioral of MOTOR1 is

24
signal shift_reg: STD_LOGIC_VECTOR(3 downto 0):="1001"; --initial value for
rotation
begin
p1: process(clk,reset)
begin
if reset='1' then
clkdiv<= clkdiv+1;
end if;
end process p1;
dclk<= clkdiv(21) when spd="00" else --varying the speed based on the spd i/p
clkdiv(19) when spd="01" else
clkdiv(17) when spd="10" else
clkdiv(15);
p2: process(dclk,dir,reset)
begin
if reset='1' then
shift_reg<="1001";
if dir='0' then
shift_reg<= shift_reg(0)& shift_reg(3 downto 1);
else
shift_reg<= shift_reg(2 downto 0)& shift_reg(3);
end if;
end if;
end process p2;
dout<= shift_reg;
end Behavioral;
28. SQUARE WAVE GENERATION USING THE DAC INTERFACE
--Generating a square wave using the DAC interface

--Logic is the same as the clkdiv logic so we shall use the same logic
--however the variables which are used might be slightly different
library IEEE;
entity SQUARE1 is
Port ( reset : in STD_LOGIC;
25
clk : in STD_LOGIC;
dacout : out STD_LOGIC_VECTOR (7 downto 0));
end SQUARE1;
architecture Behavioral of SQUARE1 is

signal temp: STD_LOGIC_VECTOR(12 downto 0);
begin
begin
if reset='1' then
temp<=(others=>'0');
elsif clk='1' and clk'event then
temp<= temp+1;
end if;
end process p1;
dacout<=(others=>'0')when temp(12)='0' else
(others=>'1')when temp(12)='1';
end Behavioral;
29. TRIANGULAR WAVE GENERATION USING THE DAC
library IEEE;
entity TRIANGLE1 is
end TRIANGLE1;
architecture Behavioral of TRIANGLE1 is

signal temp: STD_LOGIC_VECTOR(3 downto 0);
signal counter:STD_LOGIC_VECTOR(7 downto 0):=(others=>'0');
signal flag:STD_LOGIC;
begin
p1:process(clk,reset)
begin
if reset='1' then
temp<="0000";
temp<= temp+1;
end if;
26
end process;
p2:process(temp(3),reset)
begin
if reset='1' then
counter<=(others=>'0');
elsif temp(3)='1' and temp(3)'event then
if counter="00000000" then
flag<='0';
elsif counter="11111111" then
flag<='1';
end if;
if flag='0' then
counter<= counter+1;
elsif flag='1' then
counter<= counter-1;
end if;
end if;
end process;
dacout<=counter;
end Behavioral;
30. SAW TOOTH WAVEFORM GENERATION USING DAC
library IEEE;
entity SAW1 is
end SAW1;
architecture Behavioral of SAW1 is

signal temp : STD_LOGIC_VECTOR(3 downto 0);
signal counter:STD_LOGIC_VECTOR(7 downto 0):=(others=>'0');
signal flag: STD_LOGIC;
begin
begin
if reset='1' then
temp<=(others=>'0');
27
temp<= temp+1;
end if;
end process p1;
p2: process(temp(3),reset)
begin
if reset='1' then
elsif temp(3)' event and temp(3)='1' then
if counter="00000000" then
flag<= '0';
elsif counter= "11111111" then
flag<='1';
end if;
if flag='0' then
counter<=counter+1;
elsif flag='1' then
end if;
end if;
end process p2;
dacout<= counter;
end Behavioral;
31. GENERATION OF A COUNTER USING T FLIP FLOPS (FOUR BIT

BINARY RIPPLE COUNTER)
--Using the T Flip Flop as a component generate a 4 bit ripple counter

library IEEE;
entity TFFCNT is
q : inout STD_LOGIC_VECTOR (3 downto 0):="0000");
end TFFCNT;
architecture Behavioral of TFFCNT is

component TFF
port(T,ck: in STD_LOGIC;
nq: out STD_LOGIC;
q: inout STD_LOGIC:='0');
end component;
signal s: STD_LOGIC_VECTOR(3 downto 0);
28
begin
p0: TFF port map('1',clk,q(0),s(0));
p1: TFF port map('1',s(0),q(1),s(1));
p2: TFF port map('1',s(1),q(2),s(2));
p3: TFF port map('1',s(2),q(3),s(3));
end Behavioral;
--Component for the counter
library IEEE;
entity TFF is
ck : in STD_LOGIC;
q : inout STD_LOGIC:='0';
end TFF;
architecture Behavioral of TFF is
begin
process(ck)
begin
if ck='1' and ck'event then
q<= T xor q;
end if;
end process;
nq<= not q;
end Behavioral;
32. BCD TO EXCESS 3 CONVERTER
library IEEE;
entity BCDE31 is
Port ( data : in STD_LOGIC_VECTOR (3 downto 0);
ex3 : out STD_LOGIC_VECTOR (3 downto 0));
end BCDE31;
architecture Behavioral of BCDE31 is
29
begin
ex3<= data+"0011" when (data<"1010" and data>="0000") else
"0000";
end Behavioral;
33. SEQUENCE GENERATOR
--Using a Moore Model generate a sequence generator to generate the sequence

--4,8,15,16,23,42
library IEEE;
entity SEQGEN1 is
count : out STD_LOGIC_VECTOR (5 downto 0));

end SEQGEN1;
architecture Behavioral of SEQGEN1 is

type state_type is(S0,S1,S2,S3,S4,S5);
signal ps,ns:state_type;
begin
process(clk)
begin
if clk='1' and clk'event then
ps<=ns;
end if;
end process;
process(ps)
begin
case ps is
when S0=> count<="000100"; ns<=S1;
when S1=> count<="001000"; ns<=S2;
when S2=> count<="001111"; ns<=S3;
when S3=> count<="010000"; ns<=S4;
when S4=> count<="010111"; ns<=S5;
when S5=> count<="101010"; ns<=S0;
when OTHERS=> NULL;
end case;
end process;
end Behavioral;
30
34. SYNCHRONOUS D FLIP FLOP
--Code the behavioral model for a D flip flop using a synchronous clr input
library IEEE;
entity SDFF1 is
clr : in STD_LOGIC;
d : in STD_LOGIC;
end SDFF1;
architecture Behavioral of SDFF1 is
begin
process(clk)
begin
if(clr='1') then
q<= '0';
q<= d;
end if;
end process;
nq<= not q;
end Behavioral;
35. SYNCHRONOUS T FLIP FLOP
--Code and simulate a T Flip Flop with synchronous Clr input

library IEEE;
entity STFF1 is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
31
end STFF1;
architecture Behavioral of STFF1 is
begin
process(clk)
begin
if clr='1' then
q<='0';
q<= t xor q;
end if;
end process;
nq<= not q;
end Behavioral;
36. S R LATCH
--Code and Simulate an SR Latch using the behavioral description

library IEEE;
entity SRL1 is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : inout STD_LOGIC;
NQ : out STD_LOGIC);
end SRL1;
architecture Behavioral of SRL1 is
begin
Q<= S or(not R and Q);
NQ<= not Q;
end Behavioral;
37. SISO SHIFT REGISTER
--Code a 16 Bit Serial in and serial out shift register with inputs SI,enable
--and the clk and o/ps so. The clk shifts on the rising edge.
library IEEE;
32
entity SISO1 is
Port ( si : in STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
so : out STD_LOGIC);
end SISO1;
architecture Behavioral of SISO1 is

signal reg: STD_LOGIC_VECTOR(15 downto 0);
begin
process(clk)
begin
if clk='1' and clk'event then
if en='1' then
reg(15 downto 0)<= si & reg(15 downto 1);
end if;
end if;
end process;
so<= reg(0);
end Behavioral;
38. 3 BIT SYNCHRONOUS COUNTER USING T FLIP FLOPS
library IEEE;
entity SYN3BC1 is
clr : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (2 downto 0));
end SYN3BC1;
architecture Behavioral of SYN3BC1 is

component TFF
port(T,ck,cl: in STD_LOGIC;
q: inout STD_LOGIC:='0');
end component;
signal t1,t2:STD_LOGIC;
begin
t1<=q(0)and q(1);
t2<=q(0);
p0: TFF port map('1',clk , clr , q(0));
33
p1: TFF port map(t2 , clk , clr, q(1));
p2: TFF port map(t1,clk,clr,q(2));
end Behavioral;
library IEEE;
entity TFF is
ck,cl : in STD_LOGIC;
q : inout STD_LOGIC);
end TFF;
architecture Behavioral of TFF is
begin
process(ck)
begin
if cl='1' then
q<='0';
elsif ck='1' and ck'event then
q<= T xor q;
end if;
end process;
end Behavioral;
34

Basic Gates Program

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Basic Gates Program

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1.

BASIC GATES PROGRAM

architecture Behavioral of BASGAT1 is

ynot <= not a;

architecture Behavioral of FA1 is

architecture Behavioral of FS1 is

diff<= x xor y xor bin;

4. FOUR BIT PARALLEL ADDER

architecture Behavioral of FA41 is

FA0 : FA port map(a(0),b(0),cin,sum(0),t(0));

--COMPONENT FOR THE PROGRAM OF A 4 BIT FULL ADDER

sum <= x xor y xor cin;

architecture Behavioral of FS41 is

signal t: STD_LOGIC_VECTOR(2 downto 0);

FS0 : FS port map(a(0),b(0),bin,diff(0),t(0));

architecture Behavioral of MUX411 is

with sel select --selected assignment statement.. it is concurrent statement

--Code for the 8:1 MUX using a process statement

architecture Behavioral of JKFF1 is

architecture Behavioral of DFF1 is

10. T FLIP FLOP

architecture Behavioral of TFF1 is

11. 3 BIT BINARY COUNTER WITH ASYNCRONOUS CLEAR INPUT

architecture Behavioral of BCNT31 is

12. SHIFT REGISTER

architecture Behavioral of SHIFT1 is

13. DECADE COUNTER

--Wirte the VHDL description of a DECADE counter that counts from 1 to 10

architecture Behavioral of DECNT1 is

14. 4 BIT UP DOWN DECADE COUNTER

architecture Behavioral of UDCNTR1 is

15. 4:2 PRIORITY ENCODER

architecture Behavioral of PE421 is

16. 2:4 DECODER

architecture Behavioral of DEC241 is

17. 2:4 DEMULTIPLEXER

--Give a VHDL description of a 2:4 demultiplexer

architecture Behavioral of DEMUX1 is

architecture Behavioral of DEMUX1 is

18. MEALY STATE MACHINE PROGRAM

 Design a Mealy network to design a sequence detector. The input is arriving

architecture Behavioral of SEQ1 is

architecture Behavioral of MORBCD1 is

20. 4 BIT COMPARATOR

architecture Behavioral of COMP1 is

21. BINARY TO GREY CODE CONVERTER

22. COUNTER 74163/192/193

architecture Behavioral of COUNTER1 is

23. 32 BIT ALU

architecture Behavioral of ALU321 is

architecture Behavioral of KEYBOARD1 is

p1: process(clk,clr) -- clk division as the clock frequency is very high

p3: process(cnt2) -- energising the scan lines at the right instants

25. BCD COUNTER ON THE 7 SEGMENT DISPLAY

--Write a VHDL code to show a BCD counter on the 7 segment display

architecture Behavioral of CNTDIS1 is

26. DECADE COUNTER ON THE 7 SEGMENT DISPLAY

--Code a VHDL Module for a double decade counter

architecture Behavioral of DOUBDEC1 is

27. STEPPER MOTOR

architecture Behavioral of MOTOR1 is

28. SQUARE WAVE GENERATION USING THE DAC INTERFACE