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library IEEE;
use IEEE.STD_LOGIC_1164.all;
package rijndael_package is
subtype SLV_8 is std_logic_vector(7 downto 0);
subtype STATE_TYPE is std_logic_vector(127 downto 0);
subtype SLV_128 is std_logic_vector(127 downto 0);
subtype SLV_32 is std_logic_vector(31 downto 0);
subtype round_type is integer range 0 to 10;
function SBOX_LOOKUP_FUNCT (a: SLV_8) return SLV_8;
function BYTE_SUB_FUNCT (state: STATE_TYPE) return STATE_TYPE;
function SFT_RW_FN (state1: STATE_TYPE) return STATE_TYPE;
function ISBOX_LOOKUP (a1: SLV_8) return SLV_8;
function IV_BT_SB_FcT (state2: STATE_TYPE) return STATE_TYPE;
function IV_SFT_RW_FCT (state3: STATE_TYPE) return STATE_TYPE;
function MX_CLMN_FCT (state: STATE_TYPE) return STATE_TYPE;
function MULTE_FUNCT (a: SLV_8; b: SLV_8) return SLV_8;
function INV_MX_CLMN_FCT (state: STATE_TYPE) return STATE_TYPE;
function POLY_MULTD_FUNCT (a: SLV_8; b: SLV_8) return SLV_8;
function ROUNDKEY_GEN (roundkey: STATE_TYPE; round: round_type) return STATE_TYPE;
end package rijndael_package;
mixcolumn transformation:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.rijndael_package.all;
entity mx_clmn is
Port ( state4 : in STD_LOGIC_VECTOR (127 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
DATAOUT : out STD_LOGIC_VECTOR (127 downto 0));
end mx_clmn;
architecture aes_top_RTL of mx_clmn is
begin
PROCESS(clk)
begin
if(rst='1') then DATAOUT<=(others=>'0');
elsif(clk='1' and clk'event) then
DATAOUT<=MX_CLMN_FCT(state4);
end if;
end process;
end aes_top_RTL;
key expantion:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.rijndael_package.all;
entity key_gen is
Port ( key : in STD_LOGIC_VECTOR (127 downto 0);
ROUND : in round_type;
DATAOUT : out STD_LOGIC_VECTOR (127 downto 0));
end key_gen;
architecture aes_top_RTL of key_gen is
begin
process(key,ROUND)
begin
DATAOUT<=ROUNDKEY_GEN(key,ROUND);
END PROCESS;
end aes_top_RTL;
encryption program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.rijndael_package.all;
entity encryp is
Port ( DATAIN : in STD_LOGIC_VECTOR (127 downto 0);
rndkey: in std_logic_vector(127 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
DATAOUT : out STD_LOGIC_VECTOR (127 downto 0));
end encryp;
architecture structural of encryp is
signal s0: std_logic_vector(127 downto 0);
signal s1: std_logic_vector(127 downto 0);
signal s2: std_logic_vector(127 downto 0);
signal s3: std_logic_vector(127 downto 0);
signal s4: std_logic_vector(127 downto 0);
signal s5: std_logic_vector(127 downto 0);
signal s6: std_logic_vector(127 downto 0);
signal s7: std_logic_vector(127 downto 0);
signal s8: std_logic_vector(127 downto 0);
signal s9: std_logic_vector(127 downto 0);
signal s10: std_logic_vector(127 downto 0);
signal s11: std_logic_vector(127 downto 0);
signal s12: std_logic_vector(127 downto 0);
signal s13: std_logic_vector(127 downto 0);
signal s14: std_logic_vector(127 downto 0);
signal s15: std_logic_vector(127 downto 0);
signal s16: std_logic_vector(127 downto 0);
signal s17: std_logic_vector(127 downto 0);
signal s18: std_logic_vector(127 downto 0);
signal s19: std_logic_vector(127 downto 0);
signal s20: std_logic_vector(127 downto 0);
signal s21: std_logic_vector(127 downto 0);
signal s22: std_logic_vector(127 downto 0);
signal s23: std_logic_vector(127 downto 0);
signal s24: std_logic_vector(127 downto 0);
signal s25: std_logic_vector(127 downto 0);
signal s26: std_logic_vector(127 downto 0);
signal s27: std_logic_vector(127 downto 0);
signal s28: std_logic_vector(127 downto 0);
signal s29: std_logic_vector(127 downto 0);
signal s30: std_logic_vector(127 downto 0);
signal s31: std_logic_vector(127 downto 0);
signal s32: std_logic_vector(127 downto 0);
signal s33: std_logic_vector(127 downto 0);
signal s34: std_logic_vector(127 downto 0);
signal s35: std_logic_vector(127 downto 0);
signal s36: std_logic_vector(127 downto 0);
signal s37: std_logic_vector(127 downto 0);
signal s38: std_logic_vector(127 downto 0);
component byte_sub is
Port ( state : in STD_LOGIC_VECTOR (127 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
b : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component SFT_RW is
Port ( state1 : in STD_LOGIC_VECTOR (127 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
DATAOUT : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component mx_clmn is
Port ( state4 : in STD_LOGIC_VECTOR (127 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
DATAOUT : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component addrnd_key is
Port ( datain : in STD_LOGIC_VECTOR (127 downto 0);
rndkey : in STD_LOGIC_VECTOR (127 downto 0);
dataout : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component key_gen is
Port ( key : in STD_LOGIC_VECTOR (127 downto 0);
ROUND : in round_type;
DATAOUT : out STD_LOGIC_VECTOR (127 downto 0));
end component;
begin
V0:key_gen port map(rndkey,1,k1);
V1:key_gen port map(k1,2,k2);
V2:key_gen port map(k2,3,k3);
V3:key_gen port map(k3,4,k4);
V4:key_gen port map(k4,5,k5);
V5:key_gen port map(k5,6,k6);
V6:key_gen port map(k6,7,k7);
V7:key_gen port map(k7,8,k8);
V8:key_gen port map(k8,9,k9);
V9:key_gen port map(k9,10,k10);
U0: addrnd_key port map(DATAIN,rndkey,s0);
--rnd1
U1: byte_sub port map(s0,clk,rst,s1);
U2: SFT_RW port map(s1,clk,rst,s2);
U3: mx_clmn port map(s2,clk,rst,s3);
U4: addrnd_key port map(s3,k1,s4);
--rnd2
U5: byte_sub port map(s4,clk,rst,s5);
U6: SFT_RW port map(s5,clk,rst,s6);
U7: mx_clmn port map(s6,clk,rst,s7);
U8: addrnd_key port map(s7,k2,s8);
--rnd3
U9: byte_sub port map(s8,clk,rst,s9);
U10: SFT_RW port map(s9,clk,rst,s10);
U11: mx_clmn port map(s10,clk,rst,s11);
U12: addrnd_key port map(s11,k3,s12);
--rnd4
U13: byte_sub port map(s12,clk,rst,s13);
U14: SFT_RW port map(s13,clk,rst,s14);
U15: mx_clmn port map(s14,clk,rst,s15);
U16: addrnd_key port map(s15,k4,s16);
--rnd5
U17: byte_sub port map(s16,clk,rst,s17);
U18: SFT_RW port map(s17,clk,rst,s18);
U19: mx_clmn port map(s18,clk,rst,s19);
U20: addrnd_key port map(s19,k5,s20);
--rnd6
U21: byte_sub port map(s20,clk,rst,s21);
U22: SFT_RW port map(s21,clk,rst,s22);
U23: mx_clmn port map(s22,clk,rst,s23);
U24: addrnd_key port map(s23,k6,s24);
--rnd7
U25: byte_sub port map(s24,clk,rst,s25);
U26: SFT_RW port map(s25,clk,rst,s26);
U27: mx_clmn port map(s26,clk,rst,s27);
U28: addrnd_key port map(s27,k7,s28);
--rnd8
U29: byte_sub port map(s28,clk,rst,s29);
U30: SFT_RW port map(s29,clk,rst,s30);
U31: mx_clmn port map(s30,clk,rst,s31);
U32: addrnd_key port map(s31,k8,s32);
--rnd9
U33: byte_sub port map(s32,clk,rst,s33);
U34: SFT_RW port map(s33,clk,rst,s34);
U35: mx_clmn port map(s34,clk,rst,s35);
U36: addrnd_key port map(s35,k9,s36);
--rnd10
U37: byte_sub port map(s36,clk,rst,s37);
U38: SFT_RW port map(s37,clk,rst,s38);
U39: addrnd_key port map(s38,k10,DATAOUT);
end structural;
decryption program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.rijndael_package.all;
entity dcryption is
Port ( datain : in STD_LOGIC_VECTOR (127 downto 0);
rndkey:in STD_LOGIC_VECTOR (127 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dataout : out STD_LOGIC_VECTOR (127 downto 0));
end dcryption;
architecture structural of dcryption is
signal s0: std_logic_vector(127 downto 0);
signal s1: std_logic_vector(127 downto 0);
signal s2: std_logic_vector(127 downto 0);
signal s3: std_logic_vector(127 downto 0);
signal s4: std_logic_vector(127 downto 0);
signal s5: std_logic_vector(127 downto 0);
signal s6: std_logic_vector(127 downto 0);
signal s7: std_logic_vector(127 downto 0);
signal s8: std_logic_vector(127 downto 0);
signal s9: std_logic_vector(127 downto 0);
signal s10: std_logic_vector(127 downto 0);
signal s11: std_logic_vector(127 downto 0);
signal s12: std_logic_vector(127 downto 0);
signal s13: std_logic_vector(127 downto 0);
signal s14: std_logic_vector(127 downto 0);
signal s15: std_logic_vector(127 downto 0);
signal s16: std_logic_vector(127 downto 0);
signal s17: std_logic_vector(127 downto 0);
signal s18: std_logic_vector(127 downto 0);
signal s19: std_logic_vector(127 downto 0);
signal s20: std_logic_vector(127 downto 0);
signal s21: std_logic_vector(127 downto 0);
signal s22: std_logic_vector(127 downto 0);
signal s23: std_logic_vector(127 downto 0);
signal s24: std_logic_vector(127 downto 0);
signal s25: std_logic_vector(127 downto 0);
signal s26: std_logic_vector(127 downto 0);
signal s27: std_logic_vector(127 downto 0);
signal s28: std_logic_vector(127 downto 0);
signal s29: std_logic_vector(127 downto 0);
signal s30: std_logic_vector(127 downto 0);
signal s31: std_logic_vector(127 downto 0);
signal s32: std_logic_vector(127 downto 0);
signal s33: std_logic_vector(127 downto 0);
signal s34: std_logic_vector(127 downto 0);
signal s35: std_logic_vector(127 downto 0);
signal s36: std_logic_vector(127 downto 0);
signal s37: std_logic_vector(127 downto 0);
signal s38: std_logic_vector(127 downto 0);