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Q. 2) What is race around condition and how it is eliminated?

Ans: Race conditions is a severe way crashing the server/ system at times. Generally this
problem arises in priority less systems or the users who has eqal priority will be put to this
problem. Race condition is a situation in which a resource D is to be serviced to a process A and
the processB which holds the resoure C is to be given to the process A. So a cyclic chain occurs
and no way the resources will be get shared and also the systems with equal prirority wont get
the resoure so that the system wont come out of the blocked state due to race condition!

Race condition is a bug in your application, occurs when the result of your application depends on
which one of two or more threads reaches a shared block of code first. In this case, the
application output changes each time it is executed!

As an example; assume that we have a shared integer object called x, and we have two threads
1, and 2. Thread number 1 attempt to increment the x object by one, and during this increment
process, its time slice has been finished. Thread 2 time slice just start and it attempt to increment
the same x object too. Thread 2 incremented the x object successfully, and then its time slice
finished. Thread 1 starts a new time slice and completing the increment process not knowing that
the object x value is already changed. This is a race condition, and the output of such code is of
course incorrect!

The above race condition problem can be solved by using an object like "InterLock", with its
"Increment", and "Decrement" methods.

Race conditions can be avoided generally by considering each line of code you write, and asking
yourself: What might happen if a thread finished before executing this line? or during executing
this line? and another thread overtook it?
Q. 3) Give Different phases of instruction cycle.

Ans: Instruction cycle: An instruction cycle (sometimes called fetch-and-execute cycle, fetch-
decode-execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by
which a computer retrieves a program instruction from its memory, determines what actions the
instruction requires, and carries out those actions. This cycle is repeated continuously by the
central processing unit (CPU), from bootup to when the computer is shut down.

1 Circuits used

2 Instruction cycle

2.1 2. Decode the instruction

2.2 3. Execute the instruction

2.3 4. Store results

3 Fetch cycle

4 Execute cycle

5 Initiating the cycle

6 The Fetch-Execute cycle in Transfer Notation

7 References

Circuits used

The circuits used in the CPU during the cycle are:

Program Counter (PC) - an incrementing counter that keeps track of the memory address of
which instruction is to be executed next

Memory Address Register (MAR) - holds the address in memory of the next instruction to be
executed

Memory Data Register (MDR) - a two-way register that holds data fetched from memory (and
ready for the CPU to process) or data waiting to be stored in memory
Current Instruction Register (CIR) - a temporary holding ground for the instruction that has just
been fetched from memory

Control Unit (CU) - decodes the program instruction in the CIR, selecting machine resources such
as a data source register and a particular arithmetic operation, and coordinates activation of
those resources

Arithmetic logic unit (ALU) - performs mathematical and logical operations

The time period during which one instruction is fetched from memory and executed when a
computer is given an instruction in machine language. There are typically four stages of an
instruction cycle that the CPU carries out: 1) Fetch the instruction from memory. 2) "Decode" the
instruction. 3) "Read the effective address" from memory if the instruction has an indirect
address. 4) "Execute" the instruction.

Instruction cycle

Each computer's CPU can have different cycles based on different instruction sets, but will be
similar to the following cycle:

Decode the instruction

The instruction decoder interprets the instruction. If the instruction has an indirect address, the
effective address is read from main memory, and any required data is fetched from main memory
to be processed and then placed into data registers. During this phase the instruction inside the
IR (instruction register) decode.

Execute the instruction

The CU passes the decoded information as a sequence of control signals to the relevant function
units of the CPU to perform the actions required by the instruction such as reading values from
registers, passing them to the ALU to perform mathematical or logic functions on them, and
writing the result back to a register. If the ALU is involved, it sends a condition signal back to the
CU.

Store results
The result generated by the operation is stored in the main memory, or sent to an output device.
Based on the condition of any feedback from the ALU, Program Counter may be updated to a
different address from which the next instruction will be fetched.

The cycle is then repeated.

Fetch cycle

Steps 1 and 2 of the Instruction Cycle are called the Fetch Cycle. These steps are the same for
each instruction. The fetch cycle processes the instruction from the instruction word which
contains an opcode and an operand.

Execute cycle

Steps 3 and 4 of the Instruction Cycle are part of the Execute Cycle. These steps will change with
each instruction.

The first step of the execute cycle is the Process-Memory. Data is transferred between the CPU
and the I/O module. Next is the Data-Processing uses mathematical operations as well as logical
operations in reference to data. Central alterations is the next step, is a sequence of operations,
for example a jump operation. The last step is a combined operation from all the other steps.

Initiating the cycle

The cycle starts immediately when power is applied to the system using an initial PC value that is
predefined for the system architecture (in Intel IA-32 CPUs, for instance, the predefined PC value
is 0xfffffff0). Typically this address points to instructions in a read-only memory (ROM) which
begin the process of loading the operating system. (That loading process is called booting.)[1]

The Fetch-Execute cycle in Transfer Notation

Expressed in register transfer notation:

(Increment the PC for next cycle)

The registers used above, besides the ones described earlier, are the Memory Address Register
(MAR) and the Memory Data Register (MDR), which are used (at least conceptually) in the
accessing of memory.
Q. Distinguish between Hardwired control and micro programmed control.

Ans: Hardwired vs. Micro-programmed Computers

It should be mentioned that most computers today are micro-programmed. The reason is
basically one of flexibility. Once the control unit of a hard-wired computer is designed and built, it
is virtually impossible to alter its architecture and instruction set. In the case of a micro-
programmed computer, however, we can change the computer's instruction set simply by altering
the microprogram stored in its control memory. In fact, taking our basic computer as an example,
we notice that its four-bit op-code permits up to 16 instructions. Therefore, we could add seven
more instructions to the instruction set by simply expanding its microprogram. To do this with the
hard-wired version of our computer would require a complete redesign of the controller circuit
hardware.

Another advantage to using micro-programmed control is the fact that the task of designing the
computer in the first place is simplified. The process of specifying the architecture and instruction
set is now one of software (micro-programming) as opposed to hardware design. Nevertheless,
for certain applications hard-wired computers are still used. If speed is a consideration, hard-
wiring may be required since it is faster to have the hardware issue the required control signals
than to have a "program" do it.

Hardwired control is a control mechanism to generate control signals by using appropriate finite
state machine (FSM). Microprogrammed control is a control mechanism to generate
control signals by using a memory called control storage (CS), which contains the
control signals. Although microprogrammed control seems to be advantageous to CISC
machines, since CISC requires systematic development of sophisticated control
signals, there is no intrinsic difference between these 2 control mechanism.

The pair of "microinstruction-register" and "control storage address register" can be


regarded as a "state register" for the hardwired control. Note that the control storage
can be regarded as a kind of combinational logic circuit. We can assign any 0, 1 values
to each output corresponding to each address, which can be regarded as the input for a
combinational logic circuit. This is a truth table.

Hardwired systems are made to perform in a set manner, implemented with logic, switches, etc.
between any input and output in the system. Once the manner in which the control is executed,
you can not change the behavior of the system.
Microprogrammed systems are centered around a computer of some sort, often a microcontroller
in small systems, that controls the system using a program. Input is sent to the computer, and the
program determines what should be done with the input to come up with an output. So the
processor is between the input and the output, rather than a direct link between the input and
output.
The vesatility of the microprogrammed system far exceeds the hardwired system. The systems
can also be considerably smaller. The size of a complex microcontroller can be quite a bit smaller
that a bunch of logic and switches for the same functionality.
Q. What is page fault?

Ans: A page fault is a trap to the software raised by the hardware when a program accesses a
page that is mapped in the virtual address space, but not loaded in physical memory.

The hardware that detects this situation is the memory management unit in a processor. The
exception handling software that handles the page fault is generally part of an operating system.
The operating system tries to handle the page fault by making the required page accessible at a
location in physical memory or kills the program in case it is an illegal access.

Reasons for page fault

A page fault occurs when the processor accesses an address where the page corresponding to
the requested address is not marked in the memory management unit as being loaded in
memory. The hardware fault or faults generated in this case depends on the instruction set
architecture of the processor. With some instruction set architectures, the hardware fault in
question might be generated by conditions other than an access to an address in a page not
loaded in memory; this means that the handler for that hardware fault will have to determine
whether it corresponds to a page fault or not.

A closely related exception known as a protection fault is generated for page accesses where the
page corresponding to the requested address is marked in the memory management unit as
being loaded in memory, but is not marked as allowing the type of operation that the processor
tried to perform; for example, the page might be marked as not allowing stores, in which case an
attempt to store into the page will generate a protection fault, or it might be marked as not
allowing code execution, in which case an attempt to fetch an instruction from the page will
generate a protection fault. Again, the hardware fault or faults generated in this case depends on
the instruction set of the processor.

The terms "page fault" and "protection fault" are used here to refer to the way the operating
system handles the faults; they are not necessarily the names given to the hardware faults that
occur. For example, on the x86 architecture, accesses to pages that are not present and
accesses to pages that do not conform to the permission attributes for a given page (protection
faults as described above) are both reported via a hardware fault called a "page fault", and the
processor hardware provides information to the page fault handler that indicates what sort of
access triggered the fault, so that these scenarios may be differentiated by the operating system.
The usage of the term protection fault (when speaking in relation to page faults) is thus not to be
confused with the x86 general protection fault exception, which is used to signal segmentation-
based memory access violations.

Operating systems that implement copy-on-write pages might mark a page to which writing
should be permitted as not allowing writes, so that an attempt by the processor to store a value
into the page will cause a hardware fault; that hardware fault might be the same type of fault as
the hardware fault for a page not loaded into memory, or might be a different type of fault. A
"copy-on-write" fault will be handled by making a copy of the page in question, marking that page
as allowing writes, and changing the tables used by the memory management unit so that the
address into which the store was attempted refers to the new page; when that store is retried
after the fault is handled, it will succeed, but will store into the copy. Those faults can be thought
of as a type of page fault.
Q. Is it possible to have a hardwired command associated with a control memory?

Ans: To execute instructions, a computer's processor must generate the control signals used to
perform the processor's actions in the proper sequence. This sequence of actions can either be
executed by another processor's software (for example in software emulation or simulation of a
processor) or in hardware. Hardware methods fall into two categories: the processor's hardware
signals are generated either by hardwired control, in which the instruction bits directly generate
the signals, or by microprogrammed control in which a dedicated microcontroller executes a
microprogram to generate the signals.
Before microprocessors, hardwired control usually was implemented using discrete components,
flip-chips, or even rotating discs or drums. This can be generally done by two methods.
Method1: The classical method of sequential circuit design. It attempts to minimize the amount of
hardwire, in particular, by using only log2p flip flops to realize a p state circuit.
Method2: An approach that uses one flip flop per state and is known as one hot method. While
expensive in terms of flip flops, this method simplifies controller unit design and debugging.
In practice, processor control units are often so complex that no one design method by itself can
yield a satisfactory circuit at an acceptable cost. The most acceptable design may consist of
several linked, but independently designed, sequential circuits.
Microprogramming made it possible to re-wire, as it were, a computer by simply downloading a
new microprogram to it. This required dedicated hardware or an external processor. For example,
some of DEC's PDP-10 processors used a PDP-11 as a front-end which uploaded a
microprogram to the main processor at boot time.
Traditionally, a sewing machines' stitch patterns and a washing machine's wash programs were
implemented as hardwired, usually mechanical, controls. In modern machines, these are instead
implemented as software which controls a computer which controls the machine hardware. This
makes it possible, for example, to download additional stitch patterns for a small fee or upgrade a
machine without having to buy a complete new machine. It also opens up for intellectual property
rights issues.
Q. Define the following:

(a) Micro operation

(b) Micro Instruction

(c) Micro Program

(d) Micro Code

Ans:

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