Objective: To implement an 8-Bit Full Adder/Subtractor in the VHDL format.

The 8-Bit
Full Adder/Subtractor is a logic unit used to compute the sum or difference of 8-Bit
binary words.

Process: Starting with basic gates we created a Half Adder, which we then used in
creating a Full Adder. Once the Full Adder was produced we created a test bench to
verify it’s correct operation before proceeding. After verifying the proper operation of the
Full Adder, we followed the next step in hierarchical design by creating the 1-Bit Full
Adder/Subtractor device. This device includes the Full Adder and an XOR gate to
implement the device’s ability to do addition and subtractrion. After this device was
completed, we once again created an appropriate test bench to verify it’s correct
operation. Having verified it’s operation, we instantiated the 1-Bit Full Adder/Subtractor
8 times we defined the appropriate signals to make the 8 units work as a fully operational
8-Bit Full Adder/Subtractor. To finalize the project we created a test bench for the
completed 8-Bit Full Adder/Subtractor and verified it’s correct operation. Below are our
results.

Results: From the relatively small set of data we used to test our design it would seem
that our device calculates addition and subtraction of 8-Bit binary words correctly. To
support this claim below we have hand calculated the test data used in the in the
simulation. We’ve highlighted 3 of the hand calculated results, each different color
corresponds to the respective color on the simulation waveform trace. The VHDL code
used to implement all gates used in our 8-Bit Full Adder/Subtractor is attached along with
the simulation’s waveform trace.

00000000 00000000 01001000 11000110

+ 00000000 - 00000000 + 00010001 - 01001110
--------------------- --------------------- --------------------- ---------------------
00000000 00000000 01011001 01111000

10101010 10101010 11111111 11111111

+ 00101010 + 10101010 + 11111111 - 11111111
--------------------- --------------------- --------------------- ---------------------
11010100 101010100 111111110 00000000
(overflows) (overflow)

10011101 10011101
+ 00010011 - 10010011
--------------------- ---------------------
10110000 00001010