October 11, 2000 1

USB 2.0 Transceiver

Macrocell
Steve McGowan - Intel Corporation
Clarence Lewis - Texas Instruments
Haoran Duan - Agilent Technologies

October 11, 2000 2

 USB 2.0 Transceiver
Macrocell Interface

Overview

October 11, 2000 3

 Macrocell Requirements
 Enable Peripherals
 Does not address hubs and hosts
– No downstream port support
 Disconnect Detection
 40 bit EOP

– No repeater support
 Very implementation dependent
 Requires separate port

October 11, 2000 4

 Macrocell Requirements
Overview
 Simplify the design process for peripheral vendors
– Consolidate high speed logic in to a discrete module
– Provide a “standard” USB 2.0 hardware interface
 Minimize time to market
– Isolate process dependent transceiver development
 Enable standard library elements from ASIC vendors
– Peripheral vendors can focus on product
specific development
 Easy port of existing USB 1.1 SIE logic

October 11, 2000

Enable High Volume Devices 5
 USB Device Development
Overview
 Assumptions
– Prototyping
 FPGA + UTMI Compliant Discrete Transceiver

– Production
 Low Volume
 Gate Array + UTMI Compliant Discrete Transceiver

 High Volume
 ASIC + integrated UTMI Compliant Transceiver Macrocell

October 11, 2000 6

 Device Anatomy
Overview
 USB Transceiver Macrocell (UTM)
 Serial Interface Engine
 Device Specific Logic UTM
Interface

ASIC
ASIC
Serial
SerialInterface
InterfaceEngine
Engine
Device
Hardware Device
Device Endpoint Logic
Specific
Specific USB USB 2.0
Endpoint Logic
SIE USB2.0
2.0
Logic
Logic Control Transceiver
… Logic
Transceiver
Endpoint Logic

October 11, 2000 7

 Serial Interface Engine
Overview
 SIE Control Logic
– USB Transaction State Machine
– PID, Address, and EP match logic
– Checks receive completion status
– Chains packets into transactions
 Endpoint Logic
– FIFOs and FIFO control
Serial
SerialInterface
InterfaceEngine
Engine
Endpoint Logic
To Device Control
SIE
Specific Endpoint Logic Control
Data
DataInIn To Transceiver
… Logic Data
DataOut
Logic Out
Endpoint Logic
October 11, 2000 8
 Transceiver Macrocell
Overview
 Converts USB signaling into a parallel interface
– USB 2.0 compliant serial interface
– Multiple Parallel Data Interface Options
– Multiple Speed Options
 HS/FS, FS Only, LS Only

Control
USB
USB2.0
2.0 USB 2.0 To Bus
To SIE Data In
Transceiver
Transceiver
Data Out

October 11, 2000 9

 Macrocell Functions
Overview
 HS and FS signaling and termination
 HS receiver squelch
 USB clock recovery
 Bit stuffing
 NRZI encoding
 Serializing and deserializing
 Data-rate tolerance
 Data buffering
 Single interface for HS/FS, FS or LS operation
October 11, 2000 10
 Block Diagram
Overview
D- HS Shared
Shared Logic
Logic
Interface Bit
Bit TX
TX Holding
Holding
D+ Seralizer
Seralizer Data
Stuffer
Stuffer Reg
Reg
Parallel
Parallel
To
Interface
Interface
USB DLL
Bit
Bit Deseralizer
RX
RX Holding
Holding
DLL
Unstuffer Deseralizer Reg
mux
mux
Unstuffer Reg To
SIE

FS Control
Interface Control
Control

DLL
DLL

October 11, 2000 11

 Interface Features
Macrocell Functions
 Packet Engine
– Automatically handles SYNC Pattern and EOP
 Flow Control
– Compensates for Bit Stuffing and Data Rate Tolerance
 Complete Primitives for Full Protocol Support
 Speed Switching
 Clock Generation
 Power Control
October 11, 2000 12
 Interface Options
Macrocell Functions
 Integrated Macrocell
– 8-Bit Uni-directional
– 16-Bit Uni-directional
 Discrete Transceiver
– 8-Bit Bi-directional
– 16-Bit Bi-directional / 8-Bit Uni-directional

October 11, 2000 13

 8-Bit Uni-Directional
Interface Options
8-Bit Interface

DataIn(0-7) DataOut(0-7)

TXValid TXReady

RXActive
RXValid

Reset
SusepsndM CLK
RXError
XcvrSelect
TermSelect DP
DM
OpMode(0-1)
October 11, 2000
LineState(0-1) 14
 16-Bit Uni-Directional
Interface Options
16-Bit Interface
DataIn(8-15) DataOut(8-15)
DataIn(0-7) DataOut(0-7)

TXValid TXReady
TXValidH
RXActive

RXValid
RXValidH

Reset CLK
SusepsndM RXError

XcvrSelect DP
TermSelect DM

OpMode(0-1) LineState(0-1)
October 11, 2000 15
 8-Bit Bi-Directional
Interface Options
 TXValid Determines data direction
8-Bit Bi-Directional Interface

Data(0-7)

DataOut(0-7) DataIn(0-7)

TXValid

October 11, 2000 16

 16-Bit Bi-Directional
Interface Options
 ValidH provides multiplexed high-byte valid flag
16-Bit Bi-Directional Interface

DataBus16_8 Data(8-15)
Data(0-7)

ValidH

DataOut(8-15) DataIn(8-15)
DataOut(0-7) DataIn(0-7)

TXValid TXReady

RXValidH TXValidH

October 11, 2000 17

 Protocol Primitive Support
Macrocell Functions
 Resume Assertion
 Resume Detection
 Suspend Detection
 Reset Detection
 HS Detection Handshake

October 11, 2000 18

 Clock Generation
Macrocell Functions
 Macrocell supplies clocks to the SIE
 Frequency depends on implementation
– HS/FS
 60 MHz 8-bit uni-directional
 30 MHz 16-bit uni- or bi-directional

– FS Only
 48 MHz 8-bit uni-directional

– LS Only
 6 MHz 8-bit uni-directional

October 11, 2000 19

 Power Control
Macrocell Functions
 SuspendM signal
– Shuts down clocks
– Maintains terminations
 Vendor determined Drive Current Control
– Enabled during transmits HS_Data_Driver_Input

DP
– Enabled by receives
DM
– Always on
HS_Current_Source_Enable
HS_Drive_Enable

October 11, 2000 High-speed Current Driver 20

 USB 2.0 Transceiver
Macrocell Interface

Testing

October 11, 2000 21

 Testing
 UTMI Test Connector Specification
 Test Environment - 3 board set
– Off the shelf i960 eval board
– Custom SIE card
 FPGA, DPRAM, and Test Points

– Daughter Card with UTMI Transceiver

 Functionality
– Packet Blaster
 Single Packet operations

– Device Emulator
 Transaction level operations

October 11, 2000 22

 UTMI Test Connector
Specification
 UTMI Test Connector
– 100 Pins
 Electrical interface
– Timing
– Levels
 Mechanical design
– PCB layout

October 11, 2000 23

 Board Set
Testing
 Processor Card
– EVAL80960VH Evaluation Platform Board
– RAM, ROM, FLASH, Serial Port
 FPGA Card
– Dual Port RAM - 64KB
– FPGA - Quicklogic
– Test Points
 Transceiver Daughter Card
– Discrete UTMI compliant transceiver
– Custom circuitry
October 11, 2000 24
 Block Diagram
Testing
RS-232
Device Specific Logic
I960
i960 DRAM Flash UART Card
I960
Local Bus

Serial
SerialInterface
InterfaceEngine
Engine FPGA
DPRAM FPGA
Card
UTM
Interface
USB
USB2.0
2.0Transceiver
Transceiver
Transceiver / Transceiver
Macrocell Daughter
Card

USB 2.0
October 11, 2000 25
 Mechanicals
Testing
i960 Card RS-232 Connector
RAM

CPU
Test Chip Daughter
Card

FPGA FPGA
Xcvr
To USB Card
Device DP
RAM

100 Pin PCI Slots

UTMI Connector (Power)
October 11, 2000 26
 Pinout Features
 Vendor Status and Vendor Control support
 Multiple Datapath Options Supported
– 8-Bit Bi-Directional
– 8-Bit Uni-Directional
– 16-Bit Bi-Directional/8-Bit Uni-Directional
 Vendor ID
 13 General Purpose I/O pins
 Vbus Control

October 11, 2000 27

 Pinout
Testing
1 GPIO0 26 GPIO1 51 GND 76 GND
2 GND 27 GND 52 System Clock 77 ValidH
3 GPIO2 28 VBUS_out 53 GND 78 DataBus16_8
4 GND 29 GPIO3 54 GND 79 VControl1
5 GPIO4 30 VendorID_0 55 VControl0 80 GND
6 GPIO5 31 Data15 56 GPIO6 81 VDD
7 GPIO7 32 GND 57 VDD 82 Data14
8 VDD 33 Data13 58 GPIO8 83 Data12
9 GND 34 Data11 59 VControl2 84 GND
10 VControl3 35 GND 60 TxValid 85 Data10
11 GPIO9 36 Data9 61 GPIO10 86 Data8
12 GPIO11 37 Data7 62 GND 87 VDD
13 GND 38 VDD 63 GPIO12 88 Data6
14 VControlLoadM 39 GND 64 IFType0 89 IFType1
15 VStatus4 40 Force_RxErr 65 GND 90 CLK
16 VDD 41 Data5 66 RxActive 91 Data4
17 Reset 42 Data3 67 OpMode0 92 GND
18 OpMode1 43 GND 68 GND 93 Data2
19 XcvrSelect 44 Data1 69 VDD 94 Data0
20 TermSelect 45 VStatus0 70 VStatus1 95 GND
21 GND 46 GND 71 VStatus2 96 VStatus3
22 SuspendM 47 VBUS_in 72 RxValid 97 VStatus5
23 LineState0 48 VStatus6 73 GND 98 VStatus7
24 GND 49 VDD 74 RxError 99 VendorID_1
25 LineState1 50 Vdbus16_8 75 TxReady 100 GND
October 11, 2000 28
 Next Steps
 Get the USB 2.0 Transceiver Macrocell Interface
(UTMI) Specification
– http://developer.intel.com/technology/usb/
– No Royalty
 Design to the UTMI Specification
 Get the UTMI Test Connector Specification
– http://developer.intel.com/technology/usb/
 Get your ASIC vendors to provide a UTMI Compliant
Macrocells
October 11, 2000 29