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Quiz Start Time: 02:08 AM s)

Question # 2 of 10 ( Start time: 02:09:31


Total Marks: 1
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A stage in the shift register consists of

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a latch

a flip flop

a byte of storage

four bits of storage

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81
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Quiz Start Time: 02:08 AM s)

Question # 3 of 10 ( Start time: 02:10:29


Total Marks: 1
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Memory is arranged in

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linear fashion

two-dimensional manner
three-dimensional manner

randome fashion

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87
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Question # 5 of 10 ( Start time: 02:12:17


Total Marks: 1
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Which of the following is the drawback of DRAM?

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Ri8 Discharging of the capacitor over a period of time.

All the information stored in terms of binary bits wou

extra circuitry is required to refresh the capacitor

All of the above are true

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87
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Quiz Start Time: 02:08 AM s)

Question # 6 of 10 ( Start time: 02:13:44


Total Marks: 1
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With a 100 KHz clock frequency, eight bits can be serially entered into a shift register in
Select correct option:

80 micro seconds

8 micro seconds

80 mili seconds

10 micro seconds

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85
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Quiz Start Time: 02:08 AM
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Question # 7 of 10 ( Start time: 02:15:02


Total Marks: 1
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A multiplexer with a register circuit converts

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Serial data to parallel

Parallel data to serial

Serial data to serial


Parallel data to parallel

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87
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Question # 8 of 10 ( Start time: 02:16:13


Total Marks: 1
AM )
To serially shift a byte of data into a shift register, there must be

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one clock pulse

one load pulse

eight clock pulses

one clock pulse for each 1 in the data

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84
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Quiz Start Time: 02:08 AM s)

Question # 9 of 10 ( Start time: 02:17:36


Total Marks: 1
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when the transmission line is idle in an asynchronous transmission

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It is set to logic low


It is set to logic high

It remains in previous state

State of transmission line is not used to start transmi

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87
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Quiz Start Time: 02:08 AM s)

Question # 10 of 10 ( Start time:


Total Marks: 1
02:18:06 AM )
A divide-by-10 ring counter requires a minimum of

Select correct option:

ten flip-flops

five flip-flops

four flip-flops

twelve flip-flops

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