ASUS A8t.M

A
A8T/M SCHEMATIC R2.1

1
Content
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Content
PAGE
SYSTEM PAGE REF.
POWER PAGE REF.
AMD S1 CPU--HT
AMD S1 CPU--CNTL
AMD S1 CPU--DDR2
AMD S1 CPU--PWR/GND
DDR2 SO-DIMM_0
DDR2 SO-DIMM_1
DDR2 ADDRESS TERMINATION
C51M--HT TO CPU
C51M--HT TO MCP
C51M--PCI-E
C51M--CRT & LVDS
C51M--PWR/GND
VGA CONN
LVDS & INVERTER CONN
CRT & TV_OUT
MCP51--HT
MCP51--PCI
MCP51--IDE
MCP51--USB & HDA & GPIO
MCP51--PWR/GND
HDD & CD-ROM CONN
USB PORTS
SUPER I/O LPC47N217
BIOS & FIR
KBC 38857
SM BUS & POWER PORT
PCI-E--MINI CARD
PCI-E--NEW CARD
PCI--LAN RTL8110CL
RJ45 & RJ11
PCI--1394,CardReader R5C832
PCI--4 IN1 CON
AUDIO CODEC ALC660
AUDIO AMP G1420
MDC,B/T,TPM & DISCHG,HOLE
DVI CONN
ACIN, BAT, FAN, I/O PORT
SW & LED & TP
POWER-ON SEQUENCE
HISTORY
I/O PORT
61
62
63
64
65
66
67
68
69
70
71
72
POWER_VCORE
POWER_SYSTEM
POWER_I/O_1.2VO & 1.0VO
POWER_I/O_LDO
POWER_I/O_DDR2
POWER_VGA_CORE(Empty)
POWER_LOAD_SYSTEM
POWER_CHARGER
POWER_PIC
POWER_PROTECT
POWER_SWITCH_+5VLCM
POWER_DIAGRAM
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
Friday, July 21, 2006
OF
PAGE REF.
55
C
SCHEMATIC FILE NAME :
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
A8T/M AMD S1/C51MV BLOCK DIAGRAM

BATTERY
TYPE
IO PORT
3S2P
1394
USB
MIC
LINE_IN
40,44
AMD
638
POWER
SEQENCE
4,5,6,7
LFB
LVDS & INV

CON
17
LFB
VGA
CON
16
29
2
DDR2 533/667
SODIMM X2
CON
16
VGA BAORD
DDR2 SDRAM 533/667MHz
C51MV
11,12,13,14,15
+1.8V
+0.9V
DDR
CAP/RES
....
10
8,9
PCI EXPRESS X1
USB2.0
USB x5
MINI CARD
25
ACZ
38
ODD
(Secondary)
I/O LDO
64
31
3.3V, 33MHz
PCI_BUS
MCP51
PATA BUS
B/T
63
NEW
CARD
30
62
1.2VO & 1.0VO
24
Camera
+1.8V & +0.9V
19,20,21,22,23
HDD
(Primary) 24
4 IN 1
CARD
READER
38
65
LPC, 33MHz
1394
SLOT
36
68
SUPER I/O
47N217 26
KEYBOARD
CONTROLLER
M38857
28
TPM
FWH
BIOS
27
38
PIC
AUDIO AMP
G1420
37
69
PROTECT
FIR
70
27
LAN 1G
RICOH
R5C832
RTL8110SBL
34
32
LAN IO
Codec
ADI1986A
67
4
CHARGER
CARDBUS
35
LOAD SYSTEM
INTERNAL
KEYBOARD
MDC
CON
38
LINE
OUT 40
30
SWITCH 5VLCM
71
MIC AMP
LM358
DIAGRAM
SM_BUS
42
HT X8
61
SYSTEM
RESET
42
PCI-E
VGA x16
Nvidia
G7x series
DVI Dual
CH.
39
LFB
HT X16
CRT & TV
CON
18
VCORE
LFB
RJ11,RJ45
CON
33
4
40
SW & LED &

TOUCHPAD
CON
41
AC & BAT CON

FAN CTRL
40
DCIN
RTC
FAN CON.
40
H/W MONITOR
THERMAL
70
MIC_IN
5
37
72
33
40
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
OF
BLOCK DAIGRAM
55
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
PCI Device
Chipset (Host to PCI)
LAN -- Realtek
1394
4 IN 1
IDSEL#
REQ/GNT#
(AD30 internal)
AD17
0
0
A
B
AD16
MCP51_GPIO
Use As
GPI
GPIO_1
GPI
GPIO_2
GPIO_3
GPI
GPIO_4
GPIO_5
GPO
GPIO_6
GPO
GPO
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_[11:16]
GPIO_17
GPIO_18
GPIO_19
GPO
GPIO_20
GPIO_21
GPO
GPIO_22
GPIO_23
GPI
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPI
GPIO_32
GPIO_33
GPI
GPIO_34
GPIO_35
GPO
GPIO_36
GPIO_37
GPO
GPIO_38
GPO
GPIO_39
GPI
GPO
GPIO_40
GPIO_41
GPI
GPIO_42
GPIO_43
GPIO_44
GPIO_45
GPIO_46
GPO
Signal Name
PCB_ID2
KB_SCI#
PWRLMT#
SUS_STAT#
802_LED_EN#
MCP_TV_EN
CB_SD#
CR_VID0
CR_VID1
(CR_VID2)
(CPU_VID[0:5])
(LID#)
BATT_TALARM#
USB_OC#1
1 Hz
IGP_DDC_SELECT
ACZ_SDIN0_AUD
ACZ_SDIN1_MDC
CHG_FULL_OC
SMB_MEM_SCL
SMB_MEM_SDA
SMB_CLK_SB
SMB_DAT_SB
(SMB_ALERT#)
PCI_PME#
SIO_SMI#
EXTSMI#_3A
(RI#)
SUS_CLK
WLAN_ON#
OP_SD#
MXM_PWR_ON
VGA_DETECT#
BACK_OFF#
VGA_PWRGD
PM_CLKRUN#
PCI_PERR#
ACZ_SYNC
ACZ_SDOUT
BT_ON/OFF#
Interrupts
n/a
1
MCP51_GPIO
GPIO_47
GPIO_48
GPIO_49
GPIO_50
GPIO_51
GPIO_52
GPIO_53
GPIO_54
GPIO_55
GPIO_56
GPIO_57
GPIO_58
GPIO_59
GPIO_60
GPIO_61
GPIO_62
GPIO_63
GPIO_64
Power
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
PC/PCI
Use As
GPI
SM_BUS ADDRESS : Thermal MAX6657 = 1001100x

DDR_SODIMM0
= 1010000x
DDR_SODIMM1
= 1010001x
Signal Name
LOAD_TEST
GPO
GPO
GPO
Power
+3VS
FWH_WP#
LCD_VDD_EN_GM
LCD_BACKEN_GM
EDID_CLK_C51M
EDID_DATA_C51M
GPU_ON
HA20GATE
KBDCPURST
SATA_LED#
CPU_THERMTRIP#
PM_THERM#
PCB_ID0
PCB_ID1
IGP_SELECT
(CABLE_DET_P)
(CABLE_DET_S)
GPO
GPI
GPI
GPO
47N217_GPIO USE_AS
GPIO10
GPI
GPIO[11:12] GPO
GPIO[13:14] GPI
GPIO23
GPO
GPIO[40:45] GPI
GPIO46
GPI
GPIO47
GPI
SIGNAL_NAME
M38857_GPIO USE_AS
P23
GPO
P22
GPO
P21
GPO
P20
GPO
P42
GPO
P43
GPI
P44
GPO
P45
GPO
P46
GPO
P47
GPI
P50
GPI
P51
GPI
P52
GPO
P53
GPO
P54
GPI
P55
GPI
P56
GPO
P57
GPO
P67
GPI
P66
GPI
P65
GPI
P64
GPI
P63
GPI
P62
GPI
P61
GPI
P60
GPI
P76
GPIO
P77
GPIO
P27
GPO
P26
GPO
P25
GPO
P24
GPO
P40
GPO
P41
GPO
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Power
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
( 98h )
( A0h )
( A2h )
SIGNAL_NAME
MSK_INSTKEY#
BAT_LEARN
Power
+3V
+3V
+3V
KBCRSM
+3V
WATCHDOG
+3V
+3V
SWDJ_EN
KBCPURST_3Q
+3V
KBC_GA20
+3V
KBSCI_3Q
+3V
PM_CLKRUN#
+3V
BAT_LLOW#_OC +3V
FAN1_TACH
+3V
+3V
KBDDT0
KBDDT1
+3V
LID_KBC#
+3V
BAT_IN_OC#
+3V
FAN1_DC
+3V
ADJ_BL
+3V
NEWCARD_OFF# +3V
PANLOCK_#
+3V
MARATHON_#
+3V
ACIN_OC#
+3V
NEWCARD_DET# +3V
WIRELESS_#
+3V
INTERNET_#
+3V
BLUETOOTH_#
+3V
SMD_BAT
+3V
SMC_BAT
+3V
SCR_LED#
+3V
NUM_LED#
+3V
CAP_LED#
+3V
SET_PCIRSTNS# +3V
KBC_EXTSMI
+3V
PANLOCK_LED
+3V
REVISION
2.1
DATE:
SHEET
B
<Core Design>
PROJECT: A8T
DESCRIPTION:
OF
SCHEMATICS REF.
55
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
U1A
11
11
11
11
J5
K5
J3
J2
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
Y4
Y3
Y1
W1
HT_TXCTL
HT_TXCTL#
P3
P4
N1
P1
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
T5
R5
R2
R3
HTCPU_TXDP15
HTCPU_TXDN15
HTCPU_TXDP14
HTCPU_TXDN14
HTCPU_TXDP13
HTCPU_TXDN13
HTCPU_TXDP12
HTCPU_TXDN12
HTCPU_TXDP11
HTCPU_TXDN11
HTCPU_TXDP10
HTCPU_TXDN10
HTCPU_TXDP9
HTCPU_TXDN9
HTCPU_TXDP8
HTCPU_TXDN8
N5
P5
M3
M4
L5
M5
K3
K4
H3
H4
G5
H5
F3
F4
E5
F5
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
HTCPU_TXDP7
HTCPU_TXDN7
HTCPU_TXDP6
HTCPU_TXDN6
HTCPU_TXDP5
HTCPU_TXDN5
HTCPU_TXDP4
HTCPU_TXDN4
HTCPU_TXDP3
HTCPU_TXDN3
HTCPU_TXDP2
HTCPU_TXDN2
HTCPU_TXDP1
HTCPU_TXDN1
HTCPU_TXDP0
HTCPU_TXDN0
N3
N2
L1
M1
L3
L2
J1
K1
G1
H1
G3
G2
E1
F1
E3
E2
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
HTCPU_TXCLK1
HTCPU_TXCLK1#
HTCPU_TXCLK0
HTCPU_TXCLK0#
11 HTCPU_TXCTL
11 HTCPU_TXCTL#
+1.2VS_HT
R772
49.9Ohm
HT_TXCTL
HT_TXCTL#
11 HTCPU_TXDP[0..15]
R773
49.9Ohm
11 HTCPU_TXDN[0..15]
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
HYPERTRANSPORT
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
HTCPU_RXCLK1 11
HTCPU_RXCLK1# 11
HTCPU_RXCLK0 11
HTCPU_RXCLK0# 11
1
1
T221
T222
HTCPU_RXCTL 11
HTCPU_RXCTL# 11
T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
HTCPU_RXDP15
HTCPU_RXDN15
HTCPU_RXDP14
HTCPU_RXDN14
HTCPU_RXDP13
HTCPU_RXDN13
HTCPU_RXDP12
HTCPU_RXDN12
HTCPU_RXDP11
HTCPU_RXDN11
HTCPU_RXDP10
HTCPU_RXDN10
HTCPU_RXDP9
HTCPU_RXDN9
HTCPU_RXDP8
HTCPU_RXDN8
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1
HTCPU_RXDP7
HTCPU_RXDN7
HTCPU_RXDP6
HTCPU_RXDN6
HTCPU_RXDP5
HTCPU_RXDN5
HTCPU_RXDP4
HTCPU_RXDN4
HTCPU_RXDP3
HTCPU_RXDN3
HTCPU_RXDP2
HTCPU_RXDN2
HTCPU_RXDP1
HTCPU_RXDN1
HTCPU_RXDP0
HTCPU_RXDN0
HTCPU_RXDP[0..15] 11
HTCPU_RXDN[0..15] 11
SOCKET638
B
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
OF
S1 CPU HT
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
+2.5VS
L100
1
VDDA
2
C701
180NH
C702
C703
CE7
+3VS
4.7UF/6.3V 0.22UF/6.3V3300PF/25V
100UF/6.3V
U1D
R19
11
CLK_CPU
2
C704
11
CLK_CPU#
2
1
C705
3900PF/50V
R < 600 mils from CPU
AC caps < 1250 mils
1
3900PF/50V
1
R774
CLKIN
CLKIN#
2
169Ohm
CPU_PWRGD
CPU_STP#
CPU_RST#
1
R775
+1.8V
2
1KOhm
1 300Ohm 2
R777 T7128 1
+1.8V
R779
T7131
CPU_MVREF
R783
C706
2KOhm
0.1UF/16V
+1.8V
39.2Ohm
1
R781
1
R784
1
R785
1
R787
1
R788
1
R789
C707
1000PF/50V
A9
A8
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
AC6
CPU_PRESENT_L
AF4
AF5
SIC
SID
AF9
AD9
AC9
AA9
T228
E10
F6
E6
VTT_SENSE
CPU_MVREF
2 MEM_ZN
2 MEM_ZP
39.2Ohm
2
2510Ohm
2510Ohm
2300Ohm
300Ohm
Y10
W17
AE10
AF10
1
1
1
1
1
VID5
VID4
VID3
VID2
VID1
VID0
THERMTRIP_L
PROCHOT_L
TDI
TRST_L
TCK
TMS
TDO
VDD_FB_H
VDD_FB_L
DBRDY
PSI_L
M_VREF
M_ZN
M_ZP
D7
E7
F7
C7
AC8
TEST17
TEST16
TEST15
TEST14
TEST12
R20
0.1U
10K
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
R795
4.7KOhm
U2
1
2
3
4
H_THERMDA
H_THERMDC
+3VS
VCC
DXP
DXN
OVERT#
SCLK
SDA
ALERT#
GND
8
7
6
5
SCL_3S
16,29
SDA_3S 16,29
PM_THRM# 22
PM_THRM#
MAX6657MSA
C34
1000P
H_THRMTRIP#
H_PROCHOT#
AF6
AC7
AE9
T224
OTP_RESET# 42
Q102
2N7002
VDDIO_FB_H
VDDIO_FB_L
VTT_SENSE
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
A5
C6
A6
A4
C5
B5
C13
61
200
MISC
DBREQ_L
E9
E8
G9
H10
AA7
C2
C3
AA6
W7
W8
Y6
AB6
H_THERMDC
H_THERMDA
CPU_VID[0..5]
A7
F10
B7
1
1
1
1
T231
T233
T235
T236
T238
Place near CPU socket
VDDA1
VDDA2
T223
T225
T226
T227
61 CPU_VDD_FB
61 CPU_VDD_FB#
2KOhm
F8
F9
HTREF1
HTREF0
TEST29_H
TEST29_L
G10
W9
Y9
T229
20,31 PCIRST_NEWC#
CPU_VDDIO_FB 1
T7129
T7130
1
CPU_PSI# 61
+1.2VS_HT
A3
P6
R6
HT_REF1 1
HT_REF0R780
1
R782
C9
C8
FBCLKOUT
FBCLKOUT#
2
44.2Ohm
2
44.2Ohm
C
1
2
R786
80.6Ohm
< 1" from CPU
80 ohm diff impedence
+1.8VS
+3VS
+1.8V
R22
TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2
TEST24
TEST23
TEST22
TEST21
TEST20
AE7
AD7
AE8
AB8
AF7
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
J7
H8
AF8
AE6
K8
C4
1
1
1
1
R790 1
T230
T232
T234
2
300Ohm
T237
R23
R27
10KOhm
300Ohm
4.7KOhm
+1.8V
H_THRMTRIP#
1
R791
CPU_THRMTRIP# 19
Q1
PMBS3904
2
300Ohm
SOCKET638
+1.8VS
+1.8V
+2.5VS
+1.8V
R792
1
3
5
7
1KOhm
1KOhm
1KOhm
1KOhm
2 RN34A
4 RN34B
6 RN34C
8 RN34D
1
3
5
7
U52A
VCC
11 HTCPU_RST#
RN35A
300Ohm 2
RN35B
300Ohm 4
RN35C
300Ohm 6
RN35D
300Ohm 8
+1.8V
R794
For future processors
CPU_RST#
CPU_VID1
1
R793
10KOhm
300Ohm
2
300Ohm
H_PROCHOT#
GND
PROCHOT#
PROCHOT#
74LVC07AD
28
Q109
U52B
PMBS3904
VCC
11 HTCPU_PWRGD
CPU_PWRGD
+VCORE
R797
GND
74LVC07AD
CPU_VDD_FB
1
R798
1
R799
CPU_VDD_FB#
U52C
VCC
11 HTCPU_STP#
74LVC07AD
R21
Q3A
UM6K1N
Q3B
UM6K1N
R2.1
+3VSUS
U52D
PWRGD
22,68,71
+3VSUS
Q2B
UM6K1N
5
22,70
PWRLMT#
AMD circuit is 51 ohm

nVIDIA circuit is 10 ohm
GND
2
0Ohm
CPU_STP#
+5VO
1KOhm
2
51Ohm
2
51Ohm
U52E
VCC
C1
Q2A
UM6K1N
2
0.1UF/16V
U52F
VCC
11
GND
GND
74LVC07AD
VCC
10
74LVC07AD
13
12
GND
74LVC07AD
R1.1
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
OF
S1 CPU CNTL
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
M_A_DQ[0..63]
8 M_A_DQ[0..63]
M_B_DQ[0..63]
9 M_B_DQ[0..63]
U1B
U1C
Y16
AA16
E16
F16
8 M_CLK_DDR1
8 M_CLK_DDR#1
8 M_CLK_DDR0
8 M_CLK_DDR#0
8,10
8,10
8,10
8,10
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
M_A_CS#3
M_A_CS#2
M_A_CS#1
M_A_CS#0
V19
J22
V22
T19
MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0
8,10
8,10
M_ODT1
M_ODT0
V20
U19
MA0_ODT1
MA0_ODT0
8,10
8,10
8,10
M_A_CAS#
M_A_WE#
M_A_RAS#
U20
U21
T20
MA_CAS_L
MA_WE_L
MA_RAS_L
8,10
8,10
8,10
M_A_BS#2
M_A_BS#1
M_A_BS#0
K22
R20
T22
MA_BANK2
MA_BANK1
MA_BANK0
8,10
8,10
M_CKE1
M_CKE0
J20
J21
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
M_A_A15
M_A_A14
M_A_A13
M_A_A12
M_A_A11
M_A_A10
M_A_A9
M_A_A8
M_A_A7
M_A_A6
M_A_A5
M_A_A4
M_A_A3
M_A_A2
M_A_A1
M_A_A0
K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22
N22
N21
R21
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
M_A_DQS7
M_A_DQS#7
M_A_DQS6
M_A_DQS#6
M_A_DQS5
M_A_DQS#5
M_A_DQS4
M_A_DQS#4
M_A_DQS3
M_A_DQS#3
M_A_DQS2
M_A_DQS#2
M_A_DQS1
M_A_DQS#1
M_A_DQS0
M_A_DQS#0
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
8
8
8
8
8
8
8
8
M_A_DM7
M_A_DM6
M_A_DM5
M_A_DM4
M_A_DM3
M_A_DM2
M_A_DM1
M_A_DM0
Y13
AB16
Y19
AC24
F24
E19
C15
E12
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MEMORY
INTERFACE
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
M_A_DQ63
M_A_DQ62
M_A_DQ61
M_A_DQ60
M_A_DQ59
M_A_DQ58
M_A_DQ57
M_A_DQ56
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ49
M_A_DQ48
M_A_DQ47
M_A_DQ46
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ40
M_A_DQ39
M_A_DQ38
M_A_DQ37
M_A_DQ36
M_A_DQ35
M_A_DQ34
M_A_DQ33
M_A_DQ32
M_A_DQ31
M_A_DQ30
M_A_DQ29
M_A_DQ28
M_A_DQ27
M_A_DQ26
M_A_DQ25
M_A_DQ24
M_A_DQ23
M_A_DQ22
M_A_DQ21
M_A_DQ20
M_A_DQ19
M_A_DQ18
M_A_DQ17
M_A_DQ16
M_A_DQ15
M_A_DQ14
M_A_DQ13
M_A_DQ12
M_A_DQ11
M_A_DQ10
M_A_DQ9
M_A_DQ8
M_A_DQ7
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ0
9 M_CLK_DDR3
9 M_CLK_DDR#3
9 M_CLK_DDR2
9 M_CLK_DDR#2
AF18
AF17
A17
A18
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
9,10
9,10
9,10
9,10
M_B_CS#3
M_B_CS#2
M_B_CS#1
M_B_CS#0
Y26
J24
W24
U23
MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0
9,10
9,10
M_ODT3
M_ODT2
W23
W26
MB0_ODT1
MB0_ODT0
9,10
9,10
9,10
M_B_CAS#
M_B_WE#
M_B_RAS#
V26
U22
U24
MB_CAS_L
MB_WE_L
MB_RAS_L
9,10
9,10
9,10
M_B_BS#2
M_B_BS#1
M_B_BS#0
K26
T26
U26
MB_BANK2
MB_BANK1
MB_BANK0
9,10
9,10
M_CKE3
M_CKE2
H26
J23
MB_CKE1
MB_CKE0
9,10
9,10
9,10
9,10
9,10
9,10
9,10
9,10
9,10
9,10
9,10
9,10
9,10
9,10
9,10
9,10
M_B_A15
M_B_A14
M_B_A13
M_B_A12
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_A7
M_B_A6
M_B_A5
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
M_B_DQS7
M_B_DQS#7
M_B_DQS6
M_B_DQS#6
M_B_DQS5
M_B_DQS#5
M_B_DQS4
M_B_DQS#4
M_B_DQS3
M_B_DQS#3
M_B_DQS2
M_B_DQS#2
M_B_DQS1
M_B_DQS#1
M_B_DQS0
M_B_DQS#0
AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
F26
E26
A24
A23
D16
C16
C12
B12
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
9
9
9
9
9
9
9
9
M_B_DM7
M_B_DM6
M_B_DM5
M_B_DM4
M_B_DM3
M_B_DM2
M_B_DM1
M_B_DM0
AD12
AC16
AE22
AB26
E25
A22
B16
A12
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
SOCKET638
MEMORY
INTERFACE
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11
M_B_DQ63
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ59
M_B_DQ58
M_B_DQ57
M_B_DQ56
M_B_DQ55
M_B_DQ54
M_B_DQ53
M_B_DQ52
M_B_DQ51
M_B_DQ50
M_B_DQ49
M_B_DQ48
M_B_DQ47
M_B_DQ46
M_B_DQ45
M_B_DQ44
M_B_DQ43
M_B_DQ42
M_B_DQ41
M_B_DQ40
M_B_DQ39
M_B_DQ38
M_B_DQ37
M_B_DQ36
M_B_DQ35
M_B_DQ34
M_B_DQ33
M_B_DQ32
M_B_DQ31
M_B_DQ30
M_B_DQ29
M_B_DQ28
M_B_DQ27
M_B_DQ26
M_B_DQ25
M_B_DQ24
M_B_DQ23
M_B_DQ22
M_B_DQ21
M_B_DQ20
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQ15
M_B_DQ14
M_B_DQ13
M_B_DQ12
M_B_DQ11
M_B_DQ10
M_B_DQ9
M_B_DQ8
M_B_DQ7
M_B_DQ6
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ2
M_B_DQ1
M_B_DQ0
SOCKET638
M_CLK_DDR1
M_CLK_DDR3
C133
C756
1.5PF/50V
1.5PF/50V
M_CLK_DDR#1
M_CLK_DDR#3
M_CLK_DDR0
M_CLK_DDR2
C134
C757
1.5PF/50V
1.5PF/50V
M_CLK_DDR#0
M_CLK_DDR#2
<1200 mil from CPU
<1200 mil from CPU
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
OF
S1 CPU MEM
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
U1F
AC4
AD2
G4
H2
J9
J11
J13
K6
K10
K12
K14
L4
L7
L9
L11
L13
M2
M6
M8
M10
N7
N9
N11
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
V6
V8
V10
V12
V14
W4
Y2
+VCORE
C727
C728
C729
C730
C731
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
C737
C738
C741
C732
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
C740
C7114
C739
C6
180PF/50V 0.22UF/6.3V
0.01UF/25V
0.22UF/6.3V
Place under socket on bottom side
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
+1.2VS_HT
VDD
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
U1H
Place close to socket
C709
C710
C711
C712
C713
+0.9V
C720
C721
4.7UF/6.3V 4.7UF/6.3V
C733
C734
1000PF/50V1000PF/50V
C722
0.22UF/6.3V
0.22UF/6.3V
C735
C736
180PF/50V 180PF/50V
+1.8V
C743
C745
4.7UF/6.3V 4.7UF/6.3V
C746
C747
C748
C749
0.22UF/6.3V
0.22UF/6.3V0.22UF/6.3V
0.22UF/6.3V
C2
C3
C750
D4
D3
D2
D1
C714
4.7UF/6.3V 4.7UF/6.3V 0.22UF/6.3V

180PF/50V
0.22UF/6.3V
180PF/50V
C719
D10
C10
B10
AD10
W10
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
C751
0.01UF/25V 0.01UF/25V 180PF/50V 180PF/50V
SOCKET638
+1.8V
U1G
C752
+VCORE
J15
K16
L15
M16
P16
T16
U15
V16
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS130
VSS131
VSS132
VSS133
VDD
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
C753
C755
22UF/6.3V 22UF/6.3V 0.22UF/6.3V
VLDT_A4
VLDT_A3
VLDT_A2
VLDT_A1
VLDT_B4
VLDT_B3
VLDT_B2
VLDT_B1
VTT8
VTT7
VTT6
VTT5
VTT9
VTT4
VTT3
VTT2
VTT1
VDDIO23
VSS47
VDDIO1
VSS48
VDDIO2
VSS49
VDDIO3
VSS50
VDDIO4
VSS51
VDDIO5
VSS52
VDDIO6
VSS53
VDDIO7
VSS54
VDDIO8
VSS55
VDDIO9
VSS56
VDDIO10 I O
VSS57
VDDIO11 POWER VSS58
VDDIO12
VSS59
VDDIO13
VSS60
VDDIO14
VSS61
VDDIO15
VSS62
VDDIO16
VSS63
VDDIO17
VSS64
VDDIO18
VSS66
VDDIO19
VSS67
VDDIO20
VSS68
VDDIO21
VSS69
VDDIO22
VSS70
VDDIO24
VSS71
VDDIO25
VSS72
VDDIO26
VSS73
VDDIO27
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
AE5
AE4
AE3
AE2
2
1
C708 4.7UF/6.3V
+0.9V
AC10
AB10
AA10
A10
C715
C716
C717
C718
4.7UF/6.3V 4.7UF/6.3V 0.22UF/6.3V

0.22UF/6.3V
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
C723
C724
1000PF/50V1000PF/50V
C725
C726
180PF/50V 180PF/50V
SOCKET638
Place under socket on bottom side
U1E
P20
P19
N20
N19
RSVD_MA0_CLK_H3
RSVD_MA0_CLK_L3
RSVD_MA0_CLK_H0
RSVD_MA0_CLK_L0
RSVD_MA_RESET_L
RSVD_MB_RESET_L
B3
C1
RSVD_VDDNB_FB_H
RSVD_VDDNB_FB_L
RSVD_CORE_TYPE
H6
G6
D5
MISC
INTERNAL
R26
R25
P22
R22
H16
B18
RSVD_VIDSTRB1
RSVD_VIDSTRB0
RSVD_MB0_CLK_H3
RSVD_MB0_CLK_L3
RSVD_MB0_CLK_H0
RSVD_MB0_CLK_L0
FREE5
FREE6
FREE4
FREE1
FREE2
FREE3
R24
W18
R23
AA8
H18
H19
SOCKET638
SOCKET638
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
OF
S1 CPU PWR/GND
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
+1.8V
+3VS
M_A_DQ[0..63]
6 M_A_DQ[0..63]
+1.8V
+3VS
5,7,9,10,38,65
5,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
6,10 M_A_A[0..15]
CON2A
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
6,10
M_A_BS#2
6,10
M_A_BS#0
6,10
M_A_BS#1
6,10
M_A_CS#0
6,10
M_A_CS#1
6 M_CLK_DDR0
6 M_CLK_DDR#0
6 M_CLK_DDR1
6 M_CLK_DDR#1
6,10
M_CKE0
6,10
M_CKE1
6,10 M_A_CAS#
6,10 M_A_RAS#
6,10
M_A_WE#
9,22 SMB_MEM_SCL
9,22 SMB_MEM_SDA
6,10
M_ODT0
6,10
M_ODT1
6
M_A_DM[0..7]
6 M_A_DQS[0..7]
6 M_A_DQS#[0..7]
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
107
106
110
115
30
32
164
166
79
80
113
108
109
198
200
197
195
BA0
BA1
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
114
119
ODT0
ODT1
M_A_DM1
M_A_DM3
M_A_DM6
M_A_DM7
M_A_DM0
M_A_DM5
M_A_DM2
M_A_DM4
10
26
52
67
130
147
170
185
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_A_DQS1
M_A_DQS3
M_A_DQS6
M_A_DQS7
M_A_DQS0
M_A_DQS5
M_A_DQS2
M_A_DQS4
M_A_DQS#1
M_A_DQS#3
M_A_DQS#6
M_A_DQS#7
M_A_DQS#0
M_A_DQS#5
M_A_DQS#2
M_A_DQS#4
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
+1.8V
M_A_DQ9
M_A_DQ13
M_A_DQ15
M_A_DQ11
M_A_DQ8
M_A_DQ12
M_A_DQ10
M_A_DQ14
M_A_DQ30
M_A_DQ27
M_A_DQ25
M_A_DQ29
M_A_DQ24
M_A_DQ28
M_A_DQ26
M_A_DQ31
M_A_DQ51
M_A_DQ50
M_A_DQ54
M_A_DQ49
M_A_DQ55
M_A_DQ48
M_A_DQ52
M_A_DQ53
M_A_DQ57
M_A_DQ56
M_A_DQ60
M_A_DQ61
M_A_DQ58
M_A_DQ59
M_A_DQ62
M_A_DQ63
M_A_DQ6
M_A_DQ7
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ1
M_A_DQ0
M_A_DQ42
M_A_DQ47
M_A_DQ44
M_A_DQ40
M_A_DQ46
M_A_DQ43
M_A_DQ45
M_A_DQ41
M_A_DQ21
M_A_DQ17
M_A_DQ20
M_A_DQ19
M_A_DQ16
M_A_DQ22
M_A_DQ23
M_A_DQ18
M_A_DQ38
M_A_DQ36
M_A_DQ37
M_A_DQ32
M_A_DQ33
M_A_DQ39
M_A_DQ35
M_A_DQ34
CON2B
+3VS
C135
6,10
6,10
0.1U
M_A_CS#2
M_A_CS#3
VTT_REF
C136
112
111
117
96
95
118
81
82
87
103
88
104
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
199
VDDSPD
83
120
50
69
163
NC1
NC2
NC3
NC4
NCTEST
VREF
201
202
GND0
GND1
203
204
NP_NC1
NP_NC2
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
0.1U
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
DDR_DIMM_200P
Layout Note: Place these Caps near SO DIMM 0
+1.8V
C137
C138
C139
C140
0.1U
0.1U
0.1U
0.1U
DDR_DIMM_200P
+1.8V
C141
C142
C143
C144
C145
1U/6.3V
1U/6.3V
1U/6.3V
1U/6.3V
1U/6.3V
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
OF
DDR2 SO-DIMM0
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
+1.8V
+3VS
+5V
M_B_DQ[0..63]
6 M_B_DQ[0..63]
+1.8V
+3VS
+5V
5,7,8,10,38,65
5,8,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
16,18,25,28,31,38,40,41
6,10 M_B_A[0..15]
CON1A
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
6,10
+3VS
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
107
106
110
115
30
32
164
166
79
80
113
108
109
198
200
197
195
BA0
BA1
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
114
119
ODT0
ODT1
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DM4
M_B_DM3
M_B_DM2
M_B_DM0
M_B_DM1
10
26
52
67
130
147
170
185
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS4
M_B_DQS3
M_B_DQS2
M_B_DQS0
M_B_DQS1
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS#4
M_B_DQS#3
M_B_DQS#2
M_B_DQS#0
M_B_DQS#1
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
M_B_BS#2
6,10
M_B_BS#0
6,10
M_B_BS#1
6,10
M_B_CS#0
6,10
M_B_CS#1
6 M_CLK_DDR3
6 M_CLK_DDR#3
6 M_CLK_DDR2
6 M_CLK_DDR#2
6,10
M_CKE2
6,10
M_CKE3
6,10 M_B_CAS#
6,10 M_B_RAS#
6,10
M_B_WE#
8,22 SMB_MEM_SCL
8,22 SMB_MEM_SDA
6,10
M_ODT2
6,10
M_ODT3
6 M_B_DM[0..7]
6 M_B_DQS[0..7]
6 M_B_DQS#[0..7]
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
M_B_DQ43
M_B_DQ42
M_B_DQ46
M_B_DQ47
M_B_DQ41
M_B_DQ45
M_B_DQ44
M_B_DQ40
M_B_DQ48
M_B_DQ53
M_B_DQ55
M_B_DQ54
M_B_DQ49
M_B_DQ52
M_B_DQ51
M_B_DQ50
M_B_DQ58
M_B_DQ63
M_B_DQ56
M_B_DQ57
M_B_DQ62
M_B_DQ59
M_B_DQ61
M_B_DQ60
M_B_DQ35
M_B_DQ39
M_B_DQ37
M_B_DQ36
M_B_DQ38
M_B_DQ34
M_B_DQ33
M_B_DQ32
M_B_DQ30
M_B_DQ31
M_B_DQ29
M_B_DQ24
M_B_DQ26
M_B_DQ27
M_B_DQ25
M_B_DQ28
M_B_DQ18
M_B_DQ22
M_B_DQ20
M_B_DQ21
M_B_DQ19
M_B_DQ23
M_B_DQ17
M_B_DQ16
M_B_DQ0
M_B_DQ1
M_B_DQ7
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ2
M_B_DQ9
M_B_DQ8
M_B_DQ13
M_B_DQ12
M_B_DQ11
M_B_DQ14
M_B_DQ15
M_B_DQ10
+1.8V
CON1B
112
111
117
96
95
118
81
82
87
103
88
104
+3VS
199
C148
0.1U
6,10
6,10
83
120
50
69
163
M_B_CS#2
M_B_CS#3
VTT_REF
C149
C150
1U/6.3V_* 0.1U
+1.8V
NC1
NC2
NC3
NC4
NCTEST
VREF
201
202
GND0
GND1
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VDDSPD
203
204
Layout Note: Place these Caps near SO DIMM 1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
NP_NC1
NP_NC2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
DDR2_DIMM_200P
C151
C152
C153
C154
0.1U
0.1U
0.1U
0.1U
+1.8V
DDR2_DIMM_200P
+5V
+1.8V
C160
+5V
R156
C155
C156
C157
C158
C159
1U/6.3V
1U/6.3V
1U/6.3V
1U/6.3V
1U/6.3V
VTT_REF
0.1U
10K_1
C161
0.01U/X7R
R157
U5
V+
T21
4
VLMV321IDBVR
C166
C758
1U/6.3V
1000PF/50V
10K_1
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
OF
DDR2 SO-DIMM1
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
+0.9V
+0.9V
7,48,65
+0.9V
+0.9V
C167
C168
C169
C170
C171
C172
C173
C174
C175
C176
C177
C178
C179
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
R158
R159
47
47
M_CKE0
M_CKE1
R168
R184
R185
R187
47
47
47
47
M_A_BS#2
M_A_A4
M_A_A14
M_A_A15
+0.9V
+1.8V
C180
C182
C183
C184
C185
C187
C188
C189
C190
C191
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
M_ODT3
M_A_CS#3
M_ODT0
M_ODT1
M_A_CS#1
M_A_CS#0
47
47
47
47
47
47
47
47
1
3
5
7
47OHM
47OHM
47OHM
47OHM
1
2
3
4
5
6
7
8
47
47
47
47
47
47
47
47
16
15
14
13
12
11
10
9
RN4A
RN4B
RN4C
RN4D
RN4E
RN4F
RN4G
RN4H
M_A_A9
M_A_CS#2
M_A_A12
M_A_A3
M_A_A1
M_A_A5
M_A_A8
M_A_A2
1
2
3
4
5
6
7
8
47
47
47
47
47
47
47
47
16
15
14
13
12
11
10
9
RN7A
RN7B
RN7C
RN7D
RN7E
RN7F
RN7G
RN7H
M_A_A0
M_A_A11
M_A_A7
M_A_A6
M_A_BS#0
M_A_WE#
M_B_CS#2
M_CKE2
1
2
3
4
5
6
7
8
47
47
47
47
47
47
47
47
16
15
14
13
12
11
10
9
RN2A
RN2B
RN2C
RN2D
RN2E
RN2F
RN2G
RN2H
M_B_BS#2
M_B_A9
M_B_CS#1
1
2
3
4
5
6
7
8
47
47
47
47
47
47
47
47
16
15
14
13
12
11
10
9
RN6A
RN6B
RN6C
RN6D
RN6E
RN6F
RN6G
RN6H
M_CKE3
M_B_A12
M_B_A15
M_B_A11
M_B_A7
M_B_A5
M_B_A8
M_B_A4
1
2
3
4
5
6
7
8
47
47
47
47
47
47
47
47
16
15
14
13
12
11
10
9
RN5A
RN5B
RN5C
RN5D
RN5E
RN5F
RN5G
RN5H
Layout note: Place one cap close to every 2 pullup resistors terminated to +0.9V
1
3
5
7
16
15
14
13
12
11
10
9
RN9A
RN9B
RN9C
RN9D
RN9E
RN9F
RN9G
RN9H
1
2
3
4
5
6
7
8
2
4
6
8
M_A_BS#1
M_A_A13
M_A_A10
RN10A
RN10B
RN10C
RN10D
M_B_A10
M_B_BS#0
M_B_A14
M_B_A3
M_B_A6
M_B_A1
M_B_A0
M_B_A2
M_B_CS#0
M_ODT2
M_B_A13
M_B_CS#3
RN3A
47OHM 2
RN3B
47OHM 4
RN3C
47OHM 6
RN3D
47OHM 8
M_CKE0
M_CKE1
6,8
6,8
M_A_BS#2 6,8
M_A_A4
6,8
M_A_A14 6,8
M_A_A15 6,8
M_ODT3 6,9
M_A_CS#3 6,8
M_ODT0 6,8
M_ODT1 6,8
M_A_CS#1 6,8
M_A_CS#0 6,8
M_A_CAS# 6,8
M_A_RAS# 6,8
M_A_BS#1 6,8
M_A_A13 6,8
M_A_A10 6,8
M_A_A9
6,8
M_A_CS#2 6,8
M_A_A12 6,8
M_A_A3
6,8
M_A_A1
6,8
M_A_A5
6,8
M_A_A8
6,8
M_A_A2
6,8
M_A_A0
6,8
M_A_A11 6,8
M_A_A7
6,8
M_A_A6
6,8
M_A_BS#0 6,8
M_A_WE# 6,8
M_B_CS#2 6,9
M_CKE2 6,9
M_B_BS#2 6,9
M_B_A9
6,9
M_B_CS#1 6,9
M_B_CAS# 6,9
M_B_WE# 6,9
M_B_A10 6,9
M_B_BS#0 6,9
M_B_A14 6,9
B
M_CKE3
M_B_A12
M_B_A15
M_B_A11
M_B_A7
M_B_A5
M_B_A8
M_B_A4
6,9
6,9
6,9
6,9
6,9
6,9
6,9
6,9
M_B_A3
6,9
M_B_A6
6,9
M_B_A1
6,9
M_B_A0
6,9
M_B_A2
6,9
M_B_RAS# 6,9
M_B_BS#1 6,9
M_B_CS#0 6,9
M_ODT2 6,9
M_B_A13 6,9
M_B_CS#3 6,9
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
10
OF
55
DDR2 ADDRESS TERMINATION

3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
U4A
4 HTCPU_RXDP[0..15]
HTCPU_TXDP[0..15] 4
HTCPU_RXDP0
HTCPU_RXDP1
HTCPU_RXDP2
HTCPU_RXDP3
HTCPU_RXDP4
HTCPU_RXDP5
HTCPU_RXDP6
HTCPU_RXDP7
HTCPU_RXDP8
HTCPU_RXDP9
HTCPU_RXDP10
HTCPU_RXDP11
HTCPU_RXDP12
HTCPU_RXDP13
HTCPU_RXDP14
HTCPU_RXDP15
Y23
W24
V24
U22
R24
P24
P22
N22
Y21
V21
W21
T21
R18
P16
N20
M17
HT_CPU_RXD0_P
HT_CPU_RXD1_P
HT_CPU_RXD2_P
HT_CPU_RXD3_P
HT_CPU_RXD4_P
HT_CPU_RXD5_P
HT_CPU_RXD6_P
HT_CPU_RXD7_P
HT_CPU_RXD8_P
HT_CPU_RXD9_P
HT_CPU_RXD10_P
HT_CPU_RXD11_P
HT_CPU_RXD12_P
HT_CPU_RXD13_P
HT_CPU_RXD14_P
HT_CPU_RXD15_P
HT_CPU_TXD0_P
HT_CPU_TXD1_P
HT_CPU_TXD2_P
HT_CPU_TXD3_P
HT_CPU_TXD4_P
HT_CPU_TXD5_P
HT_CPU_TXD6_P
HT_CPU_TXD7_P
HT_CPU_TXD8_P
HT_CPU_TXD9_P
HT_CPU_TXD10_P
HT_CPU_TXD11_P
HT_CPU_TXD12_P
HT_CPU_TXD13_P
HT_CPU_TXD14_P
HT_CPU_TXD15_P
C23
D23
E22
F23
H22
J21
K21
K23
D21
F19
F21
G20
J19
L17
L20
L18
HTCPU_TXDP0
HTCPU_TXDP1
HTCPU_TXDP2
HTCPU_TXDP3
HTCPU_TXDP4
HTCPU_TXDP5
HTCPU_TXDP6
HTCPU_TXDP7
HTCPU_TXDP8
HTCPU_TXDP9
HTCPU_TXDP10
HTCPU_TXDP11
HTCPU_TXDP12
HTCPU_TXDP13
HTCPU_TXDP14
HTCPU_TXDP15
HTCPU_RXDN0
HTCPU_RXDN1
HTCPU_RXDN2
HTCPU_RXDN3
HTCPU_RXDN4
HTCPU_RXDN5
HTCPU_RXDN6
HTCPU_RXDN7
HTCPU_RXDN8
HTCPU_RXDN9
HTCPU_RXDN10
HTCPU_RXDN11
HTCPU_RXDN12
HTCPU_RXDN13
HTCPU_RXDN14
HTCPU_RXDN15
Y22
W23
V23
U21
R23
P23
P21
N21
Y20
W20
W22
U20
R19
P17
N19
N18
HT_CPU_RXD0_N
HT_CPU_RXD1_N
HT_CPU_RXD2_N
HT_CPU_RXD3_N
HT_CPU_RXD4_N
HT_CPU_RXD5_N
HT_CPU_RXD6_N
HT_CPU_RXD7_N
HT_CPU_RXD8_N
HT_CPU_RXD9_N
HT_CPU_RXD10_N
HT_CPU_RXD11_N
HT_CPU_RXD12_N
HT_CPU_RXD13_N
HT_CPU_RXD14_N
HT_CPU_RXD15_N
HT_CPU_TXD0_N
HT_CPU_TXD1_N
HT_CPU_TXD2_N
HT_CPU_TXD3_N
HT_CPU_TXD4_N
HT_CPU_TXD5_N
HT_CPU_TXD6_N
HT_CPU_TXD7_N
HT_CPU_TXD8_N
HT_CPU_TXD9_N
HT_CPU_TXD10_N
HT_CPU_TXD11_N
HT_CPU_TXD12_N
HT_CPU_TXD13_N
HT_CPU_TXD14_N
HT_CPU_TXD15_N
C24
D24
E23
F24
H23
J22
K22
K24
D22
E20
E21
G19
J18
K17
K19
L19
HTCPU_TXDN0
HTCPU_TXDN1
HTCPU_TXDN2
HTCPU_TXDN3
HTCPU_TXDN4
HTCPU_TXDN5
HTCPU_TXDN6
HTCPU_TXDN7
HTCPU_TXDN8
HTCPU_TXDN9
HTCPU_TXDN10
HTCPU_TXDN11
HTCPU_TXDN12
HTCPU_TXDN13
HTCPU_TXDN14
HTCPU_TXDN15
T23
T22
R21
R20
HT_CPU_RX_CLK0_P
HT_CPU_RX_CLK0_N
HT_CPU_RX_CLK1_P
HT_CPU_RX_CLK1_N
HT_CPU_TX_CLK0_P
HT_CPU_TX_CLK0_N
HT_CPU_TX_CLK1_P
HT_CPU_TX_CLK1_N
G23
G24
G22
G21
HTCPU_TXCLK0 4
HTCPU_TXCLK0# 4
HTCPU_TXCLK1 4
HTCPU_TXCLK1# 4
M23
M22
HT_CPU_RXCTL_P
HT_CPU_RXCTL_N
HT_CPU_TXCTL_P
HT_CPU_TXCTL_N
L23
L24
HTCPU_TXCTL 4
HTCPU_TXCTL# 4
CLKOUT_PRI_200MHZ_P
CLKOUT_PRI_200MHZ_N
CLKOUT_SEC_200MHZ_P
CLKOUT_SEC_200MHZ_N
B24
B23
A22
B21
4 HTCPU_RXDN[0..15]
HTCPU_TXDN[0..15] 4
4
4
4
4
HTCPU_RXCLK0
HTCPU_RXCLK0#
HTCPU_RXCLK1
HTCPU_RXCLK1#
4 HTCPU_RXCTL
4 HTCPU_RXCTL#
+1.2VS_HT
< 500 mil; 5/10
HTCPUCA_1P2V
1
2
HTCPUCA_GND
R800
150Ohm
1
2
R801
150Ohm
+1.2VS
W19
Y19
N16
L101
1
+1.2VS_PLLHT
T13
120Ohm/100Mhz
C759
C760
1UF/10V
0.1UF/16V
HT_CPU_CAL_1P2V
HT_CPU_CAL_GND
HT_CPU_REQ*
HT_CPU_STOP*
HT_CPU_RESET*
HT_CPU_PWRGD
1
1
CLK_CPU 5
CLK_CPU# 5
T239
T240
+2.5VS
Int. PU
F18 HTCPU_REQ# 1
R802
G18
D20
E19
1.5" ~ 7"
2
22kOhm_*
HTCPU_STP# 5
HTCPU_RST# 5
HTCPU_PWRGD 5
breakout: 5/5
normal: 5/10
+2.5VS
+1.2V_PLLHTCPU
L102
+1.2V_PLLHTMCP
+2.5V_PLLHTCPU
L16
+2.5VS_PLLHT
2
B
120Ohm/100Mhz
C51MV
C761
C762
1UF/10V
0.1UF/16V
Near BGA
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
11
OF
C51M HT
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
U4B
19 HTMCP_RXDP[0..7]
HTMCP_TXDP[0..7] 19
HTMCP_RXDP0
HTMCP_RXDP1
HTMCP_RXDP2
HTMCP_RXDP3
HTMCP_RXDP4
HTMCP_RXDP5
HTMCP_RXDP6
HTMCP_RXDP7
AD6
AC7
AA8
AA9
AD10
AD11
AC12
AC13
AA6
W7
Y8
V9
Y10
AA11
V11
W12
HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_RXD8_P
HT_MCP_RXD9_P
HT_MCP_RXD10_P
HT_MCP_RXD11_P
HT_MCP_RXD12_P
HT_MCP_RXD13_P
HT_MCP_RXD14_P
HT_MCP_RXD15_P
HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD8_P
HT_MCP_TXD9_P
HT_MCP_TXD10_P
HT_MCP_TXD11_P
HT_MCP_TXD12_P
HT_MCP_TXD13_P
HT_MCP_TXD14_P
HT_MCP_TXD15_P
AC24
AD23
AC22
AC20
AB18
AA17
AB16
AC16
AB21
AB20
AB19
W18
W15
AA15
Y14
W13
HTMCP_TXDP0
HTMCP_TXDP1
HTMCP_TXDP2
HTMCP_TXDP3
HTMCP_TXDP4
HTMCP_TXDP5
HTMCP_TXDP6
HTMCP_TXDP7
HTMCP_RXDN0
HTMCP_RXDN1
HTMCP_RXDN2
HTMCP_RXDN3
HTMCP_RXDN4
HTMCP_RXDN5
HTMCP_RXDN6
HTMCP_RXDN7
AC6
AB7
AB8
AB9
AC10
AC11
AB12
AB13
Y6
Y7
AA7
W9
W10
Y12
W11
V13
HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_RXD8_N
HT_MCP_RXD9_N
HT_MCP_RXD10_N
HT_MCP_RXD11_N
HT_MCP_RXD12_N
HT_MCP_RXD13_N
HT_MCP_RXD14_N
HT_MCP_RXD15_N
HT_MCP_TXD0_N
HT_MCP_TXD1_N
HT_MCP_TXD2_N
HT_MCP_TXD3_N
HT_MCP_TXD4_N
HT_MCP_TXD5_N
HT_MCP_TXD6_N
HT_MCP_TXD7_N
HT_MCP_TXD8_N
HT_MCP_TXD9_N
HT_MCP_TXD10_N
HT_MCP_TXD11_N
HT_MCP_TXD12_N
HT_MCP_TXD13_N
HT_MCP_TXD14_N
HT_MCP_TXD15_N
AC23
AD22
AC21
AD20
AC18
AB17
AB15
AD16
AB22
AA20
AA19
V17
V15
Y15
W14
Y13
HTMCP_TXDN0
HTMCP_TXDN1
HTMCP_TXDN2
HTMCP_TXDN3
HTMCP_TXDN4
HTMCP_TXDN5
HTMCP_TXDN6
HTMCP_TXDN7
HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N
AC19
AD19
Y17
W17
HT_MCP_TXCTL_P
HT_MCP_TXCTL_N
AC15
AD15
19 HTMCP_RXDN[0..7]
HTMCP_TXDN[0..7] 19
AD9
AC9
U10
T10
19 HTMCP_RXCLK0
19 HTMCP_RXCLK0#
AD14
AC14
19 HTMCP_RXCTL
19 HTMCP_RXCTL#
breakout: 5/5
normal: 5/10
OD
19 HTMCP_REQ#
19 HTMCP_STP#
19 HTMCP_RST#
19 HTMCP_PWRGD
1.5" ~ 7"
1.5" ~ 7"
OD
AB5
AA5
AC5
AD5
HT_MCP_RX_CLK0_P
HT_MCP_RX_CLK0_N
HT_MCP_RX_CLK1_P
HT_MCP_RX_CLK1_N
HT_MCP_RXCTL_P
HT_MCP_RXCTL_N
HT_MCP_REQ*
HT_MCP_STOP*
HT_MCP_RESET*
HT_MCP_PWRGD
CLKOUT_CTERM_GND
SCLKIN_MCLKOUT_200MHZ_P
SCLKIN_MCLKOUT_200MHZ_N
19
CLK_25M
19
19
CLK_NBHT
CLK_NBHT#
AC4
Y5
W5
1
1
HTMCP_TXCLK0 19
HTMCP_TXCLK0# 19
T241
T242
HTMCP_TXCTL 19
HTMCP_TXCTL# 19
B22 CLKOUT_CTERM_GND
1
R805
2
2.37KOhm
A20
B20
CLKIN_25MHZ
CLKIN_200MHZ_P
CLKIN_200MHZ_N
+1.2VS
HT_MCP_CAL_1P2V
HT_MCP_CAL_GND
AB23
AB24
< 500 mil; 5/5/10

HTMCPCA_1P2V
1
2
HTMCPCA_GND R806
150Ohm
1
2
R807
150Ohm
C51MV
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
12
OF
C51M HT TO MCP
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
U4C
16 EXP_RXP[0..15]
EXP_TXP[0..15] 16
EXP_RXP15
EXP_RXP14
EXP_RXP13
EXP_RXP12
EXP_RXP11
EXP_RXP10
EXP_RXP9
EXP_RXP8
EXP_RXP7
EXP_RXP6
EXP_RXP5
EXP_RXP4
EXP_RXP3
EXP_RXP2
EXP_RXP1
EXP_RXP0
J8
J6
K9
L6
L7
M9
N8
N6
R6
P3
R8
U6
T8
U7
V4
Y3
PE0_RX0_P
PE0_RX1_P
PE0_RX2_P
PE0_RX3_P
PE0_RX4_P
PE0_RX5_P
PE0_RX6_P
PE0_RX7_P
PE0_RX8_P
PE0_RX9_P
PE0_RX10_P
PE0_RX11_P
PE0_RX12_P
PE0_RX13_P
PE0_RX14_P
PE0_RX15_P
PE0_TX0_P
PE0_TX1_P
PE0_TX2_P
PE0_TX3_P
PE0_TX4_P
PE0_TX5_P
PE0_TX6_P
PE0_TX7_P
PE0_TX8_P
PE0_TX9_P
PE0_TX10_P
PE0_TX11_P
PE0_TX12_P
PE0_TX13_P
PE0_TX14_P
PE0_TX15_P
L1
L3
L4
M4
P1
R1
R3
R4
U4
V1
W1
W3
AA1
AB1
AC1
AD2
EXP_TXP15
EXP_TXP14
EXP_TXP13
EXP_TXP12
EXP_TXP11
EXP_TXP10
EXP_TXP9
EXP_TXP8
EXP_TXP7
EXP_TXP6
EXP_TXP5
EXP_TXP4
EXP_TXP3
EXP_TXP2
EXP_TXP1
EXP_TXP0
EXP_RXN15
EXP_RXN14
EXP_RXN13
EXP_RXN12
EXP_RXN11
EXP_RXN10
EXP_RXN9
EXP_RXN8
EXP_RXN7
EXP_RXN6
EXP_RXN5
EXP_RXN4
EXP_RXN3
EXP_RXN2
EXP_RXN1
EXP_RXN0
J7
J5
J9
L5
L8
M8
N7
N5
R5
P4
R7
U5
T9
U8
V3
AA3
PE0_RX0_N
PE0_RX1_N
PE0_RX2_N
PE0_RX3_N
PE0_RX4_N
PE0_RX5_N
PE0_RX6_N
PE0_RX7_N
PE0_RX8_N
PE0_RX9_N
PE0_RX10_N
PE0_RX11_N
PE0_RX12_N
PE0_RX13_N
PE0_RX14_N
PE0_RX15_N
PE0_TX0_N
PE0_TX1_N
PE0_TX2_N
PE0_TX3_N
PE0_TX4_N
PE0_TX5_N
PE0_TX6_N
PE0_TX7_N
PE0_TX8_N
PE0_TX9_N
PE0_TX10_N
PE0_TX11_N
PE0_TX12_N
PE0_TX13_N
PE0_TX14_N
PE0_TX15_N
L2
M2
M3
N3
P2
R2
T2
T3
U3
V2
W2
Y2
AA2
AB2
AC2
AD3
EXP_TXN15
EXP_TXN14
EXP_TXN13
EXP_TXN12
EXP_TXN11
EXP_TXN10
EXP_TXN9
EXP_TXN8
EXP_TXN7
EXP_TXN6
EXP_TXN5
EXP_TXN4
EXP_TXN3
EXP_TXN2
EXP_TXN1
EXP_TXN0
PE0_PRSNT*
PE0_REFCLK_P
PE0_REFCLK_N
K1
K2
PE1_TX_P
PE1_TX_N
G4
G5
PE1_REFCLK_P
PE1_REFCLK_N
G2
G3
16 EXP_RXN[0..15]
EXP_TXN[0..15] 16
+3VS
R808
16,20
GPU_ON
16,20 VGA_DETECT#
1
R7141
2
0Ohm_*
1
R7140
2
0Ohm
10KOhm
D1
30 PCIE_RXP1_MINICARD
30 PCIE_RXN1_MINICARD
G6
H6
PE1_RX_P
PE1_RX_N
E2
PE1_PRSNT*
+3VS
R7133
31 PCIE_RXP2_NEWCARD
31 PCIE_RXN2_NEWCARD
J4
K3
31 PRSNT_NEWCARD#
E3
PE2_PRSNT*
30 CLK_REQ_MINICARD#
31 CLK_REQ_NEWCARD#
D3
E4
PE1_CLKREQ*/CLK
PE2_CLKREQ*/DATA
PE2_RX_P
PE2_RX_N
PE2_TX_P
PE2_TX_N
H4
J3
PE2_REFCLK_P
PE2_REFCLK_N
H2
H3
PE_TSTCLK_P
PE_TSTCLK_N
F1
F2
CLK_PCIE_VGA 16
CLK_PCIE_VGA# 16
PCIE_TXP1 2
10.1UF/10V
PCIE_TXN1 C763 2
1
C764 0.1UF/10V
PCIE_TXP1_MINICARD 30
PCIE_TXN1_MINICARD 30
CLK_PCIE_MINICARD 30
CLK_PCIE_MINICARD# 30
PCIE_TXP2 2
10.1UF/10V
PCIE_TXN2 C765 2
1
C766 0.1UF/10V
PCIE_TXP2_NEWCARD 31
PCIE_TXN2_NEWCARD 31
CLK_PCIE_NEWCARD 31
CLK_PCIE_NEWCARD# 31
10KOhm_*
PRSNT_NEWCARD#
AC3
AB3
PE_REFCLKIN_P
PE_REFCLKIN_N
PE_RESET*
1
R809
2
100Ohm_*
G1
PE_RST# 16,30
+1.2VS
L103
+1.2VS_PLLPE
T11
+1.2V_PLLPE
120Ohm/100Mhz
C767
PE_CTERM_GND
D2
1
R810
2
2.37KOhm
C51MV
C768
1UF/16V_* 0.1UF/16V
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
13
OF
C51M PCI-E
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
U4D
DAC_R_C51M
DAC_G_C51M
DAC_B_C51M
R813
R814
A5
B6
A6
18 DAC_HSYNC_C51M
18 DAC_VSYNC_C51M
R815
DAC_RED
DAC_GREEN
DAC_BLUE
B7
C7
DAC_HSYNC
DAC_VSYNC
D8
D9
C8
DAC_RSET
DAC_VREF
DAC_IDUMP
R816
Place near C51M
R817
C769
124Ohm_*124Ohm 0.01UF/25V
+3VS
L104
1
+3VS_DAC
120Ohm/100Mhz
C770
10 mA
A9
+3.3V_DAC
C771
4.7UF/6.3V 0.1UF/16V
+2.5VS
H13
L105
1
+2.5VS_PLLGPU
120Ohm/100Mhz
C773
+2.5V_PLLGPU
20 mA
LVDS_YA0P_C51M 17
LVDS_YA1P_C51M 17
LVDS_YA2P_C51M 17
IFPA_TXD0_N
IFPA_TXD1_N
IFPA_TXD2_N
IFPA_TXD3_N
B15
C15
B14
E14
LVDS_YA0N_C51M 17
LVDS_YA1N_C51M 17
LVDS_YA2N_C51M 17
IFPB_TXC_P
IFPB_TXC_N
A10
B10
LVDS_CLKBP_C51M 17
LVDS_CLKBN_C51M 17
IFPB_TXD4_P
IFPB_TXD5_P
IFPB_TXD6_P
IFPB_TXD7_P
B11
E13
D13
B12
LVDS_YB0P_C51M 17
LVDS_YB1P_C51M 17
LVDS_YB2P_C51M 17
IFPB_TXD4_N
IFPB_TXD5_N
IFPB_TXD6_N
IFPB_TXD7_N
A11
F13
C13
C12
LVDS_YB0N_C51M 17
LVDS_YB1N_C51M 17
LVDS_YB2N_C51M 17
IFPAB_VPROBE
IFPAB_RSET
C774
X1
X2
4.7UF/6.3V 0.1UF/16V
LVDS_CLKAP_C51M 17
LVDS_CLKAN_C51M 17
A15
D15
A14
F14
IFPA_TXC_P
IFPA_TXC_N
150Ohm 150Ohm 150Ohm

DAC_RSET
DAC_VREF
C14
B13
IFPA_TXD0_P
IFPA_TXD1_P
IFPA_TXD2_P
IFPA_TXD3_P
C9
B9
+2.5V_PLLCORE
R51
16
27MREF
X6
2
X1
0Ohm_*
F12
E11
E17
F17
G17
X2
27Mhz
C778
C779
18PF/50V
18PF/50V
R1.1
R819
20.1UF/16V
1
1KOhm
+2.5VS
20 mA
XTAL_IN
XTAL_OUT
+2.5V_PLLIFP
A16 IFPAB_VPROBE C7721

F15 IFPAB_RSET
2
R818
NC1/DDC_CLK
NC2/DDC_DATA
NC3/HPDET
NC4/EE_CLK
NC5/EE_DATA
E16 +2.5VS_PLLIFP
+2.5VS_PLLIFP
+2.5VS
L106
1
L107
H12 +2.5VS_PLLCORE
20 mA
C776
120Ohm/100Mhz
C775
120Ohm/100Mhz
C777
1UF/10V
4.7UF/6.3V 0.1UF/16V
22KOhm_*
+3VS
PKG_TEST
TEST_MODE_EN
D17
C17
1
R820
2
1KOhm
+1.2VS
1
R823
2
0Ohm
+1.2VS_PLLGCI
C780
C781
R9
+1.2V_PLLGPU
P9
+1.2V_PLLCORE
H16
0.1UF/16V 0.1UF/16V
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
+1.2V_PLLIFP
C18
2
B19 R824
C19
B18
A19
R821
R822
22KOhm_*
22KOhm_*
1
22KOhm_*
+5VS
C51MV
R825
TV SLI Mux Between C51 & G7X
22KOhm_*
C7109
TV_C_NV
TV_Y_NV
TV_CVBS_NV
0.1UF/16V
Place near connector

U54
C51MV TV/CRT
SELECT
+5VS
R201
R202
R203
150_1
150_1
150_1
17,18,22 IGP_SELECT
16
TV_C_NV
+3VS
R1.1
C7110
18
16
TV_C
TV_Y_NV
18
TV_Y
1
2
3
4
5
6
7
8
TVDAC_C_NB
TVDAC_Y_NB
Place near switch
R826
S
IA0
IA1
YA
IB0
IB1
YB
GND
16
15
14
13
12
11
10
9
VCC
E#
ID0
ID1
YD
IC0
IC1
YC
TVDAC_CVBS_NB
LCD_BACKEN_NV 16
LCD_BKLEN_C51M 23
LCD_BACKEN 17
TV_CVBS_NV 16
TV_CVBS 18
PI5C3257QE
0.1UF/16V
22KOhm
R827
0Ohm
1
2
DAC_R_NB
TVDAC_C_NB
DAC_R_C51M
DAC_G_NB
TVDAC_Y_NB
DAC_G_C51M
22 MCP_TV_EN
U53
1
2
3
4
5
6
7
8
S
IA0
IA1
YA
IB0
IB1
YB
GND
+5VS
VCC
E#
ID0
ID1
YD
IC0
IC1
YC
16
15
14
13
12
11
10
9
CRT SLI Mux Between C51 & G7X
LOAD_VIDEO
LOAD_VGA
C7111
DAC_B_NB
TVDAC_CVBS_NB
DAC_B_C51M
DAC_R_NV
DAC_G_NV
DAC_B_NV
LOAD_TEST 22
R31
R32
150Ohm
150Ohm
IGP_SELECT
R1.1

1
3
5
7
R204
R205
R206
150_1
150_1
150_1
R33
RN36A
10KOhm 2
10KOhm 4 RN36B
RN36C
10KOhm 6
RN36D
10KOhm 8
150Ohm
R1.1
R1.1
Place near switch
0.1UF/16V
U55
PI5C3257QE
16
DAC_R_NV
DAC_R_NB
18
16
DAC_R_CRT
DAC_G_NV
DAC_G_NB
18
DAC_G_CRT
Place near switch
1
2
3
4
5
6
7
8
S
IA0
IA1
YA
IB0
IB1
YB
GND
VCC
E#
ID0
ID1
YD
IC0
IC1
YC
16
15
14
13
12
11
10
9
LCD_VDD_EN_NV 16
LCD_VDDEN_C51M 23
LCD_VDD_EN 17
DAC_B_NV 16
DAC_B_NB
DAC_B_CRT 18
PI5C3257QE
Place near
switch
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
14
OF
C51M CRT&LVDS
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
U4F
+1.2VS_CORE
+1.2VS
5.6A C51MV
3.5A C51M
C783
C784
C785
U4E
+1.2VS_NBCORE
C786
C787
C788
22UF/6.3V 22UF/6.3V 1UF/10V 1UF/10V 1UF/10V 1UF/10V
C797
C798
C799
C800
C801
1UF/10V 1UF/10V 1UF/10V 0.1UF/16V 0.1UF/16V
+1.2VS_HTMCP
2
200 mA
0Ohm
1
R831
+1.2VS
C810
C811
C812
1UF/10V 1UF/10V 1UF/10V
+1.2VS_PED
2
150 mA
0Ohm
1
R832
C813
B5
C6
D7
E8
E9
E10
F10
F11
G11
H11
J11
J12
J13
J14
+1.2V_CORE1
+1.2V_CORE2
+1.2V_CORE3
+1.2V_CORE4
+1.2V_CORE5
+1.2V_CORE6
+1.2V_CORE7
+1.2V_CORE8
+1.2V_CORE9
+1.2V_CORE10
+1.2V_CORE11
+1.2V_CORE12
+1.2V_CORE13
+1.2V_CORE14
T15
U13
U11
Y9
AB11
AA18
W16
U16
U15
+1.2V_HTMCP1
+1.2V_HTMCP2
+1.2V_HTMCP3
+1.2V_HTMCP4
+1.2V_HTMCP5
+1.2V_HTMCP6
+1.2V_HTMCP7
+1.2V_HTMCP8
+1.2V_HTMCP9
C814
B4
C5
D6
E7
0.1UF/16V 0.1UF/16V
C
+1.2VS_HT
1
R834
K16
M16
R16
M21
J20
T16
U17
C21
H17
+1.2VS_C51MHT 370 mA
2
0Ohm
C817
C818
C819
C820
C821
47UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
C824
C825
C826
C827
+1.2V_PEA1
+1.2V_PEA2
+1.2V_PEA3
+1.2V_PEA4
+1.2V_PEA5
+1.2V_PEA6
+1.2V_PEA7
+1.2V_PEA8
A3
B3
C4
D5
E6
F7
F8
F9
+1.2V_PLL1
+1.2V_PLL2
+1.2V_PLL3
+1.2V_PLL4
+1.2V_PLL5
+1.2V_PLL6
+1.2V_PLL7
+1.2V_PLL8
+1.2V_PLL9
+1.2V_PLL10
+1.2V_PLL11
+1.2V_PLL12
A2
B2
C2
C3
D4
E5
F6
G7
G8
G9
H10
J10
+1.2VS_PEA
C789
C790
L108
300 mA
1
C791
C792
C793
C794
C795
C796 120Ohm/100Mhz
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 1UF/10V 1UF/10V 22UF/6.3V 22UF/6.3V
L109
+1.2VS_PLL
C802
C804
260 mA
C805
C806
1
C807
C808
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 4.7U/6.3V
C809 120Ohm/100Mhz
47UF/6.3V
+2.5VS
+2.5VS_CORE
+1.2V_PED1
+1.2V_PED2
+1.2V_PED3
+1.2V_PED4
C803
C815
200 mA 1
2
0Ohm
R833
C816
D18
C10
15 mA
C828
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
V19
T14
C20
R17
AB14
U12
G13
Y16
H21
C22
AB6
F22
L22
R22
V22
AA22
A23
AA23
AA24
L11
M11
N11
P11
M12
N12
P12
M13
N13
P13
M14
N14
P14
L12
0.1UF/16V 0.1UF/16V
+1.2V_HT1
+1.2V_HT2
+1.2V_HT3
+1.2V_HT4
+1.2V_HT5
+1.2V_HT6
+1.2V_HT7
+1.2V_HT8
+1.2V_HT9
+2.5V_CORE_1
+2.5V_CORE_2
C16
B16
+2.5V_IFPA
+2.5V_IFPB
G15
H15
+1.8VS
L110
+1.8VS_IFPAB 100 mA 1
C822
C823 120Ohm/100Mhz
F3
L9
P8
N9
K4
N4
T4
W4
Y4
U9
H9
0.1UF/16V 1UF/10V
+3VS
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
C1
AA21
AA13
U14
H14
C11
AB4
AA4
J15
E12
AB10
Y18
E18
U18
E15
Y11
U19
N17
F16
J17
L13
B1
T17
D11
T12
J16
D19
H19
L21
M19
P19
T19
L14
+3.3V_1
+3.3V_2
C51MV
1UF/10V
PE_GND1
PE_GND2
PE_GND3
PE_GND4
PE_GND5
PE_GND6
PE_GND7
PE_GND8
PE_GND9
PE_GND10
PE_GND11
PE_GND12
PE_GND13
PE_GND14
PE_GND15
PE_GND16
PE_GND17
PE_GND18
PE_GND19
PE_GND20
PE_GND21
PE_GND22
K6
M6
P6
T6
W6
W8
H8
K8
V6
F4
V8
C51MV
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
15
OF
C51M PWR/GND
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
+1.5VS
+1.8VS
+2.5VS
+3VS
+5V
+12VS
Polarity Inversion:
PEXP_TXP0, 1, 2, 4, 5,
6, 8, 14
CON3A
39
39
39
39
39
39
DVI_TX0P_NV
DVI_TX0N_NV
DVI_TX1P_NV
DVI_TX1N_NV
DVI_TX2P_NV
DVI_TX2N_NV
28
30
34
36
40
42
GF_VGA_230P
DVI_A_TX0
DVI_A_TX0#
DVI_A_TX1
DVI_A_TX1#
DVI_A_TX2
DVI_A_TX2#
DVI
PEX_TX0
PEX_TX0#
PEX_RX0
PEX_RX0#
C194 0.1U/10V
121 PEXP_TXP0#
123 PEXP_TXP0
C193 0.1U/10V
122
124
EXP_TXN0 13
EXP_TXP0 13
EXP_RXP0 13
EXP_RXN0 13
PEX_TX1
PEX_TX1#
PEX_RX1
PEX_RX1#
C196 0.1U/10V
127 PEXP_TXP1#
129 PEXP_TXP1
C195 0.1U/10V
128
130
EXP_TXN1 13
EXP_TXP1 13
EXP_RXP1 13
EXP_RXN1 13
39 DVI_CLKP_NV
39 DVI_CLKN_NV
46
48
DVI_A_CLK
DVI_A_CLK#
39 DVI_HDP_NV
50
49
DVI_A_HPD
DVI_B_HPD/GND
PEX_TX2
PEX_TX2#
PEX_RX2
PEX_RX2#
C198 0.1U/10V
133 PEXP_TXP2#
135 PEXP_TXP2
C197 0.1U/10V
134
136
EXP_TXN2 13
EXP_TXP2 13
EXP_RXP2 13
EXP_RXN2 13
39 DVI_DDCCLK_NV
39 DVI_DDCDAT_NV
18 DDC2BC_NV
18 DDC2BD_NV
66
68
58
60
DDCB_CLK
DDCB_DAT
DDCA_CLK
DDCA_DAT
PEX_TX3
PEX_TX3#
PEX_RX3
PEX_RX3#
139 PEXP_TXP3 C199 0.1U/10V

C200 0.1U/10V
141 PEXP_TXP3#
140
142
EXP_TXP3 13
EXP_TXN3 13
EXP_RXP3 13
EXP_RXN3 13
14
DAC_B_NV
14
DAC_R_NV
14
DAC_G_NV
18 DAC_HSYNC_NV
18 DAC_VSYNC_NV
65
57
61
69
71
PEX_TX4
PEX_TX4#
PEX_RX4
PEX_RX4#
C203 0.1U/10V
145 PEXP_TXP4#
147 PEXP_TXP4
C202 0.1U/10V
146
148
VGA_BLU
VGA_RED
VGA_GRN
VGA_HSYNC
VGA_VSYNC
VGA
99
101
114
LVDS_PPEN
LVDS_BLEN
LVDS_BL_BRGHT
LVDS_YA0P_NV
LVDS_YA0N_NV
LVDS_YA1P_NV
LVDS_YA1N_NV
LVDS_YA2P_NV
LVDS_YA2N_NV
86
84
92
90
98
96
108
110
LVDS_UTX0
LVDS_UTX0#
LVDS_UTX1
LVDS_UTX1#
LVDS_UTX2
LVDS_UTX2#
LVDS_UTX3
LVDS_UTX3#
17 LVDS_CLKAP_NV
17 LVDS_CLKAN_NV
102
104
LVDS_UCLK
LVDS_UCLK#
87
89
93
95
83
81
105
107
LVDS_LTX0
LVDS_LTX0#
LVDS_LTX1
LVDS_LTX1#
LVDS_LTX2
LVDS_LTX2#
LVDS_LTX3
LVDS_LTX3#
17 LVDS_CLKBP_NV
17 LVDS_CLKBN_NV
77
75
LVDS_LCLK
LVDS_LCLK#
+0.9VS
222
224
228
230
221
223
IGP_UTX0
IGP_UTX0#
IGP_UTX1
IGP_UTX1#
IGP_UTX2
IGP_UTX2#
227
229
IGP_UCLK
IGP_UCLK#
14 LCD_VDD_EN_NV
14 LCD_BACKEN_NV
C
17
17
17
17
17
17
17
17
17
17
17
17
LVDS_YB0P_NV
LVDS_YB0N_NV
LVDS_YB1P_NV
LVDS_YB1N_NV
LVDS_YB2P_NV
LVDS_YB2N_NV
39
39
39
39
39
39
DVI_TX3P_NV
DVI_TX3N_NV
DVI_TX4P_NV
DVI_TX4N_NV
DVI_TX5P_NV
DVI_TX5N_NV
27
29
33
35
39
41
45
47
LVDS
IGP
IGP_LTX0/DVI_B_TX0
IGP_LTX0#/DVI_B_TX0#
IGP_LTX1/DVI_B_TX1
IGP_LTX2/DVI_B_TX2
IGP_LCLK/DVI_B_CLK
IGP_LCLK#/DVI_B_CLK#
TV-OUT
14
TV_Y_NV
14
TV_C_NV
14 TV_CVBS_NV
62
64
17 EDID_CLK_NV
17 EDID_DATA_NV
5,29
5,29
72
76
80
109
111
SCL_3S
SDA_3S
TV_Y/HDTV_Y/TV_CVBS
TV_C/HDTV_Pr
TV_CVBS/HDTV_Pb
SMBUS
DDCC_CLK
DDCC_DAT
PEX
151 PEXP_TXP5#
153 PEXP_TXP5
152
C205 0.1U/10V
154
PEX_TX6
PEX_TX6#
PEX_RX6
PEX_RX6#
C208 0.1U/10V
157 PEXP_TXP6#
159 PEXP_TXP6
C207 0.1U/10V
158
160
EXP_TXN6 13
EXP_TXP6 13
EXP_RXP6 13
EXP_RXN6 13
PEX_TX7
PEX_TX7#
PEX_RX7
PEX_RX7#
163 PEXP_TXP7 C209 0.1U/10V

C210 0.1U/10V
165 PEXP_TXP7#
164
166
EXP_TXP7 13
EXP_TXN7 13
EXP_RXP7 13
EXP_RXN7 13
PEX_TX8
PEX_TX8#
PEX_RX8
PEX_RX8#
C213 0.1U/10V
169 PEXP_TXP8#
171 PEXP_TXP8
C212 0.1U/10V
170
172
EXP_TXN8 13
EXP_TXP8 13
EXP_RXP8 13
EXP_RXN8 13
PEX_TX9
PEX_TX9#
PEX_RX9
PEX_RX9#
175 PEXP_TXP9 C214 0.1U/10V

C215 0.1U/10V
177 PEXP_TXP9#
176
178
EXP_TXP9 13
EXP_TXN9 13
EXP_RXP9 13
EXP_RXN9 13
PEX_TX10
PEX_TX10#
PEX_RX10
PEX_RX10#
181 PEXP_TXP10 C216 0.1U/10V

C217 0.1U/10V
183 PEXP_TXP10#
182
184
EXP_TXP10 13
EXP_TXN10 13
EXP_RXP10 13
EXP_RXN10 13
PEX_TX11
PEX_TX11#
PEX_RX11
PEX_RX11#
187 PEXP_TXP11 C218 0.1U/10V

C219 0.1U/10V
189 PEXP_TXP11#
188
190
EXP_TXP11 13
EXP_TXN11 13
EXP_RXP11 13
EXP_RXN11 13
PEX_TX12
PEX_TX12#
PEX_RX12
PEX_RX12#
193 PEXP_TXP12 C220 0.1U/10V

C221 0.1U/10V
195 PEXP_TXP12#
194
196
EXP_TXP12 13
EXP_TXN12 13
EXP_RXP12 13
EXP_RXN12 13
PEX_TX13
PEX_TX13#
PEX_RX13
PEX_RX13#
199 PEXP_TXP13 C222 0.1U/10V

C223 0.1U/10V
201 PEXP_TXP13#
200
202
EXP_TXP13 13
EXP_TXN13 13
EXP_RXP13 13
EXP_RXN13 13
PEX_TX14
PEX_TX14#
PEX_RX14
PEX_RX14#
C225 0.1U/10V
205 PEXP_TXP14#
207 PEXP_TXP14
C224 0.1U/10V
206
208
EXP_TXN14 13
EXP_TXP14 13
EXP_RXP14 13
EXP_RXN14 13
PEX_TX15
PEX_TX15#
PEX_RX15
PEX_RX15#
C227 0.1U/10V
211 PEXP_TXP15#
213 PEXP_TXP15
C226 0.1U/10V
212
214
EXP_TXN15 13
EXP_TXP15 13
EXP_RXP15 13
EXP_RXN15 13
CLK_REQ#
PEX_RST#
PEX_REFCLK
PEX_REFCLK#
116
118 PEX_RST#
C204 0.1U/10V
19,21,22,23,30,31,38,48
5,15,17,48
5,11,14,15,18,38,48
5,8,9,13,14,15,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
9,18,25,28,31,38,40,41
17
AC_BAT_SYS
CON3B
1
3
5
7
9
11
13
15
PWR_SRC1
PWR_SRC2
PWR_SRC3
PWR_SRC4
PWR_SRC5
PWR_SRC6
PWR_SRC7
PWR_SRC8
2
4
6
8
10
12
14
1V8RUN_1
1V8RUN_2
1V8RUN_3
1V8RUN_4
1V8RUN_5
1V8RUN_6
1V8RUN_7
17
19
21
3V3RUN_1
3V3RUN_2
3V3RUN_3
+2.5VS
18
16
5VRUN
2V5RUN
+5V
20
22
23
52
54
51
53
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
AC/BATT#
C201
15UF/25V
C206
10U/10V
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
+3VS
C211
10U/10V
+12VS
CLK_VGA27SS
CLK_VGA27FIX
20 MXM_PWR_ON
1
R7139
2
0Ohm_*
47,67 SUSB#_PWR
1
R7138
2
0Ohm
18
25
217
218
220
219
216
215
210
209
204
203
198
+1.8VS
HDTV_EN#
HDTV_EN#
+3VS
GND66
GND65
GND64
GND63
GND62
GND61
GND60
GND59
GND58
GND57
GND56
GND55
1
R101
2 PE_RST#
0Ohm
100K_*
B
Q116
2N7002_*
1
S 2
GPU_ON
13,20
R41
14
27MREF
2
22Ohm_*
R42
REFCLK
2
22Ohm_*
PE_RST# 13,30
+3VS
U42
CLK_PCIE_VGA 13
CLK_PCIE_VGA# 13
CLK_VGA27SS
24
225
226
26
R100
CLK_VGA27FIX
115
117
31
32
37
38
43
44
55
56
59
63
67
70
73
74
78
79
82
85
88
91
94
97
100
103
106
112
113
119
120
125
126
131
132
137
138
143
144
149
150
155
156
161
162
167
168
173
174
179
180
185
186
191
192
197
PEX_RST#
R44
THERM#
PRSNT1#
PRSNT2#
RUNPWROK
GF_VGA_230P
+1.5VS_VG
EXP_TXN4 13
EXP_TXP4 13
EXP_RXP4 13
EXP_RXN4 13
EXP_TXN5 13
EXP_TXP5 13
EXP_RXP5 13
EXP_RXN5 13
PEX_TX5
PEX_TX5#
PEX_RX5
PEX_RX5#
+1.5VS
+1.8VS
+2.5VS
+3VS
+5V
+12VS
2
22Ohm_*
VGA_DETECT# 13,20
SSCLK
1
2
3
4
X1/ICLK
X2
GND
VDD
S0
PD#
SSCLK REFCLK
120Ohm/100Mhz_*
1
2
8
7
6
5
L1
C40
MK1726_08STR
0.1UF/16V_*
VGA_PWRGD 20,70
R43
OTHER
27M_X1 1
X2
27M_X2
10KOhm_*
27Mhz
SMB_CLK
SMB_DAT
C38
C39
18PF/50V_*
18PF/50V_*
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
16
OF
VGA CONN
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
+1.8_2.1VS
+1.8VS
Vref=1.215V
+3VS
U56A
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
16 LVDS_YA0P_NV
16 LVDS_YA0N_NV
16 LVDS_YA1P_NV
16 LVDS_YA1N_NV
14 LVDS_YA0P_C51M
14 LVDS_YA0N_C51M
14 LVDS_YA1P_C51M
14 LVDS_YA1N_C51M
16 LVDS_YA2P_NV
16 LVDS_YA2N_NV
16 LVDS_CLKAP_NV
16 LVDS_CLKAN_NV
14 LVDS_YA2P_C51M
14 LVDS_YA2N_C51M
14 LVDS_CLKAP_C51M
14 LVDS_CLKAN_C51M
0B1
1B1
2B1
3B1
0B2
1B2
2B2
3B2
VDD6
4B1
5B1
6B1
7B1
4B2
5B2
6B2
7B2
GND1
A0
A1
GND2
VDD1
A2
A3
VDD2
SEL
GND3
A4
A5
VDD3
GND4
A6
A7
GND5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
LVDS_YA0P
LVDS_YA0N
2
3
LVDS_YA1P
LVDS_YA1N
C15
IGP_SELECT
IGP_SELECT 14,18,22
+1.8V
+3VS
+3VSUS
+12VS
+1.8_2.1VS
1
R38
U31
1
LVDS A Channel SLI MUX

2
0Ohm_*
+1.8V
+3VS
+3VSUS
+12VS
+2.1VS
1
VIN
VOUT
GND
FB
SD#
1
R37
R36
1
2
0Ohm
FootPrinter from 12-172010300

CON4
34KOhm
SI9183DT
R35
47KOhm
1UF/16V
C14
4.7U/6.3V
+LCD_VCC
+3VS
LVDS_YA2P
LVDS_YA2N
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
EDID_CLK
LVDS_YB0N
LVDS_YB0P
+3VS
LVDS_CLKAP
LVDS_CLKAN
LVDS_YB1N
LVDS_YB1P
C228
LVDS_YB2N
LVDS_YB2P
U56B
44
45
46
47
PI2PCIE412E
5,7,8,9,10,38,65
5,8,9,13,14,15,16,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
5,20,22,23,28,29,32,42,46,48,70
16
0.1U
GND11
GND12
GND13
GND14
LVDS_CLKBN
LVDS_CLKBP
LVDS_CON
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
+LCD_VCC
+LCD_VCC
EDID_DATA
LVDS_YA0N
LVDS_YA0P
LVDS_YA1N
LVDS_YA1P
LVDS_YA2N
LVDS_YA2P
LVDS_CLKAN
LVDS_CLKAP
PI2PCIE412E
+1.8_2.1VS
LVDS B Channel SLI MUX

+3VS
U57A
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
16 LVDS_CLKBP_NV
16 LVDS_CLKBN_NV
16 LVDS_YB2P_NV
16 LVDS_YB2N_NV
14 LVDS_CLKBP_C51M
14 LVDS_CLKBN_C51M
14 LVDS_YB2P_C51M
14 LVDS_YB2N_C51M
3
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
16 LVDS_YB0P_NV
16 LVDS_YB0N_NV
16 LVDS_YB1P_NV
16 LVDS_YB1N_NV
14 LVDS_YB0P_C51M
14 LVDS_YB0N_C51M
14 LVDS_YB1P_C51M
14 LVDS_YB1N_C51M
+3VS
EDID SLI MUX

GND1
A0
A1
GND2
VDD1
A2
A3
VDD2
SEL
GND3
A4
A5
VDD3
GND4
A6
A7
GND5
0B1
1B1
2B1
3B1
0B2
1B2
2B2
3B2
VDD6
4B1
5B1
6B1
7B1
4B2
5B2
6B2
7B2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
LVDS_CLKBP
LVDS_CLKBN
+3VS
LVDS_YB2P
LVDS_YB2N
R7120
47K
IGP_SELECT
16 EDID_DATA_NV
LVDS_YB1P
LVDS_YB1N
18,22 IGP_DDC_SELECT
U57B
GND11
GND12
GND13
GND14
10K
EDID_CLK
EDID_DATA
C229
C230
100P
100P
+3VS
2 S
R7122
2.7K
22 EDID_CLK_C51M
3
22 EDID_DATA_C51M
R736
R189
10K
Q111
2N7002
R7121
2.7K
PI2PCIE412E_*
R188
18 NV_DDC_EN
3
PI2PCIE412E_*
16 EDID_CLK_NV
R7117
2.7K
Q110A
UM6K1N
6
1
Q110B
UM6K1N
LVDS_YB0P
LVDS_YB0N
44
45
46
47
R7116
2.7K
Q112A
UM6K1N
1
Q112B
UM6K1N
100
Q4
2N7002
INVERTOR
CNT
+3VSUS
+12VS
+3VS
AC_BAT_SYS
L14
80/2A
C231
R192
CON5
R193
Q5
10K
1M
1
2
3
D1
1
L17
5
C235
28
+LCD_VCC
G
PMN45EN
1SS355
R195
470K
ADJ_BL
+LCD_VCC
100K
D11 RB717F
LID_SW#
BACK_OFF#
41,42
1000P
R194
80/2A
C234
Q8B
UM6K1N
1
2
3
4
5
6
7
0.1U/X7R
6
5
S 4
20
C236
C237
C238
C239
0.1U
0.1U
10U/10V
10U/10V
L15
L16
1K/300mA
1K/300mA
C232
C233
VCC1
VCC2
GND1
GND2
VREF
BKEN
PWM
8
9
8
9
Inverter_CON
3
0.1U
0.1U
14 LCD_VDD_EN
Q8A
UM6K1N
0.1U/X7R
14 LCD_BACKEN
R198
5
D2 F01J4L
2
1
10K
R26
10K
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
17
OF
55
LVDS,INVERTER CONN
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
D6
+5VS
+3VS
2
1SS355
R828
RN43A
2.2kOhm2
RN43B
2.2kOhm4
1
3
2.2KOhm
Q113A
UM6K1N
6
1
16
DDC2BC_NV
16
DDC2BD_NV
17
NV_DDC_EN
+2.5VS
+3VS
+5V
+5VS
R829
2.2KOhm
DDC2BD_5
14
DAC_R_CRT
14
DAC_G_CRT
14
+3VS
RN43C
2.2kOhm6
RN43D
2.2kOhm8
22 DDC2BC_C51M
3
22 DDC2BD_C51M
5,11,14,15,16,38,48
5,8,9,13,14,15,16,17,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
9,16,25,28,31,38,40,41
14,23,24,28,29,36,37,38,39,40,41,61
DDC2BC_5
Q113B
UM6K1N
5
7
+2.5VS
+3VS
+5V
+5VS
DAC_B_CRT
DAC_R_CRT
L18
0.068U/300mA
DAC_G_CRT
L19
0.068U/300mA
GREEN
DAC_B_CRT
L20
0.068U/300mA
BLUE
RED
DDC2BD_5
L21
120/400mA
DDC2BD
Q114A
UM6K1N
6
1
HSYNC_CRT
R199
33_0603
HSYNC
VSYNC_CRT
R200
33_0603
VSYNC
DDC2BC_5
L22
120/400mA
DDC2BC
Q114B
UM6K1N
17,22 IGP_DDC_SELECT
2
D3
D4
D5
BAV99_*
BAV99_*
BAV99_*
C241
C242
C243
C244
C245
C246
C247
C248
C249
C250
8.2P
8.2P
8.2P
8.2P
8.2P
8.2P
82P
10P
10P
82P
DDC MUX Between C51 & G7X

+2.5VS
H,VSYNC SLI MUX

+5V
CON6
IGP_SELECT#
RED
GREEN
U58A
3
2 VCC
GND
14 DAC_HSYNC_C51M
+3VS
HSYNC_CRT
BLUE
SN74HCT125DR
+5V
R7131
47K
IGP_SELECT#
3
Q115
2N7002
G
IGP_SELECT#
11
12
DDC2BD
13
HSYNC
14
VSYNC
15
DDC2BC
D_SUB_15P3R
U58C
14,17,22 IGP_SELECT
6
1
7
2
8
3
9
4
10
5
14 DAC_VSYNC_C51M
VCC
VSYNC_CRT
GND
2 S
SN74HCT125DR
+5V
16
IGP_SELECT
U58B
5 VCC
GND
16 DAC_HSYNC_NV
14
+3VS
D7
1
SN74HCT125DR
TV_C
1
R46
HDTV_EN#
TV_C
L23
BAV99_*
3 TV_C
1.8U/50mA
C251
C252
82P
82P
2
+5V
+5V
D8
1
IGP_SELECT
C240
U58D
12 VCC
GND
16 DAC_VSYNC_NV
D9
1
11
3
1
C_CON
CON7
GND1
GND0
NC
BAV99_*
3 TV_Y
0.1U
2
0Ohm_*
14
TV_Y
TV_Y
L24
BAV99_*
3 TV_CVBS
1.8U/50mA
C253
C254
82P
82P
Y_CON
6
4
CVBS_CON
7
2
C
Y
CVBS2
CVBS1
MINI_DIN_7P
2
SN74HCT125DR
14
TV_CVBS
TV_CVBS
L25
1.8U/50mA
C255
C256
82P
82P
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
18
OF
55
CRT & TV OUT

C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
U3A
12 HTMCP_TXDP[0..7]
HTMCP_RXDP[0..7] 12
HTMCP_TXDP0
HTMCP_TXDP1
HTMCP_TXDP2
HTMCP_TXDP3
HTMCP_TXDP4
HTMCP_TXDP5
HTMCP_TXDP6
HTMCP_TXDP7
K1
L1
M1
N1
R1
T1
U1
V1
HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
AA1
Y1
AA3
W5
U5
T5
R5
P5
HTMCP_RXDP0
HTMCP_RXDP1
HTMCP_RXDP2
HTMCP_RXDP3
HTMCP_RXDP4
HTMCP_RXDP5
HTMCP_RXDP6
HTMCP_RXDP7
HTMCP_TXDN0
HTMCP_TXDN1
HTMCP_TXDN2
HTMCP_TXDN3
HTMCP_TXDN4
HTMCP_TXDN5
HTMCP_TXDN6
HTMCP_TXDN7
K2
L2
M2
N2
R2
T2
U2
V2
HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_TXD0_N
HT_MCP_TXD1_N
HT_MCP_TXD2_N
HT_MCP_TXD3_N
HT_MCP_TXD4_N
HT_MCP_TXD5_N
HT_MCP_TXD6_N
HT_MCP_TXD7_N
AA2
Y2
AA4
W6
U6
T6
R6
P6
HTMCP_RXDN0
HTMCP_RXDN1
HTMCP_RXDN2
HTMCP_RXDN3
HTMCP_RXDN4
HTMCP_RXDN5
HTMCP_RXDN6
HTMCP_RXDN7
12 HTMCP_TXDN[0..7]
HTMCP_RXDN[0..7] 12
P1
P2
12 HTMCP_TXCLK0
12 HTMCP_TXCLK0#
W1
W2
12 HTMCP_TXCTL
12 HTMCP_TXCTL#
AD1
AA5
12 HTMCP_REQ#
12 HTMCP_STP#
C
1
R8381
R840
HTMCP_COMP_GND1 AB1
HTMCP_COMP_GND2 AB2
2
2 150Ohm
49.9Ohm
VDLT_PWRGD
VCORE_PWRGD
VDDIO_PWRGD
1
2
R7134
0Ohm
48
HT_VLD
61,70 CPUPWR_GD
48
MEM_VLD
67 HTVDD_EN
61 CPU_VRON
1
R843
+1.5VS
HTVDD_EN
F22
N26
M24
F23
N25
HT_MCP_RX_CLK_P
HT_MCP_RX_CLK_N
HT_MCP_RXCTL_P
HT_MCP_RXCTL_N
HT_MCP_REQ#
HT_MCP_STOP#
HT_MCP_COMP_GND1
HT_MCP_COMP_GND2
HT_MCP_TX_CLK_P
HT_MCP_TX_CLK_N
V5
V6
HTMCP_RXCLK0 12
HTMCP_RXCLK0# 12
HT_MCP_TXCTL_P
HT_MCP_TXCTL_N
N5
N6
HTMCP_RXCTL 12
HTMCP_RXCTL# 12
CLKOUT_200MHZ_N
CLKOUT_200MHZ_P
AC2
AC1
CLKOUT_25MHZ
HT_MCP_PWRGD
HT_MCP_RST#
THERMTRIP#/GPIO_58
CLK200_TERM_GND
Y5
AD2
AE1
J6
K6
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
H22
H21
H23
D26
F25
HT_VLD
CPU_VLD
MEM_VLD
HTVDD_EN
CPUVDD_EN
CLK_NBHT# 12
CLK_NBHT 12
1
R839
2
22Ohm
2
R841
1
976Ohm
150 mA
2
0Ohm
CLK_25M 12
HTMCP_PWRGD 12
HTMCP_RST# 12
CPU_THRMTRIP# 5
+3VS
C829
C7112
0.1UF/16V
+3VS
L111
0.1UF/16V_*
1
+3VS_PLL_CPUHT
120Ohm/100Mhz
C830
0.1UF/16V
M6
M5
20 mA
+1.5V_PLL_CPU_HT
+3.3V_PLL_CPU_HT
1
3
RN1A
10KOhm2
RN1B
10KOhm4
5
7
RN1C
10KOhm6
RN1D
10KOhm8
MCP51
C4
C5
C831
10uF/10V 0.01UF/25V 0.1UF/16V
+3VS
R848
R849
R850
R851
1.5KOhm 1.5KOhm 1.5KOhm 1.5KOhm

HTMCP_PWRGD
HTMCP_RST#
HTMCP_REQ#
HTMCP_STP#
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
19
OF
MCP51 HT I/F
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
32,34 PCI_AD[0..31]
PCI_AD[0..31]
U3B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
32,34 PCI_C/BE#[0..3]
PCI_C/BE#[0..3]
AF19
AB21
AC19
AA20
AA19
AF20
AE19
AE20
AB20
AB19
AA18
AB18
AE18
AF18
AC17
AA17
AB15
AF15
AE15
AF14
AE14
AA14
AB14
AC13
AB13
AE13
AA12
AF13
AB12
AF12
AE12
AF11
PCI_C/BE#0 AD19
PCI_C/BE#1 AB17
PCI_C/BE#2 AA15
PCI_C/BE#3 AA13
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_PME#
PM_CLKRUN#
32,34 PCI_FRAME#
32,34 PCI_IRDY#
32,34 PCI_TRDY#
32,34 PCI_STOP#
32,34 PCI_DEVSEL#
32,34 PCI_PAR
32,34 PCI_PERR#
32,34 PCI_SERR#
32,34 PCI_PME#
26,28,34,38 PM_CLKRUN#
+3VS
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
1
R857
1
R859
1
R7112
1
R864
1
R866
1
R7142
1
R7143
1
R7144
34 PCIRST_CB#
5,31 PCIRST_NEWC#
24 IDE_RST#
26 LPCSIO_RST#
27 LPCFWH_RST#
28 LPCKBC_RST#
38 LPCTPM_RST#
2
33Ohm
2
33Ohm
2
33Ohm
2
33Ohm
2
33Ohm
2
33Ohm
2
33Ohm
2
33Ohm
AA22
AE22
AF21
AF22
AE23
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#/GPIO_39
PCI_GNT4#/GPIO_41
AE21 PCI_GNT#0
AC21 PCI_GNT#1
AA21 T2451
AB24 1
2
AB22 R103
1
20Ohm
R102
0Ohm_*
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
AE11
AB11
AC11
AA11
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
AE24
AF24
AD23
AF23
AB23
PCI_CLKIN
AC23
MXM_PWR_ON 16
BACK_OFF# 17
PCI_GNT#0 34
PCI_GNT#1 32
VGA_DETECT# 13,16
VGA_PWRGD 16,70
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
PCI_INTA# 34
PCI_INTB# 34
PCI_INTC# 32
PCI_CLK0
PCI_CLK1
PCI_CLK2
1
R852
2
1 22Ohm 2
R853
22Ohm
1
R7115
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
K24
H26
H25
K22
CLK_LANPCI 32
CLK_CBPCI 34
CLK_TPMPCI 38
2
22Ohm
PCI_FRAME#
RP6A
8.2K
PCI_IRDY#
RP6B
8.2K
PCI_TRDY#
RP6C
8.2K
PCI_STOP#
RP6D
8.2K
PCI_SERR#
RP6E
8.2K
PCI_DEVSEL#
RP6F
8.2K
PCI_PERR#
RP6G
8.2K
PM_CLKRUN#
RP6H
8.2K
C833
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_PAR
PCI_PERR#/GPIO_43
PCI_SERR#
PCI_PME#/GPIO_30
PCI_CLKRUN#/GPIO_42
AE25
PCI_RESET0#
AD24
PCI_RESET1#
AE26
PCI_RESET2#
LPC_CLK0
F26
LPC_CLK0
W22
PCI_RESET3#
LPC_CLK1
G26
LPC_CLK1
C7108
C834
10PF/50V
_*
10PF/50V
_*
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
26,27,28,31,38
26,27,28,31,38
26,27,28,31,38
26,27,28,31,38
PCI_REQ#1
RN12B
8.2KOHM4
PCI_REQ#2
RN12C
8.2KOHM6
MXM_PWR_ON
RN12D
8.2KOHM8
G25
K21
K23
L22
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
LPC_PWRDWN#/GPIO_54
H24
GPU_ON
LPC_RESET#
RN12A
8.2KOHM2
LPC_AD0
RP7A
8.2K
LPC_AD1
RP7B
8.2K
LPC_AD2
RP7C
8.2K
LPC_AD3
RP7D
8.2K
LPC_DRQ#0
RP7E
8.2K
LPC_DRQ#1
RP7F
8.2K
RP7G
8.2K
RP7H
INT_SERIRQ
LPC_FRAME#
LPC_DRQ0#
LPC_CS#/LPC_DRQ1#
LPC_SERIRQ
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
PCI_REQ#0
PCI_CLKIN
10PF/50V10PF/50V
_*
_*
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
2
22Ohm
1
R854
PCI_CLK4
AC15
AD15
AB16
AE16
AA16
AE17
AF16
AF17
AD11
AF25
L26
PCI_REQ#0 34
PCI_REQ#1 32
C832
32 PCIRST_LAN#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
MXM_PWR_ON
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#/GPIO_38
PCI_REQ4#/GPIO_40
8.2K
R858
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
10K
LPC_FRAME# 26,27,28,31,38
LPC_DRQ#0 26
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
INT_SERIRQ 26,28,34,38
GPU_ON
1
R860
1
R862
1
R865
C835
13,16
2
22Ohm
2
22Ohm
2
22Ohm
1
3
5
7
8.2KOHM2
8.2KOHM4
8.2KOHM6
8.2KOHM8
RN44A
RN44B
RN44C
RN44D
CLK_KBCPCI 28
CLK_SIOPCI 26,31
CLK_FWHPCI 27
+3VSUS
C836
MCP51
10PF/50V10PF/50V
_*
_*
PCI_PME#
2
R867
1
8.2KOhm
BACK_OFF#
R30
10K
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
20
OF
MCP51 PCI
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
IDE_PDD[15..0]
U3C
24
24
SATA_TXP0
SATA_TXN0
B20
A20
SATA_A0_TX_P
SATA_A0_TX_N
24
24
SATA_RXN0
SATA_RXP0
A19
B19
SATA_A0_RX_N
SATA_A0_RX_P
B18
A18
SATA_A1_TX_P
SATA_A1_TX_N
A17
B17
SATA_A1_RX_N
SATA_A1_RX_P
B15
A15
SATA_B0_TX_P
SATA_B0_TX_N
A16
B16
SATA_B0_RX_N
SATA_B0_RX_P
B13
A13
SATA_B1_TX_P
SATA_B1_TX_N
A14
B14
SATA_B1_RX_N
SATA_B1_RX_P
C20
SATA_LED#/GPIO_57
D14
E13
SATA_TSTCLK_P
SATA_GND
F8
D8
A9
E9
A10
E10
C10
E11
F11
D10
F10
B10
F9
B9
E8
A8
IDE_ADDR_P0
IDE_ADDR_P1
IDE_ADDR_P2
A6
D6
B6
IDE_PDA0 24
IDE_PDA1 24
IDE_PDA2 24
IDE_CS1_P#
IDE_CS3_P#
IDE_DACK_P#
IDE_IOW_P#
IDE_INTR_P
IDE_DREQ_P
IDE_IOR_P#
IDE_RDY_P
CABLE_DET_P/GPIO_63
A5
B5
B7
F7
E6
B8
E7
A7
C6
R941
IDE_PDCS1# 24
IDE_PDCS3# 24
IDE_PDDACK# 24
IDE_PDIOW# 24
IDE_PINTR 24
IDE_PDDREQ 24
IDE_PDIOR# 24
IDE_PIORDY 24
IDE_PDIAG 24
IDE_SDD[15..0]
IDE_DATA_S0
IDE_DATA_S1
IDE_DATA_S2
IDE_DATA_S3
IDE_DATA_S4
IDE_DATA_S5
IDE_DATA_S6
IDE_DATA_S7
IDE_DATA_S8
IDE_DATA_S9
IDE_DATA_S10
IDE_DATA_S11
IDE_DATA_S12
IDE_DATA_S13
IDE_DATA_S14
IDE_DATA_S15
E4
D1
D4
C2
B2
C3
A3
A4
B4
B3
A2
B1
C1
D2
E3
E5
IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
IDE_ADDR_S0
IDE_ADDR_S1
IDE_ADDR_S2
G4
G6
G2
IDE_SDA0 24
IDE_SDA1 24
IDE_SDA2 24
IDE_CS1_S#
IDE_CS3_S#
IDE_DACK_S#
IDE_IOW_S#
IDE_INTR_S
IDE_DREQ_S
IDE_IOR_S#
IDE_RDY_S
CABLE_DET_S/GPIO_64
G1
G3
F5
E1
F6
E2
F2
F1
G5
IDE_SDCS1# 24
IDE_SDCS3# 24
IDE_SDDACK# 24
IDE_SDIOW# 24
IDE_SINTR 24
IDE_SDDREQ 24
IDE_SDIOR# 24
IDE_SIORDY 24
IDE_SDIAG 24
24
SATA_LED#
1
R868
23 SATA_TSTCLK#
SATA_TSTCLK
2
100Ohm_*
F13
T7127
1
R869
SATA_TEST
2
2.49KOhm
F14
E14
SATA_TERMP
SATA_TERMN
+1.5VS_PLL_SP_VDD
F18
+1.5V_PLL_SP_VDD
+1.5VS
L112
1
180 mA
2
120Ohm/100Mhz
C837
0.1UF/16V
C838
10uF/10V
C839
C840
0.01UF/25V 0.1UF/16V
IDE_PDD[15..0]
24
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
IDE_DATA_P0
IDE_DATA_P1
IDE_DATA_P2
IDE_DATA_P3
IDE_DATA_P4
IDE_DATA_P5
IDE_DATA_P6
IDE_DATA_P7
IDE_DATA_P8
IDE_DATA_P9
IDE_DATA_P10
IDE_DATA_P11
IDE_DATA_P12
IDE_DATA_P13
IDE_DATA_P14
IDE_DATA_P15
R274
0_*
IDE_SDD[15..0]
24
0_*
+3VS
B
+3VS
+3VS_PLL_SP_SS
L113
1
F19
D20
2 12 mA
120Ohm/100Mhz
C841
0.1UF/16V
IDE_COMP_3P3
IDE_COMP_GND
+1.5V_PLL_SP_SS
+3.3V_PLL_SP_SS
B11 IDE_COMP_3P3V R870 1

A11 IDE_COMP_GND R871 1
2 121Ohm
2 121Ohm
MCP51
C842
10uF/10V
C843
C844
0.01UF/25V 0.1UF/16V
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
21
OF
MCP51 IDE
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
36 ACZ_BCLK_AUD
38 ACZ_BCLK_MDC
36 ACZ_SYNC_AUD
38 ACZ_SYNC_MDC
1
R872
1
R873
2
22Ohm
2
22Ohm
1
R874
1
R875
2
22Ohm
2
22Ohm
1
R876
1
R877
2
22Ohm
2
22Ohm
1
R878
1
R879
2
22Ohm
2
22Ohm
AC_SRT# STRAP (LAN)

0
M11
1
RGMII
AC_BITCLK
AC_BITCLK
38 ACZ_RST#_MDC
36 ACZ_SDOUT_AUD
38 ACZ_SDOUT_MDC
AC_SDOUT
AC_SDIN_0
AC_SDIN_1
36 ACZ_SDIN0_AUD
38 ACZ_SDIN1_MDC
69 CHG_FULL_OC
AC_RST#
AC_RST#
AC_SYNC
AC_SDOUT
USB_PP0
USB_PN0
USB_PP1
USB_PN1
U3D
AC_SYNC
36,37 ACZ_RST#_AUD
R22
U26
AC97_CLK
AC_BITCLK/HDA_BCLK
USB0_P
USB0_N
AC26
AC25
USB_PP0 25
USB_PN0 25
T25
R26
T24
U21
(AC/HAD)_SDATA_OUT0/GPIO_45
(AC/HAD)_SDATA_IN0/GPIO_22
USB1_P
USB1_N
AB26
AB25
USB_PP1 25
USB_PN1 25
AA26
AA25
U25
R21
USB2_P
USB2_N
USB_PP2 38
USB_PN2 38
AC_RESET#/HDA_RST#
AC_SYNC/HDA_SYNC/GPIO_44
USB3_P
USB3_N
Y26
Y25
USB_PP3 38
USB_PN3 38
USB4_P
USB4_N
W26
W25
USB_PP4 40
USB_PN4 40
USB5_P
USB5_N
V24
V23
USB_PP5 25
USB_PN5 25
USB6_P
USB6_N
V26
V25
USB_PP6 31
USB_PN6 31
USB7_P
USB7_N
T22
T23
USB_PP7 25
USB_PN7 25
BT_ON/OFF#
38 BT_ON/OFF#
1
R880
SPDIFO strap for BUF_SIO_CLK

0 14.318MHz (default)
1 24MHz
18 DDC2BC_C51M
18 DDC2BD_C51M
2
T26
10KOhm
DDC_CLKC51M
AE10
AF10
AF9
14 LOAD_TEST
17 EDID_DATA_C51M
EDID_CLKC51M
17 EDID_CLK_C51M
AB10
AE9
AA10
SPDIF0/GPIO_46
DDC_CLK0
DDC_DATA0
HPLUG_DET0/GPIO_47
DDC_DATA1/GPIO_53
NC
DDC_CLK1/GPIO_52
USB_PP2
USB_PN2
USB_PP3
USB_PN3
USB_PP4
USB_PN4
USB_PP6
USB_PN6
USB_PP5
USB_PN5
USB_PP7
USB_PN7
PCB_ID2
28 KB_SCI#
5,68,71 PWRLMT#
26,38 PM_SUS_STAT#
41 802_LED_EN#
14 MCP_TV_EN
34 CB_SD#
47 CR_VID0
47 CR_VID1
1
3
5
7
1
3
10KOhm 2
10KOhm 4
10KOhm 6
10KOhm 8
10KOhm 2
10KOhm 4
RN42A
RN42B
RN42C
RN42D
RN45A
RN45B
J4
J3
J5
AE2
K5
J2
J1
AC9
AB9
AA9
P24
P25
P22
P26
R25
P23
+3VSUS
1
3
5
7
USB_OC0#/GPIO_18
USB_OC1#/GPIO_19
USB_OC2#/GPIO_20
USB_OC3#/GPIO_21
USB_RBIAS_GND
+3VSUS
1
R886T246
1
R8881
2 RTC_RST# R889
49.9KOhm
100KOhm
1
R891
LOAD_TEST
2
110KOhm
2
20Ohm
10KOhm
B25
B24
E22
G22
A25
C7113
C846
JRST1
0.01UF/25V
1UF/10V
RTC_RST#
A20GATE/GPIO_55
INTRUDER#
EXT_SMI#/GPIO_32
RI#/GPIO_33
SPKR
PWRBTN#
SIO_PME#/GPIO_31
KBRDRSTIN#/GPIO_56
PE_WAKE#
SMB_CLK0/GPIO_25
SMB_DATA0/GPIO_26
SMB_CLK1/GPIO_27
SMB_DATA1/GPIO_28
SMB_ALERT#/GPIO_29
+3.3V_VBAT
BUF_SIO_CLK
SUS_CLK/GPIO_34
THERM#/GPIO_59
RSTBTN#
LID#/GPIO_17
SLP_DEEP#
V3P3_DEEP
LLB#
RTC_RST#
+3VS_PLL_SP_SS
+RTCBAT +3VA
T301
R882
1K
L114
1
SLP_S5#
SLP_S3#
PWRGD_SB
PWRGD
FANRPM/GPIO_60
FANCTL0/GPIO_61
FANCTL1/GPIO_62
TEST_MODE_EN
+1.5VS_PLLUL 20 mA
1
C845
120Ohm/100Mhz
RB715F
T300
C849
C850
1UF/X7R
CON44
+1.5V_PLL_LEG
+3.3V_PLL_LEG
+1.5VS
3
B22
A22
5 mA
+VCC_RTC
D67
2
0.01UF/25V 0.1UF/16V
RTC_CON
Y21
AD26
PROCHOT#
Q190
Y24
Y23
U22
V22
S2
+1.5V_PLL_USB
+3.3V_PLL_USB
BATT_TALARM 69
G
2N7002
RN41A
10KOhm 2
RN41B
10KOhm 4
RN41C
10KOhm 6
RN41D
10KOhm 8
R2.1
BATT_65C#
T305
1
R7146
AD25USB_RBIAS_GND
+3VS
1HZ
41
IGP_DDC_SELECT 17,18
2
0Ohm
1
R883
2
732Ohm
SMB_MEM_SCL 1
SMB_MEM_SDA R7135
1
R7136
J22
A24
1
2
R885
1MOhm
M26
RI#
M25
5
10KOhm6
RN45C
E26
D23
M23
J21
AC3
SMB_MEM_SCL
H1
SMB_MEM_SDA
H2
M21
L25
M22 SMB_ALERT# 1
2
R892
2.7KOhm
A23
J26
N21 SUSCLK 1
2
R7147
22Ohm
K25
RSTBTN#
F21
C26
F24
B26
N22
PCB_ID0
L21
PCB_ID1
J25
K26 IGP_SEL 1
2
0Ohm
D25
1R7148
2
R894
1KOhm
2
2.7KOhm
2
2.7KOhm
+3VSUS
HA20GATE 28
+3VSUS
EXTSMI#_3A 28
SIO_SMI#
SPKR_SB 36
PM_PWRBTN# 42
SIO_SMI# 26
KBDCPURST 28
PCIE_WAKE# 30,31
SMB_MEM_SCL 8,9
SMB_MEM_SDA 8,9
SMB_CLK_SB 29,31
SMB_DAT_SB 29,31
SUS_CLK 38
PM_THRM# 5
10KOhm 8
+VCC_RTC
1
R893
2
22Ohm
CLK_SIO14 26
C847
C848
10PF/50VSB_
0.1UF/16V
SUSC#
42,67
SUSB#
31,32,42,67,70
PM_RSMRST# 42
PWRGD 5,70
RN45D
+3VSUS
PWRGD_SB => +xVSUS OK

PWRGD => +xVS and +xV OK
IGP_SELECT 14,17,18
+3VS
MCP51
+3VS
GPIO_1/SLV_RDY4PWRDWN
GPIO_2/CPU_SLP
GPIO_3/CPU_CLKRUN
GPIO_4/AGPSTP/SUS_STAT
GPIO_5/SYS_SHUTDOWN
GPIO_6/NFERR/SYS_PERR
GPIO_7/FERR/SYS_SERR
GPIO_8/CR_VID0
GPIO_9/CR_VID1
GPIO_10/CR_VID2
GPIO_11/CPU_VID0
GPIO_12/CPU_VID1
GPIO_13/CPU_VID2
GPIO_14/CPU_VID3
GPIO_15/CPU_VID4
GPIO_16/CPU_VID5
+VCC_RTC
+VCC_RTC
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
2
15KOhm
0Ohm_*
+3VS
R881
2
15KOhm
2
15KOhm
2
R87
BATT_65C#
1
1R1
1R2
1R3
R4
1
1R5
1R8
1R9
R10
1
1R11
1R12
1R13
R14
1
1R15
1R16
1R17
R18
+3VS
+3VS
L115
1
120Ohm/100Mhz
C851
0.1UF/16V
+3VS_PLL_USB
C852
C853
10uF/10V
+3VSUS
18 mA
+3V
CB_SD#
C854
802_LED_EN#
0.01UF/25V 0.1UF/16V
CHG_FULL_OC
A
RSTBTN#
PCIE_WAKE#
PWRLMT#
KB_SCI#
1
R895
1
R896
1
R897
1
R898
1
R899
1
R7113
1
R7114
2
10KOhm
2
10KOhm
2
10KOhm
2
10KOhm
2
10KOhm
2
10KOhm
2
10KOhm
IGP_SEL
SUSCLK
SUSB#
1
R7149
2
10KOhm
1
R7150
2
10KOhm
1
R25
2
22kOhm
R254
R255
R256
10K
10K_*
10K_*
PCB_(ID2, ID1, ID0)

R1.0-->000
R1.1-->001
R2.0-->010
PCB_ID0
PCB_ID1
PCB_ID2
R263
R264
R265
10K_*
10K
10K
R1.1 (NVIDIA request)
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
22
OF
MCP51 USB/HDA
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
+5VS
+1.2VS
U3F
1
R900
C857
C858
C859
C860
C861
C862
C863
22UF/6.3V
4.7U/6.3V
1UF/6.3V
1UF/6.3V
0.1UF/16V
0.1UF/16V
0.1UF/16V
C868
C869
C870
C871
C872
22UF/6.3V
4.7U/6.3V
1UF/6.3V
1UF/6.3V
0.1UF/16V
C876
C877
C878
C879
C880
0.1UF/16V
0.1UF/16V
0.1UF/16V
0.1UF/16V
0.1UF/16V
+1.2VS
1
R902
200 mA
+1.2VS_MCPHT
2
0Ohm
C885
C886
50 mA
750 mA
+1.2VS_MCPCORE
2
0Ohm
C887
C888
C889
C890
U17
U16
U15
U12
U11
U10
T17
T10
R17
R10
M17
M10
L17
L10
K17
K16
K15
K12
K11
K10
U3
R3
N3
L3
W3
+1.2V_1
+1.2V_2
+1.2V_3
+1.2V_4
+1.2V_5
+1.2V_6
+1.2V_7
+1.2V_8
+1.2V_9
+1.2V_10
+1.2V_11
+1.2V_12
+1.2V_13
+1.2V_14
+1.2V_15
+1.2V_16
+1.2V_17
+1.2V_18
+1.2V_19
+1.2V_20
+5V_1
+5V_2
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_HT
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_DUAL_1
+3.3V_DUAL_2
+3.3V_DUAL_3
+3.3V_DUAL_4
+1.5VSUS
C856
0.1UF/16V
0.1UF/16V
+3VS
AD21
AD17
AD13
AD9
AD5
C12
C8
C4
C865
C866
C867
0.1UF/16V
0.1UF/16V
0.1UF/16V
0.1UF/16V
C901
C902
10uF/10V
C874
C875 120Ohm/100Mhz
0.1UF/16V
0.1UF/16V
+3VSUS
55 mA
Y6
T21
P21
G21
C881
C882
C883
C884
0.1UF/16V
0.1UF/16V
0.1UF/16V
0.1UF/16V
R901
120 mA
+1.5V_SP_A_1
+1.5V_SP_A_2
+1.5V_SP_D_1
+1.5V_SP_D_2
F17
E17
F15
E15
450 mA
+1.5V_SP_A_3
+1.5V_SP_A_4
E16
F16
+3VSUS_USB
+1.5VS
L117
+1.2V_DUAL_1
+1.2V_DUAL_2
+1.5VS_SP
C891
C892
C893
C894 120Ohm/100Mhz
C895
4.7U/6.3V
0.1UF/16V
0.1UF/16V
0.1UF/16V
0.1UF/16V 10uF/10V
C897
C898
C899
C900
175 mA
MCP51
2
0Ohm
L116
150 mA
+3VS_MCPHT
C864
C873
W21
V21
+1.2V_HT_1
+1.2V_HT_2
+1.2V_HT_3
+1.2V_HT_4
+1.2V_HT_5
+3VS
150 mA
+3VS_MCPHT
+3.3V_USB_DUAL_1
+3.3V_USB_DUAL_2
+1.5VSUS_DUAL
150 mA
1
R903
C855
0Ohm
0.1UF/16V 0.1UF/16V 0.1UF/16V 1UF/6.3V 22UF/6.3V 22UF/6.3V

AE3
AF3
Y22
F12
10uF/10V
C903
0.1UF/16V 0.01UF/16V
U3G
1UF/6.3V
AF26
AF1
AD22
AD20
AD18
AD16
AD14
AD12
AD10
AD8
AD6
AD4
AC24
AB3
AA24
Y3
W24
V3
U24
U14
U13
T16
T15
T14
T13
T12
T11
T3
R24
R16
R15
R14
R13
R12
R11
P17
P16
P15
P14
P13
P12
P11
P10
P3
N24
N17
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
F20
E18
D18
D16
E20
C18
C16
B21
A21
SATA_GND1
SATA_GND2
SATA_GND3
SATA_GND4
SATA_GND5
SATA_GND6
SATA_GND7
SATA_GND8
SATA_GND9
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
N16
N15
N14
N13
N12
N11
N10
M16
M15
M14
M13
M12
M11
M3
L24
L16
L15
L14
L13
L12
L11
K14
K13
K3
J24
H3
G24
F3
E24
D3
C23
C11
C9
C7
C5
A26
A1
H5
H6
U4
R4
N4
L4
W4
L5
L6
SATA_GND10
SATA_GND11
SATA_GND12
SATA_GND13
SATA_GND14
SATA_TSTCLK_N
SATA_GND15
SATA_GND16
C21
C19
C17
C15
C13
C14
B12
A12
0.1UF/16V 0.01UF/16V
U3E
1
R904
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
37
2
10KOhm
10kOhm1RP9A
10kOhm2
RP9B
3
10kOhm RP9C
10kOhm4RP9D
10kOhm6
RP9E
10kOhm7RP9F
10kOhm8
RP9G
10kOhm9
RP9H
OP_SD#
1
R905
AE7
AF6
AB6
AA6
AA7
AB7
RGMII_TXD0/MII_TXD0
RGMII_TXD1/MII_TXD1
RGMII_TXD2/MII_TXD2
RGMII_TXD3/MII_TXD3
RGMII_TXCLK/MII_TXCLK
RGMII_TXCTL/MII_TXEN
AF7
AF8
AD7
AB8
AC7
AE8
RGMII_RXD0/MII_RXD0
RGMII_RXD1/MII_RXD1
RGMII_RXD2/MII_RXD2
RGMII_RXD3/MII_RXD3
RGMII_RXCLK/MII_RXCLK
RGMII_RXCTL/MII_RXDV
AF4
2
10KOhm
AF5
AE6
AD3
AC4
AF2
AE5
AA8
NC1
NC2
LCD_BKL_ON/GPIO_51
NC3
LCD_BKL_CTL/GPIO_49
NC4
LCD_PANEL_PWR/GPIO_50
E19
D12
C25
E25
C24
E12
D24
LCD_BKLEN_C51M 14
FWH_WP# 27
LCD_VDDEN_C51M 14
RGMII_VREF/MII_VREF
RGMII_MDC/MII_MDC
RGMII_MDIO/MII_MDIO
MII_RXER/GPIO_36
MII_COL
MII_CRS
RGMII_PWRDWN/MII_PWRDWN/GPIO_37
RGMII_INTR/MII_INTR/GPIO_35
XTALIN
XTALOUT
E21
D22
XIN_25M
XOUT_25M
1
C904
32
BUF_25MHZ AC5
2
22Ohm
1
R28
BUF_25M
BUF_25MHZ
X7
2
C905
25Mhz
18PF/50V
18PF/50V
+1.5VSUS_DUAL
+3VSUS
1
R907
C907
0.1UF/16V
2
0Ohm
10 mA AE4
5 mA
C908
10uF/10V
AB5
C909
C910
+1.2V_PLL_MAC_DUAL
+3.3V_PLL_MAC_DUAL
XTALIN_RTC
XTALOUT_RTC
MCP51
C22 RTC_X0
B23 RTC_X1
2
R906
0.1UF/16V 0.01UF/16V
X8
1
SATA_TSTCLK# 21
MCP51
1
1MOhm_*
32.768Khz
4
C911
C906
18PF/50V
18PF/50V
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
23
OF
MCP51 PWR/GND
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
IDE_PDD[15:0]
21 IDE_PDD[15:0]
+5VS
PATA HDD CON
+5VS
+5VS
U9
1 A
20
IDE_RST#
R273
VCC 5
2 B
4
Y
NC7ST32M5X_*
+3VS
R275
4.7K_*
IDE_PIORDY
R913
4.7K
IDE_SIORDY
R276
1K_*
IDE_SCSEL
R277
2
470
R278
470_*
IDE_PCSEL
R279
5.6K_*
IDE_PDDREQ
R914
5.6K
IDE_SDDREQ
R280
10K_*
IDE_PDD7
R186
10K_*
IDE_PINTR
R915
10K
IDE_SINTR
R916
15K_*
IDE_PDIAG
R917
15K_*
IDE_SDIAG
R7137
10K
IDE_SDD7
C304
C305
C306
C307
0.1U
0.1U
10U/10V
10U/10V
10K_*
CON9
44
44
42 42
40 40
38 38
36 36
34 34
32 32
30 30
28 28
26 26
24 24
22 22
20 20
18 18
16
16
14 14
12 12
10 10
8 8
6 6
4 4
2 2
IDERST#_5
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
3 GND
1
R908
2
33Ohm
IDE_PDDREQ
IDE_PDIOW#
IDE_PDIOR#
IDE_PIORDY
IDE_PDDACK#
IDE_PINTR
IDE_PDA1
IDE_PDA0
IDE_PDCS1#
IDE_PDASP#
21 IDE_PDDREQ
21 IDE_PDIOW#
21 IDE_PDIOR#
21 IDE_PIORDY
21 IDE_PDDACK#
21
IDE_PINTR
21
IDE_PDA1
21
IDE_PDA0
21 IDE_PDCS1#
PATA_HDD_CON_*
43 43
41 41
39 39
37 37
35 35
33 33
31 31
29 29
27 27
25 25
23 23
21 21
19 19
17 17
15
15
13 13
11 11
9 9
7 7
5 5
3 3
1 1
+3VS
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
+3VS
+3VS
R282
R748
10K
10K
R281
41
HDD_LED#
1K_*
D62
IDE_PCSEL
IDE_PDIAG
IDE_PDA2
IDE_PDCS3#
IDE_PDIAG 21
IDE_PDA2 21
IDE_PDCS3# 21
Q108B
UM6K1N
Q108A
UM6K1N
IDE_PDASP#
IDE_SDASP#
3
DAP202K
1
D68
21 IDE_SDD[15:0]
SATA_LED# 21
1SS355
IDE_SDD[15:0]
Differential
Pair
PATA CD-ROM CON

SATA HDD CON
C693 0.01UF/16V
21 SATA_TXP0
C691 0.01UF/16V
21 SATA_TXN0
SATA_HDD_RXP0
SATA_HDD_RXN0
SATA_HDD_TXN0
SATA_HDD_TXP0
C692 0.01UF/16V
21 SATA_RXN0
C694 0.01UF/16V
21 SATA_RXP0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND1
NP_NC1
25
23
36
36
CD_L_A
CD_GND_A
21
21
21
21
21
21
IDE_SDIOW#
IDE_SIORDY
IDE_SINTR
IDE_SDA1
IDE_SDA0
IDE_SDCS1#
Differential
Pair
+3VS
Differential
Pair
+5VS
CON42
+5VS
T220
+3VS
C688
C689
C690
0.1U_*
10U/10V_*
10U/10V_*
NP_NC2
24
GND2
26
+5VS
CON10
1
1
3
3
5
5
7 7
9 9
11 11
13 13
15 15
17
17
19
19
21 21
23 23
25 25
27
27
29
29
31 31
33 33
35 35
37 37
39 39
41
41
43
43
45
45
47 47
49 49
CD_L_A
CD_GND_A
IDERST#_5
IDE_SDD7
IDE_SDD6
IDE_SDD5
IDE_SDD4
IDE_SDD3
IDE_SDD2
IDE_SDD1
IDE_SDD0
IDE_SDIOW#
IDE_SIORDY
IDE_SINTR
IDE_SDA1
IDE_SDA0
IDE_SDCS1#
IDE_SDASP#
IDE_SCSEL
ODD_CON
2
2
4
4
6
6
8 8
10 10
12 12
14 14
16 16
18
18
20
20
22 22
24 24
26 26
28
28
30
30
32 32
34 34
36 36
38 38
40 40
42
42
44
44
46
46
48 48
50 50
CD_R_A
CD_R_A
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
IDE_SDDREQ
IDE_SDIOR#
36
IDE_SDDREQ 21
IDE_SDIOR# 21
4
IDE_SDDACK#
IDE_SDDACK# 21
IDE_SDIAG
IDE_SDA2
IDE_SDCS3#
IDE_SDIAG 21
IDE_SDA2 21
IDE_SDCS3# 21
+5VS
C308
C309
C310
C311
0.1U
0.1U
10U/10V
10U/10V
SATA_HDD_CON
+3VS
+5VS
+5V
+3VS
+5VS
+5V
5,8,9,13,14,15,16,17,18,19,20,21,22,23,26,27,28,29,30,31,34,36,38,39,41,48,61,70
14,18,23,28,29,36,37,38,39,40,41,61
9,16,18,25,28,31,38,40,41
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
24
OF
55
HDD & CD-ROM CONN

C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
CON11
22
22
USB_PN5
USB_PP5
R141
USBP5-
R140
USBP5+
L28
80/2A +5VUSB5
FOR EMI
C312
+5V
+12V
USB_PN7
22
USB_PP7
R139
USBP7-
R137
USBP7+
F1
2
5
1
2
3
4
6
SIDE_G1
SIDE_G3
VCC
USB
DATA0DATA0+
GND
SIDE_G2
SIDE_G4
+5V_USB57
R133
22
+5VUSB5
USBP5USBP5+
0.1U
1.5A/6V
+5VUSB_57
1
L30
USB_CON_1X4P
80/2A +5VUSB7
10K
C313
Q22
PMN45EN
10U/10V
R764
R765
R762
R763
C314
CE1
100UF/10V
CON12
0.1U
+5VUSB7
USBP7USBP7+
FOR EMI
5
1
2
3
4
6
SIDE_G1
0_0805_*
0_0805_*
0_0805_*
0_0805_*
SIDE_G3
VCC
USB
DATA0DATA0+
GND
SIDE_G2
SIDE_G4
USB_CON_1X4P
22
USB_PN1
22
USB_PP1
R138
USBP1-
R136
USBP1+
+5V
+12V
F3
2
10K
FOR EMI
22
USB_PN0
22
USB_PP0
R135
USBP0-
R134
USBP0+
1.5A/6V
+5VUSB_01
1
+
C317
Q19
PMN45EN
10
+5V_USB01
R132
10U/10V
L35
80/2A +5VUSB0
CE3
C318
100U/6.3V
0.1U
USBP1+
USBP1+5VUSB0
8
7
6
5
USBP0+
USBP0+5VUSB0
4
3
2
1
GND4
GND2
0P+
0PVCC2
12
CON14
GND6
USB
GND1
1P+
1PVCC1
GND3
GND5
11
USB_CON_2X4P
FOR EMI
+5V
+5V
9,16,18,28,31,38,40,41
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
25
OF
55
USB PORTS
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
+3VS
CLK_SIOPCI
C319
C321
C322
C323
C324
C320
10P_*
10U/10V
0.1U
0.1U
0.1U
0.1U
+3VS
DSR1#
U10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CTS1#
RI1#
DCD1#
IO_PME#
+3VS
22
CLK_SIO14
20,27,28,31,38 LPC_AD0
+3VS
20,27,28,31,38 LPC_AD1
20,27,28,31,38 LPC_AD2
20,27,28,31,38 LPC_AD3
20,27,28,31,38 LPC_FRAME#
20
LPC_DRQ#0
LPC47N217
nRTS1
nCTS1
nDTR1
nRI1
nDCD1
IO_PME#
VTR
VSS1
CLOCKI
LAD0
VCC1
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PD3
PD2
PD1
VCC3
PD0
VSS3
nSLCTIN
nINIT
GP23
IRMODE/IRRX3
IRTX2
IRRX2
GP14/IRQIN2
GP13/IRQIN1
GP12/IO_SMI#
GP11/SYSOPT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
+3VS
ATI_RST#
FIR_SEL
IR_TXD
IR_RXD
GPI14
GPI13
IO_SMI#
SYSOPT
+3VS
27
27
27
SIO_SMI# 22
3
Q107
2N7002
SYSOPT=0 --> 0x002E

SYSOPT=1 --> 0x004F
20 LPCSIO_RST#
22,38 PM_SUS_STAT#
20,28,34,38 PM_CLKRUN#
20,31 CLK_SIOPCI
20,28,34,38 INT_SERIRQ
R299
0_*
LPCPD#
T7125
CLK_SIOPCI
+3VS
+3VS
+3VS
+3VS
+3VS
R294
R295
10K_*
10K_*
GPI14
GPI13
R297
R298
10K_*
10K
IO_PME#
LPCPD#
R666
10K_*
ATI_RST#
1 10K_*
3 10K_*
5 10K_*
7 10K_*
R300
2
4
6
8
RN26A
RN26B
RN26C
RN26D
10K
DSR1#
CTS1#
RI1#
DCD1#
SYSOPT
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,27,28,29,30,31,34,36,38,39,41,48,61,70
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
26
OF
55
SUPER IO LPC47N217
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
+3VS
+3VS
R7151
0_*
U11
R7132
R301
20 LPCFWH_RST#
10K
100
20 CLK_FWHPCI
R303
1 10K
3 10K
5 10K
7 10K
FWH_FGPI4
FWH_FGPI3
FWH_FGPI2
FWH_FGPI1
FWH_FGPI0
10K
2
4
6
8
RN27A
RN27B
RN27C
RN27D
T74
T75
28,31,38 DIS_FWH
T76
24
2
INIT#
RST#
31
CLK
30
3
4
5
6
FGPI4
FGPI3
FGPI2
FGPI1
FGPI0
9
10
11
12
ID3
ID2
ID1
ID0
CLK_FWHPCI
16
26
28
GND1
GND2
GNDA
C327
10U/10V
TBL#
WP#
8
7
FWH_WP# 23
FWH4
FWH3
FWH2
FWH1
FWH0
23
17
15
14
13
LPC_FRAME# 20,26,28,31,38
LPC_AD3 20,26,28,31,38
LPC_AD2 20,26,28,31,38
LPC_AD1 20,26,28,31,38
LPC_AD0 20,26,28,31,38
RSVD5
RSVD4
RSVD3
RSVD2
RSVD1
10P_*
C326
0.1U
1
25
32
27
IC
2
C325
VPP
VCC1
VCC2
VCCA
R302
10K_*
29
22
21
20
19
18
Internal PD w/
20-100K Ohm
R304
10K
SST 49LF004A-33-4C-N
PLCC32 Socket Part Number :

12G043400324
Graphics from:
05-001005111
Trace Wide=40mil
Trace Wide=40mil
R305
+3VS
2.7
1206
IR_LEDA
C328
C329
C330
10U/10V
0.1U
1000P
IR1
26
26
IR_TXD
IR_RXD
26
FIR_SEL
11
10
9
8
7
6
5
4
3
2
1
IR_TXD_Q
IR_RXD
+3VS
C331
SHIELD
LEDA
TXD
RXD
GND
NC
MD1
MD0
FIR_SEL
AGND
VCC
HSDL_3602_007
0.47U
+3VS
+3VS
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,28,29,30,31,34,36,38,39,41,48,61,70
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
27
OF
55
BIOS , IR
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
+3V
+3V
+3VS
+3VSUS
+5V
+5VS
+5VLCM
+3V
CON43
P2.1 Low : Power Button Override disable

14
Input Event only at P54, P55, P60 - P67

P50, P43, P54, P55 are wake-up event
inputs when KBC in standby mode
1
13
EC should set
OP_SD low in S3,
keep from
leakage.
12
SIDE2 11
10
9
8
7
6
5
4
3
SIDE1 2
1
12
11
10
9
8
7
6
5
4
3
2
1
LPC_AD0
KSI0
LPC_AD1
KSI1
LPC_AD2
DIS_FWH
LPC_AD3
KSI2
DIS_FWH 27,31,38
KSI3
LPC_FRAME#
KSI4
CLK_KBCPCI
KSI5
KSI6
DEBUG_CON
KSI7
1
RP4A
2
RP4B
3
RP4C
4
RP4D
6
RP4E
7
RP4F
8
RP4G
9
RP4H
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
10K
10K
10K
10K
10K
10K
10K
10K
+3V
+3VS
+3VSUS
+5V
+5VS
+5VLCM
+3V
CLK_KBCPCI
+3V
C337
10P_*
+3V
U13
20,26,34,38 INT_SERIRQ
20 CLK_KBCPCI
20 LPCKBC_RST#
20,26,27,31,38 LPC_FRAME#
20,26,27,31,38 LPC_AD3
20,26,27,31,38 LPC_AD2
20,26,27,31,38 LPC_AD1
20,26,27,31,38 LPC_AD0
41 MSK_INSTKEY#
40
41
68
BAT_LEARN
42
KBCRSM
BAT_LEARN
R321
WATCHDOG
SWDJ_EN
100K
KBCPURST_3Q
KBC_GA20
KBSCI_3Q
20,26,34,38 PM_CLKRUN#
BAT_LLOW#_OC
FAN1_TACH
KBDDT0
KBDDT1
69 BAT_LLOW#_OC
40 FAN1_TACH
3
42
71
40
17
LID_KBC#
BAT_IN_OC#
FAN1_DC
ADJ_BL
41
PANLOCK_#
41 MARATHON_#
68
AC_IN#
41 WIRELESS_#
41 INTERNET_#
41 BLUETOOTH_#
D14
1SS355
+3V
RN30A
RN30B
RN30C
RN30D
1
3
5
7
2
4
6
8
10K
10K
10K
10K
INTCLK_5S
INTDATA_5S
4
M38857
63
64
65
66
67
68
69
70
P87/SERIRQ
P86/LCLK
P85/LRESET#
P84/LFRAME#
P83/LAD3
P82/LAD2
P81/LAD1
P80/LAD0
35
36
37
38
P23
P22
P21
P20
23
22
21
20
19
18
P42/INT0
P43/INT1*
P44/RXD
P45/TXD
P46/SCLK1
P47/SRDY1#/CLKRUN#
17
16
15
14
13
12
11
10
P50/INT5*
P51/INT20
P52/INT30/1-WIRE1
P53/INT40/1-WIRE2
P54/CNTR0*
P55/CNTR1*
P56/DA1/PWM01
P57/DA2/PWM11
74
75
76
77
78
79
80
1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
C338 C339
VCC
71
VREF
72
P27
P26
P25
P24
31
32
33
34
P17/KSO15
P16/KOS14
P15/KSO13
P14/KSO12
P13/KSO11
P12/KSO10
P11/KSO9
P10/KSO8
P07/KSO7
P06/KSO6
P05/KSO5
P04/KSO4
P03/KSO3
P02/KSO2
P01/KSO1
P00/KSO0
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
P37/KSI8
P36/KSI7
P35/KSI6
P34/KSI5
P33/KSI4
P32/KSI3
P31/PWM10/KSI2
P30/PWM00/KSI0
55
56
57
58
59
60
61
62
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
XIN
XOUT
28
29
X1_KBC
X2_KBC
P40/XCOUT
P41/XCIN
27
26
KBC_EXTSMI
RESET#
25
PCI_RSTNS#
CNVSS
VSS
AVSS
24
30
73
P54,P55,P43,P50 are
wake-up event
inputs when KBC in
standby mode
4
5
6
7
8
9
P75/INT41
P74/INT31
P73/INT21
P72
P71
P70
2
3
P77/SCL
P76/SDA
0.1U
0.1U
22,30,31,35,37,38,42
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,29,30,31,34,36,38,39,41,48,61,70
5,17,20,22,23,29,32,42,46,48,70
9,16,18,25,31,38,40,41
CON16
14,18,23,24,29,36,37,38,39,40,41,61
68,69,70,71
SIDE2 30
28 28
27
27
26
26
25
25
24 24
23 23
22 22
21 21
20 20
19 19
18 18
17
17
16 16
15 15
14 14
13 13
12 12
11 11
10 10
9 9
8 8
7 7
6 6
5 5
4
4
3
3
2 2
1 1
SIDE1 29
SCR_LED#
Matrix
US
UK
JP
+3V
R319
R320
10K
10K
KBDDT0
KBDDT1
Internal_KB_CON
+3VS
R322
R323
10K
10K
KBC_GA20
D15 1SS355
2
1
HA20GATE 22
KBCPURST_3Q
D16 1SS355
2
1
KBDCPURST 22
+5VS
KBSCI_3Q
KB_SCI#
22
Q13
2N7002
PANLOCK_LED 41
X1_KBC
C340 10P
R324
X3
2
1M
8MHZ
X2_KBC
+5VLCM
KSI1
KSO7
KSI7
KSO0
KSI6
KSO9
KSI5
KSO3
KSI4
KSO1
KSI2
KSI3
KSO5
KSO13
KSI0
KSO2
KSO4
KSO8
KSO6
KSO11
KSO10
KSO12
KSO14
KSO15
KBDDT0
1
0
1
NUM_LED# 41
CAP_LED# 41
SET_PCIRSTNS#
80mA
+5VLCM
KBDDT1
1
1
0
C341 10P
+3VSUS
+3V
+5V
R326
R327
4.7K
4.7K
+3V
R325
C342
39,69
4.7K
6
SMC_BAT
BAT_LLOW#_OC
FAN1_TACH
1
+5VS
Q14A
UM6K1N
39,69
SMD_BAT
1
3
5
7
+5VS
10K
10K
10K
10K
2
4
6
8
RN33A
RN33B
RN33C
RN33D
EXTSMI#_3A 22
3
KBC_EXTSMI
4
Q14B
UM6K1N
R332
4.7K
4.7K
R333
INTCLK_5S
INTDATA_5S
10K
41
41
BAT_LEARN
R331
INTCLK_5S
INTDATA_5S
R734
100K
LPCKBC_RST#
U14
1 B
SET_PCIRSTNS#
2 A
D
Q15
R330
2N7002
47K
1
G
2 S
3 GND
VCC 5
4
Y
74LVC1G32GV
0.1U
PCI_RSTNS#
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
28
OF
55
KBC 38857
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
+3VSUS
+3VSUS
+3VS
RN31A
RN31B
2.2K
2.2K
+3VS
RN31D
RN31C
2.2K
2.2K
+5VS
Q18A
UM6K1N
6
22,31 SMB_CLK_SB
SCL_3S
5,16
Termal Sensor,
TPM
MCP51
Q18B
UM6K1N
3
22,31 SMB_DAT_SB
+3VA
SDA_3S
5,16
+3VA
22,38,41,42,48,71
+3VSUS
5,17,20,22,23,28,32,42,46,48,70
+0.9VS
+0.9VS
16
+1.5VS
+2.5VS
+3VS
+5VS
+12VS
+1.5VS
+2.5VS
+3VS
+5VS
+12VS
19,21,22,23,30,31,38,48
5,11,14,15,16,18,38,48
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,30,31,34,36,38,39,41,48,61,70
14,18,23,24,28,36,37,38,39,40,41,61
16,17
+1.8V
+3V
+5V
+12V
5,7,8,9,10,38,65
22,28,30,31,35,37,38,42
9,16,18,25,28,31,38,40,41
25,40
+VCORE
+VCORE
5,7,61
+5VLCM
+5VLCM
28,68,69,70,71
+3VSUS
C
+1.8V
+3V
+5V
+12V
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
29
OF
55
SM BUS & POWER PORT

C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
+3VS
+3V +1.5VS
CON19
WLAN_WAKE#
R359
0
R360
0
38 CH_DATA_A
38
CH_CLK_A
13 CLK_REQ_MINICARD#
13 CLK_PCIE_MINICARD#
13 CLK_PCIE_MINICARD
13 PCIE_RXN1_MINICARD
13 PCIE_RXP1_MINICARD
13 PCIE_TXN1_MINICARD
13 PCIE_TXP1_MINICARD
2
3
WAKE#
BT_DATA
BT_CHCLK
CLKREQ#
GND1
REFCLKREFCLK+
GND2
3.3V_1
GND7
1.5V_1
Reserved11
Reserved12
Reserved13
Reserved14
Reserved15
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Reserved1
Reserved2
GND3
PERn0
PERp0
GND4
GND5
PETn0
PETp0
GND6
Reserved3
Reserved4
Reserved5
Reserved6
Reserved7
Reserved8
Reserved9
Reserved10
GND8
W_DISABLE#
PERST#
3.3Vaux
GND9
1.5V_2
Reserved16
Reserved17
GND10
Reserved18
Reserved19
GND11
NC1
LED_WLAN#
NC2
1.5V_3
GND12
3.3V_2
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
NP_NC2
NP_NC1
56
55
53
54
CON20
3
1
3
5
7
9
11
13
15
P_GND2
GND
GND13
GND14
R123
0_*
WLAN_LED#
802_ON/OFF# 41
PE_RST# 13,16
T218
MINI_PCI_LATCH_52P
+3V
P_GND1
MINI_PCI_LATCH_3P
WLAN_WAKE#
22,31 PCIE_WAKE#
+3VS
+3V
Q100
2N7002
C375
C376
C377
C378
C379
0.1U
0.1U
0.1U
0.1U
0.1U
C380
C381
C382
C383
C384
10U/10V
0.1U
0.1U
0.1U
0.1U
+1.5VS
+1.5VS
+3V
+3VS
+1.5VS
+3V
+3VS
19,21,22,23,31,38,48
22,28,31,35,37,38,42
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,31,34,36,38,39,41,48,61,70
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
30
OF
55
MINI CARD
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
CP_PE#
PCIE_WAKE#
SMB_CLK_SB
SMB_DAT_SB
1
3
5
7
0
0
0
0
2
4
6
8
RN8A
RN8B
RN8C
RN8D
CP_PE#_R
PCIE_WAKE#_R
SMB_CLK_SB_R
SMB_DAT_SB_R
+3V
22
R119
USB_PN6
USB_P6-
U51
22
R118
USB_PP6
D57
B0
B1
B2
B3
B4
D0
D1
D2
D3
D4
5
9
15
19
23
DEBUG_EN#
1
13
BE#
BX
VCC
GND
24
12
CP_PE#
D58
90ohm Diff. pair

RSB6.8S_*
PCIE_WAKE#
SMB_CLK_SB
SMB_DAT_SB
4
8
14
18
22
3
7
11
17
21
20,26 CLK_SIOPCI
20,26,27,28,38 LPC_FRAME#
20,26,27,28,38 LPC_AD0
20,26,27,28,38 LPC_AD1
20,26,27,28,38 LPC_AD2
USB_P6+
A0
A1
A2
A3
A4
SN74CBT3383PWR_*
C0 2
C1 6
10
C2
C3 16
C4 20
22,30 PCIE_WAKE#
22,29 SMB_CLK_SB
22,29 SMB_DAT_SB
RSB6.8S_*
CP_PE#_R
CLK_REQ#
PCIE_WAKE#_R
SMB_CLK_SB_R
SMB_DAT_SB_R
R754
100K_*
DEBUG_EN#
3
C
Q17
PMBS3904_*
E
2
B 1 R771
47K_* 2
D65
1SS355_*
1
C696
2200PF/50V_*
PERST#
C697
R755
0.1UF/16V_*
10K_*
+5V
C695
0.1U_*
CON37
D59
2
42,46,67 VSUS_ON
USB_P6USB_P6+
CP_USB#
SHDN#
1SS355_*
U48
22,32,42,67,70 SUSB#
PERST#
SHDN#
R758
R757
R756
SMB_CLK_SB_R
SMB_DAT_SB_R
20,26,27,28,38 LPC_AD3
27,28,38 DIS_FWH
R5538D001
Int.PU 1
Int.PU 20
1K
8
STBY#
SHDN#
PERST#
OC#
1.5VOUT_1
1.5VOUT_2
19
11
13
2
4
3.3VIN_1
3.3VIN_2
AUXOUT
15
OD
T83
+1.5VS_PE
+1.5VS_PE
PCIE_WAKE#_R
+3V_PE
2A
+3VS
+1.5VS
+3V
1A
14
12
0.7A
17
Int.PU 6
7
21
5,20 PCIRST_NEWC#
B
1.5VIN_1
1.5VIN_2
AUXIN
SYSRST#
GND1
GND2
3.3VOUT_1
3.3VOUT_2
CPPE#
CPUSB#
RCLKEN
NC
+3V_PE
3
5
10
9
18
33_*
33_*
PERST#
+3VS_PE
CLK_REQ#
CP_PE#_R
+3VS_PE
CP_PE#
Int.PU
CP_USB#
13 CLK_PCIE_NEWCARD#
13 CLK_PCIE_NEWCARD
PRSNT_NEWCARD# 13
Int.PU
Int.PU
13 PCIE_RXN2_NEWCARD
13 PCIE_RXP2_NEWCARD
16
13 PCIE_TXN2_NEWCARD
13 PCIE_TXP2_NEWCARD
+3VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND1
GND5
USB_DUSB_D+ NP_NC1
CPUSB#
RESERVED1
RESERVED2
SMBCLK
SMBDATA
+1.5V_1
+1.5V_2
WAKE#
+3.3VAUX
PERST#
+3.3V_1
+3.3V_2
CLKREQ#
CPPE#
REFCLKREFCLK+
GND2
PERn0
PERp0
GND3
PETn0
NP_NC2
PETp0
GND6
GND4
29
27
CON41
P_GND2
P_GND1
2
1
CARD_EJECTOR_2P_*
28
30
EXPRESS_CARD_26P
R909
R910
22KOhm
22KOhm
+3VS_PE
CLK_REQ_NEWCARD#
+3VS
+3V
+1.5VS
C666
C667
C668
C669
C670
10U/10V
0.1U
10U/10V
0.1U
10U/10V
0.1U
+3V_PE
+1.5VS_PE
C659
C660
C661
C662
C663
C664
10U/10V
0.1U
10U/10V
0.1U
10U/10V
0.1U
Q104
2N7002
1
C665
13
2 S
CLK_REQ#
+1.5VS
+3VS
+3V
+1.5VS
+3VS
+3V
19,21,22,23,30,38,48
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,34,36,38,39,41,48,61,70
22,28,30,35,37,38,42
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
31
OF
55
NEW CARD
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
PCI_AD[31:0] 20,34
+3V_LAN
1
R948
PCI_C/BE#0 20,34
PCI_C/BE#1 20,34
PCI_PAR 20,34
PCI_SERR# 20,34
2
0Ohm
PCI_PERR# 20,34
U16
LAN_EECS
LAN_EESK
LAN_EEDI
LAN_EEDO
1
2
3
4
CS VCC
SK
DC
DI ORG
DO GND
8
7
6
5
PCI_STOP# 20,34
PCI_DEVSEL# 20,34
PCI_TRDY# 20,34
C360
0.1UF/16V
1
R949
AT93C46
2
10KOhm
/*
U17
C933
C934
C935
C936
0.01UF/16V 0.01UF/16V 0.01UF/16V 0.01UF/16V

PCI_AD1
PCI_AD0
+3V_LAN
23
R950 1 10KOhm 2
LAN_EEDO
LAN_EEDI
R951 1 10KOhm_*
2
LAN_EESK
XTAL1
BUF_25M
XTAL2
1
C366
X4
CTRL12
DVDD_A
25Mhz_*
C367
27P_*
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
LAN_EECS
27P_*
PCIAD1
PCIAD0
LANWAKE
EECS
VDD33_6
EEDO
EEDI
VDD12_7
EESK
GND8
LED3
LED2
LED1
VDD12_8
LED0
GND9
VSSPST7
AVDDH2
XTAL1
XTAL2
VSS4
VSS5
CTRL12
VDD12_9
RSET
VSS6
GND
VDD12_4
IRDYB
GND4
FRAMEB
CBEB2
PCIAD16
PCIAD17
PCIAD18
VDD33_2
PCIAD19
VDD12_3
PCIAD20
GND3
VSSPST2
PCIAD21
PCIAD22
GND2
PCIAD23
IDSEL
VDD12_2
CBEB3
PCIAD24
PCIAD25
VDD33_1
PCIAD26
PCIAD27
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
PCI_IRDY#
8100:NO STUFF
8110:STUFF
20,34
PCI_FRAME# 20,34
PCI_C/BE#2 20,34
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
1 49.9Ohm
1 49.9Ohm
1 49.9Ohm
1 49.9Ohm
2 R355
2 R356
2 R357
2 R358
1 49.9Ohm
1 49.9Ohm
1 49.9Ohm
1 49.9Ohm
8100:NO STUFF
8110:STUFF
PCI_AD21
PCI_AD22
PCI_AD23
1 R918
2
100Ohm
L_TRDM2
L_TRDP2
L_TRDM3
L_TRDP3
L_TDN
L_TDP
L_RDN
L_RDP
33
33
33
33
L_TRDM2
L_TRDP2
L_TRDM3
L_TRDP3
33
33
33
33
PCI_AD17
PCI_C/BE#3 20,34
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
RTL8100C
R953
8100:5.6KOHM(1%)
8110:2.49KOHM(1%)
L_TDN
L_TDP
L_RDN
L_RDP
2 R350
2 R351
2 R352
2 R354
RTL8110SB
RTL8110SBL
2.49KOhm
AVDDH
N/A
3.3AVDD
PIN 10/120
71mA
GND
AVDDH
DVDD
V_12P
2.5AVDD
3.3AVDD
AVDDL
3.3AVDD
2.5AVDD
15mA
+3V_LAN
V_DAC
R952
0Ohm 8100:NOT SYUFF
8110:STUFF
AVDDL
N/A
DVDD
2.5VDD
PCI_PME# 20,34
PCI_REQ#1 20
PCI_GNT#1 20
CLK_LANPCI 20
PCIRST_LAN# 20
PCI_INTC# 20
L_TDP
L_TDN
L_RDP
L_RDN
L_TRDP2
L_TRDM2
L_TRDP3
L_TRDM3
1 R6
R9541
V_DAC
2
0Ohm
SUSB#
DVDD_A
N/A
PIN 12
307mA PIN 3/7/20/16
2.5AVDD
PIN 24/32/45/54/64
/78/99/110/116
1.2VDD
226mA
1.2AVDD
PIN 126
11mA
22,31,42,67,70
8100:NO STUFF
8110:STUFF
2 0Ohm
8100:NO STUFF
8110:STUFF
PIN 10/120
R942
L48 1
+3VSUS
AVDDH
+3V_LAN
8100:NO STUFF
8110:STUFF
0Ohm
120Ohm/100Mhz
DVDD_A
8100:STUFF
L49
8110:NO STUFF 120Ohm/100Mhz_*
1
2
L3
700mA
1
+3V_LAN
C369
120Ohm/100Mhz
8100:NO STUFF
R943
8110:STUFF
1
C368
10UF/10V
22UF/6.3V
PIN 3/7/20/16
8100/3.3V
8110/2.5V
AVDDL
C924
0.1UF/16V
C925
0.1UF/16V
C926
0.1UF/16V
C365
0.1UF/16V
C364
0.1UF/16V
C927
10UF/10V
C363
0.1UF/16V
C361
0.1UF/16V
0Ohm
Q51
2SB772PT
PIN 24/32/45/54/64
/78/99/110/116
R944
1
DVDD
8100/2.5V
8110/1.2V
0Ohm_*
CTRL25
8100:STUFF
8110:NO STUFF
R955
2 V_12P
0Ohm_*
8100:STUFF
8110:NO STUFF
C937
22UF/6.3V
R946
PIN 12
8100/ 2.5V
8110/ 3.3V
AVDDL
AVDDH
V_12P
C362
0.1UF/16V
C370
22UF/6.3V
C915
0.1UF/16V
C921
0.1UF/16V
C951
0.1UF/16V
C916
0.1UF/16V
C928
0.1UF/16V
C917
0.1UF/16V
C932
0.1UF/16V
C931
0.1UF/16V
C914
0.1UF/16V
C918
0.1UF/16V
C922
0.1UF/16V
C371
22UF/6.3V
C919
0.1UF/16V
C372
22UF/6.3V
0Ohm_*
DVDD
Q52
2SB772PT
R947
AVDDL
1
R45
2
0Ohm
1
R945
2
0Ohm
0Ohm
C939
22UF/6.3V
8100/ N/A
8110/1.2V
C938
22UF/6.3V
CTRL12
DVDD_A
C923
0.1UF/16V
PIN
126
C920
0.1UF/16V
C913
0.1UF/16V
8100:NO STUFF
8110:STUFF
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
32
OF
DESCRIPTION:
55
LAN -- RTL8110CL
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
U59
L_RDN
L_RDP
RDC
1
3
2
L_TDN
L_TDP
6
8
7
4
5
TD+
TX+
TDTXTDCT
TXCT
HA003
RD+
RX+
RDRXRDCT
RXCT
TAIMIC
NC1
NC3
NC2
NC4
LFE8505
16
14
15
L_RXN
L_RXP
L_CMT1
11
9
10
L_TXN
L_TXP
L_CMT0
12
13
D
_*
8100:NO STUFF
8110:STUFF
V_DAC
R7
1
U15
RDC0Ohm
R150
24 MCT1
TCT1 1
L_CMT3
LTXN
L_TXN
L42
32
32
L_TRDM3
TD1+ 2
L_TRDP3
TD1- 3
23 MX1+
22 MX121 MCT2
L_TRLP3
L_CMT2
20 MX2+
L_TRLM2
R149
R148
TD2- 6
L_TRDP2
TCT3 7
19 MX218 MCT3
L_TRLP2
L_CMT1
17 MX3+
L_RXN
32
L_RDN
32
L_RDP
TD3- 9
R147
R146
L_TDN
TD4+ 11
L_TDP
TD4- 12
L_RXP
L_CMT0
14 MX4+
L_TXN
L_TRLM3
13 MX4-
L_TXP
L_TRLP3
LG_2402S_1
C941
1000PF/3KV 1000PF/3KV
180OHM/100MHz_*
RING_J
TIP_J
LTXP
LTXN
LRXP
LTRLP2
LTRLM2
LRXN
LTRLP3
LTRLM3
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
SIDE1
P_GND1
NP_NC1
17
15
13
NP_NC2
P_GND2
SIDE2
14
16
18
180OHM/100MHz_*
LTRLP2
R145
R143
0
LTRLM3
L45
0.01UF/25V
C940
C674
2 1KOhm/100Mhz
2 1KOhm/100Mhz
MODULAR_JACK_12P
L_TRLP2
16 MX315 MCT4
TCT4 10
32
C675
L46 1
L47 1
LTRLM2
L44
32
RING
TIP
LRXP
L_TRLM2
TD3+ 8
3
1
2
4
MODEM_CON
L43
L_RXP
32
SIDE1
1
2
SIDE2
LRXN
L_RXN
TD2+ 5
L_TRDM2
CON17
CON18
LTXP
L_TXP
TCT2 4
32
180OHM/100MHz_*
L_TRLM3
180OHM/100MHz_*
LTRLP3
R142
C942
0.01UF/25V
8100:NO STUFF
8110:STUFF
0.01UF/25V
C943
8100:0.1UF
8110:0.01UF
L_CMT3
L_CMT2
L_CMT1
L_CMT0
0.01UF/25V
RN32A
75Ohm 2
RN32B
75Ohm 4
RN32C
75Ohm 6
RN32D
75Ohm 8
1
3
5
7
FGND1S
Co- layout
C944
1000PF/50V
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
33
OF
DESCRIPTION:
55
RJ45 & RJ11

3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
+3VS
+3VS
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,36,38,39,41,48,61,70
L50 120/400mA
U18A
R5C832
AVCC_PHY_CB
+3VS
C385
C386
C387
C388
10U/10V
0.1U
0.1U
0.01U/X7R
U18B
C389
C390
C391
10
20
27
32
41
128
10U/10V
0.1U
0.1U
61
C397
16
34
64
114
120
+3VS
C396
0.1U
Open Drain:
PME#,
SERR#,
INTn#
20,32 PCI_AD[31:0]
20,32
PCI_PAR
20,32 PCI_C/BE#[3:0]
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
CB_IDSEL_J
20
PCI_REQ#0
20
PCI_GNT#0
20,32 PCI_FRAME#
20,32 PCI_IRDY#
20,32 PCI_TRDY#
20,32 PCI_DEVSEL#
20,32 PCI_STOP#
20,32 PCI_PERR#
20,32 PCI_SERR#
CB_GBRST#
C393
C392
0.1U
10U/10V
C431 18P
VCC_ROUT1
VCC_ROUT2
VCC_ROUT3
VCC_ROUT4
VCC_ROUT5
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL
124
123
23
24
25
26
29
30
31
REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
X1_1394 94
TPBIAS0
113
C402
C400
1000P
0.1U
0.1U
10U/10V
XI
X5
24.576Mhz
C430 18P
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
33
7
21
35
45
8
AVCC_PHY3V_1
AVCC_PHY3V_2
AVCC_PHY3V_3
AVCC_PHY3V_4
+3VS
C394
TPBIAS0
C433 0.01U/X7R
C434 0.33U
VCC_RIN
AGND1
AGND3
AGND2
AGND4
AGND5
HWSPND#
X2_1394 95
86
+3VS
4
13
22
28
54
62
63
68
118
122
0.01U/X7R
1394_FIL 96
U22
8
7
6
5
A0 VCC
A1
WP
A2 SCL
GND SDA
MSEN
99
102
103
107
111
1394_SCL
1394_SDA
R362
TPAN0
108
69
56_1
10K_1
FIL0
101
REXT
1394_REF 100
VREF
TPAP0
109
R364
R361
100K
UDIO3
UDIO4
65
59
1394_SCL
1394_SDA
R383
R384
UDIO2
56
40
TPA0-_0
40
TPA0+_0
40
56_1
56_1
1.CLOSE TO R5C841
2.The area is as compact as possible,length<10 mm
3.TPA Pair and TPB pair mismatch<2.5mm
4.No via recommend , maxmium is one.
5.Total length<50 mm
6.Differential impedance is 110+/- 6 ohm
7.TPA Pair trace or TPB pair trace mismatch < 1.25mm
MDIO17
87
MDIO17
35
MDIO16
92
MDIO16
35
MDIO15
89
MDIO15
35
MDIO14
91
MDIO14
35
MDIO13
90
MDIO13
35
MDIO12
93
MDIO12
35
MDIO11
81
MDIO11
35
MDIO10
82
MDIO10
35
MDIO05
75
MDIO05
35
MDIO08
88
MDIO08
35
MDIO19
83
MDIO19
35
MDIO18
85
MDIO18
35
MDIO02
78
MDIO02
35
MDIO03
77
MDIO03
35
MDIO00
80
MDIO00
35
+3VS
10K
10K
60
72
40
TPB0+_0
10K
10K
R369
TPB0-_0
R368
10K
57
R392
5.11K_1
0.01U/X7R
CB_HWSUSP#
58
R393
R391
C399
UDIO5
INTB#
105
R385
56_1
C435 270P
+3VS
55
INTA#
104
TPBP0
AT24C02N
XDEN
UDIO0/SRIRQ#
TPBN0
R386
C424
C432 0.1U
1
2
3
4
XO
+3VS
UDIO1
115
PCI_INTA# 20
116
PCI_INTB# 20
71
119
GBRST#
PCIRST#
MDIO01
79
MDIO01
35
PCIRST_CB#
20
CLK_CBPCI
121
PCICLK
MDIO09
84
MDIO09
35
MDIO04
76
MDIO04_SD/MS/XDPWR 35
20,26,28,38 PM_CLKRUN#
117
C405
C406
10P_*
10P
PME#
TEST
66
R371
20
70
4
67
CLOSE TO R5C832
VCC_MD
VCC_3V
0.1U
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
+3VS
R5C832
VCC_PCI3V_1
VCC_PCI3V_2
VCC_PCI3V_3
VCC_PCI3V_4
VCC_PCI3V_5
VCC_PCI3V_6
98
106
110
112
C401
10K
CLKRUN#
MDIO06
97
RSV
MDIO07
74
73
+3VS
Q105
2N7002_*
20,32
PCI_PME#
GBRST# POWER SEQ
+3V ==> (GBRST#/CB_HWSUSP#) ==>PCIRST#
PCI_AD16
R374
100
CB_GBRST#
R375
10K
CB_IDSEL_J
+3VS
+3VS ==> CB_GBRST#

1ms <
T
< 100ms
C407 1UF/X7R
H/W SUSPEND# POWER SEQ :

SUSPEND : CB_HWSUSP# LO=> PCIRST# LO=> +3VS OFF
RESUME : +3VS ON => PCIRST# HI=> CB_HWSUSP# HI
CB_HWSUSP#
1
D18
2
1SS355
CB_SD#
22
5
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
34
OF
DESCRIPTION:
55
PCI R5C832
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
34
34
34
34
34
34
34
34
34
34
34
34
34
MDIO05
MDIO08
MDIO19
MDIO18
MDIO02
34
MDIO03
34
MDIO00
34
MDIO01
34
MDIO09
+3V
MDIO17_XDDAT7
MDIO16_XDDAT6
MDIO15_XDDAT5
MDIO14_XDDAT4
MDIO13_SD/MS/XDDAT3
MDIO12_SD/MS/XDDAT2
MDIO11_SD/MS/XDDAT1
MDIO10_SD/MS/XDDAT0
MDIO17
MDIO16
MDIO15
MDIO14
MDIO13
MDIO12
MDIO11
MDIO10
R396
2
10K
MDIO05_XDWP#
MDIO08_SDCMD_MSBS_XDWE#
MDIO19_XDALE
MDIO18_XDCLE
MDIO02_XDCE#
11
3
Q28
SI2301BDS
+MC_VCC
3 D
Q29
2N7002
34 MDIO04_SD/MS/XDPWR
2 S
MDIO03_SDWP_XDR/B#
Place as
close to
C436
C437
R397
0.1U
0.1U
150K card reader
socket as
possible
MDIO00_SDCD#_XDCD#
MDIO01_MSCD#_XDCD#
MDIO09_SD/MSCLK_XDRE#
+MC_VCC
CON23
2
SD_DAT2
MDIO13_SD/MS/XDDAT3
Solve MS Duo Adaptor

short problem
2N7002
MDIO11_SD/MS/XDDAT1
MDIO13_SD/MS/XDDAT3
MSCD#
MDIO12_SD/MS/XDDAT2
MDIO10_SD/MS/XDDAT0
MDIO11_SD/MS/XDDAT1
SD_DAT1
Q23
2N7002
MDIO12_SD/MS/XDDAT2
SD_DAT2
Q24
2N7002
+MC_VCC
+12V
MDIO10_SD/MS/XDDAT0
SD_DAT1
XD_VCC
R394
10K
R395
10K
SD_CD
Q25
SDCD#
XD_CD
3
3
Q26
2N7002
1
G
34 MDIO00_SDCD#_XDCD#
2N7002
G
XD_VCC
SD_CARD_38P
NP_NC2
DAT2
CD/DAT3
CMD
VSS1
VSS2
VCC1
SCLK
Reserved1
INS
Reserved2
SDIO
VCC2
BS
VSS3
VDD
CLK
VSS4
DAT0
DAT1
GND1
CD
R/-B
-RE
-CE
CLE
ALE
-WE
-WP
GND2
D0
D1
D2
D3
D4
D5
D6
D7
VCC3
X1
X0
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
X16
X17
X18
XD_CD#
MDIO03_SDWP_XDR/B#
MDIO02_XDCE#
MDIO18_XDCLE
MDIO19_XDALE
MDIO05_XDWP#
MDIO10_SD/MS/XDDAT0
MDIO11_SD/MS/XDDAT1
MDIO12_SD/MS/XDDAT2
MDIO13_SD/MS/XDDAT3
MDIO14_XDDAT4
MDIO15_XDDAT5
MDIO16_XDDAT6
MDIO17_XDDAT7
NP_NC1
Q27
XD_CD# 1
2 S
S9
S1
S2
S3
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
S4
S5
S6
S7
S8
34 MDIO01_MSCD#_XDCD#
2 S
SDCD#
MDIO03_SDWP_XDR/B#
MSCD#
D21
C438
C439
C440
270P_*
270P_*
270P_*
SDCD#
MSCD#
XD_CD#
DAN202K
+3V
+12V
+3V
+12V
22,28,30,31,37,38,42
25,37,40,67
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
35
OF
DESCRIPTION:
55
4 IN 1 CONN
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
Vout=1.25*(1+(100K/34.8K)= 4.84V
+5VAUD
+5VS
+5VAUD
U25
G913CF
C463
1
2
3
C462
10UF/10V
C460
SHDN#
GND
IN
20PF/50V
2
R412
100K_1
SET
OUT
0.1UF/16V
C465
AGND_A
37
R_36_A
EAPD
R674
C472 1UF/X7R
L_35_A
4.7K
C473 1UF/X7R
OUTR_A
37
OUTL_A
37
1UF/16V
L118
1
R413
C468
34.8K_1
1UF/16V
0Ohm
2
HP_R_CODEC 37
37
SPDIF_A
AGND_A
HP_L_CODEC 37
+3VS
C469
C470
C471
10U/10V
0.1U
0.1U
U26
AGND_A
R2.0
AD1986AJCPZ
+5VAUD
R2.1
R414
1
2
3
4
5
6
7
8
9
10
11
12
10K
T107
22 ACZ_SDOUT_AUD
22 ACZ_BCLK_AUD
22 ACZ_SDIN0_AUD
1
R416
2
33Ohm
22 ACZ_SYNC_AUD
22,37 ACZ_RST#_AUD
DVDD1
AC97CK
GPO
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET#
PCBEEP
SURR_OUT_R
SURR_OUT_L
AVDD3
VREF_OUT/C/LFE
LFE_OUT
CENTER_OUT
AVSS2
VREF_OUT/LINE_IN
VREF_OUT/MIC_1/2
VREF_FILT
AVSS1
AVDD1
36
35
34
33
32
31
30
29
28
27
26
25
C474
22PF/50V_*
VREFOUT_I 37
C67
1UF/X7R_*
C66
1UF/X7R_*
MIC_IN_A
Trace
wide=10 mils
VREFOUT 37
C475
C476
C477
C478
10U/10V
1UF/X7R
0.1U
0.1U_*
_*
AGND_A
3
22
1
R418
SPKR_SB
2
47KOhm
PC_BEEP_C
2
C482
AGND_A
AGND_A
1
0.1UF/16V
R420
4.7KOhm
AGND_AAGND_A
C912
0.01UF/50V
R675
R676
+5VAUD
R2.1
2.2K
2.2K
C479 1UF/X7R
R76
0_*
C480 1UF/X7R
R77
R419
47K_1
C484 1UF/X7R
40 MIC_IN#_JACK
2
R59
1
20KOhm _*
R58
40.2KOhm _*
37
MIC_IN_A 37
CD_L_A
24
R423
Trace
wide=10 mils
R2.0
C967
1UF/10V_*
+5VAUD
EXT_MIC
C485 1UF/X7R
47K_1
AGND_A
R424
23.7K_1
CD_GND_A 24
4
R425
AGND_A
23.7K_1
R79
100KOhm_*
Q125B
5
C486 1UF/X7R
AGND_A
R426
47K_1
CD_R_A
24
UM6K1N_*
R427
37,40 HP_IN#_JACK
Q125A
UM6K1N_*
47K_1
For EMI
AGND_A
R912
AGND_A
AGND_A
R78
2 0Ohm
L57
2 120Ohm/100Mhz_*
L58
2 120Ohm/100Mhz_*
1
+3VS
+5V
+5VS
+5VAUD
0Ohm _*
+3VS
+5V
+5VS
+5VAUD
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,38,39,41,48,61,70
9,16,18,25,28,31,38,40,41
14,18,23,24,28,29,37,38,39,40,41,61
37
AGND_A
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
36
OF
DESCRIPTION:
55
CODEC_ADI1986A
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
+5VS
C652 100P
R428
36
12.7K_1
2
+5VS
U28
36
R430
OUTR_A
10K_1
C490 1UF/X7R
21
Q33
SI2301BDS
G1420F31UF
RLINEIN
20
RHPIN
19
RBYPASS
22
SPKR+
ROUT-
15
SPKR-
RVDD
18
ROUT+
R431
100K
3
G
L60
80/2A
C491
C492
C493
+5VAMP
C494
R432
100K
11
MUTE
10U/10V
0.1U
10U/10V
0.1U
R751
0_*
8
6
AGND_A
AGND_A
5
36
R433
OUTL_A
10K_1
TJ
MUTE IN
HP/LINE#
SHUTDOWN
LVDD
LBYPASS
NC1
NC2
16
LHPIN
LOUT+
SPKL+
LLINEIN
LOUT-
10
SPKL-
SPKR+ 1
1
SPKL+
R66 0Ohm_*
R67 0Ohm
HP_L_SW
2
2
1
1
36 HP_L_CODEC
CON27
SPKRSPKR+
SPKLSPKL+
17
23
47K
Q35A
UM6K1N
S 2
G
1
R441
D25
100K
1SS355
100K
2.2M
R0603
3
C501
EAPD
2
D
Q39B
UM6K1N
Q39A
UM6K1N
1
CE5
2 AOUTR_C
100U/6.3V
R440
100 2_AJK_R
R0603
1
CE6
2 AOUTL_C
100U/6.3V
R442
100 2_AJK_L
R0603
C504
L68
1K/300mA
L69
1K/300mA
R445
R446
C502
C503
1K
R0603
1K
R0603
100P
R761
R759
100P
1UF/X7R
AGND_A
SIDE1
1
2
SIDE2
+5VAUD
R677
VREFOUT_I
OPTIC_VCC_JACK 40
SPDIF_O_JACK 40
C497
C500
C498
C499
0.1U
100P
100P
100P
L70
1K/300mA
3
1
2
4
INT_MIC_CON
EXT_MIC
R447
1K/300mA
R678
C508
22K_1
1UF/X7R
AGND_A
INT_MIC_JACK 40
EXT_MIC_JACK 40
C507
C506
100P
100P
AGND_A
U29A
LM358MX
+5VAUD
AGND_A
36
1K/300mA
L71
100P_*
0_*
AGND_A
L99
C698
INT_MIC_CON
22K_1
Digital Area
36
HP_IN#_JACK 36,40
D24
RB751V_40
1
2
CON30
+5VAUD
2 S
R2.0
OPTIC_HP_JACK 40
HP_JACK_R 40
HP_JACK_L 40
HP_L_SW
C505 0.1U
4
2 S
Q66
2N7002
EAPD
D69
36
47K
R760
HP_JACK_R
HP_JACK_L
HP_IN#
HP_IN#
OPTIC_VCC
SPDIF_O
Q37
2N7002
R435
47K
AGND_A
Q36
2N7002
1UF/X7R
NC1
R438
3 DEPOP#
1SS355_*
R434
OPTIC_HP
Q35B
UM6K1N
+12V
R2.0
MUTE
D26
DAP202K
NC2
4
3
2
1
R437
AGND_A
DEPOP#
R670
4
3
2
1
12.7K_1
HP_R_SW
OP_SD#
SPKR-_MB_CON
SPKR+_MB_CON
SPKL-_MB_CON
SPKL+_MB_CON
80/2A
80/2A
80/2A
80/2A
SPEAKER_CON
HP_R_SW
23
L61
L62
L63
L64
+5VAMP
+3V
2 S
C496 100P
R68 0Ohm_*
22,36 ACZ_RST#_AUD
SE/BTL#
36 HP_R_CODEC
SPDIF_O
4
Y
SN74AHCT1G08DBVR
3 GND
+5VAMP
R436
R65 0Ohm
2
2
0.1U
HP_IN#
14
AUDIO OUT
AMP
C489
100K
SE/BTL#
SE/BTL#
MUTE OUT
R429
Q34
2N7002
OPTIC_HP
VCC 5
2 B
+5VAMP
+5VAMP
+5VS
U27
1 A
SPDIF_A
OPTIC_VCC
AGND_A
MIC_IN_A
U29B
LM358MX
R448
R449
R450
1KOhm
1K
R0603
2.2K
C509 1UF/X7R
R71
0Ohm_*
MIC_JACK
R72
0Ohm
+5VAUD
VREFOUT
R81
VREFOUT 36
R69
4.7KOhm_*
22K_1_*
+3V
+5VAUD
+12V
+5VS
+3V
+5VAUD
+12V
+5VS
22,28,30,31,35,38,42
36
25,35,40,67
14,18,23,24,28,29,36,38,39,40,41,61
AGND_A
R451
15KOhm
EXT_MIC
36
C510 100P
R82
22K_1_*
R2.0
AGND_A
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
37
OF
DESCRIPTION:
55
AUDIO_AMP(G1420)
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
+3V
CON31
22 ACZ_SDOUT_MDC
22 ACZ_SYNC_MDC
22 ACZ_SDIN1_MDC
22 ACZ_RST#_MDC
R452
39
1
3
5
7
9
11
1
3
5
7
9
11
2
4
6
8
10
12
CON32
2
4
6
8
10
12
22
22
+3V
30
CH_CLK_A
22 BT_ON/OFF#
30
CH_DATA_A
ACZ_BCLK_MDC 22
BTOB_CON_12P
41
C511
11
1
2
3
4
5
6
7
8
9
10
12
USB_PP2
USB_PN2
R182
R183
BT_LED
0_*
0
C512
0.1U
HOLD1
GND1
USB_D+
USB_DRSVD
CLK
HW_DIS#
DATA
+3.3V
LED
GND2
HOLD2
BLUE_TOOTH_CON
0.1U
Azalia MDC MODEM CON
Bluetooth Module CON
L95
+5V
CON39
1 1
3 3
5 5
7
7
9
9
11 11
13 13
15 15
17
17
19
19
20 CLK_TPMPCI
20,26,27,28,31 LPC_FRAME#
20 LPCTPM_RST#
20,26,27,28,31 LPC_AD3
+3VS
20,26,27,28,31 LPC_AD0
+3V
C
22,26 PM_SUS_STAT#
TPM_CON
2 2
4 4
6 6
8
8
10
10
12 12
14 14
16 16
18
18
20
20
SUS_CLK 22
+3VA
LPC_AD2 20,26,27,28,31
LPC_AD1 20,26,27,28,31
R731
USBP3USBP3+
22
1
2
3
4
USB_PP3
R453
+5V
Q42A
UM6K1N
2
330
R458
41,42
PM_SUSB
+5VS
B
Q40A
UM6K1N_*
2
+1.8V
330
R454
330
+1.5VS
R459
Q40B
UM6K1N_*
5
330_*
R455
330_*
3
Q43
2N7002_*
1
G
Camera_CON
Camera Module CON
Q42B
UM6K1N
5
+1.5VS
+1.8V
+2.5VS
+3V
+3VS
+5V
+5VS
330
+1.5VS
+1.8V
+2.5VS
+3V
+3VS
+5V
+5VS
1 SIDE1
2
3
4 SIDE2
+3VS
R457
PM_SUSC
0.1U
USB_PN3
+3V
41,42
C684
10U/16V
L96
90/370mA
TPM Module CON
C700
CON40
22
PM_CLKRUN# 20,26,28,34
DIS_FWH 27,28,31
0_*
+5V_Camera
80/3A
+2.5VS
D
Q41A
UM6K1N_*
2
2 S
R456
150_*
Q41B
UM6K1N_*
5
19,21,22,23,30,31,48
5,7,8,9,10,65
5,11,14,15,16,18,48
22,28,30,31,35,37,42
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,39,41,48,61,70
9,16,18,25,28,31,40,41
14,18,23,24,28,29,36,37,39,40,41,61
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
38
OF
DESCRIPTION:
55
MDC,B/T,TPM,Camera & DISCHG

C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
H8
+5VS
+5VS
14,18,23,24,28,29,36,37,38,40,41,61
DVI_DDCCLK_NV
DVI_DDCDAT_NV
R732
R733
2.2K
2.2K
1
2
3
+5VS
H16
NP_NC
GND1 GND4
GND2 GND3
5
4
1
2
3
NP_NC
GND1 GND4
GND2 GND3
CR315X354D110N
5
4
H5
CT276B167D138
H6
CT276B167D138
C315D87N
CON15
16 DVI_TX2P_NV
16 DVI_TX2N_NV
2
1
16 DVI_TX4P_NV
16 DVI_TX4N_NV
5
4
16 DVI_TX1P_NV
16 DVI_TX1N_NV
10
9
16 DVI_TX3P_NV
16 DVI_TX3N_NV
13
12
TMDS_DATA_3+
TMDS_DATA_3-
16 DVI_TX0P_NV
16 DVI_TX0N_NV
18
17
TMDS_DATA_0+
TMDS_DATA_0-
16 DVI_TX5P_NV
16 DVI_TX5N_NV
21
20
TMDS_DATA_5+
TMDS_DATA_5-
16 DVI_CLKP_NV
16 DVI_CLKN_NV
23
24
TMDS_CLK+
TMDS_CLK-
25
26
27
28
TMDS_DATA_2+
TMDS_DATA_2TMDS_DATA_4+
TMDS_DATA_4-
DDC_CK
DDC_DATA
HOT_PLUG_DETECT
L75
L76
6
7
1K/300mA
1K/300mA
L77
16
1K/300mA R73
10K
DVI_HDP_NV 16
D17
TMDS_DATA_1+
TMDS_DATA_1-
P_GND1
P_GND2
H9
DVI_DDCCLK_NV 16
DVI_DDCDAT_NV 16
1
2
3
GND_for+5V
15
+5V_POWER
14
TMDS_CLK_Shield
TMDS_2/4_Shield
TMDS_DATA_1/3_Shield
TMDS_DATA_0/5_Shield
22
3
11
19
BAV99_*
80/2A
F4
2
1
2
3
5
4
NP_NC
GND1 GND4
GND2 GND3
H3
CT276B167D138
H4
CT276B167D138
CPU
H18
5
4
1
2
3
NP_NC
GND1 GND4
GND2 GND3
5
4
R2.0
1.5A/6V
D10
+5V_DDC 2
1
C334
NP_NC
GND1 GND4
GND2 GND3
C315D87N
H10
100K
L78
5
4
CR315X354D110N
1
R74
8
NP_NC
GND1 GND4
GND2 GND3
+3VS
V_SYNC
H17
1
2
3
CR315X354D110N
+5VS
FS1J4TP
0.1U
1
2
3
NP_NC1
NP_NC2
NP_NC
GND1 GND4
GND2 GND3
H33
DO276X39
C315D87N
H11
IO Board
H19
5
4
1
2
3
NP_NC
GND1 GND4
GND2 GND3
5
4
DVI_CON_24P
CR315X354D110N
C315D87N
H7
1
2
3
H20
NP_NC
GND1 GND4
GND2 GND3
5
4
1
2
3
NP_NC
GND1 GND4
GND2 GND3
CR315X354D87N
NP_NC
GND1 GND4
GND2 GND3
PT7008TPC28T
PT7009TPC28T
PT7010TPC28T
PT7011TPC28T
1
1
1
1
1KOhm/100Mhz
1
2
3
2
680Ohm/100Mhz
2
NP_NC
GND1 GND4
GND2 GND3
BAT
NP_NC
GND1 GND4
GND2 GND3
1
2
3
4
5
6
7
8
9
NP_NC2
10
1
2
3
NP_NC
GND1 GND4
GND2 GND3
H34
F40M20_701130AS
H35
F40M20_701130AS
5
4
VGA_NUT
680Ohm/100Mhz
C315D87N
H13
1
2
3
PL7005 1
PL7001 1
PL7006 1
2 1KOhm/100Mhz
2 1KOhm/100Mhz
2 1KOhm/100Mhz
SCREW
SMC_BAT 28,69
SMD_BAT 28,69
TS#
68,69,71
NP_NC
GND1 GND4
GND2 GND3
5
4
H27
H28
O295X413DO216X334 O295X413DO216X334
KEYBOARD
C315D87N
_*
J1
11
BATT_CON_9P
PT7017TPC28T
PT7018TPC28T
PT7019TPC28T
PT7021TPC28T
H12
5
4
PT7001PT7012PT7013
TPC28TTPC28TTPC28T
1
2
3
4
5
6
7
8
9
TPM_NUT
C315D87N
CT217B315D87N
NP_NC1
H25
L4E_1A
5
4
BAT_S
PCO701
1
2
3
H14
1
PL7002
1
PL7003
1
PL7004
MDC_NUT
H21
5
4
CR315X354D87N
BAT_S
H2
L4E_1A
C315D87N
H31
1
2
3
H1
L4E_1A
5
4
EMI_SPRING_PAD
H15
1
2
3
NP_NC
GND1 GND4
GND2 GND3
H36
B40M20
5
4
KB NUT
C315D87N
1
1
1
1
H32
1
2
3
GND
NP_NC
GND1 GND4
GND2 GND3
5
4
C315D87N
H29
hole_c87d87n
H30
hole_c87d87n
FIXED HOLE
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
39
OF
55
DVI CONN & HOLE

C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
+5V
+12V
+5V_USB4
28
R129
D53
1
FAN1_TACH
RB751V_40
2
CON24
10K
+5VS_FAN
U23
Q38
PMN45EN
F2
2
1.5A/6V
+5VUSB_4
1
+
C315
10U/10V
L32
80/2A +5VUSB4
CE2
C316
100U/6.3V
0.1U
1
2
3
4
+5VS
28
FAN1_DC
28
WATCHDOG
R400
1K
1
D22
VEN
VIN
VO
VSET
GND4
GND3
GND2
GND1
8
7
6
5
C441
C442
10U/10V
0.1U
1
2
3
HOLD1
HOLD2
FAN_CON
G993P1U
2
RB751V_40_*
FAN CONTROL
Differential
Pair
Differential
Pair
L51
34
TPA0+_0
1 LTPA0+
34
TPA0-_0
2 LTPA0-
22
USB_PN4
34
TPB0+_0
3 LTPB0+
22
USB_PP4
34
TPB0-_0
Common
Choke
R131
USBP4-
R130
USBP4+
T98
4 LTPB0IEEE1394
T99
3
4
5
6
7
NP_NC
P_GND
P_GND
P_GND
P_GND
USBP4USBP4+
LTPA0LTPA0+
LTPB0+
LTPB0MIC_IN#_JACK
36 MIC_IN#_JACK
CON34
19 19
17 17
15 15
13
13
11
11
9 9
7 7
5 5
3 3
1 1
I/O_PORT_CON
+5VUSB4
20 20
18 18
16 16
14
14
12
12
10 10
8 8
6 6
4 4
2 2
T101
L53
1vcc
2GND
A/D_DOCK_IN
150Ohm/100Mhz
DC_PWR_JACK_2P
T100
CON25
FOR EMI
A/D_DOCK_IN 42,68,69,70,71
C444
C446
C447
0.1U/X7R
0.1U/X7R
0.1U/X7R
DC IN
EXT_MIC_JACK 37
INT_MIC_JACK 37
OPTIC_VCC_JACK 37
SPDIF_O_JACK 37
HP_IN#_JACK 36,37
HP_JACK_L 37
HP_JACK_R 37
OPTIC_HP_JACK 37
T102
T103
T104
T105
ACIN_CONN
I/O PORT
5
+5V
+5VS
+5V
+5VS
9,16,18,25,28,31,38,41
14,18,23,24,28,29,36,37,38,39,41,61
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
40
OF
55
FAN_CTRL & ACIN

C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
INTERNET_#
SW2
1
28 MARATHON_#
100P_*
28 BLUETOOTH_#
4
5
4
5
C449
1
SW1
2
SW4
4
5
C448
TACT_SWITCH_5P
100P_*
28
WIRELESS_#
4
5
1
3
4
5
C451
TACT_SWITCH_5P
100P_*
SW3
2
28
PANLOCK_#
4
5
4
5
C450
TACT_SWITCH_5P
100P_*
T302
GATE_PWR_SW#
SW5
28
INTERNET_#
4
5
SW6
100P_*
42 GATE_PWR_SW#
4
5
4
5
C452
TACT_SWITCH_5P
4
5
C454
TACT_SWITCH_5P
100P_*
2
4
5
TACT_SWITCH_5P
SW7
17,42
1
5
2
LID_SW#
C453
4
6
3
+3VS
SWITCH_4P
Pwr4_Gear
SW
100P_*
B/T
SW
WLAN
SW
PADlock
SW
+3VS
U50A
Q16
2N7002
R743
28 MSK_INSTKEY#
1K
R740
U50B
7
3
Q12
2N7002
38,42
PM_SUSB
C74
0.1U
1
G
CK
12
+3VA
R739
1UF/X7R
GND
VCC
VCC
Q#
R741
R403
R691
200
200
200
390
LED1
GREEN
LED2
GREEN
LED3
GREEN
LED9
GREEN
5
14
24
28
28
HDD_LED#
CAP_LED#
NUM_LED#
HDD
LED
R742
SWDJ_EN 28
38,42
PM_SUSC
CAP
LED
NUM
LED
PWR
LED
Q10
2N7002
10K
INTERNET_#
+5VS
R402
SN74LVC74APWR
Q# 6
Q
+3VS
R401
14
C77
2 S
CK
+3VS
PWR
SW
SN74LVC74APWR
GND
11
100K
Internet
SW
10K
INTERNET_#
C79
100K
0.1U
2
D66
GATE_PWR_SW#
1
1SS355
SW8
TP_LEFT#
1
3
C455
69 CHG_LED_UP
SW9
4
5
4
5
TP_RIGHT#
3
C456
100P_*
+5V
+5VS
4
5
4
5
100P_*
TACT_SWITCH_5P
+5VS
TACT_SWITCH_5P
+3VS
+5VS
R405
R406
390
R407
R408
R409
390
390
100K
CON26
R752
390
L54
+5VS_TP
1K/300mA
1
2
3
4
5
6
7
8
9
10
11
12
390_*
LED5
GREEN
28
28
LED6
ORANGE
LED7
GREEN
LED8
GREEN
38
1Hz
+3VS
R753
10K
5
1
D64
BT_LED
Q30B
UM6K1N
Q31B
UM6K1N
5
Q30A
UM6K1N
Q31A
UM6K1N
2
R411
802_LED_EN# 22
28 PANLOCK_LED
Charger
LED
B/T
LED
2
4
6
8
LN1
120/150mA
+5VS_TP
C457
T106
0.1U
2S
C458
WLAN
LED
+3VS
+5V
+5VS
+12VS
+3VS
+5V
+5VS
+12VS
C459
Q32
2N7002
1
2 SIDE1
3
4
5
6
7
8
9
10
11 SIDE2
12
13
14
TOUTH_PAD_CON
+5V
Q50
2N7002_*
0.1U
PWR
LED
1
3
5
7
+12VS
3
100K
2
1SS355
TP_LEFT#
TP_RIGHT#
LED4
GREEN_*
802_ON/OFF# 30
INTDATA_5S
INTCLK_5S
TOUCH PAD
CNT
0.1U
5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,48,61,70
9,16,18,25,28,31,38,40
14,18,23,24,28,29,36,37,38,39,40,61
67
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
41
OF
55
SW &
C
LED & TP
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
D27
2
46,70 FORCE_OFF#
1SS355
1
OTP_RESET# 5
+3VA
R467
R461
+3VSUS
+3VA
U49 PST9128NR
5 VCC
+3VSUS
100K
+3VA
20K
RS#
VOUT 4
1 NC
C515
R468
U21B
100K
T108
U30B
VCC 74LVC14APW_T
R463
4
GND
74LVC14APW_T
SUB GND
R766
+3VA
U30D
VCC
8
PWRBTN#
0
C699 0.1U/X7R
PM_RSMRST# 22
GND
PWR_SW# R767
C514
0_*
100K
12
PWR_SW
11
CK
Q106
2N7002
GND
SN74LVC74APWR
Q 9
Q#
VCC
D63
3
14
+3VA
DAN202K
VSUS_ON 31,46,67
R725
1M
G
0.1U
2 S
1UF/X7R
R472
3
C654 1UF/X7R
PM_SUSC
1
Q103
2N7002
100K
C517
C481
0.1U/X7R
0.1U
G
S
R473 2
1M
+3VSUS
+3VA
R7145
+3VA
10KOhm
100K
R471
PWRBTN#
U30E
74LVC14APW_T
U30F
74LVC14APW_T
VCC
1
22 PM_PWRBTN#
+3VA
R726
+3VA
D30
11
12
GND
1SS355
Q47
2N7002
100K
VCC
10
U21A
PWR_SW
PWR_SW#
13
GND
GATE_PWR_SW# 41
+3VA
C519
0.1U
3
+3V
28
KBCRSM
R476
R656
1M
1K
Q49
2N7002
G
T303
R475
CK
D
GND
SN74LVC74APWR
Q# 6
Q
VCC
5
14
D31
2
1M
LID_KBC# 28
C686
1SS355
R727
LID_SW#
2 S
17,41
100K
A/D_DOCK_IN 40,68,69,70,71
0.1U/X7R
C521
JP8
C520
R728
R729
0.1U
OPEN_PIN
0.1U/X7R
100K
100K
Q46B
UM6K1N
5
Q46A
UM6K1N
2
R730
C685
100K
0.1U/X7R
+3VA
74LVC14APW_T
VCC
22,67
SUSC#
PM_SUSC 38,41
GND
U30A
+3VA
22,31,32,67,70 SUSB#
74LVC14APW_T
VCC
6
PM_SUSB 38,41
GND
U30C
+3V
+3VA
+3VSUS
+3V
+3VA
+3VSUS
22,28,30,31,35,37,38
22,38,41,48,71
5,17,20,22,23,28,29,32,46,48,70
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
42
OF
55
POWER-ON SEQUENCE
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
Revision History
Power:
1
System:
<Core Design>
PROJECT: A8T
A
REVISION
2.1
DATE:
SHEET
B
DESCRIPTION:
43
OF
55
HISTORY
C
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
D
1394A
IO_CON2
OPTIC_HP_JACK_I/O
HP_JACK_R_I/O
HP_JACK_L_I/O
6
1
4
5
HP_IN#_JACK_I/O
IO_CON1
11
12
GND
A
B
C
OPTIC_VCC_JACK_I/O
SPDIF_O_JACK_I/O
LINE_OUT
SPDIF
GND
VCC
Vin
LTPB0-_I/O
LTPB0+_I/O
LTPA0-_I/O
LTPA0+_I/O
1
2
3
4
P_GND1
P_GND3
5
7
P_GND4
P_GND2
8
6
1
2
3
4
9
MS 10
1394_CON
PHONE_CON
GND
USBP2-_I/O
USBP2+_I/O
LTPA0-_I/O
LTPA0+_I/O
LTPB0+_I/O
LTPB0-_I/O
MIC_IN#_JACK_I/O
1
3
5
7
9
11
13
15
17
19
IO_CON3
2
4
6
8
10
12
14
16
18
20
GND
+5VUSB2_I/O
EXT_MIC_JACK_I/O
INT_MIC_JACK_I/O
OPTIC_VCC_JACK_I/O
SPDIF_O_JACK_I/O
HP_IN#_JACK_I/O
HP_JACK_L_I/O
HP_JACK_R_I/O
OPTIC_HP_JACK_I/O
I/O_PORT_CON
IO_CON4
10
9
8
7
5
4
3
6
2
1
MIC_IN#_JACK_I/O
INT_MIC_JACK_I/O
EXT_MIC_JACK_I/O
GND
NP_NC2
NP_NC1
P_GND2
P_GND1
5
4
3
6
2
1
IO_CON5
USB_CON_1X4P
+5VUSB2_I/O
USBP2-_I/O
USBP2+_I/O
MIC
1
2
3
4
1
2
3
4
USB
EXT_MIC_CON
IO_H1
O63X157DO39X98
IO_H2
O63X157DO39X98
GND
IO_H3
O63X157DO39X98
IO_H4
O63X157DO39X98
IO_R1
0_0603
IO_R2
0_0603
GND
GND
<Core Design>
PROJECT: A8T
5
REVISION
2.1
DATE:
SHEET
4
DESCRIPTION:
44
OF
I/O PORT
55
3
DESIGN ENGINEER :
Albert Su
RELEASE DATE :
2
PQ7102
1
+5VLCM
1%
AC_BAT_SYS_IN
PT7105
PT7106 PT7101 PT7107 PT7108
TPC28T
TPC28T TPC28T TPC28T TPC28T
PR7102
10mOhm
1
2
PT7102 PT7103 PT7104

TPC28T TPC28T TPC28T
TPC8107
D
+2.5VREF
PQ7105
5/26 PD ISSUE
TPC8107
A/D_DOCK_IN
PU7103
3 A+ + VCC 8
1
2 A- - AO
AC_BAT_SYS
5 B+
+
BO 7
6 B- - GND 4
1%
LM358DR
68
CHG_SRC
+5VLCM
PT7109 PT7110
TPC28T TPC28T
CSSN
CSSP
PT7111
TPC28T
PR7112
1
68 MAX8725_PDS
68
68
PU7104
1
2
3
PR7113
2
PQ7101
BAT
3/9 for
soft
start
18KOhm
6.8KOhm
5
4
MAX4073HAXK_T
5,22,68
OUT RSGND
VCC RS+
PWRLMT#
4
TPC8107
PT7118
TPC28T
PT7112
TPC28T
1
D
68 MAX8725_PDL
PQ7106
2N7002
+5VCHG +5VO
PT7114
20050406
PT7115
TPC28T
1
TPC28T
PU7102
1
2
3
IN
OUT
EN NC or ADJ
PR7111
10KOhm
PT7113
TPC28T
PD7103
6/14 EE change
+5VLCM
6/7 for bat

current
limit
PR7109
1KOhm
PT7117
TPC28T
+2.5VREF
Ibat=2.5*200k/256k/100/0.003=6.51A
PT7116
TPC28T
F02JK2E
MIC5235YM5
B
PR7122
100KOhm
1%
PR7110
31.6KOHM
1
2
GND
1
2
+5VCHG
1 BATT_PWRLMT
S 2
+3VA
A/D_DOCK_IN
PD7104
1SS355
BAT_IN_OC# 28
PC7104
2.2UF/16V
PC7105
1UF/25V
PC7106
1UF/10V
39,68,69
GND
PQ7104A
UM6K1N
TS#
PQ7104B
UM6K1N
+5VCHG, +5VLCM, +2.5VREF

6/14 EE change
Ref: 1.24V
GND
ON: EN>2V (A/D_DOCK_IN:17V)
BATTERY IN CIRCUIT
OFF: EN<0.6V(A/D_DOCK_IN:5.1V)
<Core Design>
Title :
Engineer:
ASUSTECH
Size
Custom
4
Eric_Ko
Rev
A8T
2.1
Date: Friday, July 21, 2006

5
POWER_SWITCH_5VLCM
Project Name
Sheet
1
54
of
55
A/D_DOCK_IN
+2.5VREF
LM4040BIM
78L05
(Regulator)
SI4925BDY
(500uA)
+5VCHG (100mA)
+5VO (20mA)
SWITCH
(F02JK2E)
+5VLCM
SWITCH
VSUS_GD#
+5VO (6A)
+5VAO
TPS51020
(Regulator)
ON_SUS
+5VS
SUSB#_PWR
ON_SUS
+5V
SUSC#_PWR
+3VSUS
(2.0A)
(0.7A)
+3VO (6.3A)
+3V
SUSC#_PWR
(0.12A)
+1.5VSUS
SI9183
(3.6A)
+3.3VS
SUSB#_PWR
(0.6A)
(4A)
+1.2VSUS
AC_BAT_SYS
+1.2VO (5.4A)
SUSB#_PWR
ISL6227
+1.0VO (3.75A)
SUSB#_PWR
+1.2VS (3.3A)
HTVDD_EN
+1.2VS_HT
+1.0VS
+1.8V (10A)
+1.8VO (18.2A)
SUSC#_PWR
ISL6227
SUSC#_PWR
(2.1A)
+1.8VS
SUSB#_PWR
+0.9VO (4.5A)
+0.9VS
SUSB#_PWR
(4.5A)
(0.5A)
+0.9V (4.0A)
B
MIC5236BM
+3VAO
+3VA (0.06A)
CPU_VDD_FB,
CPU_VDD_FB#,CPU_VID
+VCORE (35A)
MAX8760
CPUPWR_GD
VGA_VCORE (16.5A)
MAX1844
SUSB#_PWR
MAX8725
(Charger)
BAT
<Core Design>
Title : POWER DIAGRAM
TPC8107
Engineer: Eric_Ko
ASUSTECH
Size
Custom
Project Name
Rev
A8T
2.1

5
Sheet
1
55
of
55
AC_BAT_SYS
3/8 emi
issue
PQ6101
FDS6298
PQ6102
FDS6298
PR6142
2
(35A)
PT6102
TPC28T
0Ohm
r0603_h24
+3VS
+VCORE
PR6102
1mOhm
PL6101
1
0.56UH
5/26 VDS issue
19,70 CPUPWR_GD
5
5
5
5
5
5
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
PR6109
1.82KOhm
PD6102
EC31QS04
2
PQ6103
FDS6676S
PQ6104
FDS6676S
PR6125 1KOhm
1
2
5 CPU_VDD_FB
PR6119 2
PR6120 2
RB717F
5 CPU_VDD_FB#
PR6127
10Ohm
PR6129
10Ohm PC6101
1000PF/50V
PC6114
100PF/50V
D4
D5
SKIP#
OAIN+
OAINFB
CCI
GNDS
CCV
GND1
PGND
DLS
DHS
LXS
BSTS
V+
CMP
CMN
CSN
CSP
GND2
31
32
33
34
35
36
37
38
39
40
41
PR6143 0Ohm
1
2
1
AC_BAT_SYS
PC6111
2
PR6124
1Ohm
PC6113
0.1UF/50V
PQ6105
FDS6298
PQ6106
FDS6298
PR6128
PT6103
TPC28T
5/26 VDS issue
1.82KOhm
PL6102
PT6104
TPC28T
1
CPU_VRON
0.22UF/25V
PC6116
4.7UF/16V
REF =
300kHz,
PR6130 10Ohm
2
1
2
0.56UH
PD6101
2
PR6131
0Ohm
1 0Ohm
1 0Ohm
3/8 emi
issue
r0603_h24
20
19
18
17
16
15
14
13
12
11
PR6122 10KOHM @
PR6123 1MOhm
2
1
1
2
PR6121 470Ohm
1
2
@ 1
2
+VCORE
PR6126 1KOhm
1
2
PC6112
470PF/50V
2
1
OAINOAIN+
PC6108
4.7UF/16V
PR6122 close
to PL6101
OAIN+
OAIN-
PC6107
1000PF/50V
@
1
2
MAX8760ETL
PU6101
19
PC6106
0.22UF/25V
2
1
1
PD6103
3
+5VS
PC6104
0.1UF/50V
PR6112
1Ohm
OAIN+
PR6132
2
67 CPU_VRON_PWR
1
121KOhm
@
PC6119
0.1UF/50V
@
+5VS
PR6133
200KOhm
1
FDS6676S
EC31QS04
PQ6107
PQ6108
FDS6676S
PR6136
200KOhm
PR6140
100KOhm
PR6139
100KOhm
1%
5/10 change to change OCP >40A
PT6105
TPC28T
PR6144
53.6KOhm
1%
PQ6109B
UM6K1N
5
CPU_PSI#
CPU_PSI#:HIGH, SKIP#=5V
CPU_PSI#:LOW, SKIP#=1.74V
@
2
PR6141
470KOhm
@
6/14 EE change
VREF = 2V
SKIP#>2.7V , TWO PHASE PWM MODE
2.3V>SKIP#>1.2V , TWO PHASE PFM MODE
SKIP#<0.8V , SINGLE PHASE PFM MODE
PQ6109A
UM6K1N
PT6112
TPC28T
PT6113
TPC28T
PT6114
TPC28T
PT6115
TPC28T
PT6116
TPC28T
PT6101
TPC28T
PT6117
TPC28T
PT6118
TPC28T
PT6119
TPC28T
PT6120
TPC28T
PT6122
TPC28T
PT6123
TPC28T
PT6124
TPC28T
PT6125
TPC28T
PT6126
TPC28T
PT6127
TPC28T
PT6128
TPC28T
PT6129
TPC28T
PT6130
TPC28T
PT6131
TPC28T
PT6106
1 TPC28T
CPU_VID0
PT6107
1 TPC28T
CPU_VID1
PT6108
1 TPC28T
CPU_VID2
PT6109
1 TPC28T
CPU_VID3
PT6110
1 TPC28T
CPU_VID4
PT6111
1 TPC28T
CPU_VID5
+VCORE
PT6121
PT6132
PT6133
TPC28T
1
TPC28T
1
TPC28T
1
<Core Design>
CPUPWR_GD
Title :
CPU_VDD_FB
Size
Custom
Project Name
Rev
A8T
2.1

5
POWER_VCORE
Engineer: Eric_Ko
ASUSTek
CPU_VDD_FB#
Sheet
1
61
of
55
PR6202
0Ohm
1
AC_BAT_SYS
2
PC6202
1UF/25V
PC6204
0.1UF/25V
PQ6202
SI4800BDY
(6A)
PR6205
0Ohm
1
AC_BAT_SYS
PT6202
TPC28T
PT6204
TPC28T
PT6201 PT6203
TPC28T TPC28T
+5VO
+5VAO
PL6201
3.8UH
2
PR6209
10KOhm
1
PC6205
1 1
3900PF/50V
PR6206
2
1.8KOhm
0.1UF/50V
PC6206
1
2
PU6202
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RUN_5VO PT6209
RUN_3VO
VSUS_GD#
2
1 1
PC6209
3300PF/50V
2
PR6210
2.7KOhm
INV1
VBST1
COMP1
OUT1_U
SSTRT1
LL1
OUT1_D
SKIP#
VO1_VDDQ OUTGND1
DDR#
TRIP1
GND
VIN
REF_X
TRIP2
ENBL1
VREG5
ENBL2
REG5_IN
VO2
OUTGND2
PGOOD
OUT2_D
SSTRT2
LL2
COMP2
OUT2_U
INV2
VBST2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TPS51020
PQ6203
SI4894DY
PD6202
FS1J4TP
+
PC6207
1UF/10V PT6205 PT6206 PT6207 PT6208
TPC28T TPC28T TPC28T TPC28T
PCE622
100UF/6.3V
AC_BAT_SYS
+5VAO
+5VAO
+5VO
PR6211
0Ohm
PC6210
1
2
PC6208
1UF/25V
1
PQ6204
SI4800BDY
0.1UF/50V
PC6211
4.7UF/16V
PR6215
2
(6.3A)
PT6213
TPC28T
PL6202
3.8UH
11/23/05
10KOhm
PT6210
TPC28T
PT6211
TPC28T
PT6212
TPC28T
PJP621
2
F=450KHZ
PT6218
3/3
+12VSUS
PC6216
4.7UF/16V
PU6201
1
2
3
VSUS_ON
IN
OUT
(0.02A)
31,42,67 VSUS_ON
+12VO
PCE624
150UF/4V
EN NC or ADJ
42,70 FORCE_OFF#
4
PT6214 PT6215 PT6216

TPC28T
PR6218 1KOhm
2
1
PC6201
4.7UF/16V
2
PR6219
845KOhm
PD6203 RB751V_40
2
1
+5VAO
TPC28T
RUN_3VO
PT6220
RUN_5VO
+3VSUS
PR6201 0Ohm
TPC28T
3/3
PR6220
95.3KOhm
70
VSUS_GD#
<Core Design>
VSUS_GD#
(REF=1.24V)
Title :
1.24*(95.3+845)/95.3=12.235
Engineer:
ASUSTECH
Size
Custom
POWER_SYSTEM
Eric_Ko
Project Name
Rev
A8T
2.1

5
11/02
GND
MIC5235YM5
+3VSUS
2
PT6217
TPC28T
PD6201
FS1J4TP
PT6219
1MM_OPEN_5MIL
@
PQ6201
SI4894DY
AC_BAT_SYS
(0.7A)
+3VO
Sheet
1
62
of
55
AC_BAT_SYS
D
PC6302
0.1UF/50V
PR6303
0Ohm
+5VO
PD6302
RB717F
(6.1A)
+1.2VS_CORE
C
PC6306 4.7UF/6.3V
1
2
PT6302
(6.1A)
TPC28T
PT6307
TPC28T
PT6301
TPC28T
PL6301
3.8UH
PJP632
2
+1.0VO
3MM_OPEN_5MIL
@
PJP633
2
PU6301
PT6308
TPC28T
+1.0VO
2
PR6306
1
2.1KOhm
PCE634
390UF/2.5V
3MM_OPEN_5MIL
@
PR6308 @
2
1
PQ6304
SI4894DY
0Ohm
PR6310
0Ohm
6/14
EE
change
PT6306
PQ6303
PQ6302
SI4800BDY
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
LGATE2
PGND2
PHASE2
UGATE2
BOOT2
ISEN2
EN2
VOUT2
VSEN2
OCSET2
SOFT2
PG2/REF
PG1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
LGATE1
PGND1
PHASE1
UGATE1
BOOT1
ISEN1
EN1
VOUT1
VSEN1
OCSET1
SOFT1
DDR
VIN
D1_1
G1
D1_2 S1/D2_3
G2
S1/D2_2
S2
S1/D2_1
PT6305
PT6304
TPC28T TPC28T
PT6303
TPC28T
(2.1A)
+1.2VO
+1.2VS
3.8UH
SI4914DY
+
PCE631
390UF/2.5V
PR6307
2
1.2KOhm
PR6301 @ 0Ohm
2
1
ISL6227CAZ_T
PR6309
old 1.07k
0Ohm
PR6312 6.81KOhm
2
1
PR6314 6.81KOhm
2
1 +1.0VO_VSEN
F=300KHZ
0.01UF/50V
2
4/19 CHANGE
PC6311 0.01UF/50V
VREF = 0.9V
+3VS
PR6315
18.2KOhm
+1.0VO_VSEN
PR6317
10KOhm
@
old 196k
PR6321
100Ohm
16,67 SUSB#_PWR
TPC28T
3MM_OPEN_5MIL
@
PJP631
1
2
1 2
PL6302
PC6301
0.1UF/25V
PC6312
1
(2.1A)
+1.2VO
PR6319
100KOhm
@
PQ6305A
UM6K1N
@
2
PQ6305B
UM6K1N
@
22
5
@
PC6313
0.01UF/50V
@
PR6320
100KOhm
@
PR6318
4.53KOHM
@
PQ6301B
UM6K1N
@
PQ6301A
UM6K1N
@
+1.0VO_VSEN
CR_VID0
CR_VID1
22
5
@
PR6322
100Ohm
1
2
PC6314
0.01UF/50V
PT6309
TPC28T
PT6310
TPC28T
PT6311
TPC28T
PT6312
TPC28T
PT6313
TPC28T
@
A
1.0V
+1.0VO
1.21V
CR_VID0
1.11V
0
CR_VID1
<Core Design>
70 1.2VO_1.0VO_PWRGD
Title :
Engineer:
ASUSTECH
+3VS
+3VS
5,13,14,15,19,20,21,22,23,39,48,61,67,70
Size
Custom
Eric_Ko
Rev
A8T
2.1

5
POWER_I/O_1.2VO & 1.0VO
Project Name
Sheet
1
63
of
55
+3VA
TPC28T
PT6402
+3VAO
3/13
change
+5VO
1MM_OPEN_5MIL
3/13 change
@
TPC28T
PT6406
Vref = 1.23V
TPC28T
PT6408
IOUT = 40 ~ 60mA
+1.5VS
PU6403
1
2
3
4
ADJ GND4
IN
GND3
OUT GND2
EN GND1
PR6404
16.9KOhm
8
7
6
5
1
2
3
4
PJP643
2MM_OPEN_5MIL
@
1
2
1 2
VIN
VFB
VOUT0
VOUT1
PR6402
18.2KOhm
PGND
AGND
VCCA
REFEN
TPC28T
PT6407
8
7
6
5
CM8562GISTR
(2A)
+
TPC28T
PT6401
MIC5236YM
+1.8VS
TPC28T
PT6405
PU6402
@
1
+1.8VS
+3VAO
TPC28T
PT6404
PJP642
2MM_OPEN_5MIL
AC_BAT_SYS
TPC28T
PT6403
PJP641
1
PCE641
150UF/2V
PC6402
0.1UF/25V
+1.5VO
PC6404
10UF/6.3V
PC6405
1UF/25V
PR6407
10KOhm
+3VA
+1.5VS
3/13
change
C
+5VO
3/13 change
TPC28T
PT6419
PJP647
2MM_OPEN_5MIL
PR6423
18.2KOhm
PU6405
(0.12A)
Vref=1.215V
+3VO
+1.5VSUS
PT6410
TPC28T
PU6401
+1.8VS
PT6411
TPC28T
1
TPC28T
PT6422
+1.8VS
TPC28T
PT6420
1
2
3
4
PJP648
2MM_OPEN_5MIL
VIN
VFB
VOUT0
VOUT1
PGND
AGND
VCCA
REFEN
TPC28T
PT6421
8
7
6
5
PJP644
VIN
GND
SD#
VOUT
FB
PR6411
2
+1.5VS_VG
CM8562GISTR
1MM_OPEN_5MIL
@
23.7KOhm
+
TPC28T
PT6423
SI9183DT
PR6414
100KOhm
PC6408
4.7UF/6.3V
PC6409
1UF/10V
PC6419
10UF/10V
PCE643
150UF/2V
PC6418
0.1UF/25V
+1.5VO_VG
+1.5VS_VGA
B
+1.5VSUS
+3VS
+3VSUS
3/13 change
+5VO
PJP645
1MM_OPEN_5MIL
@
1
+3VS
TPC28T
PT6417
+2.5VS
TPC28T
PT6414
1
2
3
4
PJP646
1MM_OPEN_5MIL
@
1 1 2 2
VIN
VFB
VOUT0
VOUT1
PGND
AGND
VCCA
REFEN
PT6413
TPC28T
HT_VLD 19
PR6419
100KOhm
3
C
1 B
CM8562GISTR
PR6401
165KOhm
PC6413
0.1UF/25V
E
2 PQ6406
PMBS3904
2 S
MEM_VLD 19
0Ohm
D
PQ6403
2N7002
PR6413
20KOhm
G
3
C
PC6411
0.1UF/25V
2N7002
2 S
PC6407
1 B
c0603
@
PC6414
0.22UF/10V
PR6410
100KOhm
PQ6405
PT6409
TPC28T
PR6409
+0.9V
PR6420
82KOhm
8
7
6
5
TPC28T
PT6418
PR6408
100KOhm
+3VA
+1.2VS_HT
TPC28T
PT6416
PR6418
18.2KOhm
PU6404
(0.85A)
+3VS
TPC28T
PT6415
PR6417
100KOhm
+3VSUS
3/13 change
PC6410
0.22UF/10V
PR6426
51KOhm
PR6416
165KOhm
Von=0.8V
E
2 PQ6404
PMBS3904
0.1UF/25V
c0603
@
6/14 EE change
6/14 EE change
+2.5VO
A
3/13 change
<Core Design>
Title : POWER_I/O_LDO
Engineer:
ASUSTECH
+2.5VS
Size
C
Date:
5
Eric_Ko
Project Name
Rev
A8T
2.1
Sheet
1
64
of
55
+5VO
PR6502
2
1
0Ohm
@
AC_BAT_SYS
PR6504
0Ohm
PR6505
0Ohm
@
SUSC#_PWR
70 DDR_PWRGD
PD6503
2
1
1SS355
1
PC6508
0.033UF/16V
PR6510 22KOhm
VILIM=0.905V,
Set OCP to
PR6511
12.57A
150KOhm
+1.8VO
PC6510
0.22UF/10V
6/29 modify ocp

point
PR6512
0Ohm
@
TON
OVP/UVP
REF
ILIM
POK1
POK2
STBY#
DL
BST
LX
DH
VIN
OUT
FB
21
20
19
18
17
16
15
PR6509
1Ohm
1
+1.8VO
PL6501
1
PC6506
2
2
1
PT6503
TPC28T PT6504
TPC28T
PT6505
TPC28T
(12A)
PJP652
(12A)
2
1.8UH
+1.8V
3MM_OPEN_5MIL
@
H=4.0mm
0.22UF/25V
PJP653
PD6501
FS1J4TP
3MM_OPEN_5MIL
@
PU6501
MAX8632ETI
3MM_OPEN_5MIL
@
FB=AVDD,OUTPUT=1.8V
For foldback
current limit
1
2
3
4
5
6
7
PT6501
TPC28T
PT6506
TPC28T
PJP651
1%
C
PT6502
TPC28T
RB751V_40
PR6507
0Ohm
5/26 VDS issue
@
PR6508
0Ohm
@
SUSC#_PWR
1
PC6504
0.033UF/16V
67
PQ6501
FDS6298
PD6502
PR6506
22KOhm
67
PR6513
124KOhm
1%
PR6514 10Ohm
2
1
6/29
change
For output adjustable
PR6501
15.8KOhm
1
+0.9VO
PT6507
TPC28T
PR6515
10KOhm
1%
(1.0A)
+0.9V
PC6517
4700PF/50V
(1.0A)
@ PJP654
1 1 2 2
1MM_OPEN_5MIL
PT6508
TPC28T
PT6509
TPC28T
PT6510
TPC28T
PT6511
TPC28T
PT6512
TPC28T
PC6518
0.1UF/25V
<Core Design>
Title :
Size
Custom
Project Name
Rev
A8T
2.1

5
POWER_I/O_DDRII
Engineer: Eric_Ko
<OrgName>
Sheet
1
65
of
55
TPC28T
PT6702
+1.2VO
8
7
6
5
PT6705
TPC28T
PQ6702
D
S
1
2
3
4
+3VO
+1.2VS_HT
(2.62A)
PC6702
0.1UF/25V
1.2VHT_EN_ON
PQ6703A
UM6K1N
2
PQ6704
SI4800BDY
1
2
3
+0.9VO
6
D
5
S 4
G
PMN45EN
+0.9VS
3/13
change
+1.8VO
PT6707
TPC28T
PJP674
1
+3VA
VSUS_ON 31,42,46
CPU_VRON_PWR
61
PJP671
PC6706
0.1UF/25V
3/13 change
SUSB#_PWR
SGL_JUMP
@
PJP673
1
PQ6706
DRAIN_1
1
SOURCE_1
2
3
SOURCE_2
4
GATE_1
+3VO
PT6713
TPC28T
TPC28TTPC28T
PT6711PT6712
DRAIN_2
8
SOURCE_3
7
6
SOURCE_4
5
GATE_2
6/29 change for power sequence
3/13 change
TPC28T TPC28T
PT6716 PT6717
DRAIN_2
8
SOURCE_3
7
6
SOURCE_4
5
GATE_2
PQ6707B
UM6K1N
5
SUSC#_PWR
+3VA
+5VO
AC_BAT_SYS
TPC28T
PT6720
PQ6709
UMC4N
PR6711
100KOhm
+5VAO
+3VO
46,48
+3V
22
+1.2VO 47
+12VSUS 46
+0.9VS
+0.9VS 16
+2.5VO
+2.5VO 48
+1.2VSUS
+1.2VSUS
TPC28T TPC28T
PT6723 PT6724
TPC28T
PT6725
TPC28T
PT6726
TPC28T
PT6727
PQ6710
1
2
3
6
5
S 4
+1.2VS
+1.2VS 11,12,13,14,15,23,47
+3VS
+3VS
+3VSUS 5,20,22,23,32,46,48,70
+1.5VSUS
+1.5VSUS 23,48
(0.81A)
PC6712
0.1UF/25V
+0.9V
+0.9V
+12V
+12VS
TPC28T TPC28T
PT6729 PT6730
TPC28T TPC28T
PT6701 PT6728
TPC28T
PT6731
+5V
+5VS
DRAIN_1
1
SOURCE_1
2
3
SOURCE_2
4
GATE_1
PQ6711
DRAIN_2
8
SOURCE_3
7
6
SOURCE_4
5
GATE_2
PC6701
0.1UF/25V
SUSC#_PWR_ON
41
+5V
31
+5VS
14,23,61
+2.5VS 5,11,14,15,48
(3.0A)
+1.8VO
+1.8VO 65
+1.8V
+1.8V
+1.8VS
+1.8VS 5,15,17,48
TPC28T
PT6733
PQ6712
UMC4N
PT6734
TPC28T
25,35,37,40
+12VS
+2.5VS
BAT
BAT
+12VSUS
7,48,65
+12V
+5V
PR6713
10KOhm
FDW2501NZ
TPC28T
PT6732
5,13,14,15,19,20,21,22,23,39,47,48,61,70
+3VSUS
+3V
G
PMN45EN
46,70
+3VO
+12VSUS
+3VO
5,46,47,48,65,71
+3V
+1.2VO
PR6701
100KOhm
@
16,47 SUSB#_PWR
B
22,38,41,48,71
+5VO
+VCORE 5,7,61
+5VAO
+12VS
(0.01A)
+3VA
AC_BAT_SYS 16,17,46,47,48,61,65,68,71
+VCORE
PR6710
1KOhm
PT6722
TPC28T
PQ6701B
UM6K1N
5
PR6719
470KOhm
@
+5VS
SUSB#_PWR_ON
SUSC#_PWR_ON
PQ6701A
UM6K1N
2
(4.137A)
PC6710
0.1UF/25V
PR6709
10KOhm
22,31,32,42,70 SUSB#
+3VO
PR6707
100KOhm
PT6718
TPC28T
FDW2501NZ
PT6721
TPC28T
FOR TEST
PQ6707A
UM6K1N
2
SUSB#_PWR
TPC28T
PT6719
SUSC#_PWR
SUSB#_PWR_ON
PR6706
100KOhm
TPC28T TPC28T
PT6714 PT6715
+5VO
+3VS
(5.18A)
PC6708
0.1UF/25V
11/17
PQ6708
DRAIN_1
1
SOURCE_1
2
3
SOURCE_2
4
GATE_1
SGL_JUMP
@
+3VO
FDW2501NZ
5,7,10,65
39,68,71
+5VCHG
+5VCHG 68,69,71
+5VLCM
+5VLCM 68,69,70,71
+12V
PR6714
1KOhm
(0.01A)
PT6735
TPC28T
PR6715
100KOhm
+2.5VREF 68,69,70,71
+2.5VREF
+1.2VS_HT
+1.2VS_HT 4,5,7,11,15,48
+1.0VO
+1.0VO 47
+3VAO 48
+3VAO
PR6716
100KOhm
65 SUSC#_PWR
SGL_JUMP
@
(4.08A)
TPC28T TPC28T
PT6709 PT6710
22,42 SUSC#
PJP672
SGL_JUMP
@
+5VO
PR6717
470KOhm
@
3/14
add
PT6708
TPC28T
+1.8VS
FDW2501NZ
+12VSUS
PQ6703B
UM6K1N
HTVDD_EN
5
19 HTVDD_EN
3/6 for
timing
issue
DRAIN_2
8
SOURCE_3
7
6
SOURCE_4
5
GATE_2
PT6706
TPC28T
+12VSUS
PC6704
0.1UF/25V
PQ6705
DRAIN_1
1
SOURCE_1
2
3
SOURCE_2
4
GATE_1
PR6703
10KOhm
1.2VHT_EN_ON 1
(0.5A)
PC6703
0.1UF/25V
PT6704
TPC28T
PR6702
100KOhm
<Core Design>
Title :
Engineer:
ASUSTECH
Size
Custom
Date:
5
POWER_LOAD_SYSTEM
Eric_Ko
Project Name
Rev
A8T
2.1
Sheet
1
67
of
55
71
CHG_SRC
71
71
CSSP
CSSN
maxim
recommend
1uF 3/6
change
PT6802
TPC28T
71 MAX8725_PDS
71 MAX8725_PDL
AC_BAT_SYS
+
A/D_DOCK_IN
MAX8725_LDO
PT6803 PT6804
TPC28T TPC28T
A/D_DOCK_IN
PT6805
TPC28T
PKPRES#
PQ6802
SI4835BDY
MAX8725_LDO
CHG_GND
PD6802
1SS355
LDO : 5.4V
PQ6803A
UM6K1N
2
MAX8725_LDO
MAX8725_REF
TS#
PQ6803B
UM6K1N
5
PU6801
1
2
3
4
5
6
7
PT6810
TPC28T
39,69,71
PR6803
33Ohm
PR6805
100KOhm
1
2
REF : 4.2235V
PC6807
0.22UF/10V
PT6811
TPC28T
PR6807
13.3KOhm
DCIN
LDO
ACIN
REF
GND/PKPRES#
ACOK
MODE
DLOV
DLO
PGND
CSIP
CSIN
BATT
GND1
21
20
19
18
17
16
15
PC6806
1UF/25V
2
PT6808
TPC28T
PT6807
TPC28T
PL6801
10UH
1
PT6809
TPC28T
PR6806
25mOHM
1
2
BAT
PQ6804
SI4800BDY
MAX8725ETI
6/14 EE change
5/17
12/19
BAT
CHG_CCS
PKPRES#
CHG_GND
AD_IINP
5/17
PC6811
0.047UF/16V
PR6813
2.7KOhm
PR6816
10KOhm
PT6812
TPC28T
PQ6806
2N7002
69
69
PR6828
470KOhm
PT6801
TPC28T
69 AC_APR_UC
PR6818
4.7KOhm
1
2
+5VCHG
PWRLMT#
2 S
CHG_EN#
AC_IN Threshold 2.048Vmax A/D_DOCK_IN

>17.46V active
Adapter Iin(max) = [0.075V/Rsense(ADin)]*[VCLS/VREF]
Rsense(ADin)=0.01 ohm
VCLS= 2.59V
=> Iin(max)=4.6A
=> Constant Power = 19 * 4.737A = 90W
PT6814
TPC28T
3/3
PQ6801B
UM6K1N
PRECHG
5,22,71
05/05
PR6825
470KOhm
@
PT6818
TPC28T
AC_IN#
28
D
3
PD6801
1SS355
PQ6807
2N7002
@
D
PQ6808
A/D_SD#
2 S
2N7002
PC6814
0.1UF/25V
S 2
PU6802
LMV321IDBVR
PR6801
107KOhm
1
V+
1
70
+2.5VREF
B
PD6803
1SS355
PR6826
15KOhm
PT6816
TPC28T
+5VLCM
1
PT6815
TPC28T
PR6819
100KOhm
1%
V-
1 AD_IINP
3
@
@
PC6816
0.1UF/25V
Charge Current Ichg = [0.075V/Rsense(CHG)]*[ICTL/3.6V]

Rsense(CHG)=0.025 ohm
VICTL= 3.0V => Ichg = 2.5A
VICTL= 1.5V => Ichg = 1.25A
VICTL= 0.18V => Ichg = 150mA
D
PQ6809
1
Vbatt = Cell * { Vref +[ (VCTL- 1.8V) / 9.52 ] }
VCTL= 1.615V
=> Vbatt = 4.2V
Mode pin : Vmode > 2.8V (trie to LDO pin) ----> 4 Cells
2.0 > Vmode > 1.6V (floating) ----> 3 Cells
0.8 > Vmode (trie to GND)
----> Learning mode
2 S
2N7002
AD_IINP(5%) , R(0.7%) , 2.5VERF(0.2%) = 5.9%
PT6817
TPC28T
28
BAT_LEARN
VICTL< 0.8V or DCIN < 7V -->Charger Disable
90W / 19V * 0.941 = 4.46A

4.46A * 10mOHM = 44.6mV
PQ6801A
UM6K1N
2
44.6*3uA*10K = 1.338V
PR6823
470KOhm
@
<Core Design>
Title :
Engineer:
ASUSTECH
Size
Custom
4
Eric_Ko
Project Name
Rev
A8T
2.1

5
POWER_CHARGE
Sheet
1
68
of
55
PIC16F54
+5VLCM
PU6902
TPC28T
TPC28TTPC28T
PT6901
PT6902PT6903
TPC28T TPC28T
PT6904 PT6905
PC6902
1UF/25V
MLCC/+80%-20%
TPC28T
PT6906
VCC
NC
SUB
VOUT GND
1
2
3
TPC28T
PT6907 TPC28T
PT6908
PST9142NR
PU6903
1
2
3
VPP4
5
6
7
8
9
10
41 CHG_LED_UP
68
CHG_EN#
1
22 CHG_FULL_OC
PD6901
2
RB751V_40
28,39 SMC_BAT
28,39 SMD_BAT
ADP_ERR#
22 BATT_TALARM
RA2
RA3
T0CKI
MCLR#/VPP
VSS1
VSS2
RB0
RB1
RB2
RB3
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD2
VDD1
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
PIC16F54
20
19
18
17
16
15
14
13
12
11
AC_APR_UC 68
TS#
39,68,71
PT6909 PT6910 PT6911
ICSPDAT
ICSPCLK
BAT_LLOW
TPC28T
PT6912
PR6905
1
TPC28T
PT6913
BATSEL_2P#
BATSEL_3S#
PRECHG 68
PR6904
10KOhm_0402
1MOhm_0402
PD6906
RB751V_40
@
2
PX6901
3
4MHZ
TPC28T
PT6914
@
PC6903
0.1UF/10V
MLCC/+/-10%
GND
BAT_LLOW#_OC 28
6/14 EE change
PQ6902
BAT_LLOW 1
1
2 S
2N7002
PR6918
0Ohm
A/D_DOCK_IN
+5VLCM
+5VLCM
PT6915
TPC28T
TPC28T
PT6916
TPC28T
PT6917
TPC28T
PT6918
TPC28T
PT6919
TPC28T
PT6920
PR6910
120KOhm
1%
+2.5VREF
ICSPDAT
ADP_ERR#
1SS355
1
PU6904
LMV321IDBVR
PC6905
0.1UF/25V
2
PR6911
100KOhm
PC6904
0.1UF/25V
PR6901
20KOhm
1%
PU6901
1 B
VCC 5
V+
V-
+5VLCM
PD6905
2
+5VCHG
2 A
+5VCHG
3 GND
4
Y
VPP
ICSPCLK
PCO691
PIC_REFRESH_5P
D
PQ6901
2N7002
1
G
2 S
NL17SZ08XV5T2
AC_APR_UC
D
PQ6903
2N7002
1
G
Adaptor error circuit for
+19V adaptor
Vth = 17.5V (MAX. 17.8V & MIN. 17.2V)
For PIC
refresh
2 S
PR6914
470KOhm
<Core Design>
Title :
Size
Custom
Project Name
Rev
A8T
2.1

5
POWER_PIC
Engineer: Eric_Ko
<OrgName>
Sheet
1
69
of
55
A/D_DOCK_IN
PR7002
47KOHM
PT7002
TPC28T
PR7003
100KOhm
PT7003
TPC28T
E
2
A/D_SD#
PC7002
0.1UF/25V
PQ7002
PMBS3906
B 1
68
+5VAO
+5VLCM
Place under CPU
+2.5VREF
BAT_S
PR7005
10KOhm
3
C
PQ7003
PMBS3904
3
C
PT7006
PT7005
TPC28T
TPC28T
PR7006
316KOhm
PT7004
TPC28T
PR7007
10KOhm
324k 1%->316k
0.1%
1
2
3
4
PR7009
5.6KOhm
@
PR7010
75KOhm
VOUT1
VIN1VIN1+
GND
VCC
VOUT2
VIN2VIN2+
PC7003
0.1UF/16V
8
7
6
5
LM393DR
PR7011
80.6KOhm
PRT701
1
100KOhm
PU7001
3/13
change
+5VLCM
B 1
E
2
THERMAL PROTECTION
OVP=13.405V
1
PT7007
TPC28T
PU7002
1
2
3
NC
VCC
SUB
GND VOUT
FORCE_OFF# 42,46
PST9013NR
6/14 EE change
5,22
+3VSUS
PT7014
TPC28T
PR7012
100KOhm
46
VSUS_GD#
TPC28T
47 1.2VO_1.0VO_PWRGD
PT7023
PT7015
TPC28T
PD7002
1SS355
1 @
SHORTPIN
PJP702
2
1 @
TPC28T
2
65 DDR_PWRGD
22,31,32,42,67 SUSB#
100KOhm
PJP701
PT7020
TPC28T
16,20 VGA_PWRGD
PR7001
PD70011SS355
2
1
PT7016
PWRGD
+3VS
SHORTPIN
PJP703
1 @
SHORTPIN
+3VSUS
PQ7001B
UM6K1N
5
TPC28T
+3VSUS PT7022
PU7003
1 A
VCC
PR7013
1MOhm
PQ7001A
UM6K1N
PWROK
2
5
PR7014
0Ohm
PC7011
1UF/10V
FORCE_OFF# 42,46
2 B
3 GND
PR7016
470KOhm
Y
NC7SZ08P5X
PR7015
100KOhm
11/09
PT7024
TPC28T
19,61 CPUPWR_GD
5
<Core Design>
Title :
Engineer:
ASUSTECH
Size
Custom
B
Eric_Ko
Project Name
Rev
A8T

A
POWER_PROTECT
2.1
Sheet
E
70
of
55

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A

A8T/M SCHEMATIC R2.1

SYSTEM PAGE REF.

POWER PAGE REF.

Friday, July 21, 2006

SCHEMATIC FILE NAME :

A8T/M AMD S1/C51MV BLOCK DIAGRAM

LVDS & INV

DDR2 SDRAM 533/667MHz

1.2VO & 1.0VO

+1.8V & +0.9V

SW & LED &

AC & BAT CON

Friday, July 21, 2006

SCHEMATIC FILE NAME :

SM_BUS ADDRESS : Thermal MAX6657 = 1001100x

Friday, July 21, 2006

SCHEMATIC FILE NAME :

Friday, July 21, 2006

SCHEMATIC FILE NAME :

Place near CPU socket

For future processors

AMD circuit is 51 ohm

Friday, July 21, 2006

SCHEMATIC FILE NAME :

<1200 mil from CPU

<1200 mil from CPU

Friday, July 21, 2006

SCHEMATIC FILE NAME :

22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V

22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V

Place under socket on bottom side

Place close to socket

Place close to socket

Place close to socket

4.7UF/6.3V 4.7UF/6.3V 0.22UF/6.3V

0.01UF/25V 0.01UF/25V 180PF/50V 180PF/50V

22UF/6.3V 22UF/6.3V 0.22UF/6.3V

4.7UF/6.3V 4.7UF/6.3V 0.22UF/6.3V

Place under socket on bottom side

Friday, July 21, 2006

SCHEMATIC FILE NAME :

Layout Note: Place these Caps near SO DIMM 0

Friday, July 21, 2006

SCHEMATIC FILE NAME :

Layout Note: Place these Caps near SO DIMM 1

Friday, July 21, 2006

SCHEMATIC FILE NAME :

Friday, July 21, 2006

DDR2 ADDRESS TERMINATION

SCHEMATIC FILE NAME :

Friday, July 21, 2006

SCHEMATIC FILE NAME :

< 500 mil; 5/5/10

Friday, July 21, 2006

SCHEMATIC FILE NAME :

Friday, July 21, 2006

SCHEMATIC FILE NAME :

Place near C51M

150Ohm 150Ohm 150Ohm

A16 IFPAB_VPROBE C7721

TV SLI Mux Between C51 & G7X