1

1
2
3
4
5
6

:
:
:
:
:
:

QT8 SYSTEM DIAGRAM

PCB STACK UP
LAYER
LAYER
LAYER
LAYER
LAYER
LAYER

DDRII-SODIMM1

TOP
IN1
IN2
VCC
IN3
BOT

DDRII

667/800 MHz

DDRII

667/800 MHz

AMD Lion
Sabie
Griffin

PAGE 7,8
DDRII-SODIMM2

CPU THERMAL
SENSOR

S1G2 Processor

CPU_CLK
NBGFX_CLK

CLOCK GEN

NBGPP_CLK

ICS9LPRS476AKLFT-->HP

SBLINK_CLK

SLG8SP626VTR-->HP

HT3

RTM880N-795 -->HP
PCI-Express 16X

HDMI
PAGE 23

PCI-E
Cable
Docking

VGA
RJ-45
CIR/Pwr btn
SPDIF Out
Stereo MIC
Headphone Jack
USB Port
VOL Cntr

X1

X1
Express
Card

LAN
Realtek
PCIE-LAN
RTL8102E/8111C

Mini PCI-E
Card

(NEW CARD)

PAGE 33

Side port

RJ45

ALINK X4
SATA0,1 150MB

21mm X 21mm, 528pin BGA

PAGE 33

DDR II SMDDR_VTERM
1.8V/1.8VSUS(TPS51116REGR)

Blueflame
PAGE 30

Cable Docking x1
PAGE 37

SATA4 150MB
PAGE 30

4.3W(Int)

Fingerprint
PAGE 30

Flash Media
for UMA only
RTS5158
PAGE 25

Azalia

PAGE 12,13.14.15.16

PAGE 27

SMBUS

PAGE 39

Accelerometer
LIS3LV02DL

IDT
92HD71B7

LPC

PAGE 28

MDC CONN

VGACORE(1.1V~1.2V)Oz8118

Keyboard
Touch Pad

PAGE 42

PAGE 34
PAGE 34

CIR (AUDIO CONN)

PAGE 27

CPU CORE ISL6265A

PAGE 40

Clock gen/Robson/TV tuner

/DDR2/DDR2 thermal/Accelerometer

ENE KBC

PAGE 27

PAGE 29
AUDIO
Amplifier
TPA6017A2

KB3926 Cx

Capacitive Sense
PAGE 34
SW

SMBUS TABLE

IEEE1394
connect for
Discrete
only

Memory
CardReader

PAGE 26

PAGE 25

PAGE 28

PAGE 35

+3V

Digital MIC

AUDIO CONN
(Phone/ MIC)

epress card
Wlan Card

+3VS5

EC --SCL/SD

Battery charge/discharge

+3VPCU

EC--SCL2/SD2

VGA thermal/system thermal

+3V

FAN

SPI

PAGE 30

PAGE 27

Audio
Conn
PAGE 28

PROJECT : QT8
Quanta Computer Inc.

PAGE 37 PAGE 35

Size
Custom
NB5/RD5

Document Number

Rev
1A

Block Diagram

Date: Tuesday, February 19, 2008

1

Touch Screen
for Discrete
only

JMICRON
JMD380 for
Discrete
only

PCIE BUS

4.5W(Ext)

E-SATA

Webcam
X1 PAGE 30

SB700 A12

SATA0 150MB

SATA - CD-ROM

USB2.0 Ports
PAGE 30
X3

SOUTH BRIDGE

PAGE 38

SB--SCL0/SD0

SBSRC_CLK

1,8,9

PAGE 33

SYSTEM POWER ISL6236IRZA-T

Express Card x1
PAGE 33

USB2.0

TWO SATA - HDD

VCCP +1.1V AND +1.2V(MAX8717)

TV-TUNER Card x1
PAGE 36

PAGE 17,18,19
20,21,22

PAGE 8

SYSTEM CHARGER(ISL6251A)

PAGE 41

11

256mb RAM
for UMA only

PAGE 31
PAGE 44

PCI-E WLAN Card x1

PAGE 36

M82-SCE A11

PAGE 8,9,10,11,

PAGE 2

10

64 Bit,DDR2*4

PAGE 37

for
Discrete
only

LVDS
PAGE 23

21mm X 21mm, 528pin BGA

PAGE 36

ATI M82-S

CRT
PAGE 24

RX781 / RS780MN
A12

(Wireless LAN/TV
TUNNER)

(10/100/GagaLAN)

PAGE 31,32

NORTH BRIDGE

X3

14.318MHz

PAGE 5

638P (uPGA)/35W
PAGE 3,4,5,6

PAGE 7,8

01

Sheet

1
8

of

45

L49
BLM18PG181SN1D(180,1.5A)_6

C523
10U/6.3V_8

C496
0.1U/10V_4

C527
C521
0.1U/10V_4 0.1U/10V_4

C476
0.1U/10V_4

C515
0.1U/10V_4

DCR: 0.5 ohm

D

600 ohms@100Mhz
+3V

+3V_CLKVDD

60 ohm, 0.5A

L51
BLM18PG181SN1D(180,1.5A)_6
C541
10U/6.3V_8

C468
0.1U/10V_4

C473
0.1U/10V_4

C512
0.1U/10V_4

+3V_CLKVDD

C522
0.1U/10V_4

L42
BLM18PG181SN1D(180,1.5A)_6

RS780

RP64 STUFF

RP64 STUFF

to NB for VGA reference clock

EXT_GFX_CLKP
EXT_GFX_CLKN

RP66 STUFF

RP66 NC

to M82-S external reference clock -RX780 only

NBGPP_CLKP
NBGPP_CLKN

RP70 STUFF

RP70 NC

to NB for RX780 for PCIEX2 interface reference clock only

RS780 is internal share with AC-LINK clock,RS780 not need

C508
0.1U/10V_4

C500
0.1U/10V_4

C474
0.1U/10V_4

C471
0.1U/10V_4

C469
0.1U/10V_4

SBLINK_CLKP
SBLINK_CLKN

RP72 STUFF

RP72 STUFF

CLK_VGA_27M_SS
CLK_VGA_27M_NSS

+3V_CLK_VDDA

C464
10U/6.3V_8

Clock pin function

VDDA
GNDA

+3V_CLK_VDDA

62
66

VDDREF
GNDREF

C470
0.1U/10V_4

69
29
54
61
38
17
44
3

VDD48
VDDATIG
VDDCPU
VDDHTT
VDDSB_SRC
VDDSRC
VDDSATA
VDDDOT

53
28
37
12
18

VDDCPU_IO
VDDATIG_IO
VDDSB_SRC_IO
VDDSRC_IO1
VDDSRC_IO2

72
27
6
52
58
47
36
11
19

GND48
GNDATIG1
GNDDOT
GNDCPU
GNDHTT
GNDSATA
GNDSB_SRC
GNDSRC1
GNDSRC2

CG_XIN
CG_XOUT

67
68

X1
X2

CLK_PD#

57

PD#

+1.2V_CLKVDDIO
CG_XIN
2

33P/50V_4

Y2
14.318MHZ
33P/50V_4

CG_XOUT

can remove MOSFET level shift

SB/clock gen / DDR2 is 3.3V/S0
6,7,13,28,36 PCLK_SMB
power level

PCLK_SMB
PDAT_SMB

6,7,13,28,36 PDAT_SMB

1
2

14 CHIPSET_PCIE_SLOW_SB#

D17

SB_SRC_SLOW#
2
*CH501H-40PT L-F

when driven lowSB_SRC clocks slow only supported with

to reduced setpoint custom CG IC

41

CPUCLKP
CPUCLKN

CPUKG0T_LPRS
CPUKG0C_LPRS

56
55

ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
ATIG2T_LPRS
ATIG2C_LPRS

33
32
31
30
26
25

NBGFX_CLKP
NBGFX_CLKN
EXT_GFX_CLKP
EXT_GFX_CLKN

SB_SRC0T_LPRS
SB_SRC0C_LPRS
SB_SRC1T_LPRS
SB_SRC1C_LPRS

40
39
35
34

PCIE_MINI2_CLKP
PCIE_MINI2_CLKN
CLK_PCIE_CARD
CLK_PCIE_CARD#

SRC0T_LPRS
SRC0C_LPRS
SRC1T_LPRS
SRC1C_LPRS
SRC2T_LPRS
SRC2C_LPRS
SRC3T_LPRS
SRC3C_LPRS
SRC4T_LPRS
SRC4C_LPRS
SRC5T_LPRS
SRC5C_LPRS
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
SRC7T_LPRS/27Mhz_SS
SRC7C_LPRS/27Mhz_NS

23
22
21
20
16
15
14
13
10
9
8
7
46
45
5
4

NBGPP_CLKN_R
NBGPP_CLKN_L
PCIE_NEW_CLKP
PCIE_NEW_CLKN
PCIE_MINI1_CLKP
PCIE_MINI1_CLKN
SBLINK_CLKP
SBLINK_CLKN
SBSRC_CLKP
SBSRC_CLKN
PCIE_LAN_CLKP
PCIE_LAN_CLKN

HTT0T/66M_LPRS
HTT0C/66M_LPRS
48MHz_0
48MHz_1

60
59
71
70

REF0/SEL_HTT66
REF1/SEL_SATA
REF2/SEL_27

65
64
63

CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#

24
51
50
43
42

eGND77
eGND76
eGND78

77
76
78

SMBCLK
SMBDAT

SB_SRC_SLOW#

eGND73
eGND74
eGND75

THERMAL GND

Del RP for TP on PV

*261_4

RP43

4
2

3 *0_4P2R_4 CPUCLKP
CPUCLKN
1

CPUCLKP 3
CPUCLKN 3

RP54

4
2
4
2

3 *0_4P2R_4 NBGFX_CLKP
NBGFX_CLKN
1
3 *0_4P2R_4 EXT_GFX_CLKP
EXT_GFX_CLKN
1

NBGFX_CLKP 10
NBGFX_CLKN 10
EXT_GFX_CLKP 17
EXT_GFX_CLKN 17

4
2
4
2

3 *0_4P2R_4 PCIE_MINI2_CLKP
PCIE_MINI2_CLKN
1
3 *0_4P2R_4 CLK_PCIE_CARD
CLK_PCIE_CARD#
1

PCIE_MINI2_CLKP 36
PCIE_MINI2_CLKN 36
CLK_PCIE_CARD 26
CLK_PCIE_CARD# 26

to TV TUNER CARD

PCIE_NEW_CLKP 33
PCIE_NEW_CLKN 33
PCIE_MINI1_CLKP 36
PCIE_MINI1_CLKN 36
SBLINK_CLKP 10
SBLINK_CLKN 10
SBSRC_CLKP 12
SBSRC_CLKN 12
PCIE_LAN_CLKP 31
PCIE_LAN_CLKN 31

to EPRESS CARD

RP53

*10P/50V_4

EXT_NB_OSC

C953

*10P/50V_4

CLK_48M_USB

C954

*10P/50V_4

CLK_48M_CR

C955

*10P/50V_4

EVGA-XTALI

C956

*10P/50V_4

OSC_SPREAD

R756
R757
R758
R759

*8.2K_4
*8.2K_4
*8.2K_4
*8.2K_4

CLKREQ0#
CLKREQ2#
CLKREQ3#
CLKREQ4#

CLK_VGA_27M_SS
CLK_VGA_27M_NSS
NBHTREFCLK0P
NBHTREFCLK0N
CLK_48M_CR_L
CLK48MUSB
SEL_HT66
SEL_SATA
SEL_27
CLKREQ0#
EXT_NWD_CLK_REQ#
CLKREQ2#
CLKREQ3#
CLKREQ4#

if use clock
request pin , need
to pull Hi for
default sttting

U10B
SLG8SP626VTR

ICS
SLG
RTL

RP48
RP55

RP51
RP49
RP47
RP45
RP44

T59
T62
3
1
3
1
3
1
3
1
3
1

4
2
4
2
4
2
4
2
4
2

R527
R215
R490

*0_4P2R_4 PCIE_NEW_CLKP
PCIE_NEW_CLKN
*0_4P2R_4 PCIE_MINI1_CLKP
PCIE_MINI1_CLKN
*0_4P2R_4 SBLINK_CLKP
SBLINK_CLKN
*0_4P2R_4 SBSRC_CLKP
SBSRC_CLKN
*0_4P2R_4 PCIE_LAN_CLKP
PCIE_LAN_CLKN
33_4
75/F_4
100/F_4

R193
R194
R201
R192

0_4
0_4
33_4
33_4

to PCIE-CARD READER

Del RP52 for NBGPP CLK

to WLAN
to NB for AC-LINK reference clock
to SB
to PCIE-LAN
to ROBSON

SI-1 Modified --remove

OSC_SPREAD

OSC_SPREAD 18
EVGA-XTALI 18

NBHT_REFCLKP
NBHT_REFCLKN
CLK_48M_CR
CLK_48M_USB

NBHT_REFCLKP 10
NBHT_REFCLKN 10
CLK_48M_CR 25
CLK_48M_USB 13
T58
T167

SSIN - for M82 - 3.3V level input

X_TALIN --for M82 -1.8V level input

Ra

R186
R184 1

158/F_4
2 90.9/F_4

EXT_NB_OSC 10

Rb

EXT_NWD_CLK_REQ# 33

RX780

Clock chip has internal serial

terminations
for differencial pairs, external resistors
are
reserved for debug purpose.

RS780

1.8V

1.1V

Ra

82.5R

158R

Rb

130R

90.9R

RES CHIP 130 1/16W +-1%(0402)L-F -->CS11302FB15

RES CHIP 158 1/16W +-1%(0402) -->CS11582FB00
RES CHIP 90.9 1/16W +-1%(0402) -->CS09092FB15
RES CHIP 82.5 1/16W +-1%(0402) -->CS08252FB11

+3V_CLKVDD

ICS9LPR476BKLFT--AJRS4760000
SLG8SP626VTR--AJ006260000
RTM880N-795-- AJ008800000
* default

+3V

R189
*8.2K_4

R195
8.2K_4

66 MHz 3.3V single ended HTT clock

SEL_27
SEL_SATA
SEL_HT66

SI-1 modified -- reserve for EMT

to NB for external Graphics

reference clock
to M82-S -RX780 only

T196
T84

SLG8SP626VTR
73
74
75

To M82-S 27Mhz - RX780 only

+3V
C952

to NB for AC-LINK reference clock

R196

Place within 0.5"

of CLKGEN

49
48

+3V_CLKVDD

R653,R656,R612 R653,R656,R612
STUFF
NC

U10A

C482
0.1U/10V_4

C465

02

RX780

NBGFX_CLKP
NBGFX_CLKN

+3V_CLKVDD

Place very
close to
C/G

C466

+1.2V_CLKVDDIO

C518
0.1U/10V_4

600 ohms@100Mhz

CLOCKS name

60 ohm, 0.5A

+1.2V

SEL_HTT66
0*

100 MHz differential HTT clock

EXT_NWD_CLK_REQ#

8.2K_4

R219

CLK_PD#

8.2K_4

R204

SB_SRC_SLOW#

8.2K_4

R261
A

100 MHz non-spreading differential SRC clock

SEL_SATA

1
0*

100 MHz spreading differential SRC clock

SEL_27

1*

27MHz non-spreading singled clock

100 MHz spreading differential SRC clock

R203
8.2K_4

R202
*8.2K_4

PROJECT : QT8
Quanta Computer Inc.

RS780M/RX780M
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

Clock Generator
1

Sheet

of

45

BLM21PG221SN1D(220,100M,2A)_8
+CPUVDDA

+2.5V
+1.2V
0_8

R473

0_8

CPU CLK

C416
LS0805-100M-N
10U/6.3V_8

C392
4.7U/6.3V_6

C368
0.22U/6.3V_4

C363
3300P/50V_4

2
2

+CPUVDDA

U31A

HT_NB_CPU_CAD_H[15..0]

8 HT_NB_CPU_CAD_H[15..0]

HT_NB_CPU_CAD_L[15..0]

8 HT_NB_CPU_CAD_L[15..0]

HT_NB_CPU_CLK_H[1..0]

8 HT_NB_CPU_CLK_H[1..0]

HT_NB_CPU_CLK_L[1..0]

8 HT_NB_CPU_CLK_L[1..0]

HT_NB_CPU_CTL_H[1..0]

8 HT_NB_CPU_CTL_H[1..0]

HT_NB_CPU_CTL_L[1..0]

8 HT_NB_CPU_CTL_L[1..0]

HT_CPU_NB_CAD_H[15..0]

8 HT_CPU_NB_CAD_H[15..0]

HT_CPU_NB_CAD_L[15..0]

8 HT_CPU_NB_CAD_L[15..0]

HT_CPU_NB_CLK_H[1..0]

8 HT_CPU_NB_CLK_H[1..0]

HT_CPU_NB_CLK_L[1..0]

8 HT_CPU_NB_CLK_L[1..0]
C

4.7U/6.3V_6
4.7U/6.3V_6
0.22U/6.3V_4
180P/50V_4

HT_CPU_NB_CTL_H[1..0]

8 HT_CPU_NB_CTL_H[1..0]

HT_CPU_NB_CTL_L[1..0]

8 HT_CPU_NB_CTL_L[1..0]

+1.2V_VLDT
+1.2V_VLDT
+1.2V_VLDT
+1.2V_VLDT

D1
D2
D3
D4
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1

J3
J2
J5
K5

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1

N1
P1
P3
P4

CNTR_VREF

AE2
AE3
AE4
AE5

+1.2V_VLDT 4.7U/6.3V_6
+1.2V_VLDT 0.22U/6.3V_4
+1.2V_VLDT 180P/50V_4
+1.2V_VLDT

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

Y1
W1
Y4
Y3

HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

R2
R3
T5
R5

HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1

HT LINK

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

FOX PZ63826-284R-41F
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2)
MLX 47296-4131
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2)
TYC 4-1903401-2
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2)

C854

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

C840
C818
C829

CPUCLKIN
CPUCLKP
CPUCLKN

R571

20K/F_4

+1.2V_VLDT

+1.8VSUS

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

CPU_SIC
CPU_SID
CPU_ALERT

AF4
AF5
AE6

SIC
SID
ALERT_L

R6
P6

HT_REF0
HT_REF1

F6
E6

R141
R108

+1.8VSUS
R776

300/F_4

R777

300/F_4
300_4
R535

T118
T9
0_4

THERMDC
THERMDA

W7
W8

CPU_THERMDC
CPU_THERMDA

VDD0_FB_H
VDD0_FB_L

VDDIO_FB_H
VDDIO_FB_L

W9
Y9

VDDIO_FB_H
VDDIO_FB_L

Y6
AB6

VDD1_FB_H
VDD1_FB_L

VDDNB_FB_H
VDDNB_FB_L

H6
G6

G10
AA9
AC9
AD9
AF9

DBRDY
TMS
TCK
TRST_L
TDI

CPUTEST23

AD7

TEST23

CPUTEST18
CPUTEST19

H10
G9

TEST18
TEST19

CPUTEST25H
CPUTEST25L

E9
E8

THERMTRIP_L
PROCHOT_L
MEMHOT_L

DBREQ_L
TDO

TEST25_H
TEST25_L

AB8
AF7
AE7
AE8
AC8
AF8

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27

C2
AA6

TEST9
TEST6

A3
A5
B3
B5
C1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

E10

CPU_DBREQ# R775

300/F_4
+1.8VSUS

AE9 CPU_TDO

TEST28_H
TEST28_L

J7
H8

CPUTEST28H
CPUTEST28L

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

CPUTEST17
CPUTEST16
CPUTEST15
CPUTEST14

TEST7
TEST10

C3
K8

TEST8

C4

TEST29_H
TEST29_L

C9
C8

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

VDDIO_FB_H 41
VDDIO_FB_L 41

CPU_VDDNB_RUN_FB_H 40
CPU_VDDNB_RUN_FB_L 40

SI-2
modified for
AMD sighting
update

T40
T43
T48
T46
T44
T49

CPUTEST29H
CPUTEST29L

T47
T50

H18
H19
AA7
D5
C5

CPU_SVC_R
CPU_SVD_R
CPU_PWRGD

R577
1K/F_4
R143
0_4

CPU_LDT_REQ# 10

CPU_LDT_RST#

CPU_LDT_RST_HTPA#
3
Q40
BSS138_NL/SOT23

G1
*SHORT_ PAD1

VFIX MODE

R145
R561
R562

*2.2K_4
1K/F_4
1K/F_4

R554
R553
R147

0_4
0_4
0_4

CPU_SVC
CPU_SVD
CPU_PWRGD_SVID_REG

R560
R559

*220_4
*220_4

C926

*0.1U/10V_4

CPU_SVC 40
CPU_SVD 40
CPU_PWRGD_SVID_REG

40

VID Override Circuit

SVC

SVD

0
0
1
1

0
1
0
1

Voltage Output

1.4V
1.2V
1.0V
0.8V

SI-2 remove for power up seq

10K/F_4
2

for debug only

R62

300_4
3

Q11
MMBT3904
CPU_MEMHOT#
1

CPUTEST20
CPUTEST22
CPUTEST12
CPUTEST15
CPUTEST14
CPUTEST19
CPUTEST18

HDT Connector

CPU_MEMHOT# 7,13

+1.8VSUS

R452

10K/F_4
300_4

R453

+1.8VSUS

R60

+1.8VSUS

R454

10K/F_4
300_4

Q35
CPU_THERMTRIP_L#

CPU_PROCHOT_L#

+1.8VSUS

SVC
SVD

Serial VID

34.8K/F_4

0_4

CPU_MEMHOT_L#

+1.8VSUS

CPU_THERMTRIP_L#
CPU_PROCHOT_L#
CPU_MEMHOT_L#

CPUTEST21
CPUTEST20
CPUTEST24
CPUTEST22
CPUTEST12
CPUTEST27

T116

+1.8VSUS
R455

510/F_4
510/F_4

M11
W18

AF6
AC7
AA8

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

T42
T45

KEY1
KEY2

R59

B7
A7
F10
C6

T7

SI-2 modified -confirm AMD R563

need to stuff

CPU_SVC_R
CPU_SVD_R

40 CPU_VDD1_RUN_FB_H
40 CPU_VDD1_RUN_FB_L

SI-2 modified for AMD

sighting update

+1.8V

A6
A4

40 CPU_VDD0_RUN_FB_H
40 CPU_VDD0_RUN_FB_L

+3V

2
+1.8VSUS

A9
A8

CPU_HTREF0
44.2/F_4
44.2/F_4
CPU_HTREF1
place them to CPU within 1.5"

R128
R135

R142
R140
R144
R563

SOCKET_638_PIN

CNTR_VREF

R570

CLKIN_H
CLKIN_L

CPUCLKIN
CPUCLKIN#
CPU_LDT_RST#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU

CPU_SIC
CPU_SID
CPU_ALERT

CNTR_VREF 5

*BSS138_NL/SOT23
3

VDDA1
VDDA2

03

H_THRMDC 5
H_THRMDA 5

U31D
F8
F9

3900P/25V_4
3900P/25V_4

SideBand Temp sense I2C 5

+1.8VSUS

Q39
CPU_LDT_REQ#_CPU 1

C408
C409

CPUCLKIN#

0_4
0_4

300_4
300_4
300_4
300_4

W/S= 15 mil/20mil
+CPUVDDA
+CPUVDDA

SOCKET_638_PIN

0.1U/10V_4

R574

169/F_4

10,12 CPU_LDT_RST#
12 CPU_PWRGD
10,12 CPU_LDT_STOP#

+3V

R137

R569
R567

CPU_LDT_RST#
CPU_LDT_STOP#
CPU_PWRGD
CPU_LDT_REQ#_CPU

CPUCLKP
CPUCLKN

CPUCLKP
CPUCLKN

Keep trace from resisor to CPU within 0.6"

keep trace from caps to CPU within 1.2"

+1.2V_VLDT

C739
C744
C758
C753

CPU_THERMDC
CPU_THERMDA

L36

+1.2V_VLDT
R474

W/S= 15 mil/20mil

3
MMBT3904

Q10
MMBT3904
3

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

CPU_THERMTRIP# 13

CPU_PROCHOT# 12

C54

*0.1U/10V_4

1
3
5
7
9
11
13
15
17
19
21
23
KEY

2
4
6
8
10
12
14
16
18
20
22
24
25

R798
R799
R800
R801
R802
R803
R804

*300/F_4
*300/F_4
*300/F_4
*300/F_4
*300/F_4
*300/F_4
*300/F_4

SI-2 reserve for AMD recommend

PROJECT : QT8
Quanta Computer Inc.

CPU_LDT_RST_HTPA#
Size
Custom
NB5/RD5

CN6 *HDT CONN

Document Number

Rev
1A

S1G2 HT,CTL I/F 1/3

Date: Tuesday, February 19, 2008

5

Sheet

of

45

+0.9VSMVTT

+1.8VSUS

T41

39.2/F_4 M_ZP
39.2/F_4 M_ZN

D10
C10
B10
AD10

VTT1
VTT2
VTT3
VTT4

AF10
AE10

MEMZP
MEMZN

MEM_MA_RESET# H16

6,7 MEM_MA0_ODT0
6,7 MEM_MA0_ODT1

6,7 MEM_MA0_CS#0
6,7 MEM_MA0_CS#1

6,7 MEM_MA_CKE0
6,7 MEM_MA_CKE1

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9
VTT_SENSE

RSVD_M1

MEMVREF

T19
V22
U21
V19

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

RSVD_M2

T20
U19
U20
V20

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

J22
J20

MA_CKE0
MA_CKE1

B18 MEM_MB_RESET#

T51
R77
MEM_MB0_ODT0 6,7
2K/F_4
MEM_MB0_ODT1 6,7

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

V26
W25
U22

MEM_MB0_CS#0 6,7
MEM_MB0_CS#1 6,7

J25
H26

MEM_MB_CKE0 6,7
MEM_MB_CKE1 6,7

MEM_MB_CLK1_P
MEM_MB_CLK1_N
MEM_MB_CLK7_P
MEM_MB_CLK7_N

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

6,7 MEM_MA_BANK0
6,7 MEM_MA_BANK1
6,7 MEM_MA_BANK2

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

MEM_MB_BANK0 6,7
MEM_MB_BANK1 6,7
MEM_MB_BANK2 6,7

6,7 MEM_MA_RAS#
6,7 MEM_MA_CAS#
6,7 MEM_MA_WE#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U25
U24
U23

MEM_MB_RAS# 6,7
MEM_MB_CAS# 6,7
MEM_MB_WE# 6,7

6,7 MEM_MA_ADD[0..15]

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

Reserved

W17 MEMVREF_CPU

P22
R22
A17
A18
AF18
AF17
R26
R25

MEM_MA_CLK1_P
MEM_MA_CLK1_N
MEM_MA_CLK7_P
MEM_MA_CLK7_N

R82
*0_4

2K/F_4
CPU_VTT_SENSE 41

W26
W23
Y26

C197
0.1U/10V_4

C177
1000P/50V_4

6
6
6
6

MEM_MB_ADD[0..15] 6,7

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

SOCKET_638_PIN

6 MEM_MB_DM[0..7]

Place close to socket

+0.9VSMVTT

C112
4.7U/6.3V_6

C399
4.7U/6.3V_6

C99
4.7U/6.3V_6

C398
4.7U/6.3V_6

C213
0.22U/6.3V_4

C369
0.22U/6.3V_4

C364
0.22U/6.3V_4

C201
0.22U/6.3V_4

+0.9VSMVTT

C401
C202
1000P/50V_4 1000P/50V_4

C400
1000P/50V_4

C185
1000P/50V_4

C183
180P/50V_4

C189
180P/50V_4

04

U31C

R81

Y10 CPU_VTT_SENSE

Processor Memory Interface

+0.9VSMVREF 6,41

750 mA

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB_CKE0
MB_CKE1

6 MEM_MB_DATA[0..63]

+1.8VSUS

W10
AC10
AB10
AA10
A10

N19
N20
E16
F16
Y16
AA16
P19
P20

6
6
6
6

+0.9VSMVTT

U31B

PLACE THEM CLOSE TO

CPU WITHIN 1"
R459
R458

C390
180P/50V_4

C396
180P/50V_4

Close to CPU within 1500 mils

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

MEM_MB_DQS0_P
MEM_MB_DQS0_N
MEM_MB_DQS1_P
MEM_MB_DQS1_N
MEM_MB_DQS2_P
MEM_MB_DQS2_N
MEM_MB_DQS3_P
MEM_MB_DQS3_N
MEM_MB_DQS4_P
MEM_MB_DQS4_N
MEM_MB_DQS5_P
MEM_MB_DQS5_N
MEM_MB_DQS6_P
MEM_MB_DQS6_N
MEM_MB_DQS7_P
MEM_MB_DQS7_N

MEM:DATA
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

MEM_MA_DATA[0..63] 6

MEM_MA_DM[0..7] 6
2

MEM_MA_DQS0_P
MEM_MA_DQS0_N
MEM_MA_DQS1_P
MEM_MA_DQS1_N
MEM_MA_DQS2_P
MEM_MA_DQS2_N
MEM_MA_DQS3_P
MEM_MA_DQS3_N
MEM_MA_DQS4_P
MEM_MA_DQS4_N
MEM_MA_DQS5_P
MEM_MA_DQS5_N
MEM_MA_DQS6_P
MEM_MA_DQS6_N
MEM_MA_DQS7_P
MEM_MA_DQS7_N

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

MEM_MA_CLK7_P
MEM_MB_CLK7_P

SOCKET_638_PIN
C734
1.5P/50V_4

C736
1.5P/50V_4

MEM_MA_CLK7_N
MEM_MB_CLK7_N
MEM_MA_CLK1_P
MEM_MB_CLK1_P
C367
1.5P/50V_4

C366
1.5P/50V_4

PROJECT : QT8
Quanta Computer Inc.

MEM_MA_CLK1_N
MEM_MB_CLK1_N
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

A

Rev
1A

S1G2 DDRII MEMORY I/F 2/3

E

Sheet

of

45

05

U31F
U31E

+VCORE0

+CPUVDDNB

3A

+1.8VSUS

2A

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

+VCORE1

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

K16
M16
P16
T16
V16

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8VSUS

SOCKET_638_PIN
+1.8VSUS

3 CNTR_VREF
R166
390_4

R167
1K/F_4

R164
390_4

Q14
1

*BSS138_NL/SOT23
18,35

MBDATA2

MBDATA2

CPU_SIC
Q15
1

*BSS138_NL/SOT23
B

CPU_SIC 3

SMBALERT#

CPU_SID

CPU_SID 3

Q13
1

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

+VCORE0

BOTTOM SIDE DECOUPLING

C287
22U/6.3V_8

C308
22U/6.3V_8

C307
22U/6.3V_8

C306
22U/6.3V_8

C285
0.22U/6.3V_4

C286
0.01U/16V_4

C301
180P/50V_4
D

+VCORE1

C230
22U/6.3V_8

C272
22U/6.3V_8

C273
22U/6.3V_8

+CPUVDDNB

C267
22U/6.3V_8

C206
0.22U/6.3V_4

C226
C205
0.01U/16V_4 180P/50V_4

C225
0.01U/16V_4

+1.8VSUS

C264
22U/6.3V_8

C231
C279
22U/6.3V_8 22U/6.3V_8

C248
22U/6.3V_8

C284
22U/6.3V_8

C309
C247
0.22U/6.3V_4 0.22U/6.3V_4

C214
180P/50V_4

C315
180P/50V_4

DECOUPLING BETWEEN PROCESSOR AND DIMMs

PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8VSUS

C750
4.7U/6.3V_6

C802
4.7U/6.3V_6

C236
4.7U/6.3V_6

C749
4.7U/6.3V_6

C803
0.22U/6.3V_4

C240
0.22U/6.3V_4

+1.8VSUS

C238
C751
C752
C120
0.22U/6.3V_4 0.22U/6.3V_4 0.01U/16V_4 0.01U/16V_4

C118
180P/50V_4

SOCKET_638_PIN

MBCLK2

MBCLK2

18,35

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

CPU_ALERT

CPU_ALERT 3

PROCESSOR POWER AND GROUND

*BSS138_NL/SOT23

+3V

+3V
+VCORE0
R572

10K/F_4

R151

R148

10K/F_4

R170

Update U36 P/N

on PV

*0_4

SYS_SHDN#

reserve for
power shutdown
( if can )

10K/F_4
C856
0.1U/10V_4

SDA

DXP

ALERT#

DXN

OVERT#

GND

13 PM_THERM#

H_THRMDA 3
C855
2200P/50V_4

SI-2 Modified for H/W thermal shutdown

R805

+1.8VSUS

R806

H_THRMDC 3

2
1

+1.8V

EC4

0.01U/16V_4

+3VPCU

EC7

0.01U/16V_4

+5V

EC1

*0.01U/16V_4

EC2

*0.01U/16V_4

EC8

0.01U/16V_4

EC9

0.01U/16V_4

PQ60

10K/F_4

+VGA_CORE

ECPWROK 16,35

0.01U/16V_4

C67

0.01U/16V_4

C64

0.01U/16V_4

+1.8VSUS

EC3

0.01U/16V_4

+5V

+5V

EC6

0.01U/16V_4

+3VPCU

+3V

+1.8V

For fix HyperTransport nets

across plane splits

+3VS5

TEMP_FAIL 18

EC13

+3VS5

+3V

+1.8V

EC14

EC11

PROJECT : QT8
Quanta Computer Inc.

EC12
Size
Custom

*0.1U/10V_4
3

+3V

ADD VGA TEMP_ FAIL function

M8X is active Hi , M7X acvite Low

*2N7002E-G

C71

+3V

*10K/F_4

SMBALERT#

+3V

CH501H-40PT

R760

CPU_THERMTRIP_L#

+3VPCU

3920_RST# 35,44

ECPWROK

R172

*10K/F_4

Q71
*MMBT3904
3

0.01U/16V_4

0.01U/16V_4

D33

MMBT3904
2

CPU_THERMTRIP_L#

3920_RST#

0_4

SMBALERT#

G781P8

*300_4

EC5

+VCORE1
C69

*CH500H

+1.8VSUS

+1.8V

38,44

Q16

MSOP

R168
3

MBDATA2

VCC

18,35

SCLK

+3VPCU

D34

U36
8

MBCLK2

SYS_SHDN#

Del R150, R152

on PV

18,35

0.01U/16V_4

200/F_6
R149

EC10

+1.8VSUS

*0.1U/10V_4

*0.1U/10V_4
2

*0.1U/10V_4

NB5/RD5

Document Number

Rev
1A

S1G2 PWR & GND 3/3

Date: Tuesday, February 19, 2008

Sheet
1

of

45

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

4
4
4
4
4
4
4
4

MEM_MA_DQS0_N
MEM_MA_DQS1_N
MEM_MA_DQS2_N
MEM_MA_DQS3_N
MEM_MA_DQS4_N
MEM_MA_DQS5_N
MEM_MA_DQS6_N
MEM_MA_DQS7_N

11
29
49
68
129
146
167
186

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

30
32
164
166

CK0
CK0
CK1
CK1

MEM_MA_CLK1_P
MEM_MA_CLK1_N
MEM_MA_CLK7_P
MEM_MA_CLK7_N

4,7 MEM_MA_CKE0
4,7 MEM_MA_CKE1
4,7
4,7
4,7
4,7
4,7

MEM_MA_RAS#
MEM_MA_CAS#
MEM_MA_WE#
MEM_MA0_CS#0
MEM_MA0_CS#1

4,7 MEM_MA0_ODT0
4,7 MEM_MA0_ODT1
DIM1_SA0
DIM1_SA1
B

PDAT_SMB
PCLK_SMB

2,7,13,28,36 PDAT_SMB
2,7,13,28,36 PCLK_SMB
+3V

C701
0.1U/10V_4

+0.9VSMVREF_DIMM

CKE0
CKE1

108
113
109
110
115

RAS
CAS
WE
S0
S1

114
119

ODT0
ODT1

198
200

SA0
SA1

195
197

SDA
SCL

199

VDDspd

VREF

2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
201
202

C849
C391 1000P/50V_4
C370 0.1U/10V_4
2.2U/6.3V_6

79
80

50
69
83
120
163

MEMHOT_SODIMM#_1
MEM_MA_RESET#1

VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34

196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133

MEM_MA_NC5

81
82
87
88
95
96
103
104
111
112
117
118
MEM_MB_BANK0 107
MEM_MB_BANK1 106
MEM_MB_BANK2
85

BA0
BA1
BA2

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

10
26
52
67
130
147
170
185

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

4
4
4
4
4
4
4
4

MEM_MB_DQS0_P
MEM_MB_DQS1_P
MEM_MB_DQS2_P
MEM_MB_DQS3_P
MEM_MB_DQS4_P
MEM_MB_DQS5_P
MEM_MB_DQS6_P
MEM_MB_DQS7_P

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

4
4
4
4
4
4
4
4

MEM_MB_DQS0_N
MEM_MB_DQS1_N
MEM_MB_DQS2_N
MEM_MB_DQS3_N
MEM_MB_DQS4_N
MEM_MB_DQS5_N
MEM_MB_DQS6_N
MEM_MB_DQS7_N

11
29
49
68
129
146
167
186

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

4
4
4
4

MEM_MB_CLK1_P
MEM_MB_CLK1_N
MEM_MB_CLK7_P
MEM_MB_CLK7_N

30
32
164
166

CK0
CK0
CK1
CK1

4,7 MEM_MB_CKE0
4,7 MEM_MB_CKE1

79
80

CKE0
CKE1

4,7 MEM_MB_RAS#
4,7 MEM_MB_CAS#
4,7 MEM_MB_WE#
4,7 MEM_MB0_CS#0
4,7 MEM_MB0_CS#1

108
113
109
110
115

RAS
CAS
WE
S0
S1

114
119

ODT0
ODT1

T155

DIM2_SA0
DIM2_SA1

198
200

SA0
SA1

T115

PDAT_SMB
PCLK_SMB

195
197

SDA
SCL

199

VDDspd

R106

4,7 MEM_MB0_ODT0
4,7 MEM_MB0_ODT1
MEMHOT_SODIMM# 7

0_4

+3V

C702
0.1U/10V_4

+0.9VSMVREF_DIMM
C848
2.2U/6.3V_6

C406
0.1U/10V_4

+1.8VSUS

R138
2K/F_4

+0.9VSMVREF_DIMM

4,41 +0.9VSMVREF

R139

*0_4

+0.9VSMVREF_DIMM

Only for reserved

R130
2K/F_4

C397
1000P/50V_4

VREF

2
o3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54

VSS0
VSS1
oVSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20

MEM_MB_DATA[0..63] 4

CN31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA45
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA44
MEM_MB_DATA41
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA60
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA61
MEM_MB_DATA57
MEM_MB_DATA62
MEM_MB_DATA63

NC1
NC2
NC3
NC4
NC/TEST

50
69
83
120
163

MEMHOT_SODIMM#_2 R105
MEM_MB_RESET#2
T156

VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34

196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11

NC1
NC2
NC3
NC4
NC/TEST

4 MEM_MB_DM[0..7]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

SO-DIMM
(REVERSE)

MEM_MA_DQS0_P
MEM_MA_DQS1_P
MEM_MA_DQS2_P
MEM_MA_DQS3_P
MEM_MA_DQS4_P
MEM_MA_DQS5_P
MEM_MA_DQS6_P
MEM_MA_DQS7_P

4,7 MEM_MB_BANK[0..2]

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

4
4
4
4
4
4
4
4

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

GND
GND

4
4
4
4

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

GND
GND

10
26
52
67
130
147
170
185

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA35
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA52
MEM_MA_DATA49
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA53
MEM_MA_DATA48
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59

59
60
65
66
71
72
77
78
121
122
127
128
132

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

4,7 MEM_MB_ADD[0..15]

201
202

BA0
BA1
BA2

SO-DIMM
(Normal)

4 MEM_MA_DM[0..7]

MEM_MA_BANK0 107
MEM_MA_BANK1 106
MEM_MA_BANK2 85

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

4,7 MEM_MA_BANK[0..2]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

59
60
65
66
71
72
77
78
121
122
127
128
132

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84

MEM_MA_DATA[0..63] 4

CN30

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11

4,7 MEM_MA_ADD[0..15]
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

07

+1.8VSUS
81
82
87
88
95
96
103
104
111
112
117
118

+1.8VSUS

MEM_MB_NC5

0_4

MEMHOT_SODIMM#

T114

DDR SO-DIMM SOCKET 1.8V

H=9.2

DDR SO-DIMM SOCKET 1.8V

H=5.2
DIM2_SA0
DIM2_SA1
R40
R43

10K/F_4
10K/F_4

DIM1_SA0
DIM1_SA1

R423
R424

10K/F_4
10K/F_4

PROJECT : QT8
Quanta Computer Inc.

+3V

SMbus address A2
Size
Custom

SMbus address A0
NB5/RD5

Document Number

Rev
1A

DDR2 SODIMMS: A/B CHANNEL

Date: Tuesday, February 19, 2008

1

Sheet

of

45

MEM_MA_ADD[0..15]

4,6 MEM_MA_ADD[0..15]

MEM_MB_BANK[0..2]

4,6 MEM_MB_BANK[0..2]

+0.9VSMVTT
MEM_MA_CKE0
MEM_MA_BANK2
MEM_MA_ADD12
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD5
MEM_MA_ADD3
MEM_MA_ADD1
MEM_MA_ADD10
MEM_MA_BANK0
MEM_MA_WE#
MEM_MA_CAS#
MEM_MA0_ODT1
MEM_MA0_CS#1
MEM_MA_ADD15
MEM_MA_CKE1

4,6 MEM_MA_CKE0
D

4,6
4,6
4,6
4,6

MEM_MA_WE#
MEM_MA_CAS#
MEM_MA0_ODT1
MEM_MA0_CS#1

4,6 MEM_MA_CKE1

RP40

3
1
3
1
1
3
1
3
3
1
3
1
3
1
3
1

MEM_MA_ADD7 RP33
MEM_MA_ADD14
MEM_MA_ADD6 RP29
MEM_MA_ADD11

4
2
4
2

3 47_4P2R_4
1
3 47_4P2R_4
1

MEM_MA_ADD2
MEM_MA_ADD4

4
2

3 47_4P2R_4
1

C102

0.1U/10V_4

2
4

1 47_4P2R_4
3

C107

0.1U/10V_4

4
2

3 47_4P2R_4
1

RP28
RP26
RP20
RP16
RP10
RP39

RP24

MEM_MA_BANK1 RP21
MEM_MA_ADD0
MEM_MA0_CS#0 RP14
MEM_MA_RAS#

4,6 MEM_MA0_CS#0
4,6 MEM_MA_RAS#

MEM_MA_ADD13 RP12
MEM_MA0_ODT0

4,6 MEM_MA0_ODT0

+0.9VSMVTT

47_4P2R_4

4
2
4
2
2
4
2
4
4
2
4
2
4
2
4
2

RP35

C176

0.1U/10V_4

C256

0.1U/10V_4

4,6 MEM_MB_CKE0
+1.8VSUS

47_4P2R_4
47_4P2R_4
C223

0.1U/10V_4

C104

0.1U/10V_4

C217

0.1U/10V_4

C96

0.1U/10V_4

+1.8VSUS

47_4P2R_4
47_4P2R_4

+1.8VSUS

47_4P2R_4
47_4P2R_4
C152

0.1U/10V_4

C271

0.1U/10V_4

C162

0.1U/10V_4

+1.8VSUS

47_4P2R_4

3 47_4P2R_4
1

4
2

C101

0.1U/10V_4

C208

0.1U/10V_4

C270

0.1U/10V_4

C146

0.1U/10V_4

C269

08

MEM_MB_ADD[0..15]

4,6 MEM_MB_ADD[0..15]

MEM_MA_BANK[0..2]

4,6 MEM_MA_BANK[0..2]

4,6
4,6
4,6
4,6
4,6

MEM_MB_WE#
MEM_MB_CAS#
MEM_MB0_ODT1
MEM_MB0_CS#1
MEM_MB_CKE1

+1.8VSUS

+1.8VSUS

+1.8VSUS

RP36

MEM_MB_ADD7
MEM_MB_ADD14

RP34

RP32
RP27
RP25
RP18
RP15
RP9
RP38

47_4P2R_4

4
2
2
4
4
2
4
2
4
2
4
2
4
2
2
4

3
1
1
3
3
1
3
1
3
1
3
1
3
1
1
3

4
2

3 47_4P2R_4
1

C193

0.1U/10V_4

C245

0.1U/10V_4

C154

0.1U/10V_4

C100

0.1U/10V_4

C137

0.1U/10V_4

C94

0.1U/10V_4

C190

0.1U/10V_4

C93

0.1U/10V_4

C160

0.1U/10V_4

C254

0.1U/10V_4

C173

0.1U/10V_4

C255

0.1U/10V_4

C126

0.1U/10V_4

C253

0.1U/10V_4

C178

0.1U/10V_4

C105

0.1U/10V_4

47_4P2R_4

+1.8VSUS
D

47_4P2R_4
47_4P2R_4

+1.8VSUS

47_4P2R_4
47_4P2R_4

+1.8VSUS

47_4P2R_4
47_4P2R_4

MEM_MB_ADD6
MEM_MB_ADD11

RP30

4
2

3 47_4P2R_4
1

MEM_MB_ADD2
MEM_MB_ADD4

RP22

4
2

3 47_4P2R_4
1

MEM_MB_BANK1
MEM_MB_ADD0

RP19

4
2

3 47_4P2R_4
1

4,6 MEM_MB0_CS#0
4,6 MEM_MB_RAS#

MEM_MB0_CS#0
MEM_MB_RAS#

RP13

4
2

3 47_4P2R_4
1

4,6 MEM_MB0_ODT0

MEM_MB0_ODT0
MEM_MB_ADD13

RP11

2
4

1 47_4P2R_4
3

+1.8VSUS

0.1U/10V_4

MEM_MB_CKE0
MEM_MB_BANK2
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD5
MEM_MB_ADD3
MEM_MB_ADD1
MEM_MB_ADD10
MEM_MB_BANK0
MEM_MB_WE#
MEM_MB_CAS#
MEM_MB0_ODT1
MEM_MB0_CS#1
MEM_MB_CKE1
MEM_MB_ADD15

+1.8VSUS

+1.8VSUS

+1.8VSUS

+1.8VSUS

+1.8VSUS
C

PLACE CLOSE TO PROCESSOR

WITHIN 1.5 INCH

PLACE CLOSE TO PROCESSOR

WITHIN 1.5 INCH
+1.8VSUS

+1.8VSUS

C239
0.1U/10V_4

C121
0.1U/10V_4

C241
0.1U/10V_4

C242
0.1U/10V_4

C117
0.1U/10V_4

C235
0.1U/10V_4

C122
0.1U/10V_4

PLACE CLOSE TO SOCKET( PER EMI/EMC)

C119
0.1U/10V_4

C237
0.1U/10V_4

C115
0.1U/10V_4

C116
0.1U/10V_4

C745
0.1U/10V_4

PLACE CLOSE TO SOCKET( PER EMI/EMC)

+3VS5

+3V

CPU_MEMHOT# 3,13

Close DDR2 socket

+3V

U25

PDAT_SMB
PCLK_SMB

1
2

SDA
SCL

O.S

GND

C706

0.1U/10V_4

MEMHOT_SODIMM#

*33_4

2
Q32
*2N7002E-G

2
Q33
*2N7002E-G

2,6,13,28,36 PDAT_SMB
2,6,13,28,36 PCLK_SMB

R416
+VS

+3V

A0
A1
A2

modified --SB internal pull HI to 3vs5

R417
*10K/F_4
R421
*10K/F_4

7
6
5

SI-2

*DS75U+T&R

+3V

R422

Address:92h

10K/F_4 MEMHOT_SODIMM#

MEMHOT_SODIMM# 6

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

DDR2 SODIMMS TERMINATIONS

Sheet
1

of

45

U32A

SI-2 modified
-- follow AMD
check list to
change part
number 300 ohm
to 301 ohm

R533

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HYPER TRANSPORT CPU I/F

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1

HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18

HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1

M22
M23
R21
R20

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1

C23
A24

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

HT_TXCALP R534
HT_TXCALN

R655

HT_RXCALP
HT_RXCALN

301/F_4

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]

HT_CPU_NB_CAD_H[15..0]

HT_CPU_NB_CAD_L[15..0]

HT_CPU_NB_CLK_H[1..0]

HT_CPU_NB_CLK_L[1..0]

HT_CPU_NB_CTL_H[1..0]

HT_CPU_NB_CLK_H[1..0]
HT_CPU_NB_CLK_L[1..0]
HT_CPU_NB_CTL_H[1..0]
HT_CPU_NB_CTL_L[1..0]

HT_CPU_NB_CTL_L[1..0]

HT_NB_CPU_CAD_H[15..0]

HT_NB_CPU_CAD_L[15..0]

HT_NB_CPU_CLK_H[1..0]

HT_NB_CPU_CLK_L[1..0]

HT_NB_CPU_CTL_H[1..0]

HT_NB_CPU_CTL_L[1..0]

HT_NB_CPU_CAD_H[15..0]
HT_NB_CPU_CAD_L[15..0]
HT_NB_CPU_CLK_H[1..0]
HT_NB_CPU_CLK_L[1..0]
HT_NB_CPU_CTL_H[1..0]
HT_NB_CPU_CTL_L[1..0]

signals

RS780

HT_TXCALP
SI-2 modified
-- follow AMD
check list to
change part
number 300 ohm
to 301 ohm

HT_TXCALN
HT_RXCALP
HT_RXCALN

08

RX780

R641
301 ohm 1%

R641
1.21k ohm 1%

R655
301 ohm 1%

R655
1.21k ohm 1%

RES CHIP 1.21K 1/16W +-1%(0402)

P/N : CS21212FB18

RES CHIP 301 1/16W +-1%(0402)

P/N : CS13012FB14
C

R641

301/F_4

RS780(RX780)
U27
L2
L3

BA0
BA1

SPM_A12
SPM_A11
SPM_A10
SPM_A9
SPM_A8
SPM_A7
SPM_A6
SPM_A5
SPM_A4
SPM_A3
SPM_A2
SPM_A1
SPM_A0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

K8
J8

CK
CK

K2

CKE

SPM_CLKN
SPM_CLKP

*100_4

Within 200mils

SPM_CKE

SPM_CS#

L8

CS

SPM_WE#

K3

WE

SPM_RAS#

K7

RAS

SPM_CAS#

L7

CAS

SPM_DM0
SPM_DM1

F3
B3

LDM
UDM

SPM_ODT

K9

ODT

SPM_DQS0P
SPM_DQS0N

F7
E8

LDQS
LDQS

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

R63
*1K_4

C89
*0.1U/10V_4

R61
*1K_4

SPM_DQS1P
SPM_DQS1N
SPM_VREF

SPM_BA2

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+1.8V

T24

L76
*BLM18PG181SN1D(180,1.5A)_6
MEM_VDDQ_VDDL

C757
*1U/10V_4
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

40mils wdith or more

U32D

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

C95
*0.1U/10V_4

This block is for UMA RS780 only , RX780 can

remove all component

SPM_DQ15
SPM_DQ14
SPM_DQ9
SPM_DQ12
SPM_DQ8
SPM_DQ10
SPM_DQ13
SPM_DQ11
SPM_DQ5
SPM_DQ3
SPM_DQ4
SPM_DQ1
SPM_DQ0
SPM_DQ7
SPM_DQ2
SPM_DQ6

AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

SPM_BA0
SPM_BA1
SPM_BA2

AD16
AE17
AD17

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

SPM_RAS#
SPM_CAS#
SPM_WE#
SPM_CS#
SPM_CKE
SPM_ODT

W12
Y12
AD18
AB13
AB18
V14

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

SPM_CLKP
SPM_CLKN

V15
W14

MEM_CKP(NC)
MEM_CKN(NC)

R502
R501

*40.2/F_4 SPM_COMPP AE12

*40.2/F_4 SPM_COMPN AD12

+1.8V_MEM_VDDQ

MEM_COMPP(NC)
MEM_COMPN(NC)

+1.8V_MEM_VDDQ
R487

PAR 4 OF 6

SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13

SBD_MEM/DVO_I/F

R56

SPM_BA0
SPM_BA1

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

SPM_DQ0
SPM_DQ1
SPM_DQ2
SPM_DQ3
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ7
SPM_DQ8
SPM_DQ9
SPM_DQ10
SPM_DQ11
SPM_DQ12
SPM_DQ13
SPM_DQ14
SPM_DQ15

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)

Y17
W18
AD20
AE21

SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N

MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)

W17
AE19

SPM_DM0
SPM_DM1

IOPLLVDD18(NC)
IOPLLVDD(NC)

AE23
AE24

IOPLLVSS(NC)

AD23

MEM_VREF(NC)

C70
*1U/10V_4

C738
*10U/6.3V_8

C76
*10U/6.3V_8

C87
*0.1U/10V_4

C77
*0.1U/10V_4

C74
*1U/10V_4

IOPLLVDD18 - memory PLL

not applicable to RX780

+1.8_IOPLLVDD18_NB
+1.1V_IOPLLVDD

Del L77, L78

for TP on PV
C762

AE18 SPM_VREF1

C763
*2.2U/6.3V_6

*2.2U/6.3V_6

IOPLLVDD- memory PLL

not applicable to RX780

RS780(RX780)
R498

C775

*1K_4

*0.1U/10V_4

R497

*1K_4

C774

*0.1U/10V_4

+1.8V_MEM_VDDQ

PROJECT : QT8
Quanta Computer Inc.
Size
Custom

*HYB18T512161B2F-25
NB5/RD5

Document Number

Rev
1A

RS740/RS780-HT LINK I/F 1/5

Date: Tuesday, February 19, 2008

5

*0_6

Sheet

of

45

U32B

PCIE_RXP5
PCIE_RXN5

PCIE_RXP0
AE3
PCIE_RXN0
AD4
PCIE_RXP1
AE2
PCIE_RXN1
AD3
PCIE_RXP6_LAN AD1
PCIE_RXN6_LAN AD2
PCIE_RXP3
V5
PCIE_RXN3
W6
PCIE_RXP4
U5
PCIE_RXN4
U6
PCIE_RXP5
U8
PCIE_RXN5
U7

PCIE_SB_NB_RX0P
PCIE_SB_NB_RX0N
PCIE_SB_NB_RX1P
PCIE_SB_NB_RX1N
PCIE_SB_NB_RX2P
PCIE_SB_NB_RX2N
PCIE_SB_NB_RX3P
PCIE_SB_NB_RX3N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

33 PCIE_RXP0
33 PCIE_RXN0
36 PCIE_RXP1
36 PCIE_RXN1
31 PCIE_RXP6_LAN
31 PCIE_RXN6_LAN
36 PCIE_RXP3
36 PCIE_RXN3
T223
T225

26
26
12
12
12
12
12
12
12
12

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

C_PEG_TX15
C_PEG_TX#15
C_PEG_TX14
C_PEG_TX#14
C_PEG_TX13
C_PEG_TX#13
C_PEG_TX12
C_PEG_TX#12
C_PEG_TX11
C_PEG_TX#11
C_PEG_TX10
C_PEG_TX#10
C_PEG_TX9
C_PEG_TX#9
C_PEG_TX8
C_PEG_TX#8
C_PEG_TX7
C_PEG_TX#7
C_PEG_TX6
C_PEG_TX#6
C_PEG_TX5
C_PEG_TX#5
C_PEG_TX4
C_PEG_TX#4
C_PEG_TX3
C_PEG_TX#3
C_PEG_TX2
C_PEG_TX#2
C_PEG_TX1
C_PEG_TX#1
C_PEG_TX0
C_PEG_TX#0

C360
C359
C362
C361
C343
C354
C351
C350
C814
C815
C810
C809
C811
C813
C806
C805
C804
C800
C798
C801
C791
C795
C792
C796
C788
C785
C787
C784
C778
C783
C771
C777

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

PCIE_TXP0_C
PCIE_TXN0_C
PCIE_TXP1_C
PCIE_TXN1_C
PCIE_TXP6_C
PCIE_TXN6_C
PCIE_TXP3_C
PCIE_TXN3_C
PCIE_TXP4_C
PCIE_TXN4_C
PCIE_TXP5_C
PCIE_TXN5_C

C158
C159
C131
C130
C149
C148
C772
C773

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

C139
C140

T224
T226
0.1U/10V_4
0.1U/10V_4

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

A_TX0P_C C766
A_TX0N_C C767
A_TX1P_C C765
A_TX1N_C C764
A_TX2P_C C150
A_TX2N_C C151
A_TX3P_C C754
A_TX3N_C C755

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

AC8
AB8

PART 2 OF 6

PCIE I/F GFX

PEG_RX15
PEG_RX#15
PEG_RX14
PEG_RX#14
PEG_RX13
PEG_RX#13
PEG_RX12
PEG_RX#12
PEG_RX11
PEG_RX#11
PEG_RX10
PEG_RX#10
PEG_RX9
PEG_RX#9
PEG_RX8
PEG_RX#8
PEG_RX7
PEG_RX#7
PEG_RX6
PEG_RX#6
PEG_RX5
PEG_RX#5
PEG_RX4
PEG_RX#4
PEG_RX3
PEG_RX#3
PEG_RX2
PEG_RX#2
PEG_RX1
PEG_RX#1
PEG_RX0
PEG_RX#0

PCIE I/F GPP

PCIE I/F SB

NB_PCIECALRP
NB_PCIECALRN

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

R491
R489

17 PEG_RX#[15:0]

PEG_TX15
PEG_TX#15
PEG_TX14
PEG_TX#14
PEG_TX13
PEG_TX#13
PEG_TX12
PEG_TX#12
PEG_TX11
PEG_TX#11
PEG_TX10
PEG_TX#10
PEG_TX9
PEG_TX#9
PEG_TX8
PEG_TX#8
PEG_TX7
PEG_TX#7
PEG_TX6
PEG_TX#6
PEG_TX5
PEG_TX#5
PEG_TX4
PEG_TX#4
PEG_TX3
PEG_TX#3
PEG_TX2
PEG_TX#2
PEG_TX1
PEG_TX#1
PEG_TX0
PEG_TX#0

17 PEG_RX[15:0]

PEG_RX#[15:0]

PEG_TX#[15:0]

PEG_RX[15:0]

PEG_TX[15:0]

PEG_TX#[15:0] 17
PEG_TX[15:0] 17

Close to North Bridge

C_PEG_TX15
C_PEG_TX#15
C_PEG_TX14
C_PEG_TX#14
C_PEG_TX13
C_PEG_TX#13
C_PEG_TX12
C_PEG_TX#12

C_PEG_TX15 23
C_PEG_TX#15 23
C_PEG_TX14 23
C_PEG_TX#14 23
C_PEG_TX13 23
C_PEG_TX#13 23
C_PEG_TX12 23
C_PEG_TX#12 23

To HDMI CONN

PCIE_TXP0 33
PCIE_TXN0 33
PCIE_TXP1 36
PCIE_TXN1 36
PCIE_TXP6_LAN 31
PCIE_TXN6_LAN 31
PCIE_TXP3 36
PCIE_TXN3 36

TO EPRESS CARD

PCIE_TXP5 26
PCIE_TXN5 26

TO PCIE CARD READER

TO WLAN
TO PCIE-LAN
TO TV TUNNER
C

PCIE_NB_SB_TX0P
PCIE_NB_SB_TX0N
PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N
PCIE_NB_SB_TX2P
PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P
PCIE_NB_SB_TX3N

1.27K/F_4
2K/F_4

12
12
12
12
12
12
12
12

+1.1V

RS780(RX780)
RX780/RS740/RS780 difference table (PCIE LINK)
RS740

RS780 Display Port Support (muxed on GFX)

RX780/RS780
GFX_TX0,TX1,TX2 and TX3

NB_PCIECALRP

562R (GND)

1.27K (GND)

DP0
AUX0 and HPD0

GPP4

NC

GPP4

GPP5

NC

GPP5

GFX_TX4,TX5,TX6 and TX7

DP1
B

AUX1 and HPD1

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Rev
1A

RS740/RS780-PCIE I/F 2/5

Date: Tuesday, February 19, 2008

1

Sheet

of

45

F12
E12
F14
G15
H15
H14

+1.8V_AVDDDI_NB

rail
or

+1.8V_AVDDQ_NB

R160

12 NB_PLTRST#
D

*0_4

S-CD1

E17
F17
F15

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

CRT_R_1

G18
G17
E18
F18
E19
F19

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

NB_RST#_IN

0_4

North Bridge RESET

18,24

CRT_R

18,24

CRT_G

18,24

CRT_B

18,19,24 HSYNC_COM
18,19,24 VSYNC_COM
18,24 DDCDATA
18,24 DDCCLK

R446
R109
R445
R110
R444
R111

*0_4
*150/F_4
*0_4
*150/F_4
*0_4
*150/F_4

R549
R540
R133
R134

*0_4
*0_4
*0_4
*0_4

HSYNC_INT
VSYNC_INT
DDCDATA_INT
DDCCLK_INT

A11
B11
E8
F8

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SDA(PCE_TCALRN)
DAC_SCL(PCE_RCALRN)

R119

*715/F_6

DAC_RSET_NB

G14

DAC_RSET(PWM_GPIO1)

+1.1V_PLLVDD
+1.8V_PLLVDD18

A12
D14
B12

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)

H17

VDDA18HTPLL

CRT_G_1
CRT_B_1

+1.8V_VDDA18HTPLL
+1.8V_VDDA18PCIEPLL

16 NB_PWRGD_IN

2 NBHT_REFCLKP
2 NBHT_REFCLKN
2

EXT_NB_OSC
+1.1V

+3V

RS780 only

R536

4.7K_4

HDTV_DET

R539

4.7K_4

NB_I2C_DATA

R538

4.7K_4

NB_I2C_CLK

R125 RS780
4.7K_4

R547
R546
R537
R544

18,23 EDIDDATA
18,23 EDIDCLK
23 HDMI_DDC_DATA
23 HDMI_DDC_CLK

RS780 R120

4.7K_4

NB_RST#_IN
NB_PWRGD_IN
NB_LDT_STOP#
NB_ALLOW_LDTSTOP

D8
A10
C10
C12

SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP

NBHT_REFCLKP
NBHT_REFCLKN

C25
C24

HT_REFCLKP
HT_REFCLKN

E11
F11

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)

NB_REFCLK_P
NB_REFCLK_N

GFX_REFCLKP
GFX_REFCLKN

I/O

NBGPP_CLKP
NBGPP_CLKN

U1
U2

GPP_REFCLKP
GPP_REFCLKN

I/O

SBLINK_CLKP
SBLINK_CLKN

V4
V3

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)

NB_I2C_DATA
NB_I2C_CLK
HDTV_DET
RS740_DFT_GPIO0
RS740_DFT_GPIO1

A9
B9
B8
A8
B7
A7

I2C_DATA
I2C_CLK
DDC_DATA/AUX0N(NC)
DDC_CLK/AUX0P(NC)
AUX1P(NC)
AUX1N(NC)

0_4 STRP_DATA

B10

STRP_DATA

G11

RSVD

R27

T164

RS780_AUX_CAL

C8

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

B18
A18
A17
B17
D20
D21
D18
D19

LB_DATAP0
LB_DATAN0
LB_DATAP1
LB_DATAN1
LB_DATAP2
LB_DATAN2
LB_DATAP3
LB_DATAN3

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

B16
A16
D16
D17

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

LB_DATAP0
LB_DATAN0
LB_DATAP1
LB_DATAN1
LB_DATAP2
LB_DATAN2

23
23
23
23
23
23

10

T159
T157

T163
T160
LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

VDDLTP18(NC)
VSSLTP18(NC)

A13
B13

+1.8V_VDDLTP18_NB

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A15
B15
A14
B14

+1.8V_VDDLT_18_NB

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

E9
F7
G12

23
23
23
23

+3V_VDLT33_NB

R132
R126
R118

R121

*1.27K/F_4

R127

*1.27K/F_4

TMDS_HPD0
TMDS_HPD1

TVCLKIN(PWM_GPIO5)

D12

SUS_STAT#_NB

THERMALDIODE_P
THERMALDIODE_N

AE8
AD8

R_NB_THRMDA
R_NB_THRMDC

TMDS_HPD(NC)
HPD(NC)

DISP_ON
LVDS_BLON
DPST_PWM

DISP_ON 19,23
LVDS_BLON 18,23
DPST_PWM 19,23

For RX780 only

UMA only

R545
*0_4

D9
D10

MIS.

*0_4
*0_4
*0_4

TMDS_HPD 18,23

T162
R131

0_4

SUS_STAT# 13

T136
T135

D13 TEST_EN

TESTMODE

R541
1.82K/F_4

AUX_CAL(NC)

R543

BLM18PG181SN1D(180,1.5A)_6

RX780 -->NC / RS780 --- ADD

RX780
RS780_AUX_CAL

+3V

3K_4

L35
BLM18PG181SN1D(180,1.5A)_6

+3V_AVDD_NB

+1.1V_PLLVDD

+1.1V

L82

+1.8V

PLLVDD - Graphics PLL

not applicable to
RX780

C842
2.2U/6.3V_6

C340
2.2U/6.3V_6

BLM18PG181SN1D(180,1.5A)_6
+1.8V_VDDLTP18_NB
L83

RS780
VSYNC_COM

R124

3K_4

+1.8V
L33
BLM18PG181SN1D(180,1.5A)_6

+3V

+1.8V_PLLVDD18

C405
10U/6.3V_8

R129

3K_4

R136

*3K_4

R107

0_6

+1.8V_VDDLT_18_NB
L85
C846
4.7U/6.3V_6

RX780 +1.8V
+1.8V

10K/F_4

R558

*10K/F_4

L32

20mils width
+1.8V_VDDA18PCIEPLL

RS780

Q37
BSS138_NL/SOT23

BLM18PG181SN1D(180,1.5A)_6

+VDDG_NB

C358
2.2U/6.3V_6

R556
4.7K_4

3,12 CPU_LDT_STOP#

R566

*0_6

R565

0_6

+VDDG_NB

+VDDG_NB

RS780/RX780
R548

0.1U/10V_4

VDDLT18 - LVDS or
DVI/HDMI digital
not applicable to
RX780

C349
2.2U/6.3V_6

+3V

VDDA18PCIEPLL -PCIE PLL

STRP_DATA

C838

AVDDQ-DAC Bandgap Reference

not applicable to RX780

BLM18PG181SN1D(180,1.5A)_6
+1.8V_AVDDQ_NB
L34

+1.8V

For extrnal EEPROM Debug only

BLM21PG221SN1D(220,100M,2A)_8

AVDDI-DAC Digital
not applicable to RX780

+1.8V_AVDDDI_NB
C321
2.2U/6.3V_6

C333
2.2U/6.3V_6

PLLVDD18 - Graphics PLL

not applicable to RX780

RS780
HSYNC_COM

VDDLTP18 - LVDS or DVI/HDMI PLL

not applicable to RX780

C841
2.2U/6.3V_6

+1.8V

Enables Debug Bus acess

through memory T/O pads and GPIO.
0 : Enable RS780 , Default
1 : Disable RS780
(RS780 use VSYNC#)

Indicates if memory Side port

is available or not
0: available RS780 , Default
1: Not available RS780
( RS780 use HSYNC#)

23
23
23
23
23
23

RS780(RX780)

AVDD-DAC Analog
not applicable to RX780

LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2

RS780 only
I

T2
T1

T161
T158

A22
B22
A21
B21
B20
A20
A19
B19

NBGFX_CLKP
NBGFX_CLKN

*0_4
*0_4
*0_4
*0_4

39 DYN_PWR_EN

selects Loading of straps from

EPROM
1 : use default vaule , default
0 : I2C Master can load strap
values from EEPROM
if connected, or use default
values if not connected
RX780 --RS780_AUX_CAL
RS780 -- SUS_ATAT

VDDA18PCIEPLL1
VDDA18PCIEPLL2

0_4

2 NBGFX_CLKP
2 NBGFX_CLKN
T168
T169
2 SBLINK_CLKP
2 SBLINK_CLKN

Del NBGPP CLK

C

D7
E7

R117

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

PLL PWR
LVTM

RS780

LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2
LA_DATAP3
LA_DATAN3

PM

R157

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

CRT/TVOUT

rail
or

R109 for UAM use 140 ohm

RX780
3,12 CPU_LDT_RST#

U32C

CLOCKs

RX780: Powered from the 1.8-V

and driven by SB600 LDT_RST#,
SB700 LDT_RST# or A_RST#.
RS780: Powered from the 3.3-V
and driven by SB600 LDT_RST#,
SB700 LDT_RST# or A_RST#.

+3V_AVDD_NB

RS780

RS780

+3V

NB_LDT_STOP#

L84
+3V_VDLT33_NB

+3V

*BLM21PG221SN1D(220,100M,2A)_8
R555

VDDA18HTPLL -HT LINK PLL

Enables Debug Bus acess

through memory T/O pads and GPIO.
1 : Enable RX780 , Default
0 : Disable RX780

L31

RX780
R810

*3K_4

+VDDG_NB
+1.8V

Q38
BSS138_NL/SOT23
3 CPU_LDT_REQ#

12 ALLOW_LDTSTOP

R568

0_4

R557
4.7K_4

R564

VDDLT33 - LVDS or DVI/HDMI ANALOG

RS740 only

RS780

RS780
C356
2.2U/6.3V_6

Reserved only

*2.2U/6.3V_6
A

20mils width
+1.8V_VDDA18HTPLL

BLM18PG181SN1D(180,1.5A)_6
S-CD1

PROJECT : QT8
Quanta Computer Inc.

NB_ALLOW_LDTSTOP

*0_4

Size
Custom

RX780
5

C844

RX780

*0_4

NB5/RD5

Document Number

Rev
1A

RS740/RS780-SYSTEM I/F 3/5

Date: Tuesday, February 19, 2008

1

Sheet

10

of

45

PART 6/6

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

GROUND

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

11

RX780/RS780 POWER DIFFERENCE TABLE

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

U32F

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

PIN NAME

RX780

RS780

PIN NAME

RX780

VDDHT

+1.1V

+1.1V

IOPLLVDD

NC

VDDHTRX

+1.1V

+1.1V

AVDD

NC

+3.3V

VDDHTTX

+1.2V

+1.2V

AVDDDI

NC

+1.8V

VDDA18PCIE

+1.8V

+1.8V

AVDDQ

NC

+1.8V

VDDG18

+1.8V

+1.8V

PLLVDD

NC

+1.1V

VDD18_MEM

NC

+1.8V

PLLVDD18

NC

+1.8V

VDDPCIE

+1.1V

+1.1V

VDDA18PCIEPLL

+1.8V

+1.8V

VDDC

+1.1V

+1.1V

VDDA18HTPLL

+1.8V

+1.8V

VDD_MEM

NC

+1.8V/1.5V

VDDLTP18

NC

+1.8V

VDDG33

NC

+3.3V

VDDLT18

NC

+1.8V

IOPLLVDD18

NC

+1.8V

VDDLT33

NC

NC

RS780
+1.1V

+1.1V

+1.1V 2A for RS780M

0.6A

C770
4.7U/6.3V_6

VDDHTRX - HT
LINK RX I/O for
RX780/RS780

0.45A

0.5A

L13
+1.35V
*BLM21PG221SN1D(220,100M,2A)_8

+1.35V for
A1-1 chip
bug , A1-2
can remove
B

C274
0.1U/10V_4

C313
0.1U/10V_4

C323
0.1U/10V_4

C843
0.1U/10V_4

L81
BLM21PG221SN1D(220,100M,2A)_8

+1.2V 2A for RS780M+SB700

C124
4.7U/6.3V_6

C195
0.1U/10V_4

C280
0.1U/10V_4

+1.1V_VDDHTRX

C847
4.7U/6.3V_6

L12
+1.2V
BLM21PG221SN1D(220,100M,2A)_8

C194
0.1U/10V_4

C839
0.1U/10V_4

+1.2V_VDDHTTX

C249
0.1U/10V_4

C199
0.1U/10V_4

VDDHTTX - HT
LINK TX I/O for
RX780/RS780

+1.8V 1A for RS780M+SB700

+1.8V

600mA

L22

+1.8V_VDDA18PCIE

BLM21PG221SN1D(220,100M,2A)_8

VDDA18PCIE PCIE TX stage

I/O for
RX780/RS780

C188
4.7U/6.3V_6

VDD18 - RS780 I/O +1.8V

transform

+1.8V

C175
4.7U/6.3V_6

R122

C258
0.1U/10V_4

0_6

C209
0.1U/10V_4

0_6

VDD18_MEM For UMA RS780 only

Not applicable to RX780
memory I/O transform

C302
0.1U/10V_4

C234
0.1U/10V_4

0.005A
C317
1U/10V_4

R499

VDDPCIE - PCIE-E Main power

U32E
+1.1V_VDDHT

L72
BLM21PG221SN1D(220,100M,2A)_8

0.005A
C769
1U/10V_4

+1.8V_VDDG18_NB
+1.8V_VDD18_MEM

J17
K16
L16
M16
P16
R16
T16

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

H18
G19
F20
E21
D22
B23
A23

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
F9
G9
AE11
AD11

PART 5/6

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

POWER

VDDHT - HT
LINK digital
I/O for
RX780/RS780

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDDG18_1(VDD18_1)
VDDG18_2(VDD18_2)
VDD18_MEM1(NC)
VDD18_MEM2(NC)

VDDG33_1(NC)
VDDG33_2(NC)

RS780(RX780)

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

0.7A

+1.1V_VDD_PCIE
C275
0.1U/10V_4

C337
0.1U/10V_4

C318
1U/10V_4

C328
1U/10V_4

R542

0_8

+1.1V

C845
4.7U/6.3V_6

VDDC - Core Logic power

7A

+1.1V_DYN
C251
0.1U/10V_4

C292
0.1U/10V_4

C297
0.1U/10V_4

C303
0.1U/10V_4

C59
10U/6.3V_8

C281
0.1U/10V_4

C278
0.1U/10V_4

AE10
AA11
Y11
AD10
AB10
AC10

+1.8V_VDD_MEM

H11
H12

+3V_VDDG33

C192
0.1U/10V_4

C336
0.1U/10V_4

C250
0.1U/10V_4

C60
10U/6.3V_8

1.8V(0.15A)

C179
0.1U/10V_4

C172
0.1U/10V_4

C216
0.1U/10V_4
RS780
0_6

R123

VDD_MEM For UMA RS780 only

Not applicable to RX780
memory I/O transform
L23

C153
4.7U/6.3V_6

+1.8V
BLM21PG221SN1D(220,100M,2A)_8

3.3V(0.03A)
+3V

VDD33 - 3.3V I/O

Not applicable to RX780

C329
0.1U/10V_4

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

RS740/RS780-POWER5/5
Sheet
1

11

of

45

9
9
9
9
9
9
9
9

L44

R581
R587

PCIE_CALRP_SB
PCIE_CALRN_SB

562/F_4
2.05K/F_4

BLM18PG181SN1D(180,1.5A)_6

PCIE_PVDD-- PCIE PLL POWER

A_RX0P_C
A_RX0N_C
A_RX1P_C
A_RX1N_C
A_RX2P_C
A_RX2N_C
A_RX3P_C
A_RX3N_C

PCIE_NB_SB_TX0P
PCIE_NB_SB_TX0N
PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N
PCIE_NB_SB_TX2P
PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P
PCIE_NB_SB_TX3N

PCIE_NB_SB_TX0P
PCIE_NB_SB_TX0N
PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N
PCIE_NB_SB_TX2P
PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P
PCIE_NB_SB_TX3N

+1.2V_PCIE_VDDR
+1.2V

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

+1.2V_PCIE_PVDD

40mA
C485
10U/6.3V_8

C503
1U/10V_4

N2

SB700
A_RST#

Part 1 of 5

V23
V22
V24
V25
U25
U24
T23
T22

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

U22
U21
U19
V19
R20
R21
R18
R17

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

T25
T24

PCIE_CALRP
PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

20M_6

C900
18P/50V_4

C899
18P/50V_4
R257

0_4

T74

If CPU have pull Hi ,this

pin should be not need
PV-1
Modified
-- change
to pull hi
to 3VS5
for power
leakage
issue
A

M23
M22

SLT_GFX_CLKP
SLT_GFX_CLKN

+1.8V

R232

RTC_X1

+3VS5

R588

GPP_CLK1P
GPP_CLK1N

M19
M20

GPP_CLK2P
GPP_CLK2N

N22
P22

GPP_CLK3P
GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

*10K/F_4
RTC_X2

10 ALLOW_LDTSTOP
3 CPU_PROCHOT#
3
CPU_PWRGD
3,10 CPU_LDT_STOP#
3,10 CPU_LDT_RST#

GPP_CLK0P
GPP_CLK0N

10K/F_4
ALLOW_LDTSTOP
CPU_PROCHOT#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_RST#

F23
F24
F22
G25
G24

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

PCIRST#

N1

PCIRST#_L

T108
T214
PCI_CLK_TPM 16
PCI_CLK3 16
PCI_CLK4 16
PCI_CLK5 16

R643

33_4

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

AD3
AC4
AE2
AE3

INTE#
INTF#
INTG#
INTH#

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

LPC_CLK0
LPC_CLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#_SB
LDRQ1#_SB
SB_GPIO65
SERIRQ

C3
C2
B2

RTC_CLK
INTRUDER_ALERT#
+AVBAT

PCI INTERFACE

CPU_HT_CLKP
CPU_HT_CLKN

100MHZ

CLOCK GENERATOR

R626

P17
M18

L20
L19

RTC_X2

32.768KHZ
*20M_6

NB_HT_CLKP
NB_HT_CLKN

RTC

R632

NB_DISP_CLKP
NB_DISP_CLKN

J19
J18

K23
K22
M24
M25

CPU

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

LPC

RTC_X1
Y8

N25
N24

RTC XTAL

SBSRC_CLKP
SBSRC_CLKN

SBSRC_CLKP
SBSRC_CLKN

PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R
PCI_CLK5_R

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

2
2

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

P4
P3
P1
P2
T4
T3

RTCCLK
INTRUDER_ALERT#
VBAT

PCIRST#

PCIRST# 35

+3V
PE_GPIO1

SB_GPIO65

R294

8.2K_4

R299

*8.2K_4

R274

*100K/F_4

R809

8.2K_4

+3V

AD23
AD24
AD25
AD26
AD27
AD28

AD23
AD24
AD25
AD26
AD27
AD28

16
16
16
16
16
16

change D21, D20 type for PV

All the PCI bus has

build-in Pull-UP/Down
resistors

D21
RB500V-40

SI-2 mofified for satify -remove R560 , add R796 ,R797

+AVBAT

20MILR796

499/F_4

+3VRTC_1

R797

20MIL

+3VPCU
10_4 +3VRTC

20MIL

C907
1U/10V_4

1U/10V_4
SERR#

SERR#

R298

SI-2 Modified-- for power leakage issue

R187

PE_GPIO1

20MIL

35

0_4

RF_OFF# 36
D3E GPIO# 26

0_4

Del R783 for

TP on PV

SI-2 Modified-- Add GPIO pin for control D3E wake up ( need low 1ms
for Jmicron request)
R631
R629

CLKRUN#_R

0_4
0_4

20MIL

LCD_BK
23
CLKRUN# 35

T213
T110
T217
INTH#
R243
R589

BAT_CONN

R589 change to 10 ohm on PV

28
LPC_CLK0 16
LPC_CLK1 16

22_4
10_4

PCLK_LPC_DEBUG
35,36
35,36
35,36
35,36
35,36

SERIRQ

35

RTC_CLK 16

SI-2
modified
-- for EMI
suggestion

C940
C939
22P/50V_4

5.6P/50V_6

SI-1 Modified - for EMI

R782

*1M/F_4

+AVBAT

+AVBAT

C902
0.1U/10V_4

PROJECT : QT8
Quanta Computer Inc.
Document Number

Rev
1A

SB700-PCIE/PCI/CPU/LPC 1/4

Date: Tuesday, February 19, 2008

3

G3
*SHORT_ PAD1

SI-2 Modified--reserve

INTRUDER_ALERT# Left not connected (Southbridge

has 50-kohm internal pull-up to VBAT).

Size
Custom

36

PCLK_LPC_KB3920 35

LAD0
LAD1
LAD2
LAD3
LFRAME#
T61
T90
T107

20MIL

BT1

T94

NB5/RD5
5

D20
RB500V-40

C906

SB700

IC CTRL(528P) SB700 A11(218S7EALA11FG)

P/N : AJALA110T00

+VCCRTC_2

C869
C868
C865
C864
C871
C870
C867
C866

Del R639, R640, R641, R642 on PV

U37A
A_RST#_SB

+BAT

PCIE_SB_NB_RX0P
PCIE_SB_NB_RX0N
PCIE_SB_NB_RX1P
PCIE_SB_NB_RX1N
PCIE_SB_NB_RX2P
PCIE_SB_NB_RX2N
PCIE_SB_NB_RX3P
PCIE_SB_NB_RX3N

12

33_4
33_4
33_4
33_4
33_4
33_4

9
9
9
9
9
9
9
9

R250
R252
R312
R251
R241
R660

NB_PLTRST#
PCIE_RST#
CARD_PLTRST#
LAN_PLTRST#
EPRESS_PLTRST#
MINI_PLTRST#

PCI CLKS

10
17
26
31
33
36

PCI EXPRESS INTERFACE

PLACE THESE
PCIE AC
COUPLING CAPS
CLOSE TO U600

To RS780

Sheet
1

12

of

45

+3VSUS

13

NC only ,Can't be install

R297

*2.2K_4

SB_TEST0

R240

*2.2K_4

SB_TEST1

R287

*2.2K_4

SB_TEST2

U37D

+3VS5

R245

2.2K_4

PCLK_SMB

R253

2.2K_4

PDAT_SMB

35

D3

SATA_IS1
LAN_DISABLE#_SB

*0_4

SB_NWD_CLK_REQ#

T222
R302

*0_4

ACZ_SPKR
PCLK_SMB
PDAT_SMB
SB_SMBCLK1
SB_SMBDATA1

T69
T75

SB_SCLK2
SB_SDATA2

*2.2K_4
*2.2K_4

*0_4 RSMRST#

R217

27,28 ACZ_SPKR
2,6,7,28,36 PCLK_SMB
2,6,7,28,36 PDAT_SMB

SCL2/SDATA2 is 3V/S5 tolerance

AMD datasheet define it
R222
R227

*0_4
0_4

R284

RSMRST#

T63
T194
31,35 LAN_DISABLE#

remove pull hi
( chip internal
have pull hi )
+3VS5

R211
R786

SI-2 modified -- Change lan

disable control from SB to EC SB
reserve

SB_SMBCLK1
SB_SMBDATA1

*2.2K_4
*2.2K_4

GATEA20
RCIN#
SCI#
KBSMI#
T109

31,33,36 PCIE_WAKE#
35
SWI#
3 CPU_THERMTRIP#
16 WD_PWRGD

SCL1/SDATA1 is 3V/S5 tolerance

AMD datasheet define it
R648
R649

35
35
35
35

Clock gen/Robson/TV
tuner
/DDR2/DDR2
thermal/Accelerometer

PM_BATLOW#
SES_INT

35 PM_BATLOW#
T72
D3E_SCI#

26

+3V

AE18
AD18
AA19
W17
V17
W20
W21
AA18
W18
K1
K2
AA20
Y18
C1
Y19
G5

CLK_48M_USB

G8

USB_RCOMP_SB

USB_FSD13P
USB_FSD13N

E6
E7

USB_FSD13P
USB_FSD13N

USB_FSD12P
USB_FSD12N

F7
E8

USB_FDS12P
USB_FSD12N

USB_HSD11P
USB_HSD11N

H11
J10

USBP11+ 36
USBP11- 36

TV Min-Card

USB_HSD10P
USB_HSD10N

E11
F11

USBP10+ 36
USBP10- 36

WLAN Min-Card

USB_HSD9P
USB_HSD9N

A11
B11

USBP9+
USBP9-

30
30

USB Connector

USB_HSD8P
USB_HSD8N

C10
D10

USBP8+
USBP8-

30
30

USB Connector

USB_HSD7P
USB_HSD7N

G11
H12

USBP7+
USBP7-

33
33

NEW CARD

USB_HSD6P
USB_HSD6N

E12
E14

USBP6+
USBP6-

30
30

FINGERPRINT

USB_HSD5P
USB_HSD5N

C12
D12

USBP5+
USBP5-

30
30

BLUETOOTH

USB_HSD4P
USB_HSD4N

B12
A12

USBP4+
USBP4-

37
37

Docking

USB_HSD3P
USB_HSD3N

G12
G14

USBP3+
USBP3-

USB_HSD2P
USB_HSD2N

H14
H15

USBP2+
USBP2-

30
30

Carama USB

USB_HSD1P
USB_HSD1N

A13
B13

USBP1+
USBP1-

30
30

E-SATA and USB Connector

USB_HSD0P
USB_HSD0N

B14
A14

USBP0+
USBP0-

30
30

USB Connector

IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

G20
G21
D25
D24
C25
C24
B25
C23

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

USB MISC

RSMRST#

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#

D3E_SCI# from Gevent5# change to Gevent7# on PV

R276

4.7K_4

SI-2 modified Del D35

SUS_STAT#

CPU_MEMHOT#_IN
R275
*0_4
SMBALERT#_1
R279
*10K/F_4
SB_JTAG_TDO
SB_JTAG_TCK
SB_JTAG_TDI
SB_JTAG_RST#

3,7 CPU_MEMHOT#
5 PM_THERM#
+3VS5

*SHORT_ PAD1
+3VS5
2.2K_4

DNBSWON#
ACZ_BCLK
ACZ_SDOUT
ACZ_SDIN0_R
ACZ_SDIN1_R

To Azalia
ACZ_SDOUT

R644

33_4

T98
T209
ACZ_SDOUT_AUDIO

C908

ACZ_SYNC
ACZ_RST#

27
16

*10P/50V_4

ACZ_RST#

HD audio
interface is
3.3S5 voltage

ACZ_SYNC

R290

33_4

ACZ_SYNC_AUDIO
C569

ACZ_BCLK

R646

33_4

R296

ACZ_SDIN0_R

R295

33_4

10P/50V_4

ACZ_RST#_AUDIO

0_4

ACZ_SDIN0

To Modem Board
R645

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

*10P/50V_4

27
+3VS5

ACZ_SDOUT

M1
M2
J7
J8
L8
M3
L6
M4
L5

BIT_CLK_AUDIO 27
C910

ACZ_RST#

27

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

33_4

27

R592

ACZ_SDOUT_AUDIO_MDC
C909

22K_4

HDD_AUX_RST#

SI-2 Modified --for

EMI suggestion

H19
H20
H21
F25

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3

D22
E24
E25
D23

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

29

INTEGRATED uC

R763

B9
B8
A8
A9
E5
F8
E4

INTEGRATED uC

SYS_RST#

HD AUDIO

USB OC

G4

CLK_48M_USB 2
R267

R292

33_4

T91
T93

USB

SB_SCLK2
SB_SDATA2
SB_SCLK3
SB_SDATA3

C577

29

ACZ_BCLK

R647

33_4

ACZ_RST#

R293

33_4

ACZ_SDIN1_R

R286

0_4

BIT_CLK_AUDIO_MDC
C911

29

10P/50V_4

SB JTAG

ACZ_RST#_AUDIO_MDC

ACZ_SDIN1

29

1
2
3
4
5
6
7
8

SB_GPIO16 16
SB_GPIO17 16

SPI/LPC define

+3VS5
+3V
R764
2K/04
3

33,36 SCLK_WLAN
+3VS5

33,36 SDATA_WLAN

PDAT_SMB

Q67

CLOSE TO SB
USBP3USBP3+
RP50

SB_JTAG_RST#

2
4

1
3

*0_4P2R_4

USBP6_CR- 25
USBP6_CR+ 25

PROJECT : QT8
Quanta Computer Inc.

UMA
Size
Custom

Document Number

Rev
1A

SB700-ACPI/GPIO/USB 2/4

Date: Tuesday, February 19, 2008

4

PCLK_SMB

2N7002EPT
SB_JTAG_TCK
SB_JTAG_TDO
SB_JTAG_TDI
SB_TEST1

NB5/RD5
5

Q66
2N7002EPT
+3V

*S/W JTAG DEBUG

29

card reader or Touch screen

SI-2 Modified -- discrete remove RP56

C462
10P/50V_4

CN16

R765
2K/04

+3VSUS

*10P/50V_4

for EMI & del R268

change 2.2P

T64
T70

SB_GPIO16
SB_GPIO17

*10P/50V_4

ACZ_SYNC_AUDIO_MDC

C554
*2.2P/50V_4

T101
T199

SB700
ACZ_SYNC

CLK_48M_USB

11.8K/F_6

is 3V tolerance
AMD datasheet define it

C8

USB_RCOMP

USBCLK/14M_25M_48M_OSC

+3V SCL0/SDATA0

PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD

USB 1.1

SI-2 modified add D3E function

E1
E2
H7
F5
G1
H2
H1
K3
H5
H4
H3
Y15
W15
K4
K24
F1
J2
H6
F2
J6
W14

USB 2.0

*10K/F_4 SWI#

R289

NEWCARD_DETECT
RI#
SLP_S2
SUSB#
SUSC#
DNBSWON#
SB_PWRGD_IN
SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0
GATEA20
RCIN#
SCI#
KBSMI#
GEVENT5#
SYS_RST#
PCIE_WAKE#
SWI#
SB_THERMTRIP#
WD_PWRGD

*0_4
*0_4
*0_4

GPIO

+3VSUS
D

R271
R191
R233

ACPI / WAKE UP EVENTS

33 NEWCARD_DETECT
T211
T99
35
SUSB#
35
SUSC#
35
DNBSWON#
16 SB_PWRGD_IN
10
SUS_STAT#

Part 4 of 5

SB700

Sheet
1

13

of

45

SATA_RXN0
SATA_RXP0

33
33

SATA_TXP4
SATA_TXN4

33
33

SATA_RXN4
SATA_RXP4

30
30

SATA_TXP2
SATA_TXN2

30
30

SATA_RXN2
SATA_RXP2

0.01U/16V_4
0.01U/16V_4

SATA_TXP0_C
SATA_TXN0_C

AD9
AE9

SATA_TX0P
SATA_TX0N

C563
C562

0.01U/16V_4
0.01U/16V_4

SATA_RXN0_C
SATA_RXP0_C

AB10
AC10

SATA_RX0N
SATA_RX0P

C544
C543

0.01U/16V_4
0.01U/16V_4

SATA_TXP1_C
SATA_TXN1_C

AE10
AD10

SATA_TX1P
SATA_TX1N

C535
C529

0.01U/16V_4
0.01U/16V_4

SATA_RXN1_C
SATA_RXP1_C

AD11
AE11

SATA_RX1N
SATA_RX1P

SATA_TXP2_C
SATA_TXN2_C

AB12
AC12

SATA_TX2P
SATA_TX2N

SATA_RXN2_C
SATA_RXP2_C

AE12
AD12

SATA_RX2N
SATA_RX2P

SATA_TXP3_C
SATA_TXN3_C

AD13
AE13

SATA_TX3P
SATA_TX3N

SATA_RXN3_C
SATA_RXP3_C

AB14
AC14

SATA_RX3N
SATA_RX3P

SATA_TXP4_C
SATA_TXN4_C

AE14
AD14

SATA_TX4P
SATA_TX4N

SATA_RXN4_C
SATA_RXP4_C

AD15
AE15

SATA_RX4N
SATA_RX4P

SATA_TXP5_C
SATA_TXN5_C

AB16
AC16

SATA_TX5P
SATA_TX5N

SATA_RXN5_C
SATA_RXP5_C

AE16
AD16

SATA_RX5N
SATA_RX5P

R613
R615

4.99/F_4
4.99/F_4

T197
T198
T88
T85
T227
T228
T229
T230

SATA PORT 4,5 are

only support IDE
mode

T89
T87

R264

R361

T86
T82
1K/F_4

SATA_RBIAS_PN
SATA_X1

PLACE SATA_CAL
RES VERY CLOSE
TO BALL OF SB700

NOTE:

SATA_X2
SB_SATA_LED#

PLVDD_SATA-SATA PLL
POWER

R361 IS 1K 1% FOR 25MHz

XTAL, 4.99K 1% FOR 100MHz
INTERNAL CLOCK

+3V

R382

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

Part 2 of 5

PLLVDD_SATA

+3V_XTLVDD_SATA

W12

XTLVDD_SATA

XTLVDD_SATA-- SATA
crystal power
C534

SATA_X1
Y4

T231
T232
T233
T234
T235
T236
T237
T238
T239
T240
T241

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

T242
T243
T244
T245
T246
T247
T248
T249
T250
T251
T252
T253
T254
T255
T256
T257

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS#/GPIO32

G6
D2
D1
F4
F3

LAN_RST#/GPIO13
ROM_RST#/GPIO14

U15
J1

IF THERE IS NO IDE, TEST

POINTS FOR DEBUG BUS
IS MANDATORY

R265
ROM_RST#

0_4

BT_OFF# 30

T215

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

P5
P8
R8

SB_FANTACH0
SB_FANTACH1
PORT_80_PWR_DWN

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

C6
B6
A6
A5
B5

TEMP_COMM
TEMPIN0
TEMPIN1
MB_THRMDA_SB

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

A4
B4
C4
D4
D5
D6
A7
B7

SATA_X2

T100
T219
T218
T111
T220

SB_FANOUT0
SB_FANOUT1

25MHZ
C517

R262
10M_6

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

M8
M5
M7

SATA_ACT#/GPIO67

AA11

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

10K/F_4

+1.2V_PLLVDD_SATA

27P/50V_4

ATA 66/100/133

E-SATA

33
33

C559
C558

SPI ROM

SATA ODD

SATA_TXP0
SATA_TXN0

T96
T97
CHIPSET_PCIE_SLOW_SB#

R216

T208
T202
T203
T207
T259
0_4

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4

SB700

+3V

C655
0.1U/10V_4

+1.2V

( 1.2V @ 60mA) +1.2V_PLLVDD_SATA

AVDD

F6

AVSS

G7

77mA

L47
BLM18PG181SN1D(180,1.5A)_6
2

+3VS5

R221

10K/F_4

BOARD_ID0

R229

*10K/F_4

R247

*10K/F_4

BOARD_ID1

R248

*10K/F_4

R225

*10K/F_4

BOARD_ID2

R228

*10K/F_4

R230

*10K/F_4

BOARD_ID3

R242

*10K/F_4

R596

*10K/F_4

BOARD_ID4

R600

*10K/F_4

Del R220 for TP on PV

ACCLED_EN 29
BT_COMBO_EN# 36

Del WAN off#

and R597 on
PV

5mA

+3V_VDD_HWM
C571
*0.1U/10V_4

L52
C572
*2.2U/6.3V_6

SI-2 modified -- for fix +3V power leakage in S5 mode

0_6

AVDD--H/W monitor
Analog power
ID4

ID3

ID2

ID1

ID0

UMA

discrete

SB_SATA_LED#
C524
1U/10V_4

SATA_LED#

SI-2 modified -- SB
internal pull Hi to 3VS5
, modified to same power
rail with SB

+3VS5

C550
0.1U/10V_4

29

T104
T92
T95

27P/50V_4

U20
TC7SH08FU

14
SB700

HW MONITOR

33
33

U37B

SERIAL ATA

SATA1

PLACE SATA AC COUPLING

CAPS CLOSE TO SB600

SATA PWR

SATA PORT 0,1,2,3

can support AHCI
mode

1mA

+3V

( 3.3V @ 1.2mA)
SI-2 modified for SATA LED fail issue

+3V_XTLVDD_SATA

L46
BLM18PG181SN1D(180,1.5A)_6
C539
1U/10V_4

Place near
ball

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

SB700-ACPI/GPIO/USB 2/4
Sheet
1

14

of

45

For SB700 issue(6/22)

PLACE ALL THE DECOUPLING CAPS ON

THIS SHEET CLOSE TO SB AS POSSIBLE.
Del R285 for TP on PV

VDD-- S/B CORE power

SB700

286mA
1
2

1
0.1U/50V_6

0.1U/50V_6

+1.2V

BLM18PG181SN1D(180,1.5A)_6
C478
2.2U/6.3V_6

C475
2

C489

2.2U/6.3V_6

C505
2

L43

L21
L22
L24
L25

C875
0.1U/10V_4

C570
0.1U/10V_4

0_6
1

+3VS5

Change to 0603
C876
10U/6.3V_8

S5_1.2V--1.2V standby power

USB_PHY_1.2V_1
USB_PHY_1.2V_2

G2
G4

A10
B10

+1.2V_S5

0.2A

S5_1.2V_1
S5_1.2V_2

0.22A
C903
0.1U/10V_4

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

R604
2

AA14
AB18
AA15
AA17
AC18
AD17
AE17

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

C901
0.1U/10V_4

+1.2V_USB_PHY_R

Del R661
for TP on
PV

+3V_AVDD_USB

AVDDTX--USB Phy
Analog I/O power

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

AE7
J16

+3V_AVDDCK

7mA

AVDDCK_1.2V

K17

+1.2V_AVDDCK

44mA

AVDDC

E9

+3V_AVDDC

R621

2 1K/F_4

1
1
D36

C898
1U/10V_4

+5V
H18
J17
J22
K25
M16
M17
M21
P16

+3V

CH501H-40PT

16mA

F9

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC

SB700

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21
AVSSCK

Part 5 of 5

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25

L17

SB700

C536
0.1U/10V_4

+3VS5

+3V_AVDDC

+1.2V_USB_PHY_R

C546
0.1U/10V_4

1
C540
10U/6.3V_8

1
2

C890
C891
C892
0.1U/10V_4 0.1U/10V_4 10U/6.3V_8

AVDDC--USB Analog PLL power

USB_PHY_1.2V--USB Phy
digital power

0_6
1
1

R616
2

L50
BLM18PG181SN1D(180,1.5A)_6

+1.2V_S5

C879
0.1U/10V_4

1
C510
0.1U/10V_4

1
C511
0.1U/10V_4

1
2

1
C885
1U/10V_4

1
C537
1U/10V_4

+1.2V

+1.2V_AVDDCK

1
C509
2.2U/6.3V_6

L48
BLM18PG181SN1D(180,1.5A)_6

+3V_AVDDCK

AVDDCK_3.3--Analog
system PLL power

L45
BLM18PG181SN1D(180,1.5A)_6

+3V

AVDDCK_1.2--USB Phy
digital power

PROJECT : QT8
Quanta Computer Inc.

C528
1U/10V_4

+5V_VREF

V5_VREF
AVDDCK_3.3V

C886
0.1U/10V_4

4mA

C878
0.1U/10V_4

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

PLL

A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

1
C882
10U/6.3V_8

C889
10U/6.3V_8

1
2

L91

+3VS5

BLM18PG181SN1D(180,1.5A)_6

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

V5_VREF--PCI 5V TOLERANCE

0.2A

USB I/O

For support USB wakeup-->3V_S5

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

S5_3.3--3.3v standby power

0.01A

A17
A24
B17
J4
J5
L1
L2

U37E

+1.2V

CKVDD_1.2V-- Internal
clock Generator I/O
power

C881
1U/10V_4

23

+1.2V_S5

C467
10U/6.3V_8

1
2

1
2

1
2

1
2

C532
1U/10V_4

+3VALW_R

SATA I/O

C883
1U/10V_4

0.2A

1
C884
0.1U/10V_4

C880
0.1U/10V_4

C888
10U/6.3V_8

1
2

BLM18PG181SN1D(180,1.5A)_6

C538
1U/10V_4

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

+1.2V_AVDD_SATA
+1.2V

C545
1U/10V_4

P18
P19
P20
P21
R22
R24
R25

3.3V_S5 I/O

C483
1U/10V_4

AVDD_SATA--SATA phy power

L92

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

CORE S5

C492
1U/10V_4

C504
1U/10V_4

844mA

C484
1U/10V_4

C502
1U/10V_4

1
C477
10U/6.3V_8

+1.2V

R198
1 0_8

A1-1 chip bug

use A1-2 chip can remove

POWER

+1.2V_PCIE_VDDR

BLM18PG181SN1D(180,1.5A)_6

C533
1U/10V_4

IDE/FLSH I/O

C488
1U/10V_4

A-LINK I/O

C497
1U/10V_4

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

CLKGEN I/O

Y20
AA21
AA22
AE25

C487
1U/10V_4

PCIE_VDDR--PCIE I/O power

L89

L15
M12
M14
N13
P12
P14
R11
R15
T16

+1.2V_CKVDD

0.45A

C501
1U/10V_4

C486
10U/6.3V_8

1 *0_8

R751 2

+1.8V

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

+VDD33_18

VDD33_18--3.3V IDE I/O power

1.8V flash memory I/O power

1 0_8
1

R226 2

+3V

Part 3 of 5

1.8V : FLASH MEMORY MODE(DEFAULT)

3.3V: IDE MODE

C574
1U/10V_4

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

604mA

C553
1U/10V_4

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

CORE S0

C547
1U/10V_4

C565
1U/10V_4

C573
1U/10V_4

C560
1U/10V_4

C557
10U/6.3V_8

100U/6.3V_3528

C576

+3V

SB700

PCI/GPIO I/O

0.8A

R590
1 *0_8

+1.2V_VCC_SB_R

U37C

VDDQ--3.3V I/O power

GROUND

C516
2.2U/6.3V_6
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

SB700-PWR/DECOUPLING 4/4
Sheet
1

15

of

45

16

OVERLAP COMMON PADS WHERE

POSSIBLE FOR DUAL-OP RESISTORS.
It must ready
refore RSMRST#
+3V

+3VS5
1

+3V

REQUIRED STRAPS

+3VS5

SI-2 Modified
-R599 change from
10kohm to 2.2kohm
for fix system can
not boot

12

LPC_CLK0

PCI_CLK5

12

12

RTC_CLK

LPC_CLK1

13

GPIO16

ACZ_RST#

R598
*2.2K_4

R255
2.2K_4

GPIO17

BOOTFAIL
TIMER
ENABLED

PULL
HIGH

R291
10K/F_4

R595
10K/F_4
2

PCI_CLK3

PCI_CLK4

PCI_CLK5

LPC_CLK0

LPC_CLK1

RTC_CLK

USE
DEBUG
STRAPS

RESERVED

RESERVED

IMC
ENABLED

CLKGEN
ENABLED

INTERNAL
RTC

BOOTFAIL
TIMER
DISABLED

IGNORE
DEBUG
STRAPS

IMC
DISABLED

CLKGEN
DISABLED

DEFAULT

DEFAULT

DEFAULT

DEFAULT

AZ_RST#

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

DISABLE PCI
ROM BOOT

FWH

L : 2.2K
pull down

L : 2.2K
pull down

LPC

NC

L : 2.2K
pull down

SPI

L : 2.2K
pull down

NC

NC

NC

RSVD

SI-2 modified -- confirm AMD R563 need to stuff

+3VS5

SI-2 modified -- remove

+3V pull Hi resistor .

R282

10K/F_4

R278

0_4

SB_PWRGD_IN

C564
*2.2U/6.3V_6

AD28
AD27
AD26
AD25
AD24
AD23

SB_PWRGD_IN 13

+1.8V
+1.8V
B

U14

R653
*2.2K_4

CH501H-40PT
2

NC VCC

3
D19

Use 2.2K PD.

5,35 ECPWROK

R637
*2.2K_4

40 VRM_PWRGD

1
R638
*2.2K_4
2

R652
*2.2K_4
2

R636
*2.2K_4
2

D18

R651
*2.2K_4

CH501H-40PT
2

GND

C549

R273

*0.1U/10V_4

R269
10K/F_4
RX780,RS780

*33_4

NB_PWRGD_IN

PCI_AD28

PULL
LOW
A

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

USE
LONG
RESET

USE PCI
PLL

USE ACPI
BCLK

USE IDE
PLL

USE DEFAULT
PCIE STRAPS

RESERVED

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

USE
SHORT
RESET

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

NB_PWRGD_IN 10

*NL17SZ17DFT2G
SOT-353
R266

0_4

NB/SB POWER GOOD CIRCUIT

PULL
HIGH

NB_PWRGD_IN:
RS780/RX780 = 1.8V; RS740 = 3.3V
Do NOT share it with SB_PWRGD when use Internal Clk Gen
(Need SB PLL initialize firstly)

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

GPIO17

DEFAULT

DEBUG STRAPS

12
12
12
12
12
12

GPIO16

ENABLE PCI
ROM BOOT

DEFAULT

PULL
LOW

TYPE

1
R231
10K/F_4
2

R657
*10K/F_4
2

PCI_CLK_TPM
C

R654
*10K/F_4
2

R658
10K/F_4

R659
10K/F_4

12

SB_GPIO17
SB_GPIO16
1

PCI_CLK4

PCI_CLK3

13
13

12
12

intermal have pull

Hi 10K , confirm AMD
ward this pull Hi
not need

12 PCI_CLK_TPM

R300
*10K/F_4

R656
10K/F_4

R655
10K/F_4

R599
2.2K_4

*10K/F_4

R272

+1.8V

WD_PWRGD 13

AL17SZ17000

IC(5P) NL17SZ17DFT2G(SOT-353)

SOT-353

ALUC1G17000

IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5)

SOT23-5

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Rev
1A

SB700-STRAPS

Date: Tuesday, February 19, 2008

1

Sheet

16

of

45

17

IC CTRL(632P) 216-0707001-00(BGA)
VGA P/N : AJ070700T00
PART 1 OF 6

2.5Gb/s bit rate

D

9
9

PEG_TX0
PEG_TX#0

9
9

PEG_TX1
PEG_TX#1

9
9

PEG_TX2
PEG_TX#2

9
9

PEG_TX3
PEG_TX#3

9
9

PEG_TX4
PEG_TX#4

9
9

PEG_TX5
PEG_TX#5

9
9

PEG_TX6
PEG_TX#6

9
9

PEG_TX7
PEG_TX#7

9
9

PEG_TX8
PEG_TX#8

9
9

PEG_TX9
PEG_TX#9

9
9

PEG_TX10
PEG_TX#10

9
9

PEG_TX11
PEG_TX#11

9
9

PEG_TX12
PEG_TX#12

9
9

PEG_TX13
PEG_TX#13

9
9

PEG_TX14
PEG_TX#14

9
9

PEG_TX15
PEG_TX#15

PEG_TX0
PEG_TX#0

AC30
AC31

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

AA28
AA27

C_PEG_RXP0
C_PEG_RXN0

C163
C156

0.1U/10V_4
0.1U/10V_4

PEG_TX1
PEG_TX#1

AC29
AB29

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

AA25
AA24

C_PEG_RXP1
C_PEG_RXN1

C167
C170

0.1U/10V_4
0.1U/10V_4

PEG_TX2
PEG_TX#2

AB31
AB30

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

Y28
Y27

C_PEG_RXP2
C_PEG_RXN2

C180
C196

0.1U/10V_4
0.1U/10V_4

PEG_TX3
PEG_TX#3

AA31
AA30

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

Y25
Y24

C_PEG_RXP3
C_PEG_RXN3

C164
C157

0.1U/10V_4
0.1U/10V_4

PEG_TX4
PEG_TX#4

W30
W31

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

V28
V27

C_PEG_RXP4
C_PEG_RXN4

C218
C204

0.1U/10V_4
0.1U/10V_4

PEG_TX5
PEG_TX#5

W29
V29

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

V25
V24

C_PEG_RXP5
C_PEG_RXN5

C203
C187

0.1U/10V_4
0.1U/10V_4

PEG_TX6
PEG_TX#6

V31
V30

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

T28
T27

C_PEG_RXP6
C_PEG_RXN6

C220
C224

0.1U/10V_4
0.1U/10V_4

PEG_TX7
PEG_TX#7

U31
U30

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

T25
T24

C_PEG_RXP7
C_PEG_RXN7

C243
C252

0.1U/10V_4
0.1U/10V_4

PEG_TX8
PEG_TX#8

P30
P31

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

P28
P27

C_PEG_RXP8
C_PEG_RXN8

C276
C268

0.1U/10V_4
0.1U/10V_4

PEG_TX9
PEG_TX#9

P29
N29

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

P25
P24

C_PEG_RXP9
C_PEG_RXN9

C259
C246

0.1U/10V_4
0.1U/10V_4

PEG_TX10
PEG_TX#10

N31
N30

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

M28
M27

C_PEG_RXP10
C_PEG_RXN10

C289
C277

0.1U/10V_4
0.1U/10V_4

PEG_TX11
PEG_TX#11

M31
M30

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

M25
M24

C_PEG_RXP11
C_PEG_RXN11

C290
C296

0.1U/10V_4
0.1U/10V_4

PEG_TX12
PEG_TX#12

K30
K31

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

L28
L27

C_PEG_RXP12
C_PEG_RXN12

C288
C295

0.1U/10V_4
0.1U/10V_4

PEG_TX13
PEG_TX#13

K29
J29

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

L25
L24

C_PEG_RXP13
C_PEG_RXN13

C330
C324

0.1U/10V_4
0.1U/10V_4

PEG_TX14
PEG_TX#14

J31
J30

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

J28
J27

C_PEG_RXP14
C_PEG_RXN14

C325
C331

0.1U/10V_4
0.1U/10V_4

PEG_TX15
PEG_TX#15

H31
H30

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

G28
G27

C_PEG_RXP15
C_PEG_RXN15

C304
C316

0.1U/10V_4
0.1U/10V_4

Clock
EXT_GFX_CLKP
EXT_GFX_CLKN

2 EXT_GFX_CLKP
2 EXT_GFX_CLKN

100MHz (+/-300ppm) input frequency,

0-0.7V single-ended swing
12

PCIE_RST#

R71

0_4

AD29
AD30

P
C
I
E
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E

NC_SMBCLK
NC_SMBDATA

AG25

PERSTB

PEG_RX1 9
PEG_RX#1 9

PEG_RX2 9
PEG_RX#2 9
PEG_RX3 9
PEG_RX#3 9
PEG_RX4 9
PEG_RX#4 9
PEG_RX5 9
PEG_RX#5 9
PEG_RX6 9
PEG_RX#6 9
PEG_RX7 9
PEG_RX#7 9
C

PEG_RX8 9
PEG_RX#8 9
PEG_RX9 9
PEG_RX#9 9
PEG_RX10 9
PEG_RX#10 9
PEG_RX11 9
PEG_RX#11 9
PEG_RX12 9
PEG_RX#12 9
PEG_RX13 9
PEG_RX#13 9
PEG_RX14 9
PEG_RX#14 9
PEG_RX15 9
PEG_RX#15 9

Calibration

PCIE_REFCLKP
PCIE_REFCLKN
SM BUS

AC28
AC27

POWER
+PCIE_VDDR=1.2V
+VDD_MEM1.8V=1.8V
+VGA_CORE=1.0~1.1V - M62S,M71S
0.95~1.1V - M72S

PEG_RX0 9
PEG_RX#0 9

PCIE_CALRN

AF25

M72_PCIE_CALRN

R74

2K/F_4

PCIE_CALRP

AE25

M72_PCIE_CALRP

R70

1.27K/F_4

NC_1
NC_2

AE23
AH30

+1.1V_PCIE_VDDC

1.27K for M82-S

M72-S/M82-S
U29A

VGA Core

BPP

VGA Core

VDDC

+1.8V

PCIE_VDDR

+1.8V

PCIE_PVDD

+1.8V

VDDR1

3.3V_Delay

PROJECT : QT8
Quanta Computer Inc.

VDDR3
20ms

Size
Custom

20ms

NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

M7X/M8X_PCIE_Interface
Sheet
1

17

of

45

U29B
R100

1K/F_4

R522

GPIO_24_JMODE

10K/F_4

AJ4
AJ5

ROMCS#

GPIO22(ROMCS#)
PD without external VBIOS ROM
R87

10K/F_4

19
R95

10K/F_4

MEM_ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

TEMP_FAIL

Vendor

Type

Qimonda (Infineon) 16*16

Qimonda (Infineon) 32*16-500MHZ
Hynix
16*16
Hynix
32*16-500MHZ
Samsung
16*16
Samsung
32*16-500MHZ

HYB18T256161BF-25
HYB18T512161B2F-20
HY5PS561621AFP-25
H5PS5162FFR-20L
K4N56163QG-ZC25
K4N51163QG-HC20
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

1.1V

1.0V

19
19

1.0V

19

M
L

1
BBEN

L
H

BBP

R526

5 TEMP_FAIL
42 GFX_CORE_CNTRL1
20 BBEN

BLM18PG181SN1D(180,1.5A)_6
+1.8V

R99

0_4

TEMP_FAIL
0_4
PWRCNTL_1
BBEN
ROMCS#
10K/F_4 GPIO_23_CLKREQb
GPIO_24_JMODE
T36
T34
T35
T38

L17
C147
0.1U/10V_4

PCIE_PVDD
PCI-E PLL power.
1.8 V 5%

+1.8V

1.8V(40mA)

R75

499/F_4

R76

249/F_4

GENERICC

T123

TX1_HDMI_LTX1_HDMI_L+

TX2M_DPB3P
TX2P_DPB3N

AL11
AK11

TX2_HDMI_LTX2_HDMI_L+

AL7
AK7

+1.8V_TPVDD

+1.8V_TPVDD

DPB_PVDD
DPB_PVSS

AE11
AF11

DPB_PVDD

DPB_PVDD

DVPCNTL_MVP_0
DVPCNTL_MVP_1

DPA_VDDR_1
DPA_VDDR_2

AJ12
AJ13

DPA_B_VDDR

DPA_B_VDDR

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DPB_VDDR_1
DPB_VDDR_2

AK13
AL13

DPA_B_VDDR

DPA_B_VDDR

DPB_VSSR_5
DPB_VSSR_4
DPB_VSSR_3
DPB_VSSR_2
DPB_VSSR_1

AL12
AK12
AJ11
AH9
AH11

DPA_VSSR_5
DPA_VSSR_4
DPA_VSSR_3
DPA_VSSR_2
DPA_VSSR_1

AJ8
AF7
AG7
AJ7 DPA_VSSR_2
AH7

PSYNC_NEW

+0.6V_M72_VREFG AC11

TXCM_DPB0P
INTEGRATED
TMDS/DP PORT TXCP_DPB0N

TX2M_DPA3P
TX2P_DPA3N
DVALID

Y8
Y7
V8
AH6
AG6

+1.8V 1.8V+R6043(249R)=1.8V/3=0.6V

BLM18PG181SN1D(180,1.5A)_6

DPA_PVDD
DPA_PVSS

DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11 EXT TMDS
DVPDATA_12 DVO
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

DP_CALR

GPIO_0
GPIO_1
GPIO_2
GENERAL
GPIO_3
PURPOSE
GPIO_4
I/O
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTFB
GPIO_20_PWRCNTL1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
GPIO_24_JMODE
GPIO_25_TDI
GPIO_26_TCK
GPIO_27_TMS
GPIO_28_TDO

L_CRT_R

AL27
AK27

L_CRT_G

B
BB

AL26
AK26

L_CRT_B

HSYNC
VSYNC

AK29
AK30

C743

C747

10U/6.3V_8

1U/10V_4

C746
0.1U/10V_4

+VGA_CORE

VDDC(345mA)

AVSSQ

AH28

VDD1DI

AJ27

VSS1DI

AJ26

R2
R2B

AL17
AK17

G2
G2B

AL15
AK15

L79

MPVDD
Memory Phase Lock Loop Power
Same as VDDC

C822
10U/6.3V_8

BLM18PG181SN1D(180,1.5A)_6

+1.8V_VPCIE_PVDD AH31

PCIE_PVDD

C823
C824
1U/10V_4

+1.1V_DPLL_VDDC AE12

0.1U/10V_4
2

L18

DPLL_PVDD
DPLL_PVSS

A9
B9

EVGA-XTALI

EVGA-XTALI

AJ31

EVGA-XTALO

AJ30

R67

AH26

1.1V(100mA)

C106
10U/6.3V_8

C169
1U/10V_4

C161
0.1U/10V_4

1K/F_4

AD12

DPLL_VDDC
Phase Lock Loop Power
Dedicated digital power pin for display PLLs.
1.1 V 5%

B2B

AL14
AK14

AJ17

AJ15

COMP

AJ14

V2SYNC
H2SYNC
A2VDD

AH14
AH16

A2VSSQ

AG16

VDD2DI

AF18

VSS2DI

AE18

R2SET

AG14

MPVDD
MPVSS

SCL
SDA
SERIAL
BUSES DDC1DATA

DDC1CLK

PLL &
XTAL

XTALIN
XTALOUT

TESTEN

DDC3DATA_DP3_AUXN
DDC3CLK_DP3_AUXP

AF4
AH4

DDC4DATA_DP4_AUXN
DDC4CLK_DP4_AUXP

AF9
AG9

THERMAL

PLLTEST

L_CRT_B

TS_FDO

AE14

DPLUS
DMINUS

AE5
AE4

R468
*10M_6

*100K/F_4
150/F_4
0_4

R462
R448

150/F_4
0_4

R461
R447

150/F_4
0_4

R484

C735

CRT_R

10,24

CRT_G

10,24

CRT_B

10,24

Del R481, R482, R483,

R68, R464, R486 for TP
on PV

499/F_4

+1.8V_A2VDD_Q

+1.8V_A2VDD_Q

C111
0.1U/10V_4
+VDDD1

+VDDD1

C127

AVDD
DAC1 Analog Power
Dedicated power for DAC1.
1.8 V 5%

VDD1DI
DAC1 Digital Power.
1.8 V 5%

0.1U/10V_4

+1.8V_A2VDD_Q

1.8V(65mA)
+1.8V_A2VDD_Q

A2VDD
DAC2 Analog Power.
3.3 V 5%

C129

A2VDDQ
DAC2 Band Gap (clean) power supply.
1.8 V 5%

Del R470, R478,

R450, R472, R471,
R469, R451 for TP on
PV
DAC2_VSY
DAC2_HSY

L16

DPB_PVDD

C165

T10

DPB_PVDD
C182

0.1U/10V_4

L24

1000P/50V_4

+3V_DELAY
+1.8V_A2VDD_Q

C136
0.1U/10V_4

+1.8V_A2VDD_Q
+VDDD1

+1.8V

BLM18PG181SN1D(180,1.5A)_6
C98
10U/6.3V_8

C168

0.1U/10V_4 1U/10V_4

VDD2DI
DAC2 Digital Power.
1.8 V 5%

T13

1.8V(20mA)
+1.8V

BLM18PG181SN1D(180,1.5A)_6
C145
10U/6.3V_8

Del L25 for

TP on PV

+VDDD1
C171
R69

715/F_4

0.1U/10V_4

EDIDCLK 10,23
EDIDDATA 10,23
DDCDATA 10,24
DDCCLK
10,24
*4.7K_4
+3V_DELAY

R511
VTHM_DAT
VTHM_CLK
R510

Del R84, R85,

R466, R467
for TP on PV

+VDDD1

1.8V(100mA)
+VDDD1
C110

*4.7K_4

T12
T11
HDMI_SDA 23
HDMI_SCL 23

+3V_DELAY

DDC 3V tolerance
--DDC1,DDC2,SDA/SCL
DDC 5V tolerance
--DDC3,DDC4

L15

+1.8V

BLM18PG181SN1D(180,1.5A)_6
C97
10U/6.3V_8

C135

0.1U/10V_4 1U/10V_4

+1.8V_TPVDD

VGATHRM+
VGATHRM-

C113

1.8V(20mA)

+1.8V_TPVDD
C108

0.1U/10V_4

Thermal Sensor

5,35 MBCLK2

R524

0_4

5,35 MBDATA2

R525

0_4

L20

+1.8V

BLM18PG181SN1D(180,1.5A)_6
C134
10U/6.3V_8

1000P/50V_4

VTHM_CLK

R518

*0_4

MBCLK2

SMCLK

VCC

VTHM_DAT

R519

*0_4

MBDATA2

SMDATA

DXP

10K/F_4

VGA_ALERT

-ALT

DXN

GND

-OVT

1.1V(S100,D200mA)
781-1_3V

R509

For Int Clk 27Mhz

+3V_DELAY

R516

200/F_6

C790
1

EVGA-XTALO
*22P/50V_4

+3V_DELAY

DPA_B_VDDR

L70

0.1U/10V_4
C740

C742

0.1U/10V_4

1000P/50V_4

VGATHRM+
C793
2200P/50V_4

CL=20PF *27MHZ

TMDS_HPD 10,23

R65
R463
R449

DPA_B_VDDR

EVGA-XTALI

Y7
A

19

M72-S/M82-S

*22P/50V_4

VIP_3

HSYNC_COM 10,19,24
VSYNC_COM 10,19,24

U30
C741

VIP_3

AA5
AA4

AC5
AC4

TEST

L_CRT_G

AJ29
AH29

DDC2DATA
DDC2CLK

DPLL_VDDC

*0_4

L_CRT_R

AE16
AF16

A2VDDQ

VREFG

+1.8V_DPLL_PVDD AH12
DPLL_PVSS
AG12

+VGACORE_MPVDD
MPVSS

AJ28

DPA_VDDR / DPB_VDDR
DP/TMDS Transmitter Power (Link A)
DP/TMDS Transmitter Power (Link B)
1.1 V 3%

TMDS_HPD

AL28
AK28

AL29

DPA_PVDD / DPB_PVDD
DP/TMDS PLL Power (Link A)
DP/TMDS PLL Power (Link B)
1.8 V 3%

150 OHM

G
GB

DAC2 (TV/CRT2) B2

GEN_A
GEN_B
GEN_C
GEN_D_HPD4
GEN_E

R476

R
RB

RSET

TX1_HDMI_L- 23
TX1_HDMI_L+ 23

M82-S 0_4

AG11

AVDD

TX0_HDMI_L- 23
TX0_HDMI_L+ 23

TX2_HDMI_L- 23
TX2_HDMI_L+ 23

R488

TMDS_HPD

DAC1 / CRT

TXC_HDMI_L- 23
TXC_HDMI_L+ 23

Remove 180R
SHUNT RESISTOR
for M82-S
from AMD Jackson
confirm

ENABLE HD AUDIO ( M8X-M )

AA8

HPD1

L71

BLM18PG181SN1D(180,1.5A)_6

+1.1V

R91

1.8V(40mA)

C114
10U/6.3V_8

EXT_LVDS_BLON
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
HDMI_HP2
OSC_SPREAD
VGA_ALERT

+3V

DPLL_PVDD
Phase Lock Loop
Power
Dedicated analog
power pin for
display PLLs.
1.8 V 3%

0_4

AL10
AK10

AE7

Y4
V3
V4
V5
U3
U2
T4
T5
T7
T8
R1
R2
R3
P1
P3
N1
N2
P4
P7
P8
P5
V7
N3
Y5
M4
M5
M7
M8
L8

HPD3

T37

+1.8V

R93

42 GFX_CORE_CNTRL0
2 OSC_SPREAD

V-CORE

MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5

GPIO0
GPIO1
T151
T18
T152
GPIO5

10,23 LVDS_BLON
19
GPIO8
19
GPIO9
T153
19
GPIO11
19
GPIO12
19
GPIO13
T154

0.9V

10K/F_4
*10K/F_4
*10K/F_4
*10K/F_4

TX1M_DPB2P
TX1P_DPB2N

AD9

Y1
Y2
Y3
AA2
AA3
AB1
AB2
AB3
AC1
AC3
AD1
AD2
AD3
AF3
AG3
AH3
AG1
AH2
AH1
AJ3
AJ1
AJ2
AK2
AK3

Memory ID
R495
R496
R493
R492

TX0_HDMI_LTX0_HDMI_L+

TX1M_DPA2P
TX1P_DPA2N

W1

+VDDR4

TX0M_DPB1P
TX0P_DPB1N

AL6
AK6

V2
V1
W3

Vendor P/N

TXC_HDMI_LTXC_HDMI_L+

TX0M_DPA1P
TX0P_DPA1N

AK4
AL3

PWRCNTL1 PWRCNTL0 V-CORE

PSYNC

PSYNC

NA- M62S,M71S
PU to 3.3V- M72S

AK9
AL9
AJ9
AJ10

TXCM_DPA0P
TXCP_DPA0N

AL5
AK5

AK8
AL8

NA - M64/M62, M71
BBEN- M66
BBEN(10K PD)- M76

BBEN

18

PART 2 OF 6

NA- M62S,M71S
PD 1K- M72S

+1.1V

BLM18PG181SN1D(180,1.5A)_6
C737
10U/6.3V_8

w/s 10 / 10

VGATHRM-

G781-1P8@EV
-VGATHRM

I2C ADDRESS: 9AH

R513

10K/F_4

+3V_DELAY

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Rev
1A

M7X/M8X_Main

Date: Tuesday, February 19, 2008

1

Sheet

18

of

45

1.8V -(300mA)
+1.8V

U29E

L14

BLM18PG181SN1D(180,1.5A)_6
C109

Part 5 of 6

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32

A13
A2
C18
A24
A30
AA1
AA11
AA14
AA17
AA20
AA6
AC2
AC7
AE3
AL4
AD14
AF12
AF14
AD16
AD18
AE6
AG2
AE9
AH25
AK1
AK31
AJ6
AL2
AL30
B1
C13

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32

PCI-Express GND

AA26
AA29
AC26
AD31
AE29
AE30
AE31
F28
G26
G29
G30
G31
H29
J25
J26
L26
L29
L30
L31
M26
M29
P26
R29
R30
R31
T26
U29
V26
Y26
Y29
Y30
Y31

+LVDDR_1-2

1U/10V_4
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102

B25
J8
B5
D11
C17
C22
C27
D29
C3
C6
D3
D28
F29
D4
F11
F12
F14
F16
F18
F20
F21
F23
F25
F7
F9
G3
G6
H23
J3
J4
J6
K1
L12
L15
L18
L21
L6
M11
M14
M17
M20
M6
P12
P15
P18
P21
P6
AC21
R14
R17
R20
T6
U1
U12
U15
U18
U21
AE20
V14
V17
V20
P2
V6
W2
Y12
Y15
Y18
Y21
Y6
M9

1.8V(100mA)

+1.8V

L19

U29F
C123

C103
1U/10V_4

BLM18PG181SN1D(180,1.5A)_6

AF20
AG20

+1.8V_LVDDC

C133
1U/10V_4

C125
1U/10V_4

LVDDR_1
LVDDR_2

VARY_BL
Control
DIGON

LVDDC
LVDS Output Driver Digital Power Supply
1.8 V 3%

LVDDC_1
LVDDC_2

AF23
AF21
AL18
AJ22
AJ25
AK18
AK23
AK25
AJ21
AL23
AL25

LVSSR_1
LVSSR_2
LVSSR_3
LVSSR_4
LVSSR_5
LVSSR_6
LVSSR_7
LVSSR_8
LVSSR_9
LVSSR_10
LVSSR_11

AG18
AH18

LPVDD
LPVSS

+1.8V_TPVDD

1.8V(40mA)
C155
C143
100P/50V_4

C132
1U/10V_4

19

10K/F_4

AA7

0_4

R89

AC6

0_4

R80

DPST_PWM 10,23
DISP_ON

10,23

LVDS channel

AJ18
AH20
C144
1U/10V_4

LVDDR
LVDS Output Driver Analog Power Supply
1.8 V 3%

LPVDD
Analog Power for
transmitter PLL. It should
be a power for the PLL
block of the macro.
1.8 V 3%

R83

PART 6 OF 6

0.1U/10V_4

TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

AD21
AE21
AJ24
AJ23
AK24
AL24
AG21
AH21
AG23
AH23

EXT_TXUCLKOUT+ 23
EXT_TXUCLKOUT- 23
EXT_TXUOUT0+ 23
EXT_TXUOUT0- 23
EXT_TXUOUT1+ 23
EXT_TXUOUT1- 23
EXT_TXUOUT2+ 23
EXT_TXUOUT2- 23

TXCLK_LP
TXCLK_LN
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

AL19
AK19
AJ20
AJ19
AK20
AL20
AK21
AL21
AK22
AL22

EXT_TXLCLKOUT+ 23
EXT_TXLCLKOUT- 23
EXT_TXLOUT0+ 23
EXT_TXLOUT0- 23
EXT_TXLOUT1+ 23
EXT_TXLOUT1- 23
EXT_TXLOUT2+ 23
EXT_TXLOUT2- 23

0.1U/10V_4
M72-S/M82-S
+3V_DELAY

CONFIGURATION STRAPS
PIN
GPIO0
GPIO1

DESCRIPTION OF DEFAULT SETTINGS

M82-S

PCIE FULL TX OUTPUT SWING

GPIO5

Allows eitherPCIe 2.5GT/s or 5GT/s operation

VIP3

ENABLE HD AUDIO ( M8X-M )

GPIO8

ENABLE HD AUDIO ( M82-S )

HSYNC

ENABLED HDMI

GPIO0

GPIO0

R92

*10K/F_4

18

GPIO1

GPIO1

R514

*10K/F_4

18

GPIO5

GPIO5

R517

*10K/F_4

VIP_3

R475

*10K/F_4

GPIO8

18

VIP_3

R94

10K/F_4

10,18,24 HSYNC_COM

R465

10K/F_4

10,18,24 VSYNC_COM

R485

*10K/F_4

R79

*10K/F_4

18

PCIE TRANSMITTER DE-EMPHASIS ENABLED

18

GPIO8

18

REV

PSYNC

Memory Aperture size

GPIO9

CORE GND

GPIO13 GPIO12 GPIO11

BIOSROM

0
0
0
0
0
0
0
0

M72-S/M82-S

SI-1 Modified -- follow AMD

reference schematic change for
reduce leakage to VDDR3 BUS

ROMIDCFG2 ROMIDCFG1 ROMIDCFG0

128M
256M
64M
32M
512M
1G
2G
4G

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

+3V_DELAY

18

GPIO9

GPIO9

R90

*10K/F_4

18

GPIO13

GPIO13

R523

*10K/F_4

18

GPIO12

GPIO12

R521

*10K/F_4

18

GPIO11

GPIO11

R520

10K/F_4

It is a shared pin strap with CONFIG[2:0] if BIOS_ROM_EN is set to 0.

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

M7X/M8X_GND / LVDS/ Straps

Sheet
1

19

of

45

20
PCIE_VDDR--PCI-E I/O power. 1.8 V 5%

U29D

+1.8V_PCIE_VDDR

VDDR1-- I/O power for the memory interface on M82 1.8 V 5%

PART 4 OF 6

+1.8V
C820

C438

10U/6.3V_8

10U/6.3V_8

C312

10U/6.3V_8

10U/6.3V_8

C300
1U/10V_4

C311

C326

C298

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

C305
1U/10V_4

C327
0.1U/10V_4

+1.8V_VDD_CT

1.8V(110mA)

+1.8V_VDD_CT

BLM18PG181SN1D(180,1.5A)_6
C314

C257
C291

Q34

Gated 3.3V
50mA by
VDDC

P-MOS,2.6A

AO3409
1

+3V

VDD_R3 --IO power for

3.3 V pins (e.g.
GPIOs). 3.3 V 5%

R443
100K/F_4

D8
1

+VDDR4
L94
BLM18PG181SN1D(180,1.5A)_6
SI-1 Modified -- follow AMD
reference schematic change

CH501H-40PT
2

1.8/3.3V 150mA

68.1K_4

0.1U/10V_4

C937
C935
*10U/6.3V_8

C936
1U/10V_4

0.1U/10V_4

AC18
AC16
AC14
AC12

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4

AF1
AF2

VDDR4_1
VDDR4_2

AE1
AE2

VDDR5_1
VDDR5_2

+VDDR5

BLM18PG181SN1D(180,1.5A)_6
3

R42

C191

C184
1U/10V_4 1U/10V_4

L95

+1.8V
MAINON

VDD_CT_1
VDD_CT_2
VDD_CT_3
VDD_CT_4
VDD_CT_5
VDD_CT_6
VDD_CT_7
VDD_CT_8

C780
C938
C781
*10U/6.3V_8 1U/10V_4 1U/10V_4

C779
0.1U/10V_4

Q8
2N7002E

M2
M3
L4
AD11

RSVD_1
RSVD_2
RSVD_3
RSVD_4

P
O
W
E
R

AF30
AF31
AF29
AF27
AF28
AG29
AG30
AG31

+1.8V_PCIE_VDDR

PCIE_VDDC_1
PCIE_VDDC_2
PCIE_VDDC_3
PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8
PCIE_VDDC_9
PCIE_VDDC_10
PCIE_VDDC_11
PCIE_VDDC_12

AA23
AC24
AC25
AE26
AE27
AE28
L23
M23
P23
T23
V23
Y23

+1.1V_PCIE_VDDC

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33

L11
L14
L17
L20
M12
M15
M18
M21
AC20
P14
P17
P20
R12
R15
R18
R21
AD20
U14
U17
U20
V12
V15
V18
V21
Y11
Y14
Y17
Y20
AA12
AA15
AA18
AA21
P9

VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4

J12
J14
J16
J18

D9
1

HWPG

+1.8V

L30

BLM18PG181SN1D(180,1.5A)_6 +1.8V_VDDRH_1
C347
C346
10U/6.3V_8
0.1U/10V_4

*CH501H-40PT L-F

R45

*75K/F_4

C58

+1.8V

L80

+1.8V_VDDRH_2

BLM18PG181SN1D(180,1.5A)_6
C826
10U/6.3V_8

VDDRH_1
VDDRH_2

B10
B19

VSSRH_1
VSSRH_2

V11
U11

BBN_1
BBN_2

R11
P11

BBP_1
BBP_2

BBN -0.75V 100mA

C825

+VBBP

1.5/1.8V 120mA
C212
C260
1U/10V_4

VDD_R4 -- Power for DVPDATA_[23:12] - external

TMDS or GPIO; corresponds to
DVOA_MSB_VMODE register bit; '1' - 3.3 V(default);
'0' - 1.8 V; 1.8 V 5% or 3.3 V 5%

C759
*0.1U/10V_4

C760
1U/10V_4

+1.8V

BLM18PG181SN1D(180,1.5A)_6
C761
10U/6.3V_8
+1.1V_PCIE_VDDC

C244
0.1U/10V_4

+1.1V

1.1V(1.0A)
L21
BLM18PG181SN1D(180,1.5A)_6

C219

C138
C186
1U/10V_4

0.1U/10V_4

C207
1U/10V_4

10U/6.3V_8

PCIE_VDDC--PCI-E
Digital Power
Supply (Either 1.0
V or 1.1 V) 1.0 V
-5% to 1.1 V +5%

VDDC+VDDCI
+VGA_CORE
0.95~1.1V(15A peak )( Ripple < 87.2mV)
C222

C232

1U/10V_4

1U/10V_4

C210

C262

C261

1U/10V_4

1U/10V_4

1U/10V_4

C233

C198

C228

1U/10V_4

1U/10V_4

1U/10V_4

C181

C265

C211

1U/10V_4

1U/10V_4

1U/10V_4

VDDC--Dedicated core
power, provides power
to the internal
logic. 0.9 V - 1.2 V
10U/6.3V_8 ( 5%)
C73

C227
1U/10V_4

C215
1U/10V_4

10U/6.3V_8

C200
1U/10V_4

10U/6.3V_8

C229
1U/10V_4

10U/6.3V_8

C91

C90

+VDDCI

L27
BLM18PG181SN1D(180,1.5A)_6

C294

C282

0.1U/10V_4

0.1U/10V_4

+VGA_CORE

C293
C283
1U/10V_4

10U/6.3V_8

VDDCI--Isolated (clean)
core power for the l/O
logic. Voltage level
should match that of
VDDC. POWER Same as VDDC

+VBBP

VDD_R5 -- Power for DVP control pins

(DVPCNTL_[0-2] and DVPCLK) and
DVPDATA_[11:0] - external TMDS or GPIO;
corresponds to DVOA_LSB_VMODE register bit;
'1' - 3.3 V(default); '0' - 1.8 V;
1.8 V
5% or 3.3 V 5%

SI-1 modified -- ADD

power play function

L93

Q61
2N7002E
+VGA_CORE

Q62
ME2303T1
1
+1.8V

BBP -- Connect to VBBP back bias regulator / generator.

If back bias is not used, connect directly to VDDC.
Back Bias Enabled:
(GPIO_21_BB_EN = 3.3 V):
1.5 V or 1.8 V
Back Bias Disabled:
(GPIO_21_BB_EN = 0 V):
VDDC

R752
1

100K/F_4
2
+5V

VDDRH_1 & VDDRH_2 --Dedicated power

pins for memory clock pads for each
channel. Should have the same
voltage level as VDDR1.

Q63
2N7002E

BBEN

PROJECT : QT8
Quanta Computer Inc.

18

Size
Custom
NB5/RD5

Document Number

Rev
1A

M7X/M8X_Power_and_NC

Date: Tuesday, February 19, 2008

5

C86
C266
1U/10V_4

0.1U/10V_4

*BLM18PG181SN1D(180,1.5A)_6
+VGA_CORE

L74

Back Bias

0.1U/10V_4

0.1U/10V_4

A10
A19

Memory
I/O
Clock

23,35,38,39,41,42

1.8V(400mA)
PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8

M72-S/M82-S
C174

+1.8V

27,35,39,42,43,44

0.1U/10V_4
+3V_DELAY

1000P/50V_4

10U/6.3V_8
+3V_DELAY

AA9
Y9
V9
T9
J11
J20
J21
L9

I/O Internal

L28

+1.8V

C263
1U/10V_4

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18

Memory I/O

VDD_CT -- Level
translation between
core and I/O,
excluding memory
receivers.1.8 V 5%

C339

A15
A22
A28
A4
A8
B8
C9
D1
H1
H11
H12
H14
H16
H18
H20
H21
B31
M1

PCI-Express

1.8V(1.1A)

Core

Sheet

20

of

45

21

U29C
Part 3 of 6

22
22

RASA0#
RASA1#

RASA0#
RASA1#

22
22

CASA0#
CASA1#

CASA0#
CASA1#

22
22

WEA0#
WEA1#

WEA0#
WEA1#

22

CSA0#_0

CSA0#_0

22

CSA1#_0

CSA1#_0

22
22

CKEA0
CKEA1

CKEA0
CKEA1

22
22

CLKA0
CLKA0#

CLKA0
CLKA0#

22
22

CLKA1
CLKA1#

CLKA1
CLKA1#

22

QSA#[7..0]

22

QSA[7..0]

22

DQMA#[7..0]

22

MDA[63..0]

22

MAA[12..0]

22
22

A_BA0
A_BA1

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

QSA#[7..0]
QSA[7..0]
DQMA#[7..0]
MDA[63..0]
MAA[12..0]

A_BA0
A_BA1

+1.8V

R116
100/F_4
MVREFD
+1.8V

C338
0.1U/10V_4

R113
100/F_4

R532
100/F_4

R98
R102
R97

E29
E30
E31
D31
C29
B29
B30
A29
E26
D26
E25
D25
G23
G21
E21
D21
C28
B28
B27
A27
C25
A25
C24
B24
C23
B23
A23
B22
C20
B20
A20
C19
C8
C7
B7
A7
A5
C4
B4
A3
G9
E9
D9
G7
G5
F5
G4
F4
B3
B2
C2
C1
E3
F3
F2
F1
G2
G1
H3
H2
K2
L3
L2
L1

DQ_0
DQ_1
DQ_2
DQ_3
DQ_4
DQ_5
DQ_6
DQ_7
DQ_8
DQ_9
DQ_10
DQ_11
DQ_12
DQ_13
DQ_14
DQ_15
DQ_16
DQ_17
DQ_18
DQ_19
DQ_20
DQ_21
DQ_22
DQ_23
DQ_24
DQ_25
DQ_26
DQ_27
DQ_28
DQ_29
DQ_30
DQ_31
DQ_32
DQ_33
DQ_34
DQ_35
DQ_36
DQ_37
DQ_38
DQ_39
DQ_40
DQ_41
DQ_42
DQ_43
DQ_44
DQ_45
DQ_46
DQ_47
DQ_48
DQ_49
DQ_50
DQ_51
DQ_52
DQ_53
DQ_54
DQ_55
DQ_56
DQ_57
DQ_58
DQ_59
DQ_60
DQ_61
DQ_62
DQ_63

F30
F31

MVREFD
MVREFS

4.7K_4
4.7K_4
240/F_4

L5
L7
J7

TEST_MCLK
TEST_YCLK
MEMTEST

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
A_BA0
A_BA1
MAA12
A_BA2

MA_0
MA_1
MA_2
MA_3
MA_4
MA_5
MA_6
MA_7
MA_8
MA_9
MA_10
MA_11
MA_BA0
MA_BA1
MA_A12
MA_BA2

B14
A14
B13
E14
B17
A17
C15
G16
E16
C14
A12
B12
C12
D14
B15
G14

DQMb_0
DQMb_1
DQMb_2
DQMb_3
DQMb_4
DQMb_5
DQMb_6
DQMb_7

D30
G25
C26
C21
C5
D6
D2
K3

QS_0
QS_1
QS_2
QS_3
QS_4
QS_5
QS_6
QS_7

C30
D23
B26
B21
B6
E7
E2
J2

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

QS_0B
QS_1B
QS_2B
QS_3B
QS_4B
QS_5B
QS_6B
QS_7B

C31
E23
A26
A21
A6
D7
E1
J1

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

ODT0
ODT1

E20
C11

ODTA0
ODTA1

CLK0
CLK1

A18
A11

CLKA0
CLKA1

CLK0b
CLK1b

B18
B11

CLKA0#
CLKA1#

RAS0b
RAS1b

G20
D12

RASA0#
RASA1#

CAS0b
CAS1b

D20
E12

CASA0#
CASA1#

CS0b_0
CS0b_1

E18
G18

CSA0#_0

CS1b_0
CS1b_1

G11
E11

CSA1#_0

CKE0
CKE1

D18
G12

CKEA0
CKEA1

WE0b
WE1b

D16
C10

WEA0#
WEA1#

MEMORY
INTERFACE

read strobe

ODTA0
ODTA1

write strobe

ODTA0
ODTA1

22
22

DRAM_RST

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

MVREFS

C817
0.1U/10V_4

Change MEMTEST to 240 1%

ohm to GND , AMD update

A_BA2

22

SI-1 modified -for support

1Gbit VRAM ( 64M
X 16 )

J5

+1.8V
R101

4.7K_4

M72-S/M82-S
A

R529
100/F_4

PROJECT : QT8
Quanta Computer Inc.
Size
B
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

M7X/M8X/MEM_Interface
Sheet
1

21

of

45

DDR2 BGA
MEMORY

U5

A_BA0
A_BA1

L2
L3

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA0#
CLKA0

K8
J8

CK
CK

CKEA0

K2

CKE

CSA0#_0

L8

CS

WEA0#

K3

WE

RASA0#

K7

RAS

CASA0#

L7

CAS

DQMA#2
DQMA#1

F3
B3

LDM
UDM

ODTA0

K9

ODT

QSA2
QSA#2

F7
E8

LDQS
LDQS

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

MDA9
MDA13
MDA10
MDA15
MDA14
MDA8
MDA12
MDA11
MDA17
MDA22
MDA16
MDA21
MDA23
MDA18
MDA20
MDA19

QSA1
QSA#1

R115
4.99K/F_4
M_VREF1

(SSTL-1.8) VREF = .5*VDDQ

C341

R114
4.99K/F_4

21
0.1U/10V_4

A_BA2

SI-1 modified -for support

1Gbit VRAM ( 64M
X 16 )

+1.8V

C418

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
BA2
NC#R3
A15
A13

L2
L3

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA0#
CLKA0

K8
J8

CK
CK

CKEA0

K2

CKE

CSA0#_0

L8

CS

WEA0#

K3

WE

RASA0#

K7

RAS

CASA0#

L7

CAS

DQMA#3
DQMA#0

F3
B3

LDM
UDM

C423

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

ODTA0

K9

QSA3
QSA#3

F7
E8

LDQS
LDQS

QSA0
QSA#0

B7
A8

UDQS
UDQS

M_VREF2

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
BA2
NC#R3
A15
A13

MDA6
MDA0
MDA7
MDA1
MDA2
MDA5
MDA3
MDA4
MDA28
MDA25
MDA30
MDA27
MDA26
MDA29
MDA24
MDA31

QSA[7..0]

21

QSA[7..0]

21

QSA#[7..0]

21 DQMA#[7..0]
21

MDA[63..0]

21

MAA[12..0]

21
21

A_BA0
A_BA1

QSA#[7..0]
DQMA#[7..0]
MDA[63..0]
MAA[12..0]

A_BA0
A_BA1

+1.8V

21

CLKA0

21

CLKA0#

+1.8V

R159
4.99K/F_4
(SSTL-1.8) VREF = .5*VDDQ

C425
R161
4.99K/F_4

21

0.1U/10V_4

A_BA2

SI-1 modified -for support

1Gbit VRAM ( 64M
X 16 )

R155
56.2/F_4
C345

C436

0.1U/10V_4

C821

0.1U/10V_4

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

C440
470P/50V_4

ODTA0

21

RASA0#

RASA0#

21

CASA0#

CASA0#

21

WEA0#

WEA0#

21

CSA0#_0

CSA0#_0

21

CKEA0

CKEA0

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

CKEA1

K2

CKE

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

C422

0.1U/10V_4

C433

C427

C426

C413

C407

C434

0.01U/16V_4
1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.01U/16V_4

U4

BA0
BA1

ODTA0

21

HYB18T512161B2F-20

U34
L2
L3

R156
56.2/F_4

J1
J7

ODT

+1.8V

*10U/6.3V_8

A_BA0
A_BA1

CLKA0
CLKA0#

0.1U/10V_4

C437

0.1U/10V_4

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDL
VSSDL

C432

C439
1U/10V_4

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

BA0
BA1

+1.8V

HYB18T512161B2F-20

C431

10U/6.3V_8

22

U35
A_BA0
A_BA1

0.1U/10V_4
+1.8V

MDA60
MDA59
MDA61
MDA58
MDA56
MDA62
MDA57
MDA63
MDA52
MDA50
MDA53
MDA49
MDA48
MDA54
MDA51
MDA55

A_BA0
A_BA1

L2
L3

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

K2

CKE

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

BA0
BA1

MDA43
MDA47
MDA41
MDA46
MDA44
MDA42
MDA45
MDA40
MDA35
MDA37
MDA33
MDA38
MDA36
MDA32
MDA39
MDA34

21

CLKA1

21

CLKA1#

ODTA1

21

ODTA1

21

RASA1#

RASA1#

21

CASA1#

CASA1#

21

WEA1#

WEA1#

21

CSA1#_0

CSA1#_0

21

CKEA1

CKEA1

CLKA1
CLKA1#
R576
56.2/F_4

R575
56.2/F_4

CSA1#_0

L8

CS

WEA1#

K3

WE

RASA1#

K7

CASA1#

L7

CAS

DQMA#6
DQMA#7

F3
B3

LDM
UDM

RAS

VDDL
VSSDL

ODTA1

K9

QSA6
QSA#6

F7
E8

LDQS
LDQS

QSA7
QSA#7

B7
A8

UDQS
UDQS

CKEA1
+1.8V

J1
J7

L8

CS

WEA1#

K3

WE

RASA1#

K7

RAS

CASA1#

L7

CAS

DQMA#4
DQMA#5

F3
B3

LDM
UDM

K9

ODT

ODTA1

C365

ODT

CSA1#_0

VDDL
VSSDL

C857
470P/50V_4
+1.8V

J1
J7
C435

0.1U/10V_4
+1.8V

R530
4.99K/F_4
M_VREF3
(SSTL-1.8) VREF = .5*VDDQ

C816
R531
A

4.99K/F_4

21
0.1U/10V_4

A_BA2

SI-1 modified -for support

1Gbit VRAM ( 64M
X 16 )

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
BA2
NC#R3
A15
A13

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

0.1U/10V_4
+1.8V

R162

QSA4
QSA#4

F7
E8

LDQS
LDQS

QSA5
QSA#5

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
BA2
NC#R3
A15
A13

4.99K/F_4
M_VREF4
(SSTL-1.8) VREF = .5*VDDQ

C424
R158
4.99K/F_4

0.1U/10V_4

21

A_BA2

SI-1 modified -for support

1Gbit VRAM ( 64M
X 16 )

HYB18T512161B2F-20

+1.8V

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

HYB18T512161B2F-20

DDR2 BGA MEMORY

+1.8V

C357
10U/6.3V_8

C393
1U/10V_4

C428
0.1U/10V_4

C335
0.1U/10V_4

C322
0.1U/10V_4

C429
0.1U/10V_4

C371
0.01U/16V_4

C444

C348

10U/6.3V_8

1U/10V_4

C421
0.1U/10V_4

C342
0.1U/10V_4

C430
0.1U/10V_4

C404

PROJECT : QT8
Quanta Computer Inc.

C395

0.1U/10V_4

0.01U/16V_4

Size
C
NB5/RD5

Document Number

Rev
1A

M7X/M8X/VRAM_A0,A1

Date: Tuesday, February 19, 2008

1

Sheet

22

of

45

+12VALW

R19

OPTION SIGNAL FROM NB to LVDS for UMA

RP7

Q3
PDTC144EU

R17
2.2K_4

2
4
2
4
2
4
4
2

0_4P2R_4

19 EXT_TXUCLKOUT19 EXT_TXUCLKOUT+
19 EXT_TXUOUT0+
19 EXT_TXUOUT019 EXT_TXUOUT119 EXT_TXUOUT1+
19 EXT_TXUOUT219 EXT_TXUOUT2+

EXT_TXUCLKOUTEXT_TXUCLKOUT+
EXT_TXUOUT0+
EXT_TXUOUT0EXT_TXUOUT1EXT_TXUOUT1+
EXT_TXUOUT2EXT_TXUOUT2+

RP58 3
1
RP62 3
1
RP64 1
3
RP63 1
3

4
2
4
2
2
4
2
4

0_4P2R_4

0_4P2R_4
0_4P2R_4
0_4P2R_4

0_4P2R_4
0_4P2R_4
0_4P2R_4

1
1

C6

1000P/50V_4

Q2
2N7002E

D5
2

+3VPCU

10,18 LVDS_BLON

EDIDDATA
+LOGO_PWR
BLONCON

C678

1000P/50V_4

R23

1K/F_4

R24

LCD_BK

LCD_BK

Q5

+3VS5

R259
*10K/F_4

C28

22P/50V_4

TXLOUT1+
TXLOUT1-

R22

100K/F_4

TXLOUT2+
TXLOUT2-

33K_6

D6 CH501H-40PT
2
1

PN_BLON

TXLOUT0+
TXLOUT0-

CH501H-40PT
BLONCON
1

12

LID_EC#

D7

LID_EC#

HWPG

34,35

10,19 DPST_PWM

CH501H-40PT

35

Del R21 and Pull hi R259 to

+3VS5, add D7 to HWPG on PV

PDTC144EU

9 C_PEG_TX#13
9 C_PEG_TX13

C_PEG_TX#13 C355
C_PEG_TX13 C344

*0.1U/10V_4 TX0_HDMI-L
*0.1U/10V_4 TX0_HDMI+L

9 C_PEG_TX#12
9 C_PEG_TX12

C_PEG_TX#12 C827
C_PEG_TX12 C828

*0.1U/10V_4 TXC_HDMI-L
*0.1U/10V_4 TXC_HDMI+L

From M82-S

TX2_HDMI_LTX2_HDMI_L+

C794
C789

0.1U/10V_4
0.1U/10V_4

TX2_HDMITX2_HDMI+

18 TX1_HDMI_L18 TX1_HDMI_L+

TX1_HDMI_LTX1_HDMI_L+

C782
C786

0.1U/10V_4
0.1U/10V_4

TX1_HDMITX1_HDMI+

18 TX0_HDMI_L18 TX0_HDMI_L+

TX0_HDMI_LTX0_HDMI_L+

C799
C797

0.1U/10V_4
0.1U/10V_4

TX0_HDMITX0_HDMI+

18 TXC_HDMI_L18 TXC_HDMI_L+

TXC_HDMI_L- C768
TXC_HDMI_L+ C776

0.1U/10V_4
0.1U/10V_4

TXC_HDMITXC_HDMI+

+5V

Q36
2N7002E
2

R528
1

L2

+VIN

C15
0.1U/50V_6

C11
0.01U/50V_4

499/F_4

TX2_HDMI-

R506

499/F_4

TX1_HDMI+

R505

499/F_4

TX1_HDMI-

R512

499/F_4

TX0_HDMI+

R515

499/F_4

TX0_HDMI-

R504

499/F_4

TXC_HDMI+

R500

499/F_4

TXC_HDMI-

100K/F_4

VADJ1
C5

C9
0.1U/50V_6

C14
*10U/25V_12

TMDS_HPD

check 3v or 5v
R64
100K/F_4

4 *0_4P2R_4 TX0_HDMI+
TX0_HDMI2

+5V_HDMVCC

4 *0_4P2R_4 TXC_HDMITXC_HDMI+
2

+5V_HDMVCC

D31

D32
CH501H-40PT

R494
4.7K_4

for Layout
concern
,placement close
HDMI conn

R503
4.7K_4

HDMI_SCLK

TX1_HDMITX0_HDMI+

DIS M82-S
499 ohm CS14992FB24

Change R494,
R503 to 4.7K for
AMD on PV

HDMI PORT

Del C748, C756 for

HDMI on PV

TX0_HDMITXC_HDMI+
TXC_HDMI-

HDMI_SCLK
HDMI_SDATA

Close to HDMI Connector

+5V

L73 1
L75 1

18
18

HDMISCL
HDMISDA

2 0_6
2 0_6

+5V_HDMVCC
FUSE1A6V_POLY
2
1
F1
C128 *0.1U/10V_4

CN29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

SHELL1
D2+SHELL3
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0CK+
CK Shield
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL4
SHELL2

RP65 0_4P2R_4
1
2
3
4

HDMI_SDA
HDMI_SCL

20
22

+3V

R680
*2K/04

3HDMI_SCLK

1
+3V
+5V

HDMI_DDC_DATA

R753
R755

Q59
*FDV301N

UMA

*0_4 HDMI_SCLK
*0_4 HDMI_SDATA

R681
*2K/04
1

10 HDMI_DDC_DATA

Q60
*FDV301N
3

HDMI_SDATA

PROJECT : QT8
Quanta Computer Inc.

23
21

HDMI CONN
NB5/RD5

Document Number

Rev
1A

LCD CONN,HDMI CONN

Date: Tuesday, February 19, 2008

3

HDMI_SDATA
HDMI_SCLK

Change 2N7002
to FDV301N for
AMD on PV

+5V

10 HDMI_DDC_CLK

HDMI_DDC_CLK

DIS

Discrete DDC4 is 5V
tolerance , the MOSFET
level shifter no need
UMA DDC is 3V
tolerance,the MOSFET
level shifter is need

HDMI_SDATA

TX2_HDMI+

UMA RS780M
750 ohm CS17502FB19

UMA AND DISCRETE HDMI I2C SELECT

Close to HDMI Connector

Size
Custom

0.1U/10V_4

20K/F_4 HDMI_DET

R66

C8
0.1U/50V_6

HDMI_DET
1

C7

*4.7U/6.3V_6

4 *0_4P2R_4 TX1_HDMITX1_HDMI+
2

TX2_HDMI+

R508

0_4

FBM2125 HM330-T(4A,0.015)_8

TX2_HDMITX1_HDMI+
499/F_4

PWM_VADJ R96

UDZS2.7BTE-17

4 *0_4P2R_4 TX2_HDMI+
TX2_HDMI2

CH501H-40PT

R507

RP31
TX2_HDMI+L 3
TX2_HDMI-L
1
RP23
TX1_HDMI-L 3
TX1_HDMI+L 1
RP37
TX0_HDMI+L 3
TX0_HDMI-L
1
RP17
TXC_HDMI-L 3
TXC_HDMI+L 1

18 TX2_HDMI_L18 TX2_HDMI_L+

TXUOUT2+
TXUOUT2-

*0.1U/10V_4 TX1_HDMI-L
*0.1U/10V_4 TX1_HDMI+L

TXUOUT1+
TXUOUT1-

CN1

PV del logo light

C_PEG_TX#14 C388
C_PEG_TX14 C389

TXUOUT0+
TXUOUT0-

PWM_VADJ

D10

9 C_PEG_TX#14
9 C_PEG_TX14

TXUCLKOUT+
TXUCLKOUT-

LCD CONN
*0_4

+VIN_BLIGHT

*0.1U/10V_4 TX2_HDMI-L
*0.1U/10V_4 TX2_HDMI+L

Camera Pin

DPST_PWM R88

10,18 TMDS_HPD

9 C_PEG_TX#15
9 C_PEG_TX15

C_PEG_TX#15 C386
C_PEG_TX15 C387

EDIDCLK 10,18

VADJ1

HDMI HPD SENSE

for Layout
concern
,placement close
HDMI conn

for Layout
concern
,placement close
north bridge

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
42

20,35,38,39,41,42

UMA/DISCRETE select for HDMI

From RS780M

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

LCDDISCHG
+3V
10,18 EDIDDATA

+VIN_BLIGHT
+3VLCD_CON
41

+3VLCD_CON

TXLCLKOUT+
TXLCLKOUT-

PN_BLON

LVDS_BLON

23

+3VLCD_CON
C12
10U/6.3V_8
C10
0.1U/10V_4
C13
0.01U/16V_4

PBY201209T-4A_8

+VIN_BLIGHT

LCDON#

TXLCLKOUTTXLCLKOUT+
TXLOUT0TXLOUT0+
TXLOUT1TXLOUT1+
TXLOUT2+
TXLOUT2TXUCLKOUTTXUCLKOUT+
TXUOUT0+
TXUOUT0TXUOUT1TXUOUT1+
TXUOUT2TXUOUT2+

L1

+3VLCD

RP59 1
3
RP57 1
3
RP60 1
3
RP61 3
1

2.2K_4 EDIDDATA

+LOGO_PWR

SI-2 modified-delete R402 and

R401 from 0ohm to 75ohm

10,19 DISP_ON

2.2K_4 EDIDCLK

R7

22_8

C22
0.1U/10V_4

EXT_TXLCLKOUTEXT_TXLCLKOUT+
EXT_TXLOUT0EXT_TXLOUT0+
EXT_TXLOUT1EXT_TXLOUT1+
EXT_TXLOUT2+
EXT_TXLOUT2-

Q4
2N7002E

75R/F_6

R8

+3VLCD

R10

OPTION SIGNAL FROM M8X to LVDS for discrete

19 EXT_TXLCLKOUT19 EXT_TXLCLKOUT+
19 EXT_TXLOUT019 EXT_TXLOUT0+
19 EXT_TXLOUT119 EXT_TXLOUT1+
19 EXT_TXLOUT2+
19 EXT_TXLOUT2-

N-MOS,5.8A
Q1
AO3404

RP8

R14

R401

+5V

100K/F_4

RP6

3
1
1
3
1
3
3
1

4 *0_4P2R_4 TXUCLKOUT+
TXUCLKOUT2
2 *0_4P2R_4 TXUOUT0+
TXUOUT04
2 *0_4P2R_4 TXUOUT1+
TXUOUT14
4 *0_4P2R_4 TXUOUT2TXUOUT2+
2

LCDONG
3

RP5

+5VSUS

RP2

RP4

330K_6

2
4
2
4
2
4
2
4

LB_CLK
LB_CLK#
LB_DATAP0
LB_DATAN0
LB_DATAP1
LB_DATAN1
LB_DATAN2
LB_DATAP2

LB_CLK
LB_CLK#
LB_DATAP0
LB_DATAN0
LB_DATAP1
LB_DATAN1
LB_DATAN2
LB_DATAP2

RP1

*0_4P2R_4 TXLCLKOUT+
TXLCLKOUT*0_4P2R_4 TXLOUT0+
TXLOUT0*0_4P2R_4 TXLOUT1+
TXLOUT1*0_4P2R_4 TXLOUT2+
TXLOUT2-

1
3
1
3
1
3
1
3

RP3

10
10
10
10
10
10
10
10

LA_CLK
LA_CLK#
LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2

LA_CLK
LA_CLK#
LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2

+3V

C16
0.1U/10V_4

AO3404 ID
current
5.8A

10
10
10
10
10
10
10
10

+3V

1. If LCD connector near GPU, then place these series Resistors near GPU
2. If LCD connector near N/B, then place these series Resistors near N/B

Sheet

23
8

of

45

CRT PORT

C670
0.1U/10V_4

+5VCRT
F2

40 mils

FUSE1A6V_POLY

CRT_R_1_L

L61

BLM18BA470SN1(47,300MA)_6

CRT_R1

CRT_G_1_L

L60

BLM18BA470SN1(47,300MA)_6

CRT_G1

CRT_B_1_L

L59

BLM18BA470SN1(47,300MA)_6

CRT_B1

R400
150/F_4

R399

R398

C677

150/F_4 150/F_4

C675

5.6P/50V_6

C672

5.6P/50V_6

C671

5.6P/50V_6

C674

5.6P/50V_6

6
1
7
2
8
3
9
4
10
5

C676

5.6P/50V_6

15

D27

17

2
D26

R1

0_4

CRTDDCCLK2

R3

33_4

CRTVSYNC

R4

33_4

CRTHSYNC

R5

0_4

CRTDDCDAT2

*BAV99W

1
2

+5V

*BAV99W
1

PR_VSYNC

37
C1

C2

*470P/50V_4

5
U22

*47P/50V_4

C3

C4
*47P/50V_4

*47P/50V_4

*BAV99W
C

1
2

PR_HSYNC

37
D3

R761

4.7K_4

+3V

*BAV99W
1

CRTHSYNC

*4.7K_4

R25

+3V

CRTVSYNC

AHCT1G125DCH

+3V_DELAY

DDCCLK2

2
D2

2
DDCCLK

DDCCLK

DDCCLK2

DDCCLK2 37

D4

Q6
2N7002E
+3V_DELAY
+3V

10,18 DDCDATA

R762

4.7K_4

R26

DDCDAT2

+3V
2

*4.7K_4

DDCDATA

*BAV99W
1

follow AMD
reference
schematic change
for reduce
leakage to VDDR3 10,18
BUS

CRT_B1

D1

AHCT1G125DCH

10,18,19 HSYNC_COM

CRT_G1

3
CRT CONN
CN20

*BAV99W

U21
10,18,19 VSYNC_COM

CRT_R1

14

*BAV99W
1

13

5.6P/50V_6

+5V

0.1U/10V_4

D28

12

close conn
within 600mils

C673

+3V

11

EMI

R400 for UAM use 140 ohm

on PV(AMD)

24

SI-2 modified --Change Layout footprint 12/27

40 MIL

+5VCRT

16

+5V

DDCDAT2

DDCDAT2 37

Q7
2N7002E
R2

R6

6.81K_4

6.81K_4

+5VCRT

CH501H-40PT

37 PR_RED
37 PR_GEN
37 PR_BLU

PR_RED
CRT_R_1_L
PR_GEN
CRT_G_1_L
PR_BLU
CRT_B_1_L

35,37 PR_INSERT#

+5V_CRT2

D25

U23
2
3
5
6
11
10
14
13
1
15

IA0
IA1
IB0
IB1
IC0
IC1
ID0
ID1
SEL
/E

inputs
YA
YB
YC
YD
VCC
GND

4
7
9
12
16
8

CRT_R
CRT_G
CRT_B

+5V_SW

R403

74CBT3257

CRT SWITCH

CRT_R
CRT_G
CRT_B

0_6

+5VCRT

C679
0.1U/10V_4

10,18
10,18
10,18

+5V

/E

R404
10K/F_4

function

SET

Y - port 0

Y - port 1

Disconnect

EMI
A

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Rev
1A

CRT

Date: Tuesday, February 19, 2008

5

Sheet
1

24

of

45

SP6

R339

*100K/F_4

XD_CD#
SP2
SD_CD#
SP4
RREF

13 USBP6_CR13 USBP6_CR+

RREF

4
5

DM
DP

SD_DAT2/XD_RE#/CF_D12
SD_DAT3/XD_WE#/CF_D5
XD_RDY/CF_D13
SD_DAT4/XD_WP#/CF_D6

40
39
38
37

SP16
SP15
SP14
SP13

SD_CMD
SD_DAT5/XD_D0/CF_D14
SD_CLK/XD_D1/MS_CLK/CF_D7
SD_DAT6/XD_D7/MS_D3/CF_D15
CF_CS0#
MS_INS#/CF_IORD#
SD_DAT7/XD_D2/MS_D2/CF_IOWR#
SD_DAT0/XD_D6/MS_D0/CF_RST#
SD_DAT1/XD_D3/MS_D1/CF_IORDY
XD_D5/MS_BS/CF_A2

36
35
34
31
30
29
28
27
26
25

SD_CMD_R
SP12
SP11
SP10

AV_PLL_IN

VREG_OUT
5V_IN
A3V3_ IN
D3V3_ IN

10
8
3
33

XTLO

Y5
XTLI

*5.6P/50V_4

47

XTLI

MS_CD#
SP8
SP7
SP6
SP5

45

MODE_SEL

*47P/50V_4

For 5158

CARD_3V3_OUT

SP2
SP13
SP19
SP4
SP10

XD_D7
XD_D1
XD_D0
XD_WP#
XD_R/B#
XD_WE#
XD_RE#
XD_ALE
XD_CE#
XD_CLE

SP14
SP12
SP17
SP18
SD_CMD_R

5158_RST# 44
C925

R323

C593
*0.1U/10V_4

C598
*4.7U/6.3V_6

*0_6

D23

+3VSUS
XD_CD#

RST#

SD_CD#

CH501H-40PT

C612

C873
270P/25V_4

C589
*4.7U/6.3V_6

RTS5158 need to remove

D23/D24/C873

+3VCARD
C624

C917

C629

C628

C618

C617

*0.1U/10V_4
*0.1U/10V_4

*1U/10V_4

*0.1U/10V_4

*0.1U/10V_4 *0.1U/10V_4

XD

XD_D0
XD_D1
XD_D2
XD_D3
XD_WE#
XD_CE#
XD_WP#
XD_CLE
SD_DAT4
XD_D4
XD_D5
SD_DAT5
XD_D6
SD_DAT6
SD_DAT7
XD_D7
XD_RE#
XD_R/B#
XD_ALE
SD1_LED# MS1_LED# XD_LED#
SD1_PCTL#MS1_PCTL#XD1_PCTL#
XD_CV#
SD1_CD#
MS1_CD# XD_CD#
MS_D0
MS_D1
MS_D2
MS_D3
MS_BS
MS_SCLK

R332

0_8

RESERVED for JMicron -- after

programming can out-put +3.3V
throught MC_PWR_CTRL_0# signal
6

PAD6

PAD3
1

*MDC_SPRING *MDC_SPRING

for MDC cable

routing

Size
Custom
NB5/RD5

Document Number

Rev
1A

RTS5158 & CR SOCKET &HOLE

Date: Tuesday, February 19, 2008

3

1
1

1
1

1
1

1
1

1
1

MDC_SPRING

*MDC_SPRING

PROJECT : QT8
Quanta Computer Inc.

PAD12

SI-2 modified - for

Jmicron updae

MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

MDC_SPRING

SI-2 for CN37

26
26
26
26
26
26
26
26

PAD2
1

H27
*H-C256D217P2

*10K/F_4

H13
*H-O173X118D173X118N

MDIO06

PAD5

H26
*H-C256D217P2

MDIO05

26

H32
*H-S315D110P2 H2
*H-S315D110P2

26

MDC_SPRING

H30
*H-C236D87P2

MDIO04

H17
*H-C256D217P2

26

Mini Card Hole

Del PAD1
for TP
on PV

H1
*H-C315d118p2

MDIO03

H29
*H-C236D87P2

MDIO02

26

H18
*H-C256D217P2

+5V

+3VCARD

26

MS_DATA0_SD_DAT0
XD-D0
SD_DAT1
MS_DATA1
XD-D1
MS_DATA2_XD_D2
SD_DAT2
MS_DATA3
SD_DAT3
XD-D3
SD_CMD
MS_BS
XD_WE
SD_CLK_MS_CLK
XD-CE#
SD_WP
XD-WP#
XD-CLE
XD-D4
XD-D5
XD-D6
XD-D7
XD-RE#
XD-RB#
XD-ALE

H8
*H-C217D157P2

XD_PWON R387

C874
0.1U/10V_4

MDIO01

+3VCARD

26 MC_PWR_CTRL_0#

MDIO00

26

0_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4
47/F_4
47/F_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4
0_4

H28
*H-C236D87P2

26

R611
R623
R608
R610
R622
R612
R620
R614
R619
R606
R618
R609
R627
R617
R634
R593
R591
R633
R605
R603
R602
R601
R679
R635
R628

PAD7

*MDC_SPRING

PAD4

VGA Hole
H10
*H-C217D181P2

*TAI TWUM 5IN1 CARD READER SOCKET

H14
*H-C256D217P2

CLOSE CONN

K/B SCREW HOLE

H20
*H-C256D217P2

Q25
*AO3409

+3V

XD-D7
XD-D6
XD-D5
SD_DAT1
XD-D4
XD-D3
MS_DATA2_XD_D2
MS_DATA0_SD_DAT0
SD_CLK_MS_CLK

H4
*H-C217D181P2

XD-D7
XD-D6
XD-D5
SD_DAT1
XD-D4
XD-D3
MS_DATA2_XD_D2
MS_DATA0_SD_DAT0
SD_CLK_MS_CLK

SD_CLK_MS_CLK
MS_DATA3
MS_CD#
MS_DATA2_XD_D2
MS_DATA0_SD_DAT0
MS_DATA1
MS_BS

SD_CD#
SD_WP
XD_CD#

H9
*H-C217D157P2

26

36
35
34
33
32
31
30
29
28
27
26
25
24
23

H25
*H-C315D118P2

SD_CD#

5IN1 CARD READER SOCKET

R607
150K/F_4

PAD10
PAD11
MDC_SPRINGMDC_SPRING

H6
*H-C217D157P2

SD_CD#
SD_CD#
SD_WP
SD_WP
XD_CD#

SD-CD
SD-WP
xD-CD
xD-VCC
xD-D7
xD-D6
xD-D5
SD-DAT1
xD-D4
xD-D3
xD-D2
SD-DAT0
SD-CLK
SD-VCC

H11
*H-S315D110P2

39
36
41
35
34
33
32
31
30
29
28
27
26
25
24
23

NC
NC

40
39

H7
*H-S315D110P2

+3VCARD

SD-C/D
SD-CD-SW
SD-W/P
SD-WP-SW
XD-CD
XD-VCC
XD-DATA7
XD-DATA6
XD-DATA5
SD-DATA1
XD-DATA4
XD-DATA3
XD-DATA2
SD-DATA0
SD-CLK
SD-VCC

37
38
41
42

H5
*H-S315D110P2

SD_CLK_MS_CLK
MS_DATA3
MS_CD#
MS_DATA2_XD_D2
MS_DATA0_SD_DAT0
MS_DATA1
MS_BS

37
38
40
42
43

GND
GND
GND
GND

H12

XD-D0
XD-D1
SD_DAT2
SD_DAT3
SD_CMD

GND
GND
GND
GND
GND

PAD9
MDC_SPRING

H23
*H-C244D181P2

XD-WP#

XD-R/B
XD-RE
XD-CE
XD-CLE
XD-ALE
XD-WE
XD-WP
XD-DATA0
XD-DATA1
SD-DATA2
SD-DAT3
SD-CMD
GND
MS-VCC
MS-SDLK
MS-DATA3
MS-INS
MS-DATA2
MS-DATA0
MS-DATA1
MS-BS
GND

xD-R/B
xD-RE
xD-CE
xD-CLE
xD-ALE
xD-WE
xD-WP
xD-D0
xD-D1
SD-DAT2
SD-DAT3
SD-CMD
GND
MS-VCC
MS-SDLK
MS-DATA3
MS-INS
MS-DATA2
MS-DATA0
MS-DATA1
MS-BS
GND

*H-C315D118P2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

H22
*H-S315D110P2

CN36
XD-RB#

PAD8
MDC_SPRING

+3VCARD
CN42

XD-RB#
XD-RE#
XD-CE#
XD-CLE
XD-ALE
XD_WE
XD-WP#
XD-D0
XD-D1
SD_DAT2
SD_DAT3
SD_CMD

+3VCARD

XD-RE#
XD-CE#
XD-CLE
XD-ALE
XD_WE

+3VCARD

SI-2 for Conn

H3
*H-C256D157P2

+3VCARD

+3VCARD

+3VCARD

+3VSUS

MS

SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
SD_CMD
SD_CLK
SD_WP

H31
*H-S315D110P2

5 IN1 CARD READER

XD,MMC/SD,MS/MSP

C894
0.1U/10V_4

MDID0
MDID1
MDID2
MDID3
MDID4
MDID5
MDID6
MDID7
MDID8
MDID9
MDID10
MDID11
MDID12
MDID13
MDID14
CR1_LEDN
CR1_PCTLN
CR1_CD0
CR1_CD1

*RTS5158

*1U/10V_4

+3VCARD

SD/MMC

CH501H-40PT
1
2 MS_CD#

C633
+3VSUS

6
46
32
12

AG33
AG_PLL
DGND2
DGND1

JMB 380 Note:

+3VSUS_RTS

C634
*0.1U/10V_4

*270P/25V_4

SP11

*100K/F_4

C905

C887
0.1U/10V_4

SD_DAT3
SD_DAT2

SP15

VREG

*0.1U/10V_4

If SD_DAT1 connect to
SP4 , MOD_SEL need to
let it to N.C

C872
2.2U/6.3V_6

SD_DAT6
SD_CLK
SD_DAT5
SD_DAT4

XD_D4
XD_D5
XD_D3
XD_D6
XD_D2

+3VSUS

MS_CD#

SP5
MS_BS
MS_D1
MS_D0
MS_D2
MS_INS#
MS_D3
MS_SCLK

SD_DAT1
SD_DAT0
SD_DAT7

25

C918

11

A3V3_OUT

R667

Del R625
for TP
on PV

SP8
SP16

C667

*10K/F_4

*10K/F_4

SI-2 remove R673 not

need -- UMA BOM remove

C647
*0.1U/10V_4

*0.1U/10V_4
D3V3_OUT

R678

AL005158B00 -->RTS5158

XD
XD_CD#

BG612000717

MODE_SEL
R394

AL005158B10 -->RTS5158E

MS

SD_WP
SD_CD#
SD_DAT1

For 5158

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16
SP17
SP18
SP19

*1U/10V_4
48

1
C668

*12MHz

R395
*270K_4

SD/MMC

*0_4

For 5158E

XTLO

*5.6P/50V_4
2

C665

R333

MS_DATA0_SD_DAT0
XD-D6
MS_DATA1
XD-D3
MS_DATA2_XD_D2
SD_DAT2
XD-RE#
MS_BS
XD-D5
SD_DAT3
XD_WE
SD_CLK_MS_CLK
XD-D1
SD_WP
XD-WP#
XD-CLE
XD-D4
MS_DATA3
XD-D7
XD-RB#
XD-D0
XD-ALE
XD-CE#
SD_CMD

*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4
*0_4

*6.19K/F_4

SP19
SP18
SP17

R362

43
42
41

SI-2 modified --Fix

Y5 layout footprint
to XTAL-5X3_2-3_8
(ME placement)

CF_CD#
GPIO0
CF_D10
CF_D9
CF_D2
CF_D8/SM_CD#
CF_D1/XD_CD#
CF_D0/SM_WPM#/SD_WP
CF_A0/SD_CD#
CF_DMACK#
CF_A1/XD_D4
CF_DMARQ

XD_CLE/CF_D3
XD_CE#/CF_D11
XD_ALE/CF_D4

13
14
15
16
17
18
19
20
21
22
23
24

R315
R316
R334
R338
R345
R666
R676
R327
R335
R675
R390
R354
R358
R319
R677
R393
R317
R351
R348
R389
R369
R391
R392
R372

SP6

U19

CARD_LEDO

*0_4

SP7

R320

26,29 CARD_LED#

Note:

SD_DAT1

*0_4

UMA BOM need to add

XTLO

SP4

26

*0_4

R321

+3VSUS

R397

2 CLK_48M_CR

For 5158

For 5158E

Sheet

25
1

of

45

+3V
TPBIAS0
C615

0.1U/10V_4

C609

0.1U/10V_4

C636

0.1U/10V_4

C657

10U/6.3V_8

C862

R586
56.2/F_4

26

0.33U/16V_4

R585
56.2/F_4

TPB0N
*WCM-2012-900T(400mA)

TPB0P
3
2

5
6
7
8

TPA0N

4
1

5
6
7
8

TPA0N
TPA0P

+1.8V

TPA0P

+1.8V_CARD
*BLM18PG181SN1D(180,1.5A)_6

L87

TPA0N

TPB0P

TPB0N

L53
10U/6.3V_8
+3V

TPB0P
TPB0N

+1.8V_CARD

R364

26

25

R359

DV18

TCPS

24

38

TXIN

MDIO13

23

MDIO13

25

39

TXOUT

MDIO14

22

MDIO14

25

MDIO7

CR_LEDN

21

CARD_LED# 25,29

1M/F_4

25

MDIO06

41

MDIO6

DV33

20

+3V

Y6

25

MDIO05

42

MDIO5

DV33

19

25

MDIO04

43

MDIO4

DV18

18

MDIO01

47

MDIO1

NC

14

25

MDIO00

48

MDIO0

D3E_WAKEN

13

49

EPAD

D3E _WAKEN pin :out put low 1ms can wake up

system when system into D3E mode 2
R324
4.7K_4

+1.8V_CARD

R313
4.7K_4

RB501V-40 D39
1

D3E GPIO# 12

SI-2 modified - for

Jmicron updae

MC_PWR_CTRL_0# 25
SD_CD#
MS_CD#

25

25

D3E_SCI# 13

T113
D3E_WAKEUP

Q69
2N7002E-G

R795

2.2K_4

+3VS5

Q69 for power

leakage
concern

D3E _WAKEN pin :out put Hi into D3E mode

out put low normal mode

APTXP

12

11

10

APTXN

25

APV18

15

APRXN

CR1_CD1N

APRXP

MDIO2

APREXT

46

APGND

16

MDIO02

APVDD

CR1_CD0N

25

APCLKP

MDIO3

APCLKN

45

XTEST

MDIO03

XRSTN

CR1_PCTLN

25

DV33

JMB380

17

24.576MHZ

4.99K/F_4

+3V

40

44

R583

D3E :
mode 1 : when card device insert can wake up card reader chip
mode 2 : need to use pin16 to wake up card reader device

10K/F_4

37

MDIO07

+3V

56.2/F_4
56.2/F_4

1394_CONN
CN34

*WCM-2012-900T(400mA)

25

C642
27P/50V_4

2
3

C863
220P/50V_4

MDIO12

27
MDIO10

MDIO11

28
MDIO9

30

32

31

29

TAV33

MDIO8

TPB1N

TREXT

U16

C641
22P/50V_4

1
4

R580
R582

TPB1P

0.1U/10V_4

34

0.1U/10V_4

C579

33

1000P/50V_4

C635

R361
12K/F_4

TPA1P

C580

12K %1
:CS31202FB15
or
CS31202FB07

TPA1N

0.1U/10V_4

36

C613

35

0.1U/10V_4

TPBIAS_1

C610

L88

25
25
25
25
25

C578

MDIO08
MDIO09
MDIO10
MDIO11
MDIO12

TPA0P

TPBIAS0

+3VCARD
R301

2 CLK_PCIE_CARD

9
9
9
9

PCIE_TXP5
PCIE_TXN5
PCIE_RXN5
PCIE_RXP5

C583
C582

0.1U/10V_4
0.1U/10V_4

MDIO06

R594

10K/F_4

MDIO13

R318

10K/F_4
+3V

+1.8V_CARD

2 CLK_PCIE_CARD#

8.2K/F_4

+1.8V_CARD

12 CARD_PLTRST#

MDIO07

R342

10K/F_4

MDIO12 R360

1 200K/F_4

MDIO14 R630

1 200K/F_4

PCIE_RXN5_C
PCIE_RXP5_C

PROJECT : QT8
Quanta Computer Inc.
Size
B
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

JMB380 Controller/1394
Sheet
1

26

of

45

+4.75VAVDD

SI-2 Modified

SI-2 Modified -- change

footrint QFN48-7X7-5-49P-1H
for datasheet update

L56
+4.75VAVDD

37
+3V

SPDIF

EAPD#

+3V_DVDD

C626
10U/6.3V_8

28

C645
0.1U/10V_4

U15

C644
1U/10V_4

L55

Vout

BYP

GND

Vin

EN

C587
0.1U/10V_4

C586
0.047U/25V_4

C581
1U/10V_4

AGND

AGND

C608
1U/10V_4

AGND

R325

0_4

C597
R306

DIGITAL_D2

T221

3 ACZ_SDOUT_AUDIO
BIT_CLK_AUDIO

13 BIT_CLK_AUDIO

R305

VOL_DN/DMIC_1

SDO

BITCLK

DVSS

SDI_CODEC

DVDD_CORE

38

39

37
NC

AVDD2**

PORTA_L

41

40
NC

43

44

45

46

42
AVSS2**

GPIO 5

GPIO 6

PORTA_R

35
34

C663

1U/10V_4

R384

39.2K/F_4

C664

1U/10V_4

Audio JACK: Normal Open

SA_A# -->EXT HP
SA_B# -->EXT MIC
SB_E#-->DOCK MIC

SB_E#

31

MIC1-VREFO-E

30

IDT_GPIO3#

VREFOUT-C

29

MIC1-VREFO-C

R788

*0_6

VREFOUT-B

28

MIC1-VREFO-B

R789

*0_6

VREFFILT

27

VREF_FLT

R368

*0_6

CDC_AVSS

R331

*0_6

R353

*0_6

R674

*0_6

PORTC_R

AGND

C662
10U/6.3V_8

AGND

Change to SHORT-1A for EMI on PV

Del R686,
R356, R349
direct on PV

IDT_GPIO3# 28

+4.75VAVDD

C620
1U/10V_4

C639
1U/10V_4

C931
1U/10V_4

C661
0.1U/10V_4
AGND
AGND

24

PORTC_L
23

22

PORTB_R

25

PORTB_L

5.11K/F_4

GPIO 3

AVDD1

NC

28

SENSE_B

VREFOUT-E / GPIO 4

PCBEEP

21

HP-L

C595
*27P/50V_4

FOR EMI

32

12

20

28

33

26

NC

HP-R

CAP2

AVSS1

19

C596
*27P/50V_4

MONO_OUT

RESET#

NC

0.01U/16V_4

PORT-D_L

11

18

10K/F_4

36

SENSE_B / NC

92HD71B7

PORTF_R

C600

ACZ_SDIN0_ADC

R385

TO Internal Speakers
PORT-D_R

ACZ_RST#_AUDIO

13

R314

47

0.1U/10V_4
+3V_DVDD

TO Headphone jack

EARP_L

+4.75VAVDD

SYNC

C594

AGND AGND
EARP_R

100U/6.3V_3528

AGND

10

47K_4

100U/6.3V_3528

BIT_CLK_AUDIO

ACZ_SYNC_AUDIO

R309

13,28 ACZ_SPKR

DVDD_IO

PORTF_L

13 ACZ_RST#_AUDIO

ACZ_SDIN0_ADC

17

13 ACZ_SYNC_AUDIO

22_4

VOL_UP/DMIC_0

16

ACZ_SDIN0

PORTE_R

13

DVDD_CORE

PORTE_L

+3V_DVDD

0.1U/10V_4

0_6

AGND

GPIO 7 / SPDIF OUT1

R787 0_6

DIGITAL_D1

15

30

*22P/50V_4

14

C961

EAPD

SI-2 for EMI

EAPD

U17
+3V_DVDD
C602 0.01U/16V_4
1
2

C584
10U/6.3V_8

Change C923, 924

footprint

DMIC_CLK

10U/6.3V_8

49

0.1U/10V_4

R78
22_6

Del R672
direct
on PV
AGND
48

1U/10V_4

C588

SPDIF0

C604

C643
0.1U/10V_4
C924
EARPO_R
C923
EARPO_L

2
C590

SENSE_A

C625
10U/6.3V_8

*.1U/10V_4

0_8

C646
0.1U/10V_4

MAINON 20,35,39,42,43,44

C947 22P/50V_4
L54

27

0_8
2

TPS793475

DIGITAL_CLK 30

C946

+5V

*0_8
2

EAPD#--DEFAULT is Hi

+5V

AGND

AGND

AGND AGND

AGND

+4.75VAVDD
C601
0.1U/10V_4

MIC1-VREFO-B

C585
10U/6.3V_8

recommand use X7R /10V

R328
5.11K/F_4

AGND
JACK_SEN# R330

39.2K/F_4

SA_B#

20K/F_4

R329

R363

4.7K_4

R357

4.7K_4

MIC1_R1

C640

2.2U/6.3V_6

EXT_MIC_R

MIC1_L1

C630

2.2U/6.3V_6

EXT_MIC_L

SENSE_A

R687
DOCK_MIC_R1
DOCK_MIC_L1

C616

4.7K_4

2.2U/6.3V_6

C611

2.2U/6.3V_6

C599
1000P/50V_4

MIC1-VREFO-E

R688

4.7K_4

R344

1.21K/F_4

R343

10K/F_4

R336

10K/F_4

R337

1.21K/F_4

AGND SHIELD
AGND SHIELD

TO EXTERNAL MIC

AGND SHIELD
AGND

AGND SHIELD

DOCK_MIC_R 37
DOCK_MIC_L 37

AGND SHIELD
AGND SHIELD

TO DOCK MIC

AGND

AGND

AGND

TO Headphone jack

TO AUDIO/B CON.

C660
1U/10V_4

SI-2 modified
-- Change
footprint for
ME request ,
pin 13,14 are
pin

R396
47K_4

Q27

1
AGND

MMBT3904

+3V

R816
2

C141
.01U/25V_4

Add C141
for
soft-star
on PV

TO DOCK Headphone

*0_4
R669

C963

100U/6.3V_3528

PROJECT : QT8
Quanta Computer Inc.
Size
Custom

Document Number

Rev
1A

Azalia AD1883

Date: Tuesday, February 19, 2008

C

37

AGND

NB5/RD5
B

LSPK_DK

47/F_6

AGND

RSPK_DK 37

Del R814, R815 on PV

Q76
2N7002E

100U/6.3V_3528

R813

Q75
2N7002E

100K/F_4
1

C962

EARPO_L

AGND
SA_A#

47/F_6

3
2

3
AGND

Q74
2N7002E
1

DKMIC_SEN 2

100K/F_4

*0_4

R668

AGND
AGND

R366
10K/F_4

Change C962, 963

footprint

*0_4

AGND

for EMI

DOCK MIC DETECT

DOCK_MIC_L
AGND

MMBT3904
2

Q72
2N7002E

R808

C920
C919
*180P/50V_4 *180P/50V_4

R812

EXT_MIC_R

C921

*180P/50V_4

Q28

C922
*180P/50V_4

Q29
2N7002E

EXT_MIC_L

+3V

R367
47K_4

SA_B#

R371
47K_4

R811

2
R807
330K/F_4

EARP_L
EARP_R
SA_A#

EARPO_R

Q73
2N7002E

37 JACK_SEN#

CIR_IN

+12VALW

R807 change to 330K

for HP on PV

+5V

13
1
2
3
4
5
6
7
8
9
10
11
12
14

+5VPCU
35,37

CN19
AUDIO CONN

0.1U/10V_4

SB_E#
C614

Sheet

27

of

45

AUDIO AMPLIFIER

+5VAMP
U18

AGND

AGND

AGND

2
1

BK1608HM241

L_SPK+

L_SPK-1

L10

BK1608HM241

L_SPK-

SI-2 modified -C53

for EMI
470P/50V_4
suggestion

AGND

INT. SPEAKER

Power =

C52
470P/50V_4

(Vrms) 2/ R

QT8 speaker -- 3.2ohm / 2W

R340

15.6dB

45K

21.6dB

25K

SI-2 modified -remove D22 , add

D40
35

R322
R376

1K_4

*1K/F_4

0_6

27

EAPD#

R386

*0_6

R310

*0_6

100K/F_4
1

R341

R347

VOLMUTE#

C649
10U/6.3V_8

C638
0.1U/10V_4

C632
0.1U/10V_4

AUDIO_G1

C631
0.047U/25V_4
AGND

AUDIO_G0

70K

90K

10dB

6dB

+5VAMP
+5V

AGND

+3V

100K/F_4

100K/F_4

RIN

INT SPEAKER CONN

L11

Vrms = Vpp / 2 2

AV

AGND

R346

GAIN1

4
3
2
1

6017A2 Gain Table

GAIN0

28

CN5

C37
470P/50V_4

L_SPK+2

100P/50V_4

TPA6017A2/FAN7031/LM4874

C637

GAIN0
GAIN1

100P/50V_4

12
21
1
11
13
20

NC
EPAD
GND1
GND2
GND3
GND4

BYPASS

R_SPK-

AGND

100P/50V_4

2
3

R_SPK+

BK1608HM241

19

SHUTDOWN

100P/50V_4

+5VAMP

10

BK1608HM241

L7

DC impedance 0.35ohm

C622

AMP_BYPASS

AUDIO_G0
AUDIO_G1

LIN+
RIN+

L6

R_SPK-3

C34

C651

1 0.47U/10V_6

9
7

R_SPK+4

470P/50V_4

C619

C650 2

AGND

PV-1 Modified --R383 , R373

change from 20Kohm to 0 ohm
for Volume too low issue

LINRIN-

4
8

PC_BEEP

5
17

LOUT+
LOUT-

2 0.047U/16V_6 C_SPKR_L
2 0.047U/16V_6 C_SPKR_R

C659 1
1
C656

18
14

20K/F_4 HP_L_C
20K/F_4 HP_R_C

ROUT+
ROUT-

R383
R373

PVDD1
PVDD2
VDD

6
15
16
HP-L
HP-R

SI-2 Modified -- remove C621/C623

LIN-,RIN- and LIN+,RIN+ swap for BOBO noise on PV

27
27

D40
BAT54A

R386, R310 change

to SHORT-1A on PV

AGND

AGND

MUTE_LED

SI-2 Modified

Low -->un-MUTE

+5VAMP

High-->Mute

C942 *.1U/16V/04

SI-2 modified - from Hp suggestion

R311
100K/F_4

SI-2 Modified -R311 change from

10k to 100k

AGND

+5VPCU

SI-2 modified -- remove

R307,Q24 , add
R781,D41,Q70

PC-BEEP

*1K/04

+3V

PC_BEEP
35

U38
*NC7SZ86

R772
*1K/04

TO CODE

R781

10K/F_4

C944
*.47U/10V_6

Q70
ME2N7002E

VOLMUTE#

3
C945
*.47U/10V_6

27

R771

MUTE_LED

13,27 ACZ_SPKR

TO AMP

C943 *0.1UF/06

IDT_GPIO3#

D41
BAT54A

AGND

35,37

5
KEY_BEEP

35

AGND
R773

*0_4
AMP_GND

Acceleration sensor
+3V

+3V
U6
1
6
C449
10U/6.3V_8

C448
0.1U/10V_4

C450
0.1U/10V_4

3
11

reserved second source

Vdd_IO
VDD
C443
*0.1U/10V_4

Reserved
Reserved

C442
*0.22U/6.3V_4

U7
2
9

VDD
VDD_IO

INT

8
6
5

SDI
SCK
CSB

Del R768
Del R767

12

8
9

INTH#

2,6,7,13,36 PDAT_SMB
2,6,7,13,36 PCLK_SMB
+3V

R169

PDAT_SMB
PCLK_SMB
10K/F_4

12
13
14
7

INT1
INT2

12

SDO
SDA/SDI/SDO
SCL/SPC
CS

GND
GND
GND
GND

INTH#

2
4
5
10

2,6,7,13,36 PDAT_SMB
2,6,7,13,36 PCLK_SMB

PDAT_SMB
PCLK_SMB

Reserved
Reserved

SDO
GND

1
10

7
3

*BOSCH BMA150

SGT-LIS302DLTR

SGT-LIS302DLTR interrupt pin default

is low / active Hi , BIOS need to
programming 22h to change status
from active Hi to low

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

1

Rev
1A

AMP_TPA6017/INT SPK
Sheet

28
8

of

45

29

H19
FBSA1017

H21
FBSA1017

Modem CONN

+3V

MDC
CN18
4

1
3
5
7
9
11

ACZ_SDOUT_AUDIO_MDC

13 ACZ_SDOUT_AUDIO_MDC

ACZ_SYNC_AUDIO_MDC
AC_SDIN1_MDC
33_4

13 ACZ_SYNC_AUDIO_MDC
13 ACZ_SDIN1

R326
C603

*10P/50V_4

GND
REV
A_SDO
REV
GND
VCC
A_SYNC
GND
A_SDI
GND
A_RST# A_BCLK

C653
0.1U/10V_4

2
4
6
8
10
12

R377

C654
2.2U/6.3V_6

C658
1000P/50V_4

0_4

BIT_CLK_AUDIO_MDC

13

MDC CONN

For EMI

13 ACZ_RST#_AUDIO_MDC

C652
*10P/50V_4

+3V

SI-2 modified -- LED4

change footprint
R750
*10K/F_4

SATA_R_LED1 R381
LED4
LED 3P WHITE/AMBER

3
1

*PDTC144EU

14

LED PWR CONTROL

R817

Q18
*2N7002E
3

+3V

20~40mils
+3V_LED

C457
10U/6.3V_8
R178

Del R380
Change R381 to 100
Add R766, R817, R818,
R819
LED PWR control no-stuff
on PV

+3V_LED

34,35 PWR_LED#

LED6
1

2P WHITE LED
2 PWR_R_LED1 R378

20_6

35

MBATLED0#

LED5
1

2P WHITE LED
2 MBAT_R_LED1 R379

20_6

25,26 CARD_LED#

LED7
1

C460
0.1U/10V_4

3 White

*2N7002E
Q17

*1U/25V_8

C932

C933

*.22U/25V_6

*.22U/25V_6

LED1
1

1
R818

35

CAPSLED#

CARD_LED1

R584

20_6

2P WHITE
2 CAP_LED

+3VPCU_LED

R185

20_6

+3V_LED

I = Vcc -Vf / R

LED Vf
C566
10U/6.3V_8

C568
0.1U/10V_4

35

TP_LED1#

35

TP_LED2#

TP_LED1#

(Amber)

TP_LED2#

(White)

R819

TPLD3

R183

TPLD4

R182

LED3 LED 4P WHITE/AMBER

Amber
200/F_6
20_6

+3V_LED

Vcc

2 +

1 +

Anode

+3V_LED

White

For PA

0_8
1

Q12
*AO3404
1

+5V_LED

PROJECT : QT8
Quanta Computer Inc.

20~40mils

C410
0.1U/10V_4

C556
*10U/6.3V_8

LED_CTL

Size
Custom
NB5/RD5

Document Number

Rev
1A

MDC1.5 Con Accelerometer/lLED

Date: Tuesday, February 19, 2008

A

1 Amber

+3V

20~40mils
+3VPCU_LED

LED_CTL

+5V

0_8

Q23
*2N7002E

Anode 2

Dual Color ,Right angle

LTW-326DSKF-5A

add LED auto dim

function

+3VPCU

+3VPCU_LED

2P WHITE LED

LEDVCC_EN# 2

35 LEDVCC_EN#

+3VPCU_LED

*1M/F_4 LED_CTL
C451

R180
*1M_4

2 -

Single Color ,Right angle

LTW-110TLA

SI-1 modified -change LED part

number

0_8

+12VALW

SI-2 change R180

from 100k to
1Mohm for current
limit

PDTC144EU

SATA_LED#

+ 1

SI-1 modified -for fix SATA LED

no support LED
light control

14 ACCLED_EN

*PDTC144EU

Q64

+3V

(Amber)

R766
0_6

100F_6

3
2

35 LEDVCC_EN#

Q26

2
Q65

LED

(White)

Sheet

29

of

45

+5VSUS

C819
1U/10V_4

24mil
1

*100U/6.3V_3528

13
13

USBP0USBP0+

L37

T258
BLUELED 35,36
USBP513
USBP5+
13

1
2

C334
*Clamp-Diode_6

C414
*Clamp-Diode_6

SI-2 modified -- Change

Connector layout type
from SMD PAD to Dip as
SMT request

C812

2
USBP1USBP1+

USB & ESATA

CN32

2. SYSTEM GND

13
13

USBP2USBP2+

L26 4
1

3
2

6
5
4
3
2
1

SATA_TXP2
SATA_TXN2

14
14

SATA_RXN2
SATA_RXP2

Modified

C412

USBP6+
USBP6-

1
4

2
3

USBP6+
USBP6-

+3.9V-CAMARA
*WCM-2012-900T(400mA)
R86
*0_6

SHDN

GND

5
4
3
2
1

13
13

USBP8+
USBP8-

13
13

USBP9+
USBP9-

15

Shield

12

Shield

13

USB_ESATA_COMBO

1
2
3
4
5
6
7
8
9
10

C56
0.1U/10V_4

PCB footprint
BL123-10R-10P-L-QT6

PCB footprint
BL123-05R-5P-L-QT6

+5VSUS

CN7
DUAL USB CONN

FINGER PRINTER CONN

U3

14

Shield

+5VSUS

0.1U/10V_4

L40
13
13

+3V

VOUT

Shield

CN13

VIN

0.01U/16V_4
0.01U/16V_4

GND
A+
AGND
BB+
GND

RIGHT SIDE USBX2

DIGITAL_CLK

C310
C299

5
6
7
8
9
10
11

Del R154 on PV

Add for EMI solution

+5V

0.01U/16V_4
0.01U/16V_4

USB Vcc
DD+
GND

5. USB PWR(+3V)

SI-2

C951
*27P/50V_4

C352
C353

Close to ESATA
CON from AMD
recommend

4. USB+

+3V

SI-2

14
14

1
2
3
4

3. USB-

*WCM-2012-900T(400mA)
C92
0.1U/10V_4

USB0PWR
USBP1USBP1+
C320
*47P/50V_4

1. ESD GND

CN10
CAMERA-BOARD

C807
*470P/50V_4

*WCM-2012-900T(400mA)
4
3
1
2
L29

USB Fingerprint CON

C808
0.1U/10V_4

C332
*47P/50V_4

remove touch-screen function

13
13

C420
*Clamp-Diode_6

C319
*Clamp-Diode_6

*100UF_16V

SI-2 Modified --

+3.9V-CAMARA
USBP2USBP2+

C419
*47P/50V_4

8
7
6
5

GND
GND
GND
GND

USB CONN

C415
*47P/50V_4

1
2
3
4

BTV

For Discrete Touch-Screen

DIGITAL_D1
DIGITAL_CLK

CN33
1
2
3
4

USBP1+
USBP1-

USB CAMERA CONNECT

USB 0

USB0PWR
USBP0USBP0+

*WCM-2012-900T(400mA)
4
3
1
2

BTCON_P1
BLUELED
USBP5USBP5+

C452

6
5
4
3
2
1

SI-2 Modified footprint -for ME change pitch for

1.25mm to 1.0mm

C447
0.1U/10V_4

C454
10U/6.3V_8

CN15
BLUE TOOTH CONN
87213-0600-6P-L

DIGITAL_D1
DIGITAL_CLK

C850
+

C852
0.1U/10V_4

AL000545017
IC(8P)G545B2P8U(MSOP-8) - 1.5A
AL000545000
IC OTHER(8P) G545A2P8U(MSOP-8) - 2A

C459
0.1U/10V_4
BTV

27
27

C853
*470P/50V_4

G545B2PU8
(TPS2061D)

Q20
PDTC144EU

BT_OFF#

14

USB0PWR

8
7
6
5

OUT3
OUT2
OUT1
OC

Q19
ME2303T1

VIN1
VIN2
EN
GND

100UF_16V

Del R179 on PV

2
3
4
1

30

80 mils (Iout=2A)

U33

R181
4.7K_4

LEFT SIDE USBX1 and E-SATA/USB COMBO

+3VSUS

BLUETOOTH

+3VPCU

C221
C166

R1

1U/10V_4

R73
*215K/F_4

4.7U/6.3V_6

SET

IC(5P) G913C (SOT23-5)EP

R2

R72
*100K/F_4

R73 and R72

no-stuff for
fix Vout on PV

PROJECT : QT8
Quanta Computer Inc.
Size
Custom

Vout=1.25(1+R1/R2)
5

NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

4

Rev
1A

BT/WEBCAM/FT/USBX4/ESATA
1

Sheet

30

of

45

R425

+3VLANVCC

32

R41

+FB12

0_6

31

+CTRL15_E

0_6
C713

C700

C703

+LAN_A1.8_FB12
0.1U/10V_4

10U/6.3V_8

10U/6.3V_8

Stuffed for 8101E/8102E/RTL8111C

R426

+3VLANVCC
D

LAN_TX#

Del R50 on PV

0_6 +LAN_D1.5_RVD

R38

+LAN_D1.5
+3V_A_LAN

+3V_A_LAN

Stuffed for RTL8111C(10/100/1000)

LAN_LED_100# R30

0_4

LAN_GLINK100#

XTAL1

LAN_GLINK10#

Y1

32

LAN_GLINK1000#

R418

+CTRL15

XTAL2

+3V_LAN

+3V_GVDD
25MHZ

LAN CABLE DETECT 35

+CTRL15_E

+LAN_D1.5

Del R36, C712,

C710 on PV

C44
30P/50V_4

R37

LANRSET

2.49K/F_4

+LAN_D1.5

use BIOS to programming

EEPROM , EEDI should be
pull Hi

Del R766 for TP on PV

+LAN_D1.5

+LAN_D1.5

+LAN_D1.5

R778

*0_4
+3V_LAN

+3V_LAN

2
1

+3V

+3V_LAN

Remove R456 and Add D42 on PV

R460

*0_4

IC CTRL(64P) RTL8111C-VB-GR(QFN)
IC(64P)RTL8101E-GR(QFN)

C82
C81

LAN_TX#

12 LAN_PLTRST#

LAN_PLTRST#

0_4

330_4

0.01U/16V_4

0.01U/16V_4

0.1U/10V_4

C62

0.01U/16V_4
MDI2+

LAN_REST_R#
MDI2C65

TC7SH08FU

0.01U/16V_4

LAN_GLED#
LAN_YLED#
R785

LAN_MX3LAN_MX3+
LAN_MX1LAN_MX2LAN_MX2+
LAN_MX1+
LAN_MX0LAN_MX0+

PCIE_RXN6_LAN 9
PCIE_RXP6_LAN 9
PCIE_LAN_CLKN 2
PCIE_LAN_CLKP 2

R34

330_4

C39

C85

*0.01U/16V_4 *0.01U/16V_4
A

LAN_YLED
LAN_YLED#

LED_GRE_P
LED_GRE_N

8
7
6
5
4
3
2
1

RX1RX1+
RX0TX1TX1+
RX0+
TX0TX0+

9
11

GND1

14

GND

13

LED_YEL_P
LED_YEL_N

RJ45_CONN

*0_4

V_DAC 1

TCT1

MCT1

24

TD1+

MX1+

23

LAN_MCT0

TD1-

MX1-

22

LAN_MX0-

V_DAC 4

TCT2

MCT2

21

LAN_MCT1

TD2+

MX2+

20

TD2-

MX2-

19

LAN_MX1-

TCT3

MCT3

18

LAN_MCT2

TD3+

MX3+

17

TD3-

MX3-

16

LAN_MX2-

V_DAC 10

TCT4

MCT4

15

LAN_MCT3

11

MDI3-

12

TD4+

MX4+

14

TD4-

MX4-

13

LAN_MX3-

SI-2 modified -LAN_PLTRST# is 3VS5 power

rail , Maybe can remove
NAND GATE

75/F_4

LAN_MX0- 37
C928

0.01U/100V_6 R44

75/F_4

LAN_MX1+ 37
LAN_MX1- 37
C929

LAN_MX2+

LAN_MX3+

0.01U/100V_6 R39
LAN_MX0+ 37

LAN_MX1+

V_DAC 7

MDI3+

C927

LAN_MX0+

0.01U/100V_6 R47

75/F_4

LAN_MX2+ 37
LAN_MX2- 37
C930

0.01U/100V_6 R51

75/F_4

LAN_MX3+ 37
LAN_MX3- 37

C708

NS892402

Link

LAN_GLED
12
LAN_GLED# 10

U26

1
BAT54A

R58

Del R428 on PV

C68

R55

0.1U/10V_4
0.1U/10V_4

+LAN_E1.8

MDI1U28

CN27

+3V_LAN

AL08101E005

C40
*0.1U/50V_6

RJ45

D42

LAN_REST_R#

AL08111C001

RB501V-40

*RB501V-40

+3V_LAN

MDI1+

D38 1

LAN_GLED

EMI
C88
*0.1U/50V_6

LAN_DISABLE# 13,35

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

LAN_REST#

C733

LAN_GLINK1000#

100_4

LAN_YLED

PCIE_TXP6_LAN
PCIE_TXN6_LAN

+3V_LAN

D37

R457

2
R441

MDI0-

LAN_GLINK100#

ISOLATEB

15K/F_4

MDI0+

R456
*1K/F_4

+LAN_D1.5
+3V_LAN +3V_LAN

C709

LAN_GLINK10#

if ISOLATEB pin
pull-low,the LAN
chip will not drive
it's PCI-E outputs
( excluding
PCIE_WAKE# pin )

+LAN_D1.5

PCIE_RXN6_LAN_L
PCIE_RXP6_LAN_L
+LAN_E1.8
PCIE_LAN_CLKN
PCIE_LAN_CLKP

+LAN_D1.5
+LAN_E1.8

9 PCIE_TXP6_LAN
9 PCIE_TXN6_LAN

EEDI

R46
only for 8111B,
8101E&8102E&8111C can
remove

Del U1, R46 on PV

+LAN_D1.5

PCIE_WAKE#

+LAN_D1.5
+LAN_E1.8

35

EESK
EEDI
VDD33
EEDO
EECS
VDD15
NC
VDD15
RTL8111C-VB-GR
NC
NC
VDD15
VDD33
ISOLATEB#
NC
NC
VDD15

T5
T6

13,33,36 PCIE_WAKE#

Del R429, R431, R433, R435,

C718, C726 for 8111B on PV

R427
3.6K_6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

R778
SI-2 modified -RTL8111C remove ,
RTL8111B,8101E,8102E
need to stuff

VCTRL18
AVDD33
MDIP0
MDIN0
AVDD18
MDIP1
MDIN1
AVDD18
MDIP2
MDIN2
AVDD18
MDIP3
MDIN3
AVDD18
VDD15
VDD33

+3V_LAN

+LAN_A1.8

EPAD
RSET
VCTRL15
GVDD
CKTAL2
CKTAL1
AVDD33
VDD15
LED_TX#
LED_100#
LED_10#
LED_1000#
VDD33
VDD15
NC
NC
VDD15

+3V_A_LAN
MDI0+
MDI0+LAN_A1.8_FB12
MDI1+
MDI1+LAN_A1.8
MDI2+
MDI2+LAN_A1.8
MDI3+
MDI3+LAN_A1.8

+3V_A_LAN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

PCLK_SMB
PDAT_SMB
LANWAKEB#
PERSTB#
VDD15
EVDD18
HSIP
HSIN
AGND
REFCLK_P
REFCLK_N
EVDD18
HSOP
HSON
AGND
VDD15

+CTRL18

65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

U2

32

+CTRL15_E

*0_6

Stuffed for 8102E/RTL8101E

+3V_LAN

C45
30P/50V_4

+3V_GVDD

0_6

1000P/3KV_1808

NS892402:GIGABIT

DB0AT9LAN05

NS892405:10/100

DB0ZB1LAN04

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

RTL8111C/8101E/RJ11-RJ45 CN
1

Sheet

31

of

45

32

Power trace Layout > 30mil

LANVCC
1.2W
364mA

+3V_LAN

>30mil

+3VLANVCC

C719
0.1U/10V_4

Del L68, L69 direct

on PV

C722
0.1U/10V_4

C716
0.1U/10V_4

C729
0.1U/10V_4

these CAP are for LAN CHIP LANVCC

pins--16, 37, 46 and 53.placement close lan
chip

C720
C723
0.1U/10V_4

10U/6.3V_8

+3V_A_LAN

placement close to lan chipset

>30mil
C715
0.1U/10V_4

L8
RTL8111C ( Gaga lan ) use 4.7uH
power choke A>500mA tolerance
15%
RTL8101E & RTL8102E stuff 0ohm

+FB12

L8

4.7UH,+-20%,580MA_8

L9

L9

31

C51
10U/6.3V_8
C50
*10U/6.3V_8

Power domain chart

Power trace Layout > 30mil

>30mil +LAN_A1.8

0_8

L8

+CTRL18

these CAP are for LAN CHIP LAN_A3.3

pins-- 2 and 59.placement close lan chip

L9
RTL8111C stuff
RTL8102E need to remove L9
+LAN_A1.8

31

C714
0.1U/10V_4

C57
C728
0.1U/10V_4

0.1U/10V_4

C727
0.1U/10V_4

C721
0.1U/10V_4

C730
0.1U/10V_4

C46
10U/6.3V_8

RTL8111B /
RTL8101E

these cap are for lan

chip LAN_A1.8
pins--5, 8, 11 and 14.
placement close chip

C46

RTL 8101E /8102E stuff ,

RTL 8111C need to remove

placement close to lan chipset

+LAN_E1.8
R442

C46
RTL8111C stuff
RTL8101E / 8102E can remove

0_8

R220
C731
0.1U/10V_4

R220
8102E need to remove
8101E use 0 ohm
8111C use 4.7uH

C732
1U/10V_4

RTL8111C
RTL8102E

LANVCC

3.3V

3.3V

LAN_D1.8

1.8V

1.2V

LAN_A1.8

1.8V

1.2V

LAN_D1.5

1.5V

1.2V

C732 change to 1U on PV

these cap are for lan chip

LAN_D1.8 pins, such as 22 and 28.
placement close lan chip

L66
0_8

L66

L66
RTL8111C used 0ohm
RTL 8101E/8102E need to
remove

Power trace Layout > 30mil

C705
RTL8111C stuff
RTL8101E / 8102E can remove
31

L67

+CTRL15

C704

L67

L67 & C704

8101E/8102E stuff
8111C need to remove
C704
*10U/6.3V_8

+LAN_D1.5

>30mil

*0_8

C705
C705
10U/6.3V_8

C711
10U/6.3V_8

C49
0.1U/10V_4

C79
0.1U/10V_4

C84
0.1U/10V_4

C83
0.1U/10V_4

C61
0.1U/10V_4

C63
0.1U/10V_4

C48
0.1U/10V_4

C47
0.1U/10V_4

C80
0.1U/10V_4

C55
0.1U/10V_4

C66
0.1U/10V_4

these cap are for lan chip LAN_D1.5 pins-- 15,

21, 32, 33, 38, 41, 43, 49, 52 and 58.placement
close lan chip

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Rev
1A

LAN Power

Date: Tuesday, February 19, 2008

5

Sheet

32

of

45

R624
1

1K/F_4
2

ODD_5V

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

14

USBP7USBP7+
NEWCARD_DETECT

13
USBP713
USBP7+
13 NEWCARD_DETECT

S7
P1

15

15

PCIE_WAKE#

13,31,36 PCIE_WAKE#

+3VAUX

PERST#

P6
SATA ODD
CLK_NEW_OE#
NEWCARD_DETECT
R260
0_4
CPPE#
PCIE_NEW_CLKN
PCIE_NEW_CLKP
L96
*WCM2012-110
PCIE_RXN0
PCIE_RXN0
1
2
PCIE_RXP0
PCIE_RXP0
4
3

ODD_5V

120 mils

9
9

PCIE_RXN0
PCIE_RXP0

9
9

PCIE_TXN0
PCIE_TXP0

+5V
C897
0.1U/10V_4

C895
0.1U/10V_4

PCIE_TXN0
PCIE_TXP0

1
4
L97

PCIE_TXN0
PCIE_TXP0

2
3
*WCM2012-110

+3V
C567

C561

0.1U/10V_4

0.1U/10V_4

C506

0.1U/10V_4

0.1U/10V_4

C531

C530

0.1U/10V_4

0.1U/10V_4

+1.5V_NEWCARD

SATA_TXP0 14
SATA_TXN0 14

R5538 NEW CARD

+3V_HDD1
SATA_RXN0 14
SATA_RXP0 14

+5V_HDD1

pin name

+1.5V

C499

0.1U/10V_4

0.1U/10V_4

3
5

+3V_NEWCARD

PCIE_RXN0
PCIE_RXP0
PCIE_TXN0

11
13

+1.5V_NEWCARD

SI-2
modified for
R5538D001-TR-F
add Pin
21~25 as U25
POWER SWITCH
Thermal pad
tied to Gnd

2A

PCIE_TXP0

Del R790,
R791,
R792,
R793 for
RF on PV

1A

C957
*.1U/10V_4

C958
*.1U/10V_4

R270

OC#
0_6

+3V

12
14

C959
*.1U/10V_4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Gnd : (5 Pin)

STBY#
3.3VIN
AUXIN
3.3VIN
AUXOUT
SYSRST# 1.5VIN
CPPE#
1.5VIN
CPUSB#
PERST# 3.3VOUT
SHDN# 3.3VOUT
RCLKEN
OC#
1.5VOUT
GND
1.5VOUT

20

PERST#
2231_SHDN#
NEWCLKEN
NEW_OC#

+3V: 2 A(4 Pin)

C498

For HP request to
reserve

SI-2
2
4

+5V: 2 A(4 Pin)

Main HDD

1
17
15
6
10
9
8
20
18
19
7

+3VS5
+3VAUX
N_PLTRST#
NEWCARD_DETECT

0.1U/10V_4

SATA HDD(1ST)

23
24

21
22

CN40

C513

0.1U/10V_4

*10K/F_4
*10K/F_4
*10K/F_4
*10K/F_4

U13

0.7A

2231_STBY#

C519

+3VS5

SI-2 Modified footprint -- Modify Size as SMT request

SI Build

0.1U/10V_4

+3VS5

R218
R258
R280
R281

C520

10U/6.3V_8

+3V_NEWCARD
C507

CPUSB#
CPPE#
2231_SHDN#
2231_STBY#

C575

R258 SI-2 remove --internal pull hi

+3VS5

+3VAUX

27
28
29
30

C893
0.1U/10V_4

USB7-1
USB7+1
CPUSB#

+1.5V_NEWCARD

Del L90 direct on PV

C896
0.1U/10V_4

0_4
0_4
0_4

SCLK_WLAN
SDATA_WLAN

13,36 SCLK_WLAN
13,36 SDATA_WLAN

2 PCIE_NEW_CLKN
2 PCIE_NEW_CLKP

C877
10U/6.3V_8

R209
R212
R214

33

+3V
CN17
EXPCARD-48303-0042-26P-L-QT6
1 GND_1
2 USB3 USB+
4 CPUSB#
5 RSV_0
6 RSV_1
7 SMBCLK
8 SMBDATA
9 +1.5V_0
10 +1.5V_1
11 WAKE#
12 +3.3VAUX
13 PERST#
14 +3.3V_1
15 +3.3V_2
16 CLKREQ#
17 CPPE#
18 REFCLK19 REFCLK+
20 GND_2
21 PERn0
22 PERp0
23 GND_3
NC5 31
24 PETn0
NC5 32
25 PETp0
26 GND_4

SATA_RXN4
SATA_RXP4

14

+3V_NEWCARD

14
14

S1

SATA_TXP4
SATA_TXN4

GND1
TXP
TXN
GND2
RXN
RXP
GND3

14
14

1
2
3
4
5
6
7

SI-1 modified -- change

footprint CN17 #31,32 as
ME request for Hole pad
change

CN37

NEWCARD

SI-2 Modified footprint -- Modify 12/27

NEWCARD (PCIEXPRESS*1 + USB*1)

SATA CD-ROM

NC1
NC2
NC3
NC4

C960
*.1U/10V_4

pull hi/low
+1.5V

+5V
+3V_HDD1

C860
4.7U/6.3V_6

C861
0.1U/10V_4

C859
10U/6.3V_8

CPUSB##

internal pull up to AUXIN

PERST#

a logic level power good

SHDN#

internal pull up to AUXIN

RCLKEN

internal pull up to AUXIN

*0_8

+3V_HDD1

C33
*10U/6.3V_8

C31
*4.7U/6.3V_6

C697
*0.1U/10V_4

C32
*10U/6.3V_8

C525

C526

0.1U/10V_4

0.1U/10V_4
+3VS5
R224

2 EXT_NWD_CLK_REQ#

0_6
R223
*22K_4
NEWCLKEN

2
Q21
2N7002E

OC#

over current status

STBY#

internal pull up to AUXIN

C858
10U/6.3V_8

internal pull up to AUXIN

Del R578 direct on PV

+5V_HDD1

SYSRST#

+3V

R754

internal pull up to AUXIN

1

CPPE#

+5V_HDD1

CLK_NEW_OE#

follow AMD schematic

+3VS5
0.1U/10V_4

C514
U11
A

EPRESS_PLTRST#

12 EPRESS_PLTRST#

2
4

N_PLTRST#

1
*TC7SH08FU

PROJECT : QT8
Quanta Computer Inc.

SI-2 modified -EPRESS_PLTRST# is

3VS5 power rail ,
Maybe can remove NAND
GATE

Size
Custom
R784

NB5/RD5

0_6

Document Number

Date: Tuesday, February 19, 2008

A

Rev
1A

NEW CARD/SATA ODD/SATA HDD

E

Sheet

33

of

45

34

POWER BUTTON CONNECT

NBSWON1#

+PWLEDVCC

C36

C38

0.1U/10V_4

0.1U/10V_4

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

MY1
MY2
MY4
MY0

C836
C835
C377
C381

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

MX7
MX0
MX5
MX1

C384
C378
C382
C385

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

MY8
MY9
MY10
MY11

C376
C403
C830
C373

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

MX4
MX6
MX3
MX2

C402
C383
C837
C380

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

MY12
MY13
MY14
MY15

C832
C374
C831
C372

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

SI-2 Modified
-- net swap for
layout concern

KEYBOARD PULL-UP

+3VPCU

Add R36 for +5VPCU

MY15
MY11
MY13
MY3

1. +3VPCU(LIDSWITCH PWR)
R36
1

*39_6
2

39_6
2

R33
+3VPCU_LED
23,35
LID_EC#
35
NBSWON1#
29,35 PWR_LED#

CN4
PWR BTN CONN

2. LEDVCC(+3VPCU)

10
9
8
7
6

1
2
3
4
5

3. LIDSWITCH
+PWLEDVCC
PWR_LED#

MY0
MY5
MY4
MY8

10K_10P8R

+3VPCU

4.POWERON#

1
2
3
4
5
6

RP41

5. PWRLED#

MY9
MY1
MY2
MY7

6. GND

10
9
8
7
6

1
2
3
4
5

MY10
MY14
MY12
MY6

10K_10P8R

35
35

MY[0..15]

MY[0..15]

CN11
MX1
MX7
MX6
MY9
MX4
MX5
MY0
MX2
MX3
MY5
MY1
MX0
MY2
MY4
MY7
MY8
MY6
MY3
MY12
MY13
MY14
MY11
MY10
MY15

RP42

C699 0.1U/10V_4

+5VPCU

G2
*SHORT_ PAD1

C481
0.1U/10V_4

C379
C833
C375
C834

MY5
MY6
MY3
MY7

MX[0..7]

MX[0..7]

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

KB CONN
gb1rf240-1253-7f-24p-l

Del R770 on PV

CAP SW CONNECT

+5V_LED

SI-2
140 mA

Modified 12/27
CN12
4
3
2
1

C394
0.1U/10V_4

BL123-04R-TAND
BL123-04R-4P-L-QT6

1.LEDVCC
2.LEDVCC

SI-2

Modified

3. NC
4. GND

+3VPCU
B

C75
0.1U/10V_4
CN8
CAP SW BOARD

1. +3VPCU
2. MBCLK

35,44
35,44
35
35

1
2
3
4
5
6
7
8
9

MBCLK
MBDATA
IC2_INT
NUMLED#

+5V_LED
C934
0.1U/10V_4

3. MBDATA
4. CAP_INT
5. GND
6. NUM LOCK LED
7. +5V
8. ESB_CLK
9. ESB_DAT

35 CAP_ESB_CLK
35 CAP_ESB_DAT

L77

BK1608HS470

L57

BK1608HS470

ESB_CLK

PV modified:
CN8 update type
Add L57, L77, C904, C621 for ESB
Del R104, R103

ESB_DAT

C904
10P/50V_4

C621
10P/50V_4

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

LED/KEYBOARD/SW
1

Sheet

34

of

45

Change U9 layout footprint

+3VPCU

+3VPCU

+3VPCU_EC

34

12

37
37
24,37
28,37
36

KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

R200

83
84
85
86
87
88

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
PSCLK3/GPIO4E
PSDAT3/GPIO4F

ACIN

119
120
128
89
76
109
110
112
114
115
116
117
118

RD
WR
SELMEM/SPICS
SELIO/GPIO50
AD5/GPI43
D0/GPXD0
D1/GPXD1
D2/GPXD2
D3/GPXD3
D4/GPXD4
D5/GPXD5
D6/GPXD6
D7/GPXD7

BIOS_RD#
BIOS_WR#
BIOS_CS#
0_4
SERR#_1

R234

VOLME_UP#
VOLME_DN#
PR_INSERT#
MUTE_LED
RF_LINK#
BLUELED
LAN CABLE DETECT

VOLME_UP#
VOLME_DN#
PR_INSERT#
MUTE_LED
RF_LINK#

31 LAN CABLE DETECT

T60
R235

*4.7K_4

BIOS_A0
SUSON
MAINON
LAN_POWER
S5_ON
VR2.5_ON

41,43 SUSON
20,27,39,42,43,44 MAINON
43 LAN_POWER
B
42,43
S5_ON
41
VR2.5_ON
13,31 LAN_DISABLE#
29 LEDVCC_EN#
29 MBATLED0#

LEDVCC_EN#
MBATLED0#
TP_LED1#
TP_LED2#

29 TP_LED1#
29 TP_LED2#

97
98
99
100
101
102
103
104
105
106
107
108

C493
0.1U/10V_4

1U/10V_4

PM_BATLOW1#

DNBSWON#1

KBSMI#1

SWI#1

D15

A0/GPXA0
A1/GPXA1
A2/GPXA2
A3/GPXA3
A4/GPXA4
A5/GPXA5
A6/GPXA6
A7/GPXA7
A8/GPXA8
A9/GPXA9
A10/GPXA10
A11/GPXA11

63
64
65
66

TEMP_MBAT
AD_TYPE
AD_AIR
SYS_I

DA0/GPO3C
DA1/GPO3D
DA2/GPO3E
DA3/GPO3F

68
70
71
72

CC-SET
CELL_SLT
FAN1ON
D/C#

PWM1/GPIOF
PWM2/GPIO10

21
23

PWM_VADJ
KEY_BEEP (1KHz)

FANPWM1/GPIO12
FANPWM2/GPIO13
FANFB1/GPIO14
FANFB2/GPIO15

26
27
28
29

FAN2ON
FAN1SIG

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

77
78
79
80

MBCLK
MBDATA
MBCLK2
MBDATA2

TEMP_MBAT 44
AD_AIR
SYS_I

44
44

CC-SET

44

+3V_LED

FAN1ON
D/C#

R794

0_4

TPCLK
TPDATA

D16

RB500V-40

D12

D14

RB500V-40

2 *CH501H-40PT L-F

PM_BATLOW# 13

DNBSWON# 13

13

SWI#

13

C441
*10P/50V_4

TP_L
TP_R

37
27,37

Del R249 on PV
CN14
TOUCH PAD CONN

Battery charge/discharge
Cap button

34,44
34,44
5,18
5,18

VGA thermal
system thermal

SW2
3
4
6

MY7

PA

1
2
5

PCB footprint
BL121-12R-12P-L-QT6

MX4

Update SW2, SW4, SW6

P/N on PV

SUSB#

14
15

HWPG
PM_BATLOW1#

GPIOA
GPIOB
GPIOC
GPIOD
GPIO11
GPIO16
GPIO17
GPIO18

16
17
18
19
25
30
31
32

SUSC#

SWI#1
KBSMI#1

GPIO19
GPIO1A

34
36

VRON
NUMLED#

SUSB#

13

HWPG

20,23,38,39,41,42

TOUCH PAD ON/OFF

Pin 17 (GPIO0B) ==> assigned for
ESB_CLK / Pull high 4.7K
Pin 18 (GPIO0C) ==> assigned for
ESB_DAT / Pull high 4.7K

SUSC#
13
CAP_ESB_CLK 34
CAP_ESB_DAT 34
NBSWON1# 34
LAN_REST# 31
EC_DEBUG1 36

NBSWON1#

TP_L

LAN_RESET#
move to Pin 25
pin 18 (SWI#1)
move to Pin 31

SW4
3
4
6

1K/F_4 TP_L_CONN

R352

C445
0.1U/10V_4

1
2
5

TMG-533-S-V-TR

VRON
39,40
NUMLED# 34

reserved for H/W CIR Del R256 for TP

on PV
GPIO40
GPIO41
AD4/GPI42
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59

73
74
75
90
91
92
93
95
121
126
127

DNBSWON#1
CAPSLED#
PWR_LED#
ECPWROK
RSMRST#
VOLMUTE#
SPI_CLK
LID_EC#

XCLKO

123

CRY2

XCLKI

122

CRY1

GND1
GND2
GND3
GND4
GND5
AGND

11
24
35
94
113
69

CIR_IN

SI-2 ADD R256

for H/W CIR

TP_R

27,37

R365

T56
T57
CAPSLED# 29
PWR_LED# 29,34
ECPWROK 5,16
RSMRST# 13
VOLMUTE# 28
LID_EC#

+3V

R199

*10K/F_4

R244
R188
R236
R237
R207
R190
R197
R210
R175
R213
R256
R220

+3VPCU

23,34

Y3
32.768KHZ

HWPG

D11
RB500V-40

change D11 type

for PV

R174

R173
33.2K/F_4

C941
0.1U/10V_4

SB internal pull Hi 10k

to 3v_s5

100K/F_4
10K/F_4
10K/F_4
10K/F_4
10K/F_4
4.7K_4
4.7K_4
*8.2K_4
*8.2K_4
*8.2K_4
4.7K_4
4.7K_4

CIR_IN
NBSWON1#
VOLME_UP#
VOLME_DN#
SLPBTN#
MBCLK
MBDATA
PM_BATLOW#
CLKRUN#
SERIRQ
CAP_ESB_CLK
CAP_ESB_DAT

TMG-533-S-V-TR

Blue LED change to 100K ohm

pull low on PV

3920_RST#
C453
2

47K_4

SLPBTN#

R206

0_4

NBSWON1#

R205

*0_4

R268

100K/F_4
+3VPCU

U12

UMA BOM missing

100/F_4

C542
0.1U/10V_4

Del R246, R254 direct on PV

AD_ID

44

BIOS_CS#
SPI_CLK
BIOS_WR#
BIOS_RD#
+3VPCU

64.9K -->65W

R239

33_4

10K/F_4 SPI_3P

R238

R263

1
6
5
2

CE#
SCK
SI
SO

VDD

HOLD#

WP#

VSS

10K/F_4
SPI_7P

MX25L8005

33.7K -->90W

CS33322FB13

Change D12, D16 to RB500

for current loss

BLUELED

30,36 BLUELED

SI-1
modified
-- change
vaule

CS36492FB17

R176

C446
0.1U/10V_4

1
2
5

SB780 internal have pull hi

+3VPCU
18P/50V_4

SI-2 modified
for avoid AD-_ID
noise

SW6
3
4
6

TP_R_CONN

TOUCH PAD L/R

C479 18P/50V_4

C480

1K/F_4

SST AKE5GFK0Z09 1M byte

RES CHIP 64.9K 1/16W +-1%(0402) WINBOND AKE3GFP0N08 SPI
BIOS
PME AKE3GZP0500
RES CHIP 33.2K 1/16W +-1% (0402)

EON AKE3GZP0Q00
3920_RST# 5,44

PROJECT : QT8
Quanta Computer Inc.

0.1U/10V_4
1

Size
Custom

SLP_BTN# 37

NB5/RD5

Document Number

Rev
1A

KB3926/ROM/TP

Date: Tuesday, February 19, 2008

5

12
11
10
9
8
7
6
5
4
3
2
1

SI-2 Modified for hp request

FAN1SIG
CIR_IN

MBCLK
MBDATA
MBCLK2
MBDATA2

GPIO7
GPIO8

SB internal pull Hi
10k to 3v_s5

TPCLK-1
TPDATA-1
TP_LED1#
TP_LED2#

C417
*10P/50V_4

CIR_IN

+3VPCU
KBSMI#

0.1U/10V_4

T54
T53

GPIO4

13

0.1U/10V_4

C411

BLM18BA470SN1(47,300MA)_6
BLM18BA470SN1(47,300MA)_6

37
44

PWM_VADJ 23
KEY_BEEP 28

SCI#

L38
L39

TMG-533-S-V-TR

V18R

C851

SI-2 for fix cpu vcore

CPU_SVID 40

KB3926

2 CH501H-40PT

TOUCH PAD CONNECTOR

+5VSUS
AD0/GPI38
AD1/GPI39
AD2/GPI3A
AD3/GPI3B

C494
4.7U/6.3V_6

2 CH501H-40PT

TPDATA

25 mils

SI-2 Add Pin 117,103 for DSM,116 for Bluetooth,Pin 23 for Key Beep to Amplifier

TPCLK

4.7K_4

Del L86 on PV

AD_TYPE

D13

4.7K_4

R163

close conn

For KB3926 C version

SCI1#

R153

C458

+3VPCU_EC

124

BLM18BA470SN1(47,300MA)_6

+5VSUS

Vin

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

IC2_INT
SLPBTN#
10K/F_4
ACIN
TPCLK
TPDATA

IC2_INT

SERR#

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15

+3VPCU
44

55
56
57
58
59
60
61
62

Vout

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34

SCI/GPIOE
GA20/GPIO0
KBRST/GPIO1
ECRST

L41

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

20
1
2
37

4.7U/6.3V_6
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
4.7U/6.3V_6

34
34
34
34
34
34
34
34

SCI1#
GATEA20
RCIN#
3920_RST#

C456
C472
C463
C491
C495
C490
C455
C461

9
22
33
96
111
125
67

GATEA20
RCIN#

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
AVCC

13
13

SERIRQ
LFRAME
LAD0
LAD1
LAD2
LAD3
PCICLK
PCIRST/GPIO5
CLKRUN

3
4
10
8
7
5
12
13
38

35

U8
*GMT_G910T21U

SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3
PCLK_LPC_KB3920
R208
0_4
CLKRUN#

12
SERIRQ
12,36 LFRAME#
12,36
LAD0
12,36
LAD1
12,36
LAD2
12,36
LAD3
12 PCLK_LPC_KB3920
12
PCIRST#
12
CLKRUN#

+5VPCU

to LQFP128-16X16-4-AA1
U9

GND

Sheet
1

35

of

45

36

Mini PCI-E Card 1 WLAN

SI-2 modified --Change Library to MIPCI-C-1775861-52P-LDV-QT6

+3VSUS
+1.5V

+3V

R57

*10K/F_4

Del R419
C78
0.01U/16V_4
+3V_WLAN

9
9

PCIE_TXP1
PCIE_TXN1

PCIE_TXP1
PCIE_TXN1

9
9

PCIE_RXP1
PCIE_RXN1

PCIE_RXP1
PCIE_RXN1

PCLK_LPC_DEBUG
MINI_PLTRST#

12 PCLK_LPC_DEBUG

15
13
11
9
7
5
3
1

PCIE_MINI1_CLKP
PCIE_MINI1_CLKN

2 PCIE_MINI1_CLKP
2 PCIE_MINI1_CLKN
T3

CLK_MINI_OE#

14 BT_COMBO_EN#
MINICAR_PME#

T4
C

13,31,33 PCIE_WAKE#

CN25
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
Reserved
Reserved

C72
0.1U/10V_4

C35
10U/6.3V_8

+1.5V

+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

Reserved
Reserved
Reserved
Reserved
Reserved
+1.5V
GND
+3.3V

16
14
12
10
8
6
4
2

GND
REFCLK+
REFCLKGND
CLKREQ#
BT_CHCLK
BT_DATA
WAKE#

MINI_BLED
RF_LINK#

R277

*0_4

R288

10K/F_4

MINICAR_PME#

+3V_WLAN

BLUELED 30,35
RF_LINK# 35
+3V
USBP10+ 13
USBP10- 13

DAT_SMB
CLK_SMB

SDATA_WLAN 13,33
SCLK_WLAN 13,33

C30
0.1U/10V_4

Del R48, R49

for USB
power shape

C707
10U/6.3V_8

Change +3VSUS to +3V

Del R35 on PV

MINI_PLTRST#

LAD0_1
LAD1_1
LAD2_1
LAD3_1
LFRAME#_1

1
Q9
*PDTC144EU

MINI_PLTRST# 12
RF_OFF# 12

R434
R436
R437
R438
R440

0_4
0_4
0_4
0_4
0_4

LAD0
LAD1
LAD2
LAD3
LFRAME#

LAD0
LAD1
LAD2
LAD3
LFRAME#

12,35
12,35
12,35
12,35
12,35

INTEL WLAN
CARD PIN 20
W_DISABLE#
have
internal
pull-up 110k
ohm

+3V

C42
0.1U/10V_4

C41
1U/10V_4
C

MINI PCIE H=4.0

BT_DATA,BT_CHCLK,CLKREQ#
internal pull-DOWN 100k
ohm

R579
*10K/F_4

PCLK_LPC_DEBUG

R432

*0_4

C717 *27PF/50V_4

for EMI request

Mini PCI-E Card 2 TV tuner card

+3V

Del R308
Del EC_debug2 for
CAP board update
on PV
B

MINIEC_5V

FOR KBC DEBUG

+5V
35

9
9

PCIE_TXP3
PCIE_TXN3

9
9

PCIE_RXP3
PCIE_RXN3

2 PCIE_MINI2_CLKP
2 PCIE_MINI2_CLKN

R350

*0_6

EC_DEBUG1

PCIE_TXP3
PCIE_TXN3
PCIE_RXP3
PCIE_RXN3

PCIE_MINI2_CLKP
PCIE_MINI2_CLKN

+1.5V
C605
0.1U/10V_4

CN39
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17

COMP VIDEO IN
+3.3Vaux
Therm Trip out
GND
AUD_R_IN
+1.5V
AUD_L_IN
NC
GND
NC
+3.3Vaux
NC
+3.3Vaux
GND
GND
NC(USB_D+)
GND
NC(USB_D-)
PETp0
GND
PETn0
NC(SMB_DATA)
GND
NC(SMB_CLK)
GND
+1.5V
PERp0
GND
PERn0
NC(+3.3Vaux)
GND
PERST#
S-Video Y/in
NC
S-Video C/in
GND

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

15
13
11
9
7
5
3
1

GND
REFCLK+
REFCLKGND
CLKREQ#
NC
NC
NC

16
14
12
10
8
6
4
2

NC
NC
NC
NC
NC
+1.5V
GND
+3.3Vaux

C592
10U/6.3V_8

USBP11+ 13
USBP11- 13
PDAT_SMB
PCLK_SMB

PDAT_SMB 2,6,7,13,28
PCLK_SMB 2,6,7,13,28
R304
R303

0_6
*0_6

+3V
+3VSUS

MINI_PLTRST#

Del WAN off#

+1.5V

C606
C607
0.01U/16V_4 0.1U/10V_4

C591
10U/6.3V_8
A

MINIPCIE H=7.0

67910-0002

PROJECT : QT8
Quanta Computer Inc.

SI-2 modified --Change Library to MIPCIE-P04-FJ504-170-52P-QT6

Size
Custom
NB5/RD5

Document Number

Rev
1A

Mini CARD X 3

Date: Tuesday, February 19, 2008

A

Sheet

36

of

45

CABLE DOCK

37

support 6A 200mils
CX000480005
+DOCK_VA

CN21
L5
48/6A_12

44 +DOCK_VA

SI-2 modified follow QT6 schematic

remove R671,R670,C916,Q30,L65,C669,R388
4

27

R779

SPDIF

221/F_4 C949

.1U/50V_6

C29
0.1U/50V_6

C950
220P/50V_4
4
1

USBP4USBP4+

USBP4USBP4+

3
2

L4

*WCM-2012-900T(400mA)

+3VPCU

DDCDAT2

24
24

PR_HSYNC
DDCCLK2

24

PR_VSYNC

R18

44

CRT_GDK
CRT_RDK

38
40
34
36
30
32
26

CRT_BDK
PR_HSYNC_D

33_6

USBP4R20

33_6

PR_VSYNC_D

31 LAN_MX3+
31 LAN_MX331
31
31
31
31
31

LAN_MX2+
LAN_MX2LAN_MX1+
LAN_MX1LAN_MX0+
LAN_MX0-

+VIN
C698

PR_INSERT#

docking
insert is HI
voltage

VA_P

VDD

43

38
40
34
36
30
32
26

39
37
35
33
31
29
27

39
37
35
33
31
29
27

PWR_ON

28
22
24
18
20

28
22
24
18
20

25
23
21
19
17
15

MUTE_LED
SLP_BTN#
JACK_SEN#
VOLME_UP#
VOLME_DN#
SPDIF_DOCK

14
16
10
12
6
8
2
4

25
23
21
19
17
15

14
16
10
12
6
8
2
4

13
11
9
7
5
3
1

13
11
9
7
5
3
1

42
46

VSS
46

VSS
45

41
45

0.1U/50V_6

R415
*100K_4

R413
100K/F_4

VDD

CIR_IN

27,35

MUTE_LED 28,35
SLP_BTN# 35
JACK_SEN# 27
VOLME_UP# 35
VOLME_DN# 35
Remove R410, R411
AGND
RSPK_DK 27
LSPK_DK 27
DOCK_MIC_R 27
DOCK_MIC_L 27
AGND

RSPK_DK_L
LSPK_DK_L

DOCK_PRESENT

DOCKING CONN

PR_INSERT# 24,35

Q31
MMBT3904

24

VA_P

USBP4+
13
13

+3V

C17
0.1U/50V_6

SPDIF_DOCK

R780
100/F_4

SI-2 modified -for power leakage

concern

VA_P

2 DKPR#
1K/F_4

2
R414
2K/F_4

DOCK_PRESENT 1
R412

Change D29, D30 to RB500

for current loss on PV

D29
RB500V-40

+5V

24

PR_GEN

24

PR_RED

24

PR_BLU

PR_GEN

R12

0_6 CRT_GDK

PR_RED

R11

0_6 CRT_RDK

PR_BLU

R15

0_6

CRT_BDK

D30
R409 1

2 10K/F_4 DK_PWRON

PWR_ON

RB500V-40

R16

R9

R13
C25

+5VSUS

*Check
voltage on
DB

5.6P/50V_6
R408
15K/F_4

C19
5.6P/50V_6

C23

C24

C20

C21

5.6P/50V_6

5.6P/50V_6

5.6P/50V_6

5.6P/50V_6

150/F_4 150/F_4 150/F_4

S0: 4V
S3: 2.5V
S4/S5:
0V

filter for docking CRT

+3V

DOCK_MIC_R
DOCK_MIC_L

CPU FAN

R177
4.7K_6

RSPK_DK_L
LSPK_DK_L

35

VOLME_DN#

FAN1SIG

JACK_SEN#
CIR_IN

CN26

20 mil

+5VFAN1

C725

1
2
3

C724

PR_HSYNC_D

1
2
3

PR_VSYNC_D

FAN CONN
2.2U/6.3V_6

C27

0.1U/10V_4

C26
C688

C692

C691

C693

C694

C696

C695

*47P/50V_4
*100P/50V_4 *100P/50V_4

*47P/50V_4

*270P/25V_4 *180P/50V_4 *180P/50V_4 *180P/50V_4 *180P/50V_4

+5V

G955 /FON
signal have
internal
pull Hi to
VIN , R420
maybe can
remove

C687 1U/10V_4
AGND

35

2
1
4

FAN1ON

FANPWR = 1.6*VSET

AGND

AGND

AGND

U24

10K/F_4
FAN_SMBALERT#

AGND

SI-2 modified

R420

VIN

VO
GND
/FON GND
GND
VSET GND

3
5
6
7
8

+5VFAN1
8

G995 layout notice

Gnd shape

PROJECT : QT8
Quanta Computer Inc.

G995
1

4
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

A

Rev
1A

CABLE DOCKING/FAN
E

Sheet

37

of

45

+3V

2,3,5,6,7,10,11,12,13,14,15,16,18,20,23,24,25,26,27,28,29,30,31,33,35,36,37,39,43

38

DC/DC +3VPCU/+ 5VPCU/ +12VALW

TON: 5V / 3.3V
GND = 400 / 500KHz
REF = 400 / 300KHz
VCC = 200 / 300KHz

+5VPCU 27,28,34,35,39,40,41,42,43
+3VPCU 5,12,23,29,30,34,35,37,40,41,42,44
+VIN

+VIN_6237

+3VS5 5,7,12,13,14,15,16,23,26,33,43
+5VAL
2
+

REF

TON

8
7
6
5
4
3
2
1
+5VAL
6236AGND

PD18
1

I_lim*MOSFET(RDSON)=V_ILIM(mV)/10
V_ILIM(mV)=5uA*R_ILIM

3
2
1

5
6
7
8

2
PR154
*0_4

Rds(on) 15m ohm

1

2
1_6

43

PC104
*0.1U/10VC_4

3V_DL

PC101
PR216

3
0.1U/50VB_6

PC180
1U/10VC_4

MAIND

PQ34
SI4800BDY

6236AGND

6236AGND
PR183
0_4
PGOOD2

PR152
0_4

*SHORT-1A

+3V

PGOOD1

HWPG

6236AGND

+3V
6.76A

20,23,35,39,41,42

PC100

PD17
CHN217PT
2

PR147
0_6

+3VPCU

6236AGND

CHN217PT

PC97
0.1U/50VB_6

6236AGND

PQ59
FDS6690AS

PR148
1

SI-1 Modified
-ECAP6_3X6_1-7_2-QT8

3
2
1

SI-1 Modified ECAP6_3X6_1-7_2-QT8

PR157
0_4
PC174
*100P/50VA_6

3
2
1

BST1
DL1
VDD
SECFB
AGND
PGND
DL2
BST2

PAD
33

1
2
3

5VBST1

PR149 1_6
1
2

PR214
*2.2_6

3V_DH

3VBST2R

Rds(on) 15m ohm

3VBST2

PR156
0_4

5VBST1R

Rb

PC103
0.1U/50VB_6

PQ54
FDS6690AS

PGOOD2

1
2
3
8
7
6
5

5V_DL

PC161
*100P/50VA_6

2
PR155
*0_4

PR217
309K/F_4
1
2

32
31
30
29
28
27
26
25

PC102

Ra

5V_DH
5V_LX

PU8
ISL6237

REFIN2
ILIM2
OUT2
SKIP
PGOOD2
ON2
DH2
LX2

0.1U/50VB_6

PC179
0.1U/10VC_4

PC177
330U/6.3V_ESR25_6X5.8

PR208
*2.2_6

6236FB1
2
PGOOD1
6237ON1

PR153 1
309K/F_4

BYP
OUT1
FB1
ILIM1
PGOOD1
ON1
DH1
LX1

+3VPCU

PL13
2.5uH/7.5A_10

3V_LX
PC182
0.1U/10VC_4

+5V_ALWP

9
10
11
12
13
14
15
16

REFIN2

PC181
330U/6.3V_ESR25_6X5.8

+5VPCU
PL12
2.5uH/7.5A_10

6236AGND

Rb around 49.9k

+5VPCU

PQ53
SI4800BDY

PQ58
SI4800BDY

PR158
0_4

6236AGND

17
18
19
20
21
22
23
24

Vout=0.7(Ra+Rb)/Rb

6236AGND
PC105
*0.1U/10VC_4

6236AGND
4

LDOREFIN
LDO
IN
RTC
ONLDO
VCC
TON
REF

+3VPCU
C/C:8A
P/C:10A

5
6
7
8

PC107
1U/10VC_4

PC106
0.1U/10VC_4

*1U/10VC_4
6236AGND

3.3 Volt +/- 5%

Place these CAPs

close to FETs

Del PR159 for TP on PV

PC108

8
7
6
5

*47_6

5
6
7
8

6237VIN
PC109
0.1U/50VB_6

PC79
2200P/50VB_4

PC76
0.1U/50VB_6

PC157
10U/25VD_1206

+5VPCU
C/C:8A
P/C:10A

Place these CAPs

close to FETs

6237ONLDO

PR162
150K/F_4

PC110
4.7U/6.3VC_6

1
0_8

PC98
10U/25VD_1206

PR163
390K_4

PR164
2

+LANVCC

5 Volt +/- 5%

+5V_VCC1
PR160

+VIN

5,15,20,23,24,25,27,28,29,30,33,36,37,39,42,43

PC93
0.1U/50VB_6

+5V

PC94
2200P/50VB_4

+5VSUS 23,30,35,37,43

+3VSUS 13,25,30,36,39,41,43

S0-S1

6236AGND
+3VPCU

0.1U/50VB_6

+12V_ALWP

PC96
2.2U/50VB_8 SI2

PR151
0_4

+3VS5

PQ35
AP4228

PR161
100K_4

+12VALW

+5VAL
2

5,44 SYS_SHDN#

PR150
1

0.5A

6237ON2

+3VSUS
1.84A

PQ24
SI4800BDY

+5V

43

SUSD

+5VSUS
4.5A

PQ23
SI4800BDY

S0-S3

+5V

For EMI-SI

S0-S1
+5V

+5VSUS
43

PC194
0.1U/10VC_4

5,15,20,23,24,25,27,28,29,30,33,36,37,39,42,43

LAN_ON

PQ51
SI3456

SUSD

43

+5VSUS 23,30,35,37,43

+LANVCC
PROJECT : QT8
Quanta Computer Inc.

0.27A
4

3
2
1
PC195
0.1U/10VC_4

S5_OND

+3VPCU
A

4.31A

For EMI-SI

43

SUSD

1
2
5
6

MAIND4

3
2
1

MAIND

+3VSUS 13,25,30,36,39,41,43

5
6
7
8

5
6
7
8
43

S0-S3

+3VSUS

+3VSUS

5,7,12,13,14,15,16,23,26,33,43 +3VS5

+3VS5

S0-S5
+5VPCU

0_4
+5VPCU

+3VLANVCC
Size
Custom

+3VLANVCC 31,32,43
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

+5V/+3V(ISL6237)
1

Sheet

38

of

45

39

+1.1V & +1.2V

PD1
CH501H-40PT L-F
2

+VIN

13
FB

5
6
7
8

+1.2V
PR38
10.7K/F_4

RTDL

6.04K/F_6

PR50
10K/F_4

R1

R2

PQ57
SI3456

20,23,35,38,41,42 HWPG
RTPG

9338EN

PGD

EN

+5V

PR213
0_4

PC176
*.1U/10V/04

DRV

G9338 ADJ

VCC

PR211
47/F_4

PC173
10U/4VD_8

PC175
0.033U/25VB_6

9338ADJ

+1.1V 7.0A

5
6
7
8

+1.1V_DYN

S0-S1

RTLFB

Vo=0.75(R1+R2)/R2

PR224
2

PQ5
2N7002E-G

PR225
2K_4

PC189
*0.1U/10VC_4

R2

PR49
10K/F_4

PROJECT : QT8
Quanta Computer Inc.

1.1

PC165
10U/4VD_8

PR58
5.11K/F_6

PC32
*22P/50VA_4

1.0

PQ56
SI4856

R1
PR223
13.7K/F_4

0_4

+1.1V_DYN

PC90
10U/4VD_8

PR212
100/F_4

10 DYN_PWR_EN
A

+1.1V_DYN 11

R1

+3V

Low

+1.2V 2,3,11,12,14,15

PC37
22P/50VA_4

PR222
*10K/F_4

High

+1.1V 9,10,11,18,20,43

Keep R2 higher than 10Kohm

PC163
10U/4VD_8

R2

PR54
0_6

+1.1V
PR210
127/F_6

RTLDRI
PC26
22P/50VA_4

Vout1= 0.5 * ( 1 + R1/R2 )

DYN_PWR_EN

R_ILIM=I_LIMIT*Rsense/20uA

PC162
0.1U/10VC_4

PC178
.1U/10V/04

GND

PC150
390U/2.5V_6X5.8ESR10

PC140
*100P/50VA_6

3
2
1

PU11

+1.2V

PR215
*0_4

9338DRV 3

PC169
.1U/10V/04

Vo=0.75(R1+R2)/R2

6
5
2
1

PC170
.1U/10V/04

PC168
10U/4VD_8

PR200
*2.2_6

PC19
*100P/50VA_4

PC3
*100P/50VA_4

+1.1V

1.5uH/10A_10

RDSon=15m-ohm

0_4

+1.2V

PQ41
FDS6690AS

3
2
1

RTPG

S0-S1

PL7

PR45

RTLEN

PR52

DL

S0-S1

PQ42
SI4800BDY

BST

ILIM

12A (4.3A+7.0A)

9
VDDP

ILIM

10

VOUT

LDRI

LFB

LEN

PAD

reserved for pwr seq -- andrew

3.82A

RT8204

*0_4

RTLX

EN/DEM

14

PR13

11

+1.2V

PC160
0.1U/10VC_4

PC2
*100P/50VA_4

20,27,35,42,43,44 MAINON

17

LX

PU1

RTEN 15

0_4
0_4

DH

RTDH

3
2
1

LPGD

PC4
0.1U/50VB_6
12

5
6
7
8

PGD

0_6

RTFB

PR1

VRON

RTPG
RTLPPG

PR53
20,23,35,38,41,42 HWPG

TON

VDD

RTTON 16

PR51
47K_4

BST

PC131
*10U/25VD_1206

1U/10VC_4

PC126
10U/25VD_1206

8204VDD
PR7
604K_4

PR8

PC128
0.1U/50VB_6

PC15

PC127
2200P/50VB_4

+3VSUS

Frequency=Vout/(VIN*TON)

35,40

PC23
1U/10VC_4

PR32
10_6

+VIN

Ton=3.85p*R_TON*VOUT/(VIN-0.5)

RTBST

+5VPCU
D

PR31 for UMA only

Size
B
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

+1.2V & +1.1V(RT8204)

Sheet
1

39

of

45

+CPUVDDNB

1
47/F_4

PR100
10_6

34 UGATE_0

SVD

PHASE_0

33

CPU_SVC

PR60
1

0_4
2

SVC

PGND_0

32

PR55
1

0_4
2

ENABLE

LGATE_0

31

PVCC

30

10

ISL6265HRTZ-T

VDIFF_0
FB_0

LGATE_1

29

PGND_1

28

PHASE_1

27

11

COMP_0

12

VW_0

+VCORE1

25

UGATE_1

PC87

2
3
2
1

1
2

0_4

0_4

PQ47
SI7636DP

PC146
*100P/50VA_6

ISN_0

PR205
*2.2_8

PC11

1000P/50VB_4

PC9
0.1U/50VB_6

PR28

PR24
4.02K/F_4

PC86
2

ISN_1

0.22U/25VB_6

24

23

ISP_1

VW_1

COMP_1

22

21

20

FB_1

VDIFF_1
19

VSEN_1
18

RTN_1
17

RTN_0

VSEN_0

16

ISN_0

15

14

ISP_0

PL9
0.36uH/25A_11
1

330U/2V_ESR9_7

13

1_6

PC20

PR25
16.2K/F_4

+VCORE0
10_4

26

BOOT_1

ISP_0

PR29

Close to
CPU
socket

UGATE_1

PQ44
SI7686DP

330U/2V_ESR9_7

PC17
1000P/50VB_4

36A

PHASE_1

PR37

6.81K/F_4

PC18
180P/50VA_4

1
4.7U/6.3VC_6

LGATE_1

PR40

1200P/50VB_6

+VIN

PC8

54.9K/F_4

ISN_0

+5VPCU

OCSET

PR46
1K/F_4
PR17

RBIAS

ISP_0

PC22
10U/25VD/1206

PC28
4700P/25VB_4

LGATE_0

PQ46
SI7636DP

PC29
10U/25VD/1206

PR195
100K/F_4

PHASE_0

PC133
0.1U/50VB_6

22K/F_4

PR44
255/F_4

PC30

Pin 49 is GND Pin

180P/50VA_4

PR194

0.22U/25VB_6

PC132
2200P/50VB_4

6265AGND

PC135

3
PR207
*2.2_8

UGATE_0

0_4
2

PWROK

PR66
1

+VCORE0

PC42

3
2
1

37

38
PHASE_NB

UGATE_NB

39

PGND_NB

LGATE_NB

OCSET_NB

RTN_NB

40

41

42

44

43

FSET_NB

COMP_NB

VSEN_NB

46

45

FB_NB

VCC

CPU_SVD

PR226

PR6

36 BOOT_NB
35 BOOT_0

3
2
1

10K_4

BOOT_0

1_6

CPU_SVID

VRON

BOOT_NB

PR73

*0_4
2

SI-2 for fix cpu vcore

35,39

PGOOD

*10K_4

35

OFS/VFIXEN

PL8
0.36uH/25A_11

PR196
1_6

PC158
*100P/50VA_6

3 CPU_PWRGD_SVID_REG

36A

PC84
330U/2V_ESR9_7

PR69

PR95

PU3

PC85
330U/2V_ESR9_7

0_4
1

16 VRM_PWRGD

6265AGND

PR84
2

VIN

GND

+3VPCU
PR83
10K_4

47

2
PR82
*0_4

PQ43
SI7686DP

PC136
0.1U/50VB_6
49

+3VPCU

4
UGATE_NB

6265AGND

2
PR96
0_4

48

+5VPCU

PHASE_NB

PC36
10U/25VD/1206

0.8

PC27
10U/25VD/1206

LGATE_NB
PR198
12.1K/F_4

PC134
0.1U/50VB_6

PC139
2200P/50VB_4

PC46
0.01U/50VB_4
*short
6265AGND

PR81

PR193

0_4

1.0

PC141

PR197
44.2K/F_6

1.2

PR80
0_4

PC137

1.4

33P/10VB_4

1200P/50VB_6

0
0

+VIN

6265AGND

PR101
10_6

+VIN

Output

SVD

SVC

PR94
22.1K/F_4
PC45
1U/10VC_4

SI4914DY

PC44

VFIXEN VID Codes

LGATE_NB

SI-1 Modified ECAP6_3X6_1-7_2-QT8

1000P/50VB_4

+5VPCU

S2 4

6265AGND

5V

G2 3

PR92

3
2
1

D1 2

PC167
0.1U/10VC_4

3 CPU_VDDNB_RUN_FB_L

3.3V

PL10
2.5UH/7.5A_10

7 S1/D2

+VIN_CPU_NB
PC142
10U/25VD_1206

47/F_4

D1 1

PC149
0.1U/50VB_6

3 CPU_VDDNB_RUN_FB_H

VFIXEN

40

+VIN

8 G1

PC144
2200P/50VB_4

OFS

PC171
390U/2.5V_ESR10_6X5.8

PR93

1.2V

PQ50
UGATE_NB

ISL6265 Pin1

3A

PC13
0.1U/50VB_6

PR10
4.02K/F_4
ISP_1

PR23

Parallel

PR9
16.2K/F_4

ISN_1
+VCORE0
PR209

PR189

10_4

PC1
180P/50VA_4

3 CPU_VDD1_RUN_FB_H
PR16
255/F_4
10_4

+VCORE0 5
4

+VCORE1 5
PR2

PR3

54.9K/F_4

+VCORE1

Reserve for uni-plane

PR33

1K/F_4

3 CPU_VDD1_RUN_FB_L

PC5

PR27
0_4

PC6
4700P/25VB_4

10_4

*1K/F_4

Reserve for uni-plane

1200P/50VB_6

Close to
CPU socket

*0.001_2512

+1.8VSUS

PR4

+VCORE1

0_4
2

PR5

6.81K/F_4

3 CPU_VDD0_RUN_FB_L

PR26

3 CPU_VDD0_RUN_FB_H

+CPUVDDNB5

PROJECT : QT8
Quanta Computer Inc.
Size
C
NB5/RD5

Document Number

Rev
1A

CPU_CORE(ISL6265)

Date: Tuesday, February 19, 2008

Sheet
H

40

of

45

41

+2.5V 3
+1.8VSUS 3,4,5,6,7,40,42,43

+VIN
4

PR39

20

LL

13

S5

11

S5ON

S3

10

S3ON

VLDOIN

23

TI51116

HWPG

PR18
0_4
PR19
0_4

+1.8VSUS

DRVL
2

19

PQ48
AOL1412

COMP
PR36

51116_V5FILT
PR41
0_4

VDDQSNS

VDDQSET

6
7
12

VTTGND

MODE

VTT
VTTSNS

COMP
NC
NC

*0_4

51116_V5FILT

CS_GND
GND

1.8V_OUT

VTTREF

PR22
0_4

1
2
3

PR21
147/F_4

PC40
1U/10VC_4

2
18

PAD

25

+0.9VSMVTT 4,7
VTTSNS

PR56
0_4
PR57
*0_4

PR20
100K/F_4

VDDIO_FB_H
PR15
*0_4

PR43
0_6

EC:1108 SI

Differential Pair
4,6 +0.9VSMVREF

+2.5V
0.25A

Close to CPU

+1.8VSUS

5
6
7
8

PC196
0.1U/10VC_4

VIN

GND

VOUT

43

R1
SET

1.8V_OND

PQ27
SI4856

+
PR166
100K/F_4

PC111
4.7U/6.3VC_6

5SET

3
2
1

SHDN

3
1

PC113
1U/10VC_4

PC112
0.1U/10VC_4

+3VPCU

+1.8V
G913C

PR165
100K/F_4

V5IN

No discharge

VDDQ

Tracking discharge

Gnd

Non-tracking discharge

I_OCP=V_trip/Rds_on+I_Ripple/2

+1.8V
10.4A

VDDQSET

S0~S1

GND

Vout=1.25(1+R1/R2)

R2

Discharge Mode

V_TRIP(mV)=R_TRIP(Kohm)*10(uA)

+2.5V
4

Mode

For EMI-SI

S0~S1

SI power
PU9

VR2.5_ON

S0~S3

+1.8VSUS

PC35
0.033U/25VB_6

CPU_VTT_SENSE 4

+0.9VSMVT
2.25A

0_4

VDDIO_FB_L 3

PR167
10K_4

35,43

PR47
MODE

PR30
*0_4

Rb

SUSON

+0.9VSMVTT
PC38
10U/4VD_8

PC41
10U/4VD_8

24

PGND

17
3

Ra
PC10
*100P/50VA_4

35

20,23,35,38,39,42

1
1.8_DL

390U/2.5V_6X5.8ESR10

Fix 1.8V Output

PR31
10K_4
8.45K/F_6

PGOOD

1
2
3

1.8V_LX
5

DRVH

16 CS

PC14
*100P/50VA_4

PC153
0.1U/10VC_4

21

PR48
CS

PC7
*100P/50VA_4

1.5uH/10A_10
PC143

PQ39
AOL1426
1.8V_DH

+3VSUS

14

0_6

+1.8VSUS_J
+

VBST

V5FILT

0.1U/50VB_6

22

V5IN

BST

PL6

PC16
1U/10VC_4

PR71

PC39

+1.8VSUS

15

PU2

Rb value from 100K to 300K ohm

10_6

PC33
2200P/50VB_4

PC34
0.1U/50VB_6

PC25
2.2U/6.3VC_6

51116_V5FILT

Ra=(Vout-0.75)/0.75*Rb

S0~S3

I_lim(Valley)=10uA*R_ILIM/RDS_ON
For OCP set.

+5VPCU

1
2

PC48
10U/25VD_1206

PC47
*10U/25VD_1206

+1.8VSUS
23.65A

PC164
*100U/25V_6.3X7.7

PC159
*100U/25V_6.3X7.7

+1.8V

For EMI-SI

V5IN

3,5,8,10,11,12,15,16,18,19,20,21,22,26,43

PC197
0.1U/10VC_4

FB

VDDQ(V)

VTTREF and Vtt

2.5

V_ vddqsns/2

1.8

V _vddqsns/2

adjustable

Note
DDR
DDR2

V_VDDQSNS/2

1.5V<VDDQ<3V

Discrete:SI4856
UMA:SI4800

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

A

Rev
1A

1.8VSUS/DDR_VTER/+1.8V/2.5V
E

Sheet

41

of

45

ATI M82-SE

+1.2V_S5 15

VIN

0.01U/50VB_4
PR125
0_4

8118PG

8118BST

HDR

8118HDR

PGD

VREF

8118TSET 15

TSET

17

5
6
7
8

PR206
*2.2_6

4
PQ55
FDS6690AS

8118CSP

GNDP

3
2
1

11

CSN

12

PR103
191K/F_4

PR104

PR99
51.1/F_4

PC172
0.1U/10VC_4

PC166
390U/2.5V_ESR10_6X5.8

PC60

11K/F_4

SI-1 Modified -ECAP6_3X6_1-7_2-QT8

33N/10VB_4

8118CSN
PR89
*49.9K/F_4

PR78
130K/F_6

+VGA_CORE 5,18,20
1.5UH/16A_PCMC104T-1R5MN

PC63
22P/50VA_4

PR75
110K/F_6

8118LDR

PC49
1000P/50VB_4

PR70
665K/F_6

PC53
0.022U/25VB_6

PQ10
2N7002E-G

PC56
1000P/50VB_4

18 GFX_CORE_CNTRL0

PC54
0.1U/50VB_6

PR65
665K/F_6
PC57
1000P/50VB_4

PR116
0_4

LDR

CSP

8118AGND

8118LX

+VGA_CORE

PL11

PR79
63.4K/F_4

+8118VREF 14

10

PU6

OZ8119

VSET

GNDA1

PR74
162K/F_6

ON/SKIP

OCT

8118VSET 13

PR119
10K_4

DCR=8.1m-ohm (max)

PC151
*100P/50VA_6

PC75
*100P/50VA_4

15K_4

LX

20,27,35,39,43,44 MAINON

S0~S1

PC72
0.1U/50VB_6

43 VCORE_PG
8118EN

PQ52
SI4800BDY

SW1010CPT
PR118

2
PR121
0_6

BST

20,23,35,38,39,41 HWPG

VDDA

8118AGND

PD10

8118VIN

8118AGND
PC65
PR117
10K_4

+VGA_CORE
9.4A

3
2
1

0.9V

PC83
1U/10VC_4

5
6
7
8

PC55
1U/10VC_4

+5VPCU

PR105
1K_4

1.0V

+VIN
D

VDDP

+5VPCU

PR91
20_6

1.0V
1

8118VDDA

PC88
*10U/25VD_1206

PC89
10U/25VD_1206

1.1V

PC155
0.1U/50VB_6

PC154
2200P/50VB_4

PD9
CH501H-40PT L-F

+1.5V 33,36

16

42

+VGA_CORE5,18,20

PWRCNTL1 PWRCNTL0 V-CORE

PR98
0_4
PR76

8118AGND

*short
8118AGND

+1.8VSUS

PC114
10U/4VD_8

PR220
10K_4
35,43

PC186
*0.1U/10VC_4

GND
ADJ
VO
NC

VIN1

POK

GND

EN

VOUT

VCNTL

VOUT

PC117
0.1U/10VC_4

PC183
10U/4VD_8

PR172
47K/F_4

R2

PC184
0.1U/10VC_4

PC121
10U/4VD_8

PC118
1
2

Vo=0.8(1+R1/R2)

R2
PR219
100K/F_4

PC119
0.1U/10VC_4

R1

56P/50VA_6

PC185
0.1U/10VC_4

+1.5V 33,36

41.2K/F_6

Sequence control ??

R1
PR218
51.1K/F_6

S0~S1

PR176
5913FB

+1.2V_S5 15

G966

+1.5V
5913EN

PC116
0.1U/10VC_4

+1.2V_S5

8
7
6
5
966ADJ

PC187
0.1U/10VC_4

POK
VEN
VIN
VPP

+5VPCU

1
2
3
4

VIN

APL5913
+5V

S0~S5
PU12

+3VPCU

PC188
10U/4VD_8

+5V

+1.5V
2.0A

PU10

PR174
10K_4

+1.2V_S5
0.5A

S5EN_G966

S5_ON

PC115
0.1U/10VC_4

FB

PQ8
2N7002E-G

18 GFX_CORE_CNTRL1

Vo=0.8(R1+R2)/R2

R2<120Kohm

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Rev
1A

VGA PWR OZ8118/1.2V_S5/+1.5

Date: Tuesday, February 19, 2008

1

Sheet

42

of

45

43

SI-1 Modified - can remove +1.35V for AMD update

20,27,35,39,42,44

0.5A

PC66

+12VALW
+5V

MAINON

+1.1V

+3V

S0-S1

*0.1U/10VC_4

+VIN
PU5

PR180
1M_4

+1.35V

8
7
6
5

PR178
*22_8

PR182
*22_8

PR175
*22_8

PR179

PR106
*69.8K/F_6

MAINON_G

PQ29
*2N7002E-G

20,27,35,39,42,44

Vo=0.8(R1+R2)/R2
R2<120Kohm

PQ30
PDTC144EU

PC122
*2200P/50VB_4

PQ32
2N7002E-G
1

PR181
1M_4

MAINON

38

R2

+3VSUS

PQ33
*2N7002E-G

PC51
*0.1U/10VC_4
PR113
*100K/F_4

PQ31
*2N7002E-G

PC73
*0.1U/10VC_4

PC68
*10U/4VD_8

1M_4

R1

*G966

MAIND

GND
ADJ
VO
NC

+5VPCU
PC58
*0.1U/10VC_4

PC67
*10U/4VD_8

POK
VEN
VIN
VPP

1
2
3
4

+1.8VSUS
A

PR109
*10K_4

+12VALW

+5VSUS

+12VALW
+3VLANVCC
PR114
1M_4

38

PQ4
PDTC144EU

PQ12
*2N7002E-G

PR123
1M_4

PQ14
PDTC144EU

PC70
*2200P/50VB_4

PQ13
2N7002E-G

35 LAN_POWER

LAN_ON 38

PR87
1M_4

PC74
*2200P/50VB_4

PQ9
2N7002E-G

SUSON

LAN_ON
PR124
1M_4

SUSD

35,41

PQ7
*2N7002E-G

PR129
*22_8

SUSON_G

PQ3
*2N7002E-G

SUSD
PR90
1M_4

PR111
1M_4

+VIN

PR88
*22_8

PR188
*22_8

+VIN

LAN_POWER_G

For Discrete Only

C

+12VALW

+1.8V

+3VS5
+VIN

MAINON

PQ26
*2N7002E-G

PR169
0_4

1.8V_OND 41

42 VCORE_PG

2N7002E-G

PR168
1M_4

2
PQ25
PDTC144EU

PC120
*2200P/50VB_4

PR177
1M_4
2

PQ28
2N7002E-G

S5_ONG
1

PQ38
PDTC144EU

20,27,35,39,42,44

PQ36
PR187
1M_4

PC123
*2200P/50VB_4

1
2

S5_ON

35,42

PR170
*0_4

PR171
1M_4

38

S5_OND

S5_OND

PQ37
*2N7002E-G

PR186
1M_4

+12VALW

PR173
*22_8

PR185
*22_8

PR184
1M_4

+VIN

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Rev
1A

DISCHARGE

Date: Tuesday, February 19, 2008

1

Sheet

43

of

45

+VAD

+PRWSRC

PD19
*SW1010CPT
SW1010CPT

PC129

ACPRN

PHASE

18

6251_PHASE

24

DCIN

LGATE

14

6251_LGATE

PGND

13

GND

12

CHLIM
9

VRFE
8

ICM

VREF = 2.39V

+6251_VREF

+BATCHG

PR77

100K_4

3
2
1

PR85

ADP TYPE

SYS_I

PR72 Value

65W

102K/F

CS41022FB19

90W

7.5K/F

CS27502FB11

EC:11/05_SI

PC71
0.01U/50VB_4
+VAD2

PR227
22_6
1

VIN

GND

NC

PC190
.1U/50V_6

PG

D_CAP

6251_ACIN

35
2

*CH501H-40PT L-F
PC21
*10U/10VD_8

1
PR143
*10K_4

PC191
.1U/50V_6
PC92
*220P/50VB_4

CN

P2805

7
D/C#

PU7
*TL331

1
3

PD5
PQ1
*PDTC144EU

Vout

PR139
*22K_4

PR42
*0_4

3
1

PQ17
*2N7002E-G

+VH28

PU13

ACOK_IN

1
2

*CH501H-40PT L-F

PC91
*0.1U/50VB_6

P/N

PC59
3300P/25VB_4

2
1

35

100_4

*100_4

*1M_4

+VAD2

2
3

PR127

PR144

Charging Curret setting =

I chg = 165mV / Rsense * (Vchlim / 3.3V)

PC81

*1U/25VC_8

PC192
1U/50V_6

PC193
0.01U/50V_6

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Rev
1A

CHARGER ( ISL6251)

Date: Tuesday, February 19, 2008

5

PC95
*0.1U/50VB_6

100K_4

PQ16
*2N7002E-G

PR142
*100K_4
PR138
*47K_4

BATDIS_G

+VH28

PQ22
*IMZ2

*47K_4

PR137

PD14

*CHN217PT
2

*0.01U/50VB_4

CSON_1

V ACLIM = VREF *
(Rhi // 152K) / (Rhi // 152K + Rlow// 152K)
Input curretn = 2.9A (71.5K , 10K)
(0.05/Vref * Vaclim + 0.05 ) / Rsense

35

1
3

VADJ =
VERF >> 4.2V +5%
Float >> 4.2V
PR62
GND >> 4.2 -5%
*100K/F_4

CC-SET

PD16
PC99

PQ49
SI4800BDY

6251_CHLIM

ACIN

2
2
PR63
*100K/F_4

PC125
*100P/50VA_4

1
PR68
10K/F_4

PU4

ONLY for 3S battery pack

ACOK#

PR191
*2.2_8

PR145
*10K_4

PR97

PR108
10K_4

6251_ACIN

6251_VADJ

10

+VAD2

CSOP_1

Input Current monitor

V icm = 19.9 * (Vcsip - Vcsin)
PC62
100P/50VA_4

PR134
15K_4

PR72
7.5K/F_4

6251_ACLIM

PC50
100P/50VA_4

PC64
6800P/25VB_4

10UH/4.4A_10

+VAD2

1 +6251_VDD

PR112
0_4

VCOMP

ACLIM
EN

6251_EN 3

6251_ICM

12.4K/F_4

PQ15
PDTA124EU

12

PD2
UDZS5.6BTE-17

+6251_VREF

PC78
PR130

11

PR199
RL3720WT-R020

PL5

VADJ

6251_ICOMP

PR133
10K_4

11

12

ACSET

PR120
7.15K/F_6

PR14
10K/F_4

1
11

PQ40
SI4800BDY

6251_CELLS

ACOK

0.1U/50VB_6
3
2
1

ISL6251A

6251_VCOMP1

Setting the Vin

min to 11.42V
For ACSET
1.26V

PR132
12.4K/F_4

PR34
330_4

PD3
UDZS5.6BTE-17

6251_UGATE

CSON

23

ICOMP

100K/F_4

MBCLK

VDD

UGATE

17

22

100K/F_4

Setting the Vin min to 15.88V

For EN = 1.06V

PC82
0.1U/10VC_4

PC52

6251_BOOT

EC:11/05_SI

+DCIN

0.1U/10VC_4

PR128

ACOK#

CELLS

SW1010CPT
PR131
75K/F_4

PC12
0.01U/50VB_4

1
1

20
CSIN

CSIP

VDDP

16

PD7
CH501H-40PT L-F

5
6
7
8

20_4

6251_ACIN

AD_AIR

35

PR86

BOOT

PC80
1U/25VC_8

PR122

4.7U/6.3VC_6

PD11

PD12
CH501H-40PT L-F

35

CSOP

PC43

1
0.047U/25VB_4
CSON
PR115

MAINON

+VAD2

MBDATA

PC147
10U/25VD/1206

PD13
SW1010CPT
2
1

21

34,35

PC148
10U/25VD/1206

20,27,35,39,42,43

PC24

+6251_VDDP

1_6

PQ21
*2N7002E-G

+VA

VREF = 5.075V

1
CSOP
PC69

PR126
10_6
+DOCK_VA

20_4

CSOP_1
PQ11
IMD2
CSON_1

PR146
*680K/F_6

+6251_VDD

PR67
4.7_6

3
2

Close to AC soft start MOSFET

3
3

PR141
*200K_4

470_4 PTC

+VAD
PR110

*0_4
PQ20
*2SB1197K

CSIN

PR201

+VAD2

+6251_VDD

0.1U/50VB_6
PQ19
*2N7002E-G

PR35
330_4

PR136
*200K_4

PR202
14K/F_4

PC145
0.01U/50VB_4

*10U/25VD_1206

*200K_4
PR135
C

PR102
2_6

CSIP
PC61
PQ2
2N7002E-G

PC31

0.1U/50VB_6

+3VPCU

34,35

2200P/50VB_4

10

SMC

TEMP_MBAT 35

PR107
20_4

2
6251_ACIN

PC130

PC77
2.2U/6.3VC_6

10U/25VD_1206

PR59
*100K/F_4

5,38 SYS_SHDN#

+VAD2
PD15
*UDZS5.6BTE-17
PR140

6 10

MBATV

5,35 3920_RST#

SI-2 modified -- EMI

5
6
7
8

1000P/50V_4

PC200

*UDZS5.6BTE-17

PD6
2

PQ18
2N7002E-G

SMD

BP07061-BA015

PD4

ACOK# 2

+6251_VDD

19

PR11
10K_6

BATDIS_G

J1-1

PR203
100K/F_4

BATDIS_G

PR192
100K/F_4

+VH28
PR12
0_6

15

DC-IN CONN

JACK-LED

PC138
1U/25VC_8

ACOK_IN

+VIN

EC:11/05_SI
PR61
RC7520WT-R020
1
2

CN23
+BATT

8
7
6
5

CSIN_1

PR190
100_4

PC156
0.1U/50VB_6

44

PL2
HI0805R800R-00/5A_8

PC124
0.1U/50VB_6

9 2
10 1

S10P40CPT/40V/10A

CSIP_1

PL4
HI0805R800R_5A/08

1
2
3
4

5
6

1
1

3
4

J1-1

+BATCHG

PQ6
FDS6679AZ

CN3

+VH28

EC:SI2
For VAD noise

PD20

PC199
0.1U/50VB_6

35

PC198
0.1U/50VB_6

PQ45
IRFR3707ZCTRPBF
EC:11/05_SI

+VA

PL3
HI0805R800R_5A/08

PL1
HI0805R800R-00/5A_8

+VAD
3

1P

AD_ID

PD8
S10P40CPT/40V/10A
2

+DOCK_VA

2P

37

CP

TOP DC_JACK
65W/90W

+VAD

Sheet

44

of

45

CPU Power 1

CPU Power 2

EC Pin98
SUSON

HWPG

VRM_PWRGD
+VCORE0

+1.8VSUS
D

EC Pin99
EC Pin34

MAINON

+VCORE1

VDDA_EN
+0.9VSMVTT

+CPUVDDNB

+2.5V
+1.2V

EC Pin101
C

S5_ON

S5_OND

+1.1V

Delay

HWPG

HWPG

+3VS5
VCORE_PG

EC Pin101
S5_ON
+1.2VS5

+VGACORE

+5VSUS

HWPG

EC Pin99
MAINON
Option

EC Pin98
SUSON

SUSD

Delay

+3VSUS

Delay

1.8V_OND

+1.8V

VCORE_PG

+5V
+5V

+1.5V

EC Pin99
MAINON

MAIND

Delay

+3V

EC Pin76

S5_ON

SUSON

MAINON

HWPG

ECPWROK

SB_PWRGD_IN

NB_PWRGD_IN

SUSD

MAIND

VCORE_PG

Delay 600ms

3.3V

1.8V

S5_OND
RSMRST#

VRM_PWRGD

PROJECT : QT8
Quanta Computer Inc.
Size
Custom
NB5/RD5

Document Number

Date: Tuesday, February 19, 2008

5

Rev
1A

Power control
1

Sheet

45

of

45