Compuerta AND Ecuacin algebraica F=AB Tabla de verdad

Tabla Verdad de Compuerta AND Cdigo en VHDL utilizando un algoritmo funcional library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_and is port ( A: in std_logic; B: in std_logic; F: out std_logic ); end com_and; Declaracin de la arquitectura architecture com_arch of com_and is

begin process (A,B) begin if (A=1 and B = 1) then F <= 1; else F <= 0; end if; end process; end com_arch; Cdigo en VHDL utilizando un algoritmo flujo de datos library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_and is port ( A: in std_logic; B: in std_logic; F: out std_logic); end com_and; Declaracin de la arquitectura architecture com_arch of com_and is begin F <= 1 when ( A = 1 and B = 1) else 0; end com_arch;

Compuerta lgica digital OR Ecuacin algebraica F=A+B Tabla de verdad

Tabla de Verdad de compuerta lgica digital OR Cdigo en VHDL utilizando un algoritmo funcional library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_or is port (A: in std_logic; B: in std_logic; F: out std_logic ); end com_or; architecture com_arch of com_or is begin

process (A,B) begin if (A=0 and B = 0) then F <= 0; else F <= 1; end if; end process; end com_arch; Cdigo en VHDL utilizando un algoritmo flujo de datos library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_or is port (A: in std_logic; B: in std_logic; F: out std_logic); end com_or; architecture com_arch of com_or is begin F <= 0 when ( A = 0 and B = 0) else 1; end com_arch;

Compuerta Lgica Digital NOT Ecuacin algebraica

Tabla de verdad

Tabla de Verdad de Compuerta Lgica Digital NOT Cdigo en VHDL utilizando un algoritmo funcional library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_not is port (A: in std_logic; F: out std_logic); end com_not; architecture com_arch of com_not is begin process (A) begin if A=1 then F <= 0;

else F <= 1; end if; end process; end com_arch; Cdigo en VHDL utilizando un algoritmo flujo de datos Descripcin: Flujo de datos library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_not is port (A: in std_logic; F: out std_logic ); end com_not; architecture com_arch of com_not is begin F <= 1 when A = 0 else 0; end com_arch;

Compuerta Lgica Digital NAND Ecuacin algebraica

Tabla de verdad

Tabla de Verdad de Compuerta Lgica Digital NAND Cdigo en VHDL utilizando un algoritmo funcional library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_nand is port (A: in std_logic; B: in std_logic; F: out std_logic ); end com_nand; architecture com_arch of com_nand is

begin process (A,B) begin if (A=1 and B = 1) then F <= 0; else F <= 1; end if; end process; end com_arch; Cdigo en VHDL utilizando un algoritmo flujo de datos library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_nand is port (A: in std_logic; B: in std_logic; F: out std_logic); end com_nand; architecture com_arch of com_nand is begin F <= 0 when ( A = 1 and B = 1) else 1; end com_arch;

Compuerta Lgica Digital NOR Ecuacin algebraica

Tabla de verdad

Tabla de Verdad de Compuerta Lgica Digital NOR Cdigo en VHDL utilizando un algoritmo funcional library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_nor is port (A: in std_logic; B: in std_logic; F: out std_logic ); end com_nor; architecture com_arch of com_nor is

begin process (A,B) begin if (A=0 and B = 0) then F <= 1; else F <= 0; end if; end process; end com_arch; Cdigo en VHDL utilizando un algoritmo flujo de datos Descripcin: Flujo de datos library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_nor is port (A: in std_logic B: in std_logic; F: out std_logic); end com_nor; architecture com_arch of com_nor is begin F <= 1 when ( A = 0 and B = 0) else 0; end com_arch;

Compuerta Lgica Digital XOR Ecuacin algebraica

Tabla de verdad

Tabla de Verdad de Compuerta Lgica Digital XOR Cdigo en VHDL utilizando un algoritmo funcional Descripcin: Funcional library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_xor is port (A: in std_logic; B: in std_logic; F: out std_logic ); end com_xor;

architecture com_arch of com_xor is begin process (A,B) begin if (A = B) then F <= 0; else F <= 1; end if; end process; end com_arch; Cdigo en VHDL utilizando un algoritmo flujo de datos library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_xor is port (A: in std_logic; B: in std_logic; F: out std_logic); end com_xor; architecture com_arch of com_xor is begin F <= 0 when A = B else 1; end com_arch;

Compuerta Lgica Digital XNOR Ecuacin algebraica

Tabla de verdad

Tabla de Verdad de Compuerta Lgica XNOR Cdigo en VHDL utilizando un algoritmo funcional library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_xnor is port (A: in std_logic; B: in std_logic; F: out std_logic); end com_xnor; architecture com_arch of com_xnor is

begin process (A,B) begin if A = B then F <= 1; else F <= 0; end if; end process; end com_arch; Cdigo en VHDL utilizando un algoritmo flujo de datos library IEEE; use IEEE.std_logic_1164.all; Declaracin de la entidad entity com_xnor is port (A: in std_logic; B: in std_logic; F: out std_logic ); end com_xnor; architecture com_arch of com_xnor is begin F <= 1 when A = B else 0; end com_arch;