748

IEEE JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

SC-22, NO. 5, OCTOBER

1987

Static-Noise
EVERT SEEVINCK,

Margin Analysis SRAM Cells

J. LIST, AND JAN

of MOS
LOHSTROH, MEMBER, IEEE

SENIOR MEMBER, IEEE, FRANS

,4bsfrad The stability of both resistor-load (R-load) and full-(2MOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of
device useful tion the parameters in predicting and supply voltage are derived. The expressions SNM It are tbe effect of parameter changes on the stability as well simulawith

CMOS process. reduced

cell [8]. Cell-area usually However, in future

reductions

of 30-50

percent have

been obtained,

at the expense of a more complex will be significantly processes requiring memory

this area advantage scaled-down

as in optimizing method results

the design of SRAM by the analytic

cells. An easy-to-use SNM expressions.

is presented, predicted

the results of which are iir good agreement

supply voltage reduction to avoid hot-carrier degradation. The reason is that the SNM for R-load cells becomes much lower cient larger. order than noise for 6T cells at low supply margin the R-load voltage. then For suffiIn cells cell must the SNM be made

is further

concluded

that full-CMOS

cells are much more stable than R-load cells at

a low supply voltage.

This means that 6T cells have greater potential. to explain these statements of SRAM in this paper.

I.

INTRODUCTION

is studied cell design: the a graphical in Section simulation a Section firming

In Section II the cell stability cell area and the stability of the cell. The cell area determines about two-thirds of the total chip area. The cell stability determines the soft-error rate and the sensitivity of the memory to process tolerances and operating conditions. The two aspects are interdependent cell for improved area. There has been considerable years to understand yet cells. The basic cross-coupled appearance, attempts effort over the past several of flip-flop simple in the cell Fig. R-load a read power situation l(a) and (b) shows the II.
SRAM-CELL

is discussed with the aid of Analytical expresand 6T cells are derived easy-to-use in results thus conis developed

WO aspects are important

for SRAM

representation

of the SNM.

sions for the SNM method IV.

of both R-load for SNM

111 and Appendices In Section Good

A and B. An

investigation

since designing

V analytic

and simulation

stability

invariably

requires

a larger cell

are compared. are presented

agreement is demonstrated, of the analytic

the validity

results. The conclusions

in Section VI.

and model

the stability

cell is deceptively model

STABILITY

to analytically

stability have achieved only limited success [1]. Much of the published work has been concerned with the statistical and dynamic metastable properties [1][3]. of flip-flop The stability synchronizers in the region as expressed by the

circuit lines fact

diagrams precharged the most

of

the

cell and the 6T full-CMOS access and with supply voltage. because the bit This is in

cell, respectively,

during to the critical which com-

static-noise margin (SNM) [4] has also been investigated f& both resistor-load [5], [6] and full-CMOS [7] SRAM cells. puter This both view, The cells However, these studies have been limited to comsimulations; analytic work has not yet been reported. paper is concerned with the SNM of SRAM cells from an analytic as well as a simulation point of in the context of submicrometer MOS technology. results are useful in optimizing the design of SRAM as well as in predicting the effect of parameter (R-load) compared cells are widely SRAMS used in NMOS(6T) full-

the resistor

or p-channel

load elements

are now shunted by the n-channel access transistors, reduces the gain of the cell inverters. Both prised cell types can be represented of two inverters as shown by a flip-flop

in Fig. 2. The voltage

sources V. are static-noise sources. Static noise is dc disturbance such as offsets and mismatches due to processing and variations in operating conditions. The SNM of the flip-flop is defined as the maximum value of V. that can be tolerated by the flip-flop before changing states [4]. In this paper, only static-noise sources are taken into account. A SRAM cell should be designed such that under all conditions some SNM is reserved to cope with dynamic disturbances caused by a particles, crosstalk, voltage supply ripple, and thermal noise. A basic understanding of the SNM is obtained by drawing and mirroring the inverter characteristics and finding the maximum possible square between them. This 01987 IEEE

changes on the SNM. Resistor-load and CMOScell area when (mixed-MOS) owing to their smaller

to the six-transistor

Manuscript received April 2, 1987: revised June 4, 1987, The authors are with Philips Research Laboratories, 5600 .JA Eindhoven, The Netherlands. IEEE Log Number 8716261.

0018-9200/87/1000-0748$01.00

SEEVINCK et d.:

STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS

749

l~~

develop 10 Gfl clamped reduced

a noticeable in our

voltage drop across the resistor (about the output voltage is further with transistor is in the R-load resistor and role. that

case). Subsequently

by the access transistor and drops slope for VI. >1 V when the driver on. Note that the cell noise margin in the area where do not play the maximum the load any

access

turned

case is situated subthreshold When SNMc~ R-load When lose

I JI

current

significant it is clear

comparing > SNM~, cell.

squares,

in spite of the larger value of r for the will likewise does. In decrease cell will the

VD~ is decreased, the SNM data before the 6T cell

for both cases; however, its

it is clear that the R-load

addition.

(:)
Fig. 1. SRAM cells durink

R-load cell can only be used with a l~~ somewhat larger than 2V~ (say 3 V in the case of VT= 1 V) during access to avoid write-time problems.
and (b) 6T full

+m
Vn

re&dMa&ccss: (a) R-1oad,

III. A. Assumptions The. SNM Kirchhoff

ANALYTICAL

lIERIVATION

OF SNM

and AnaZytic Expressions can be found analytically by solving the

equations

and applying

one of the mathemati-

11

vn -

Fig.

2.

A flip-flop

comprised of two inverters. sources V, are included.

Static-noise

voltage

cally equivalent noise margin criteria [4]. For the cells of Fig. 1, we assume the right sides to be at level ZERO and the left sides at level ONE. This means that the cell circuit diagrams components can be reduced shown dotted to those shown only negligible in Fig. 4. The currents. In, Fig. are assumed to be nonconduct-

,, ,\

ing, or at most to conduct

I --f ul~-CMOS R -load

$~

4(a), we assume Ql, Q3, and Qq operate in the saturation region and Q ~ in the linear region. In Fig. 4(b), QI and Qd are assumed saturated while Q ~ and Q5 are in the linear region. These assumptions were verified by simulation as well as by back substitution. Explicit expressions for the SNM of the R-load cell dnd the 6T cell were obtained by using the basic MOS model
I

3 2

q, ..! II >.!J , . . \ . .

1 h

----------

-.

I 0123L5 V/~ resp,

equations mobility derivations the results

with

constant

threshold

voltages saturation.

(equal

for n-

Vou+ 11

[v]

and p-channel)

and neglecting

second-order

effects such as The detailed

Fig. 3. GraphicaJ representation of SNh4. Curves II have been mirrored with respect to a line passing through the origin at 450 from the horizontal

reduction

and velocity

are presented in Appendices are given below:

A and B, of which

is

a graphical

technique

of estimating

the SNM

[4], [5], [9].

It is illustrated with constant subthreshold tion,

in Fig. 3, using the most basic MOS model threshold voltage and a simple exponential current model. factor For for the purpose a square of illustraall are = 2.3 (/30 indicates transistor), dimensions

SNMR=~VT+r+l-r~:

r+i(VDD-VT)

(1)
2r+l VDD r+l
1[ ~+ r

we assume V~~ = 5 V, ~n./finP voltages in Fig.

the transconductance threshold as shown

VT

are 0.9 V, and transistor 1. The ratio

SNM6,

= VT

( k+l

of ~driv., to B.Cc.,, is an

important cell parameter called the cell ratio r. It determines the cell size as well as the cell stability. In this case, r is equal to 2 for the 6T cell and 3.5 for the R-load cell. From Fig. 3 we see that the R-load inverter it characteris-

k(r+l)

tic starts at V~~ when Vi. = O V; sharply as soon as the subthreshold

begins dropping current is able to

750

IEEE JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

SC-22, NO. 5, OCTOBER

1987

DO I 1 .,= R R ;, I 1

Qw)c.zr,a;
o x

-?1 I

.
al

Fig
1

5.

SNM

estimation

based on maximum coordinate system.

squares

in a 450 rotated

(b) Fig. 4. (a), (b) Circuit diagrams of SRAM cells when static-noise sources V. inserted. accessed, with

Third,

for particular of

values of r and q, SNM6T signs. Changing

will

be

independent will

V~~ variations. in either on with proper

q =

This is due to the coeffir or q

cients of V~~ in (2) having opposite where r = ratio= ~d/~a voltage then result of behavior through dence stability obtained lustrated q = BP/B. VT= threshold SNM6T

a positive or a negative depenrequired V~~. Thus, a particular respect choice to varying of r and V~~ can q. This be is ilr =1,

in Fig. 8 where two cases are shown with

v,=

~=~ J-()
r+l derivation where right-hand

VDD

v;

q = 3/8 and r =2, hand, for the R-load with decreasing V~~, Finally, VT. of (1) was exact; no simplifying apone increasing increasing In the case of (2), only i.e., assuming Q2 /Q4 region. around both

3/8, respectively. On the other cell the SNM will always decrease as can be seen in Fig. 7. SNMCT will will increase with that the SNM decrease with temperais

SNM ~ and

VT. It follows temperature

since VT decreases with

The

proximations approximation of the transfer ing point bottom

were needed. was required,

ture, and we have already concluded that the SNM independent of the absolute value of the ~ s.

local linearity its operat~ that the A

simulation in

curve of inverter

Qz is in the linear

See, for examIV. SNM

method Section II

ple, the full-CMOS

curve I in Fig. 3. It is apparent part is approximately Results expressions First, linear.

SIMULATION
based on

METHOD
the here. graphical To technique

B. Conclusions from Analytic When interesting studying general the SNM

described

is presented

estimate

values, we can draw some the SNM for both diagonals method conclusions.

a procedure which

is needed

that

finds

values

SNM for the for

of the maximum is quick

squares as shown in Fig. 3. A

and easy to use was developed

R-load and 6T cells depends only on threshold voltage, V~~, and /3 ratios, and not on the absolute value of the @s. Therefore, the increased /3 values associated with subrnicrometer processes will not by themselves lead to improved cell stability. Second, both SNM~ and SNM6T increase with r. SNMG~ remains larger than zero for all values of r > O; on the other hand, SNM R already becomes zero for r =1. To design the cells for maximum SNM, r = B~/~a must be maximized and also (in the case of 6T cells) q/r= fp/D~ by appropriate course, and proper choice of W/L ratios. This choice 1s, of constrained cell-write by the requirements operation. of small cell area

use together with a standard dc circuit simulator [7]. Fig. 5 shows a stylized version of Fig. 3 in two coordinate systems which are rotated 450 relative to each other. In the (u, u) system, subtraction of the u values of normal and mirrored inverter characteristics at given u yields curve A, which is a measure of the diagonals length. The maximum maximum Assume istics l?~(x), To find must and minimum squares. that the normal by of curve xt represent and mirrored the required charactery =

inverter

are defined FI

the functions of u and into

u,

y = Fl(x ) and the (x, y)

where the latter is the mirrored in terms be first transformed the

version of y = F2(x). coordinates The (u, o) system.

SEEVINCK

et U[.:

STATIC-NOISE

MARGIN

ANALYSIS

OF MOS SRAM CELLS

F]

.=

: 300 m .: 200

F, Fig.

= -1
?
500
- extended model z W o simp~e model

751

Loo

X theory

@q.(1) x

xx

r=

3,5

% = 100

qy -% 3L5 supp[y voltage

DD

v]

7.

SNM

of R-load

cell versus supply voltage.

> =
~ 600

1-1= (b)

Fig.

6.

Circuit

implementations

of (a) (4) and (b) (5).

: c .: z 300 --

7 4 extended o simple model

model

required

transformation

is
supply voltage

VDD

[1

(3a)
Fig. 8. SNM of full-CMOS cell versus supply voltage.

(3b)

Substitution

of (3) in y = Fl(.x)

gives

=u+fiF(++a
(u, u) system. now stituting The required coordinate transformation the same as (3) but with in y = Fz (x ) gives x and y exchanged;

(4)

For F;, first Fz is mirrored in the (x, y) system with respect to the u axis, and then it is transformed to the is SubFig. 9.

ok;

;
ratio

;
r

SNM

of R-load

cell versus Fd/&

atio

v=u+fiFz

1
U~ V .

(5) V.
ANALYTIC AND SIMULATION RESUI,TS

0;

Equations (4) and (5) represent the inverters comprising the SRAM flip-flop cell. They give u as an implicit function of u. Solutions can be found with a standard dc circuit simulator by translating the equations into circuits, using voltage-dependent as shown represented The in Fig. by U1 and voltage sources in a feedback loop solutions
Fk. b(a)

In Figs. 710, the SNMS

for the R-load

and 6T cells, as

predicted by (1) and (2), are plotted as a function of V~~ and r for VT = 0.9 V and q = 3/8. The plots extend down to V~~ = 3 V which is the approximate limit of validity of the analytic models. In the figures the analytically predicted SNM is compared with simulations which were performed according to the method outlined in Section IV. For the simulations, both the most basic MOS model and

6. The
V2 in

of (4)
and (b),

and

(5)

are

respectively.

difference

between

the

two

solutions,

UI V2, is

calculated by the simulator and is represented by curve A in Fig. 5. The absolute values of the maximum and minimum are the values of the diagonals of the maximum squares. Multiplying the smaller of the two by l/fi yields the SNM of the flip-flop.

a fully extended model with submicrometer transistor parameters (which includes subthreshold conduction, body effect, and mobility reduction) were used. The curves obtained for the 6T cell (Figs. 8 and 10) show a good correspondence between (2) and the simulations for both transistor models. Note that the SNM is

752

IEEE JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

SC-22,

NO. 5, OCTOBER 1987

,=

T = =
VI

x 800
700 600 500 Loo 300
12345
ratio r

design method The analytic saturation Further, much

of

SRAM

cells.

In and are

addition, easy in For to use good the

an has

SNM been

simulation developed. with cell, the

which simulation SNM in it

is quick results

agreement R-load some

.5 .

predictions. real has SNM transistors been values in to shown

velocity

causes that

deviation. cells at low have supply the avoid will

full-CMOS cells

better

than

R-load memory to

voltages.
exfended model

Therefore, voltage has

future be

processes, 3 V or less

when to cells full-CMOS values R-load cells.

simple

model eq (2)

supply hot-carrier suffer cells. ratio. reduced will be

reduced conventional

x theory:

degradation, a significant

R-load to SNM by

disadvantage to maintain the to

compared reasonable area required of full-CMOS

In

order supply close to

at cells

SNM

of full-CMOS

cell versus /3d/~<

voltage, or equal

that

approximately

constant

with

V~~ for a ratio

r =1.7.

For
APPENDIX DERIVATION OF SNM
the

smaller ratios the SNM increases with decreasing V~~ in contrast to the behavior with larger ratios. As discussed before, this behavior is predicted by (2). The curves obtained for the R-load cell (Figs. 7 and 9) show a complete fit between (1) and simulations with the simple model. with from This is expected the extended since the derivation is observed Further saturation model. of (1) for the which saturawas exact. However, simulation has shown was omitted a slope difference We
models

A CELL
4(a). The MOS

FOR R-LOAD
of Fig.

wish we

to will

analyze use are

circuit

ID=

;P(VGSVT)2
1 v~~ VT ~ (
DS )

(Al)

simulation ~~ = ~V~~ in the saturated (A2) First

that this is caused by velocity the simple model.

This velocity

tion effect reduces the effective ~ of the access transistor Q4 for large V~~ (see Fig. 4(a)). This reduces the influence of the high bit-line level on the low level in the cell, apparently increasing the SNM. In the case of the 6T cell of Fig. 4(b), this effect is compensated for by the mobility reduction of Q5 and the drain feedback effects of QI and Q4. As a general observation, we see that for decreasing v ~~, R-load supply cells need a significantly noise margins. the area advantage bigger ratio than 6T Hence, for reduced of R-load cells over

and linear

regions, respectively.

we must know the operating conditions of the transistors (whether saturated or linear). Clearly, Ql, Q3, and Qd are saturated. Suppose Qz is also saturated.
follows that

The voltage
for

gain of each inverter gain is therefore loop r >1, dent

must

is then J, for

where r = /3~/f?a. The loop r <1 the flip-flop until

be larger

equal to r. It

gain of
take

is insufficient

operation condition
than unity

[4]. For indepenand we

the cell will It follows

Q2 in equating Q2 and

be in a metastable unbalance
must linear drain the region. currents appropriate

cells to achieve similar voltage, full-CMOS

V. and will
the

Qz enters the linear

region.
When those of

that r
the Q4,

cells begins disappearing.

So far the noise-margin comparison has been done for the read-access situation. When the SRAM is in the retention-mode (switched-off access transistors and V~~ = 2 V) the differences by simulation parameters 600 better owing and between SNM ~ and SNMe~ are observed to be much less. For example, for the and SNMG~ are about These values are much respectively.

of

Q1

and

Q3 we

and find

using

models,

vGS3 vT=lF(vGsl-vT)
(V.SA - v,)= Now we write 2rV~s ( the Kirchhoff voltage equations: J&z -VT -~ v~sz 1

(A3) . (A4)

shown in Fig. 1, SNM~ 800 mV,

than the values obtained in the read-access case to the low-impedance access transistor loads being

V&l = Vn + VDS2
GS3 = VDD VGS2 V,

(A5) (A6) (A7)

switched off. However, the impedances in the K--load case are much higher compared to the full-CMOS case. This makes the R-load cell much more sensitive to ac disturbances and a particles. Substituting VI. Analytic CMOS expressions
CONCLUSIONS

v G~4= VDD VDS2. these into (A3) and (A4) yields +vDs2vT)

VDD VGS2vnvT=J(vn of R-load The and full-

(AS)

for the SNM

SRAM

cells have been derived.

expressions

(VDD D.2 - T)2= 2rv&2 -

are useful in predicting the effect of parameters and operating conditions on the SNM as well as in optimizing the

.s2 -T

- ~ .s72 .

(A9)

SEEVINCK

et al.: STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS

753

Eliminating

V&2

from

(A8)

and

(A9)

and

simplifying

results in a quadratic

equation (A1O)

av&2+ bvDs2 C= o +
with a=l+r+2r3/2 b=2{~(r+l) ~=vz
s

,(L)::::%, L----LJ
o v~
DD GS2
Fig, 11.

+r(fi-l)VT

-r(fi+l)V.

} 1

(All)

Linearizing

the transfer characteristic around its operating point

of the Q2 /Q4 P.

inverter

substitution where V, = VD~ VT. We now find marginal stability several easiest equivalent the SNM by applying a condition for to (A1O) and (All). We can choose from stability criteria [4]. For this case it is roots [4]. For requires of coinciding root, which (Al)

of the result. results in 2q

Equating

the drain
using

currents
the models

of

QI and Q5 and those of Q, and Q., and and (A2),

to use the condition

(A1O) this means a double

(V&.. VT)2 ; V&, v.s~ v, ; V,,s, = ) (

(VGS, - VT)2 = zrv~s, where the threshold

(Bl)

b2 = 4ac or b=2G since b <0. the SNM: Substituting (All) and solving for (A12) V. yields

&2 of

-V, the

-: p-

VirS2 and are

(Bz)

voltages

n-channel

devices are assumed equal and The required Kirchhoff

q = &/Ba,

r = Bd/ba.

voltage equations

V&l = V. + V&z v Ds~ = VDD Vn

(B3)

VGS2

(B4) (B5)

v ~-5 = VDD Vn VDS2 and Next analysis inversion, this means VDS2 > we determine is valid. i.e., we QI the range and of V~~ for wfich
with

this (A5) Substituting

(VDS2+K

Qg have to operate
VGS1 > VT. Together

in strong

v Gs~ = VDD VDS2. these into (Bl)

-V,)2=f(VDD

(B6)

require

and (B2) yields

-Vn-VGS2)

VT Vn .

(A14) the

When solving for VDsz from (A1O) and (All) under condition (A12) and substituting (A13), we find

.(K

-~,

Vn 2vDs,

+ VGS2)

(B7) (B8)

(~ (A15) with When next combining find the minimum valid: 2r4~
=

- VDS2)2 = zrV~s2

VGS2- VT-

~vDS2

V. = V~~ VT, as before. V&z or V~s2 from approximation these two equations to be to a lower a fourth-degree A simplifying equation which is too complex leading

(A14) and (A15) and simplifying

we is

Eliminating yields useful.

supply voltage for which this analysis

degree is therefore In Section III-A

needed. we noted in connection with Fig. 3 that

vDD min

VT.
) (A16)

{ 1+

(r+l)J~r3/2l

For example, when VT= 0.9 V t~s expression 3.2 V for r = 3.5 and 2.7 V for r =1. It follows is valid for VDD down to about 3 V.
APPENDIX DERIVATION OF SNM -B

reduces tO that (A13)

the transfer characteristic of the inverter which is ON has a fairly constant slope around its operating point. In Fig. 11 this part of the characteristic is shown, together with a straight-line approximation through point P at V~s2 = V, which is the approximate operating point when marginal noise is applied. The linear approximation is defined by the value of VDs2 and its slope at point is derived from (B8) by sulmtitUt@ (denoted by k) is determined p. Dsz at Point
&2 = V,. The

SIOPe

by first is then

differentiating at
GS2 = V,.

FOR FuLL-CMOS

CELL

(B8) with

respect to V&2 and then evaluating approximation

For the circuit of Fig. 4(b) we assume QI and Q4 to be saturated and Q2 and Q5 to operate in the linear region. These assumptions were checked by simulation and back

The required linear (see also Fig. 11)

expressed

as

v~S2 =

V(O kV&2

(B9)

754

IEEE JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

SC-22,

NO. 5, OCTOBER

1987

with

[8]

~=~ -J()
r+l
and

VT

(B1O)
[9]

T. Ohzone, M. Fukumoto, G. Fuse, A. Shinohara, S. Odanaka, and thin polycrystalline-silicon high-vafue M. Sasago, Ion-implanted resistors for high-density poly-load static RAM applications, IEEE Trans. Electron Devices, vol. ED-32, no. 9, pp. 1749-1756, Sept. 1985, C. F. Hill, Noise margin and noise immunity in logic circuits, Microelectron., vol. 1, pp. 16-21, Apr. 1968.

V(O kv, + =

l+r y.
(B12)

l+r+r/k V~~z from

Next

we

eliminate we obtain

(B7)

and

(B9).

After

simplifying,

Evert Seevinck (M75SM85) was born in Doetinchem, The Netherlands, on April 15, 1945, He was educated in South Africa, receiving the B. SC. degree in mathematics and physics in 1966, the B. SC. degree in electrical engineering in 1970, the B. SC. Hens. degree in electronic engineering (cum laude) in 1975, and the D. SC. degree in electronic engineering in 1981, all from the University of Pretoria, Pretoria, South Africa. His dissertation dealt with the anafysis and synthesis
of

X2

l+2k+Lk2 7

+2X

1kz4+A+V~-V, q

1
V,

tran.liqear
. . . . . . . . .

integrated

circuits.

+~A2=0 q (B13)

From 1970 to 1972 he was Nijmegen and Eindhoven, The design and application of analog to South Africa, where he joined

with Philips Gloeilampenfabrieken in Netherlands, where he worked on the integrated circuits. In 1973 he returned Philips in Johannesburg, continuing IC

where,

for simplicity,

we have defined

x= VDD Vn vG~2
A= As in Appendix criterion solve for V. to VO+(k+l)VnkV~~

(B14)

A, we now apply the double-root Next

the

stability

application work. From 1975 to 1981 he was employed at the Council for Scientific and Industrial Research (CSIR) in Pretoria, where he performed research and development on novel circuit techniques and custom ICS, In 1981 he remigrated to The Netherhmds, returning to Philips and working on analog IC design. In August 1983 he became Professor of Electrical Engineering at the University of Twente, Enschede, The Netherlands, In October 1985 he returned to Philips Research Laboratories, Eindhoven, The Netherlands, where he is now performing circuit research. He maintains a uart-time professorship at the University of Twente,

to (B13).
obtain

we substitute
SNM:

(B14),

and finally
Frans J. List was born in Hong Kong in 1958. He received the Ingenieur degree from Twente University, The Netherlands, in 1984. Since then he has been with the Philips Research Laboratones, Eindhoven, The Netherlands, where he worked on development and design of memories, Currently he is working on a l-Mbit SRAM design.

REFEREFJCES

[1] R.
[2]

[3] [4]

[5] [6] [7]

C. Jaeger and R. M. Fox, Phase plane analysis of the upset characteristics of CMOS RAM cells, in Proc, Uniu ,/Govt./Industry Microeiectron. Syrnp. (Auburn, AL), June 1985, pp. 183-187, H. J. M. Veendrick, The behavior of flip-flops used as synchronizers and prediction of their failure rate, IEEE J. So[id-State Circuits, vol. SC-15, no. 2? pp. 169-176, Apr. 1980. and A. Alblcki, Analysls of metastable operation in T. Kacprzak RS CMOS flip- ffops, IEEE J. Solid-State Circuits, vol. SC-22, no. 1, pp. 5764, Feb. 1987. J. Lohstroh, E, Seevinck,, and J, de Groot, Worst-case static noise margin criteria for logic clrcuils and their mathematical equivalence, IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 803807, Dec. 1983, K. Anami, M. Yoshimoto, H. Shinohara, Y. Hirata, and T. Nakano, Design considerations of a static memory cell, IEEE J, Solid-State Circuirs, vol. SC-18, no. 4, pp 414-418, Aug. 1983. B, Chappell, S. E. Schuster, and G, S. Sai-Hafasz, Stability and SER analysis of static RAM cells, IEEE J, Solid-State Circuits, vol. SC-20, no. 1, pp. 383-390, Feb. 1985, F. J. List, The static noise margin of SRAM cells, in Dig. Tech. Papers, ESSCIRC (Delft, The Netherlands), Sept. 1986, pp. 1618.

(M79) was born in Den Haag, The Netherlands, on July 11, 1946. He received the M. SC. degree in applied physics from the Technical University of Delft, Delft, The Netherlands, in 1970. He received the Ph.D. degree in electronic engineering from the Technicaf University of Eindhoven, Eindhoven, The Netherlands, in 1981, with a dissertation on integrated Schottky logic (ISL), In 1970 he joined the Philips Research Laboratories, fxndhoven, lhe Netherlands. Initially he worked on integrated magnetic memories and silicon imaging devices for optical memories. Then he was involved with bipolar logic circuitry and memories. In this area he worked on device concepts, modeling, and application of punch through devices, 12 L and ISL logic, ECL memories, and noise-margin analysis of digital circuits. He has coauthored over 30 papers and holds severaf patents in the area of microelectronics. In 1983 he became Department Head of the research group for Digital Circuitry and Memories in the Philips Research Laboratories. From 1985 to 1987 he was Department Head of the Philips Advanced Memory Design Centre. Since 1987 he has been Head of the Centraf Application Laboratory of the Philips Component Division Elcoma in Eindhoven, The Netherlands. His current interest is in consumer, industrial, and telecommunication applications of VLSI, Dr. Lohstroh became a member of the European Program Committee of the ISSCC in 1983. Since 1985 he has been chairman of this committee.

Jan Lohstroh