Protected Moda Tio Processor manning i proteded mode, following protecHon mechanisms reqdate acess ft» TO portt To addrox Space © TOPL Retd in Erg er ® To permission bit map of TSS Bo >| \ mi he anes acces to Dro powt The following inbucHOns Gin be exeuded only if CPL RTOPL ot eneute these jnstiucton #GP excepHon 1 genevaged. adh ae has oo On copy of ERAGS * So a UFR TOPL.TIO PeeMicsion bit map is Use fo modify effec ot TOPL on Dio senvitve mit acHons Allowing access fo some Tio powtz by lees privileged tusks TopL fretd can be changed by ram sunning af CPLEO. DO permesion bit map: Last 3! 1 o ot ap MTRIIRe Lat nuit be Fe, ae ee 7 ee exceed DRFFH 4 ee So eee eee af @ Vsed for permitting lieited accee fo Lilo posts by teas prvleged programs or tacks and fx tusts operating in virtua) - @0g6 mode. , ; ® Size of Lio permission bit map 2 its lo@Hon in TSS Re eons ode if CPL S uarrent ToPl, processor allows Tn recked YW ie By ne operations fo proceedthe processor cnecks *ne TO permision bit Mm to determine If anes a partudar To pot ‘is atlowed if O CPL 1s > TOPL in protected mode = @ Preceuor © operating ‘in virrudl 20g¢ mode . ZB Fach bit ‘in map corresponds 7° AN To pow byte address. 4, TRE contrat wit for Tio pox address agit in the Tio address space \s found of bir pairtion | of sixth byte In the bit map. 3 Before granting Tio acecs, he procasor tits all bits corverponding t» No port being addvecsed, Cfor a doubleword acess, YY adjacent & bit poat address are to be fered) DF bit ic eet qenesl exception is generated, SF bit t clear, Bo Operadton ‘se allowed to prxceed, 7 Tio map need not contain off To addremes, TIO addresses: wor present in bit map are hecuted at if the bis Ser fe |.snore ebeiie weed esbccac intel. adcress space. Logica! aaaress ‘orFar Pont Segment 1 Selector Ofaot a ee Figure 3-1. Segmentation and Paging [paging is not used, the linear address space of the processor is mapped directly into the phys- ical address space of processor. The physical address space is defined as the range of addresses that the processor can generate on its address bus Because multitasking computing systems commonly define a Linear eddress space much larget than it is economicaily feasibie to contain all at once in physica memory, some method of ‘virualizing” the linear address space is needed. This virwalization of the linear address space ‘s handled through the processor's paging mechanism, Paging supports a “virtual memory” environmen where a large linear address space is simulated with 2 small amount of physical memory (RAM and ROM) and some disk storage. When using Paging, each segment is divided into pages (ordinarily 4 KBytes each in size), which are stored tither in physical memory or on the disk. The operating system or executive maintains 2 page directory and a set of page tables to inn track ofthe pages. When a program (or task) attempts to access an address location in the linear address space, the processor uses the page directory