601

B. E. Vhth Semester Computer Science Engineering

Examination

ADVANCED COMPUTER ARCHITECTURE Paper-

CSE-401-C
Time allowed: 3 hours Maximum Marks: 100

Note: Attempt any five questions.

1. (a) What do you mean by virtual memory. Explain virtual
to real address mapping. 8
(b) Represent the decimal numbers
(i) (+123)
(ii) (- 4321)
(iii) 00000 as
(1) Packed decimal fonnat (2)
Unpacked decimal fonnat
Assume a length indicator is specified in each
instruction. Show length for each case. 12

2. (a) Discuss the design phaser during a project

design. 8
(b) What do you mean by code density ? What is the
effect of code density on a processor design. 12
7.
6.
3. (a) Explain the following : "
(i) System Calls
(ii) Execution dependencies.
(b) Assume for
.
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Total access time

cycles otherwise. Assume all other instructions take one (ii)
(iii) Mean total number of queued requests
cycle. What is the range of cycles per 100 HLL
instructions for the scientific workload ? What is Offered memory bandwidth
(iv)
expected no. of cycles. 6 Achieved memory bandwidth. 5x4=20
(v)
4. (a) "Branches create problems for pipelined processor." What do you mean by out of order execution? How it is
7. (a)
comment. 6 Discuss the following approaches to the dealt with? 10 Compare multiple issue and vector
(b) problem above said. (b) processors. 10
(i) Branch target capt!-:lre
8. Write short notes on :
(ii) Branch speed up. (a) runtime scheduling 10
1
(b) data consistency in shared memory multiprocessors
4
5. What ,0 you mean by two level cache? In a two level cache (one protocol) 10

systen we have
• L size 8kB with 4W set assoc, 16B lines and WTNWA.
• L. size 64 kB direct mapping, 64 B lines and CBWA.
S' 'ppose the miss in Ll and hit in L2 delay is 3 cycles al d
miss in LJ and miss in L2 delay is 10 cycles.
T::e processor makes 1.5 refrlI.
(ai What are the Ll & L2 miss rates?
(b) What is expected C.P.I.loss due to cache misses.
(el Will all lines in Ll always reside in L2 ?
Why? 20

8. Suppme two processors in a multiprocess system make a

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