@2010 Badri Computer Architecture Assembly II

198:211 ComputerArchitecture

Topics:
SystemI/O Buses

@2010 Badri Computer Architecture Assembly II

I/Oorinputandoutput
Inadditiontomemory,datatransferneedstooccur
betweenCPUandInputoutputdevices

Whenreadingfrommemory,abyteorseveralbytescanbe
transferredfrommemorytoregisterusing mov address, %eax or mov %eax, address

I/Odevicesalsoaresourcesordestinationsforbytesofdata I/Odevicescanbeviewedjustasmemory I/Odevicescanbeviewedasseparatefrommemory

@2010 Badri Computer Architecture Assembly II

I/Oprogramming
TherearetwowaysofaddressingI/Odevices MemorymappedI/O

TheaddressspaceisdividedbetweenmemoryandI/Odevices Higherorderaddressescanrefertodevice Lowerorderaddressescanrefertomemory mov %eax,addresswillfetchdatafromI/Oormemorybasedonthe address

E.g.,memoryrangetofrom0000toBFFF I/OrangefromC000toCFFF Deviceormemoryselectionbasedonaddressrange DifferentdevicescanhavedifferentaddressesintheI/Orange

@2010 Badri Computer Architecture Assembly II

MemorymappedI/O

Memory - I/O Bus

CPU

Main Memory

Disk

keyboard

Display

Network

Sendorreceivedatato/fromI/Odeviceisamemorytransferinstruction(mov)
withtherightaddress

MainmemorynotselectedwhenaddressisinI/Orange Adv

Uniformityofprogramming,samemov worksforI/Oandmemory Memoryaddressspaceisreduced

Dis adv
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@2010 Badri Computer Architecture Assembly II

I/OmappedI/O
MemoryandI/Odevicesusedistinctaddressspaces
IsolatedI/O

TwoseparateinstructionstoaddressI/Odevices Aseparatecodeorcontrolsignalbasedontheopcodewill
selectmemoryorI/O

INforinput OUTforoutput mov formemoryaccess Lessflexibleforprogramming

I/O MEM

FFFF

0000

00FF 0000

@2010 Badri Computer Architecture Assembly II

@2010 Badri Computer Architecture Assembly II

@2010 Badri Computer Architecture Assembly II

InterfacingwithI/O
Manydevices,withvaryingspeeds,complexity CPU/bussharedamongallperipheralsandmemory CPUshouldbeabletoselectadeviceandtransferdatato
thedevice

Interpretationofdatalefttoeachdevice Unlikememory,deviceneedtobereadybeforeinitiating
transfer

AllofthishandedbyI/Omodule

@2010 Badri Computer Architecture Assembly II

I/Omodule

Data lines

data status I/O logic

To device

Address Control

To device

CPUselectsdevicebymeansofaddress Datacorrespondstoinstructionsfordevice Eachdevicehasitsownsetofcommands Statusofdevicecanbecheckedbyreadingstatusregisters

@2010 Badri Computer Architecture Assembly II

Datatransferschemes
Therearetwoschemes Programmeddatatransfers
CPUtransfersdatafromI/Odevicesontoregisters Usefulforsmalldatatransfers

DirectmemoryaccessorDMA
DeviceorI/Omoduledirectlytransfersdatatomemory Usefulorlargeblocktransfers

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@2010 Badri Computer Architecture Assembly II

ProgrammedI/O

ProgrammedI/Ocanbefurtherclassifiedas Synchronoustransfer Asynchronoustransfer Interruptdriventransfer AlloftheabovecanbeusedtointerfacewithdifferentI/O devices

RequirespecialhardwarefeaturesintheCPU

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@2010 Badri Computer Architecture Assembly II

Synchronoustransfer

Simplestamongthree CPUandI/Ospeedmatch Transferabyte,word,ordoubleword Memorymapped

mov %eax ,2 Addressofdeviceportis2 I/Omapped mov $2,%edx out%eax,%edx SimilarlyforInputdevice, Memorymapped:mov 3,%eax or I/Omappedmov $3,%edx in%edx,%eax

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@2010 Badri Computer Architecture Assembly II

Asynchronoustransfer

I/Odevicesslower Instructdevicetobeready Waituntildeviceready Devicehasstatusflag/register Busywaiting WasteofCPUresources
READY No Request device to get ready

Yes

Issue data transfer command

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@2010 Badri Computer Architecture Assembly II

InterruptdrivenI/O
Processorneednotwaitforslow
device
Request device

Processorcontinueswithother
instructions

Fetch next instruction

Deviceinterruptsprocessor
whenready

Execute instruction

InterruptServiceRoutine
CPUtransferswordfromdevice
toregister
INT High No Yes

CPUwriteswordfromregister
tomemory
Call Interrupt Service routine

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@2010 Badri Computer Architecture Assembly II

DMAordirectmemory
Bulkdatatransfers Directdevicetomemory
transfer
Request DMA device

Fetch next instruction

Memorybusiscontention
betweenCPUandDMAunit
Execute instruction

DuringDMA EitherCPUisinholdstate
INT High No

Or
Yes

Cyclestealing CPUandDMAaccessin interleaved

Send R/W command Starting address, #bytes DMA interrupt

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@2010 Badri Computer Architecture Assembly II

Systembus

Memory - I/O Bus

CPU

Main Memory

Disk

keyboard

Display

Network

Abusisasharedcommunicationlink Containsaddressbus,databus Eachbusisasetofwires Buscantransferseveralbitsbetweendevicesconnectedbybus Buswidthdeterminesthenumberofbitstransferredinacycle

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@2010 Badri Computer Architecture Assembly II

Characteristicsofbus

Severaldevicescanbeconnected Singlebusforalldevices costsharing Added/removedwithoutaffectingothers I/Odevicescanbeconnectedtootherdevicesfollowingthe samebusstandard Disadvantages: Buscontention SpeedofI/Odevicesdeterminedbybusspeed Busspeeddeterminedbynumberofdevices Slowerdevicesimpactothers

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@2010 Badri Computer Architecture Assembly II

Busarchitecture

Master issues command Bus Master Data can go either way Bus Slave

Anyinteractionconsistsoftwosteps
1.Issuecommand2.transferdata

MasterInitiates
Issuescommand,startingaddress,#bytes

SlaveResponds
Sendsorreceivesdataaspercommandfrommaster

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@2010 Badri Computer Architecture Assembly II

Computerbuses

ModerncomputershaveseveralI/Odevices Varyingspeeds Asimplelinearbuswillnotsuffice Moderncomputershavehierarchicalbuses Busissplitintodifferentsegments CPUMemoryonebus CPUI/Odevicesanotherbus CPUcache anotherbus

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@2010 Badri Computer Architecture Assembly II

Backplanebus

System bus- Memory and I/O

SinglebusformemoryandI/O Cheap Slowandbusbecomesbottleneck

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@2010 Badri Computer Architecture Assembly II

Twobussystems
Processor-Memory bus

Bus Bridge I/O bus

Processormemorytrafficononebus I/Odevicesconnectedbyabridge Bridgecanconnecttodifferentkindsofbuses Trafficisisolated I/Obusescanprovidedexpansionslotsfordevices

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@2010 Badri Computer Architecture Assembly II

hierarchicalbussystems
Backside cache bus L2 cache Processor-Memory bus

Bus Bridge

I/O bus

I/O bus

Asinglebusbridgeconnectstotheprocessormemorybus OtherI/Obusesconnectedtothisbusbridge(tree) CPUmemoryseeslittlecontention Costly

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@2010 Badri Computer Architecture Assembly II

Examplesofbuses
ISAbus IndustryStandardbus
Oldtechnology 8Mhz,<1bytetransfer/cycle,busB/W5.3MB/sec

EISAbus ExtendedISA
Oldtechnology 8Mhz,4bytetransfer,busB/W32Mb/sec

PCIbus PeripheralComponentInterconnect
Speedsupto132MB/s Busspeedof33mhz,4Bytes/transfer PCIpopularizedPlugandPlay

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@2010 Badri Computer Architecture Assembly II

Examplesofbuses
PCIXextendedPCI
133MHz,8bytes/transfer,1064MB/secor1GB/sec Usedtoconnectgigabitethernet,highspeeddisks

SCSI(SmallComputerSystemInterface)
Capableofhandlinginternal/externalperipherals Speedanywherefrom80 640Mb/s ManytypesofSCSI
FastSCSI UltraSCSI UltrawideSCSI

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@2010 Badri Computer Architecture Assembly II

Parallelvs serial(pointtopoint)bus
Processor-Memory bus CPI/IO Bus Bridge I/O bus IO

IO

Parallelbus
Bussharedamongdevices Busarbitrationisslow Example:PCI,SCSI SerialI/O PointtopintlinksconnecteddirectlytoCPU Requireslotsofadditionalhighspeedhardware Examples:SATA,USB,firewire

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@2010 Badri Computer Architecture Assembly II

USB
1.0
plugandplay FullspeedUSBdevicessignalat
12Mb/s

Lowspeeddevicesusea
1.5Mb/ssubchannel.

Upto127deviceschained
together

2.0
datarateof480megabitsper
second

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@2010 Badri Computer Architecture Assembly II

Firewire (apple)

Highspeedserialport 400mbpstransferrate 30timesfasterthanUSB1.0 plugandplay

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@2010 Badri Computer Architecture Assembly II

IntelBus

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@2010 Badri Computer Architecture Assembly II

NorthbridgeandSouthbridgebus

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http://www.testbench.in/pcie_sys_2.PNG

http://www.yourdictionary.com/images/computer/CHIPSET.GIF

@2010 Badri Computer Architecture Assembly II

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