Which is 0 100000000 Question 1: (a) Perform the following arithmetic operations using binary signed 2s complement notation for

integers. You may assume that the maximum size of integers is of 10 bits including the sign bit. (Please note that the numbers given here are in decimal notation) i) Add 498 and 260 2s complement of -498 Sign value 10 bit Binary value = 1 111110010 Since sign bit is 1 complement value bits and add 1 -> Complement of 11110010 is 000001101 Adding 1we get value bits 000001110 Use sign bit as it is now we get 1 000001110 which is 2s complement of -498 2s complement of 260 Sign value 10 bit Binary value = 0 100000100 Since the sign bit is 0 2s complement is just binary value Which is 0 100000100 Adding -498 & 260 (binary addition) 1 000001110 0 100000100 1 100010010 Since the sign bit of result is 1 complement value bits ( 1 011101101 ) & add 1 We get 1 011101110 Converting value bits to decimal we get - 238 ii) Subtract 456 from 56 2s complement of 256 10 bit Binary value = Sign 0 value 100000000 iii) Add 256 and 255 Ans:
*** Sumi leave some space like previous answer ***

2s complement of 255 10 bit Binary value = Sign 0 value 011111111

Since the sign bit is 0 2s complement is just binary value Which is 0 011111111 Adding 256 and 255 (perform simple binary addition) 1 100000000 0 011111111 1 111111111 Converting value bits to decimal we get 511

(b) Convert the hexadecimal number: FA BB C9 into binary, octal and decimal.
Convert hexadecimal to Binary Convert each digit to 4 bit binary F = 15 = 1111 A = 10 = 1010 B = 11 = 1011 B = 11 = 1011 C = 12 = 1100 9 = 1001 (FA BB C9)16= (111110101011101111001001)2 Convert hexadecimal to Octal Break sequence to 3 bits i.e 111 110 101 011 101 111 001 001 converting each 3 bit block to decimal we get 7 6 5 3 5 7 1 1 is octal representation (FA BB C9)16=(76535711)8 Convert hexadecimal to Decimal

Since the sign bit is 0 2s complement is just binary value

FA BB C9 = 9 x 160 + 13 x 161 + 12 x 162 + 12 x 163 + 10 x 164 + 15 x 165 (FA BB C9)16=(16436441)10

(c) Convert the following string into equivalent ASCII code Copyright 2001 2011. Include ASCII code of spaces between words in the resultant ASCII. Are these codes same as that used in Unicode?

K map for O1

ascii code of string is: 67 111 112 121 114 105 103 104 116 NULL NULL NULL 50 48 48 49 NULL 45 NULL 50 48 49 49 unicode is: 0043 006F 0070 0079 0072 0069 0067 0068 0074 0020 00A9 0020 0032 0030 0030 0031 0020 002D 0020 0032 0030 0031 0031 So, both are different
(d) Design a logic circuit that accepts a four digit binary input and creates an odd parity bit, a sign check bit and a more than two zero value test bit. The odd parity bit is created for the four bit data. The sign bit is set to 1 if the left most bit of the data is 1. Zero value bit is set to 1 if three of the input bits are zero. Draw the truth table and use K-map to design the Boolean expressions for each of the output bits. Draw the resulting circuit diagram using AND OR NOT gates. Truth table A B C D O1(odd O2 (sign check) O3 (more than 2 parity) Zeros) 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 0 1 1 0 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 0 1 0

AB CD 00 01 11 10

00

01 x

11

10 x

x x x

x x x

K Map for output 2 (O2) AB CD 00 01 11 10

00

01

11 x x x x

10 x x x x

From map O2= A

K map for O3 AB CD 00 01 11 10 x 00 x x 01 x 11 10 x

(e ) A sequential circuit has two D flip flops A and B, two inputs x and y and one output z. Flip flops input equations and the circuit output are as follows: DA = x B DB = y A + x A z=A+B (i) Draw the circuit diagram for the above. (ii) Tabulate the state table for the flip flops.

(i)

(ii) Tabulate the state table for the flip flops. Present State Next State x y A B A B 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1

(f) Design a floating point representation of 32 bits closer to IEEE 754 format except that the exponent of the representation should be of 4 bits only. You may assume that the mantissa is in normalised form; the exponent bias of 7; and one bit is used for the sign bit. Represent the number (89.125) 10 using this format . ****Sumi leave one page for answer **** Question 2: (a) A RAM has a capacity of 64 K 64. (i) How many data input and data output lines does this RAM need to have? 64, since the word size is 64. (ii) How many address lines will be needed for this RAM? 64K = 64 1024 = 65536 words. Hence, there are 65536 memory addresses. Since 65536 = 216 it requires 16 bits address code to specify one of 65536 addresses. (b) Consider a RAM of 256 words with a word size of 16 bits. Assume that this memory have a cache memory of 8 Blocks with block size of 32 bits. For the given memory and Cache in the statements as above, draw a diagram to show the address mapping of RAM and Cache, if direct memory to cache mapping scheme is used.

(c) You want to read a file from a disk. Explain how the I/O will be performed if (i) Interrupt Driven Input/ Output Scheme is used. With interrupt driven I/O, when the interface determines that the device is ready for data transfer, it generates an interrupt request to the computer. Upon detecting the external interrupt signal, the processor stops the task it is processing, branches to a service program to process the I/O transfer, and then returns to the task it was originally performing which results in the waiting time by the processor being reduced. The interrupt-driven I/O mechanism for transferring a block of data is shown in Figure. Please note that after issuing a read command (for input) the CPU goes off to do other useful work while I/O interface proceeds to read data from the associated device. On the completion of an instruction cycle, the CPU checks for interrupts (which will occur when data is in data register of I/O interface and it now needs CPUs attention). Now CPU saves the important register and processor status of the executing program in a stack and requests the I/O device to provide its data, which is placed on the data bus by the I/O device. After taking the required action with the data, the CPU can go back to the program it was executing before the interrupt. Interrupt- Processing The occurrence of an interrupt fires a numbers of events, both in the processor hardware and software.

9. The final step is to restore the values of PSW and PC from the stack. As a result, the instruction to be executed will be from the previously interrupted program.

When an I/O device completes an I/O operation, the following sequence of hardware events occurs: 1. The device issues an interrupt signal to the processor. 2. The processor finishes execution of the current instruction before responding to the interrupt. 3. The processor tests for the interrupts and sends an acknowledgement signal to the device that issued the interrupt. 4. The minimum information required to be stored for the task being currently executed, before the CPU starts executing the interrupt routine (using its registers) are: (a) The status of the processor, which is contained in the register called program status word (PSW), and (b) The location of the next instruction to be executed, of the currently executing program, which is contained in the program counter (PC). 5. The processor now loads the PC with the entry location of the interrupthandling program that will respond to this interrupting condition. Once the PC has been loaded, the processor proceeds to execute the next instruction, that is the next instruction cycle, which begins with an instruction fetch. Because the instruction fetch is determined by the contents of the PC, the result is that control is transferred to the interrupt-handler program. The execution results in the following operations: 6. The PC & PSW relating to the interrupted program have already been saved on the system stack. In addition, the contents of the processor registers are also needed to be saved on the stack that are used by the called Interrupt Servicing Routine because these registers may be modified by the interrupt-handler. Figure shows a simple example. Here a user program is interrupted after the instruction at location N. The contents of all of the registers plus the address of the next instruction (N+1) are pushed on to the stack. 7. The interrupt handler next processes the interrupt. This includes determining of the event that caused the interrupt and also the status information relating to the I/O operation. 8. When interrupt processing is complete, the saved register values are retrieved from the stack and restored to the registers, which are shown in Figure .

 The starting location on the memory where the information will be read or written to be communicated on the data lines and is stored by the DMA interface in its address register. The number of words to be read or written is communicated on the data lines and is stored in the data count register.

(ii) Direct Memory Access is used. In both interrupt-driven and programmed I/O, the processor is busy with executing input/output instructions and the I/O transfer rate is limited by the speed with which the processor can test and service a device. What about a technique that requires minimal intervention of the CPU for input/output? These two types of drawbacks can be overcome with a more efficient technique known as DMA, which acts as if it has taken over control from the processor. Hence, the question is: why do we use DMA interface? It is used primarily when a large amount of data is to be transferred from the I/O device to the Memory. DMA Function Although the CPU intervention in DMA is minimised, yet it must use the path between interfaces that is the system bus. Thus, DMA involves an additional interface on the system bus. A technique called cycle stealing allows the DMA interface to transfer one data word at a time, after which it must return control of the bus to the processor. The processor merely delays its operation for one memory cycle to allow the directly memory I/O transfer to steal one memory cycle. When an I/O is requested, the processor issues a command to the DMA interface by sending to the DMA interface the following information (Figure 10): Which operations (read or write) to be performed, using the read or write control lines. The address of I/O devices, which is to be used, communicated on the data lines.

The DMA interface transfers the entire block of data, one word at a time, directly to or from memory, without going through the processor. When the transfer is complete, the DMA interface sends an interrupt signal to the processor. Thus, in DMA the processor involvement can be restricted at the beginning and end of the transfer, which can be shown as in the figure above. But the question is when should the DMA take control of the bus? For this we will recall the phenomenon of execution of an instruction by the processor. Figure 11 below shows the five cycles for an instruction execution. The Figure also shows the five points where a DMA request can be responded to and a point where the interrupt request can be responded to. Please note that an interrupt request is acknowledged only at one point of an instruction cycle, and that is at the interrupt cycle.

clusters - the basic unit of logical storage on a disk at the operating system level and the physical location of data in terms of cylinders, tracks and sectors - the form of addressing used by the drive's hardware controller. The FAT contains an entry for every file stored on the volume that contains the address of the file's starting cluster. Each cluster contains a pointer to the next cluster in the file, or an end-of-file indicator at (0xFFFF), which indicates that this cluster is the end of the file. The diagram shows three files: File1.txt uses three clusters, File2.txt is a fragmented file that requires three clusters and File3.txt fits in one cluster. In each case, the file allocation table entry points to the first cluster of the file

(f) Define each of the following term. Explain the main purpose / use / advantage of the term.(Word Limit for answer of each part is 50 words ONLY) (i) DIMM Dual Inline Memory Module or DIMM is a series of Random Access Memory (RAM) chips mounted on a small printed circuit board. The entire circuit collectively forms a memory module. DIMMs are commonly used in personal computers, servers and high-end workstations. The DIMM makes physical contact with the data bus of the computer through teeth like connectors that fit into a socket on the mother board. DIMMs use a 64-bit data path, since processors used in personal computers including the Intel Pentium have a 64-bit data width. (ii) LCD monitors LIQUID CRYSTAL DISPLAYS (LCD) LCDs are the screens of choice for portable computers and lightweight screens. They consume very little electricity and have advanced technologically to quite good resolutions and colour support. They were developed by the company RCA in the 1960s. LCDs function simply by blocking available light so as to render display patterns.

(d) Find the average disk access time that reads or writes a 512 byte sector. Assume that the disk rotates at 12000 rpm; each track of the disk has 100 sectors and data transfer rate of the disk is 100 MB/second. (Please calculate data transfer time for the disk in addition to the seek time and latency time). Also find out what is meant by the controller overhead in the context of disk access time. **** Sumi leave one page **** (e) What is the purpose of FAT? Explain. (Word limit for the answer is 200 words ONLY) The FAT file system was first introduced in the days of MS-DOS way back in 1981. The purpose of the File Allocation Table is to provide the mapping between

(iii) Core of a processor The "core" in a processor is the microprocessor inside of the CPU (Central Processing Unit). It is the part of the processor that actually performs the reading and executing of instructions. For example, if we have a Dual Core CPU then we have 2 microprocessors inside of the CPU, this allows us to do two things at once, as a microprocessor can only do one thing at a time the only exception to this is MultiThreading which allows one core to do the work of multiple cores, but its not as fast as having multiple cores. (iv) SATA Serial ATA (SATA or Serial Advanced Technology Attachment) is a computer bus interface for connecting host bus adapters to mass storage devices such as hard disk drives and optical drives. Serial ATA was designed to replace the older ATA (AT Attachment) standard (also known as EIDE), offering several advantages over the older parallel ATA (PATA) interface: reduced cable-bulk and cost (7 conductors versus 40), native hot swapping, faster data transfer through higher signaling rates, and more efficient transfer through an (optional) I/O queuing protocol. SATA host-adapters and devices communicate via a high-speed serial cable over two pairs of conductors. In contrast, parallel ATA (the redesignation for the legacy ATA specifications) used a 16-bit wide data bus with many additional support and control signals, all operating at much lower frequency. To ensure backward compatibility with legacy ATA software and applications, SATA uses the same basic ATA and ATAPI command-set as legacy ATA devices. (v) RAID level 5 This level belongs to independent access category. Its main features are: a) Employs independent access as that of level 4 and distributes the parity strips across all disks. b) The distribution of parity strips across all drives avoids the potential input/output bottleneck found in level 4. I/O Request Rate Read is Excellent while write is fair Data Transfer Rate Read is fair while write is poor It is used in High request rate read intensive, data lookup applications (vi) Zone Bit Recording (ZBR) in the context of disks Zone Bit Recording (ZBR) is used by disk drives to store more sectors per track on outer tracks than on inner tracks. It is also called Zone Constant Angular Velocity (Zone CAV or Z-CAV or ZCAV). On a disk consisting of concentric tracks, the physical track length may or may not be increased with distance from the center hub. Therefore, holding storage density constant, the track storage capacity likewise increases with distance from the center. ZBR is a compromise between CLV (which packs the most bits onto a disk, but has very slow seek times) and CAV

(which has faster seek times, but stores fewer bits on a disk). Hard disk controllers implement ZBR by varying the rate at which it reads and writes - faster on outer tracks. Some other ZBR drives, such as the 3.5" floppy drives in the Apple IIGS and older Macintosh computers, spin the medium faster when reading or writing inner tracks. One side effect of ZBR is the raw data transfer rate of the disk when reading the outside tracks is much higher -- in some disks, about double -- the data transfer rate of the same disk when reading the "inner" (closest to the hub) tracks. Question 3: (a) Assume that a new programming language has been developed that have an extensive use of data and instruction arrays. Such a programming language requires efficient handling of arrays. This language supports call by reference as arrays are being passed by reference. The language does not support recursion. You have been assigned the task to design the addressing modes for a machine that supports this new programming language. List four addressing mode that must be supported by such a machine. Give justification of the selection of each of the addressing modes. Types of Addressing Modes Each instruction of a computer specifies an operation on certain data. There are various ways of specifying address of the data to be operated on. These different ways of specifying data are called the addressing modes. The most common addressing modes are: Immediate addressing mode Direct addressing mode Indirect addressing mode Register addressing mode Register indirect addressing mode Displacement addressing mode Stack addressing mode To specify the addressing mode of an instruction several methods are used. Most often used are : a) Different operands will use different addressing modes. b) One or more bits in the instruction format can be used as mode field. The value of the mode field determines which addressing mode is to be used. The effective address will be either main memory address of a register. Immediate Addressing: This is the simplest form of addressing. Here, the operand is given in the instruction itself. This mode is used to define a constant or set initial values of variables. The advantage of this mode is that no memory reference other than instruction fetch is required to obtain operand. The disadvantage is that the size of the number is limited to the size of the address field, which most instruction sets is small compared to word length. INSTRUCTION

OPERAND Direct Addressing: In direct addressing mode, effective address of the operand is given in the address field of the instruction. It requires one memory reference to read the operand from the given location and provides only a limited address space. Length of the address field is usually less than the word length. Ex : Move P, Ro, Add Q, Ro P and Q are the address of operand. Indirect Addressing: Indirect addressing mode, the address field of the instruction refers to the address of a word in memory, which in turn contains the full length address of the operand. The advantage of this mode is that for the word length of N, an address space of 2N can be addressed. He disadvantage is that instruction execution requires two memory reference to fetch the operand Multilevel or cascaded indirect addressing can also be used. Register Addressing: Register addressing mode is similar to direct addressing. The only difference is that the address field of the instruction refers to a register rather than a memory location 3 or 4 bits are used as address field to reference 8 to 16 generate purpose registers. The advantages of register addressing are Small address field is needed in the instruction. Register Indirect Addressing: This mode is similar to indirect addressing. The address field of the instruction refers to a register. The register contains the effective address of the operand. This mode uses one memory reference to obtain the operand. The address space is limited to the width of the registers available to store the effective address. Displacement Addressing: In displacement addressing mode there are 3 types of addressing mode. They are : 1) Relative addressing 2) Base register addressing 3) Indexing addressing. This is a combination of direct addressing and register indirect addressing. The value contained in one address field. A is used directly and the other address refers to a register whose contents are added to A to produce the effective address. Stack Addressing: Stack is a linear array of locations referred to as last-in first out queue. The stack is a reserved block of location, appended or deleted only at the top of

the stack. Stack pointer is a register which stores the address of top of stack location. This mode of addressing is also known as implicit addressing.
(b) Assume a hypothetical machine that has only PC, AC, MAR, IR, DR and Flag registers. (you may assume the roles of these registers same as that are defined in general for a von Neumann machine) The instruction of this machine can take only one direct operand. It has an instruction: INC X; // increments the operand stored at location X. The result of increment is left in AC. Show the steps for fetch and execute operations of the instructions using suitable micro-operations. Make and state suitable assumptions, if any. Program counter or PC: The program counter, or PC (also called the instruction pointer to a seminal Intel instruction set, such as the 8080 or 4004, or instruction address register, or just part of the instruction sequencer in some computers) is a processor register that indicates where the computer is in its instruction sequence. Depending on the details of the particular computer, the PC holds either the address of the instruction being executed, or the address of the next instruction to be executed. In most processors, the program counter is incremented automatically after fetching a program instruction, so that instructions are normally retrieved sequentially from memory, with certain instructions, such as branches, jumps and subroutine calls and returns, interrupting the sequence by placing a new value in the program counter. Such jump instructions allow a new address to be chosen as the start of the next part of the flow of instructions from the memory. They allow new values to be loaded (written) into the program counter register. A subroutine call is achieved simply by reading the old contents of the program counter, before they are overwritten by a new value, and saving them somewhere in memory or in another register. A subroutine return is then achieved by writing the saved value back in to the program counter again. Accumulator (AC): In a computer's central processing unit (CPU), an accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation (addition, multiplication, shift, etc.) to main memory, perhaps only to be read right back again for use in the next operation. Access to main memory is slower than access to a register like the accumulator because the technology used for the large main memory is slower (but cheaper) than that used for a register. The canonical example for accumulator use is summing a list of numbers. The accumulator is initially set to zero, then each number in turn is added to the value in the accumulator. Only when all numbers have been added

is the result held in the accumulator written to main memory or to another, nonaccumulator, CPU register. An accumulator machine, also called a 1-operand machine, or a CPU with accumulator-based architecture, is a kind of CPU in whichalthough it may have several registersthe CPU always stores the results of most calculations in one special registertypically called "the" accumulator of that CPU. Historically almost all early computers were accumulator machines; and many microcontrollers still popular as of 2010 (such as the 68HC12, the PIC micro, the 8051 and several others) are basically accumulator machines. Modern CPUs are typically 2-operand or 3-operand machinesthe additional operands specify which one of many general purpose registers (also called "general purpose accumulators"[1]) are used as the source and destination for calculations. These CPUs are not considered "accumulator machines". The characteristic which distinguishes one register as being the accumulator of a computer architecture is that the accumulator (if the architecture were to have one) would be used as an implicit operand for arithmetic instructions. For instance, a CPU might have an instruction like:
ADD memaddress

This instruction would add the value read from the memory location at memaddress to the value from the accumulator, placing the result in the accumulator. The accumulator is not identified in the instruction by a register number; it is implicit in the instruction and no other register can be specified in the instruction. Some architectures use a particular register as an accumulator in some instructions, but other instructions use register numbers for explicit operand specification. MAR: The Memory Address Register (MAR) is a CPU register that either stores the memory address from which data will be fetched to the CPU or the address to which data will be sent and stored. In other words, MAR holds the memory location of data that needs to be accessed. When reading from memory, data addressed by MAR is fed into the MDR (memory data register) and then used by the CPU. When writing to memory, the CPU writes data from MDR to the memory location whose address is stored in MAR. The Memory Address Register is half of a minimal interface between a microprogram and computer storage. The other half is a memory data register. Far more complex memory interfaces exist, but this is the least that can work. IR (Instruction register): Instruction register is the part of a CPU's control unit that stores the instruction currently being executed or decoded. In simple processors each instruction to be executed is loaded into the instruction register which holds it

while it is decoded, prepared and ultimately executed, which can take several steps. More complicated processors use a pipeline of instruction registers where each stage of the pipeline does part of the decoding, preparation or execution and then passes it to the next stage for its step. Modern processors can even do some of the steps of out of order as decoding on several instructions is done in parallel. Decoding the opcode in the instruction register includes determining the instruction, determining where its operands are in memory, retrieving the operands from memory, allocating processor resources to execute the command (in superscalar processors), etc DR: Data registers are used to hold numeric values such as integer and floating-point values. In some older and low end CPUs, a special data register, known as the accumulator, is used implicitly for many operations. Flag Registers: The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the processor. This register is 16-bits wide. Its successors, the EFLAGS and RFLAGS registers are 32-bits and 64-bits wide, respectively. The wider registers retain compatibility with their smaller predecessors Steps for instruction execution Step 1: The first step of instruction execution is to fetch the instruction that is to be executed. To do so we require: Address of the instruction to be fetched. Normally Program counter (PC) register stores this information. Now this address is converted to physical machine address and put on address bus with the help of a buffer register sometimes called Memory Address Register (MAR). This, coupled with a request from control unit for reading, fetches the instruction on the data bus, and transfers the instruction to Instruction Register (IR). On completion of fetch PC is incremented to point to the next instruction. In Step 2: The IR is decoded; let us assume that Instruction Register contains an instruction. ADD Memory location B with general purpose register R1 and store result in R1, then control unit will first instruct to: Get the data of memory location B to buffer register for data (DR) using buffer address register (MAR) by issuing Memory read operation. This data may be stored in a general purpose register, if so needed let us say R2 Now, ALU will perform addition of R1 & R2 under the command of control unit and the result will be put back in R1. The status of ALU operation for example result in zero/non zero, overflow/no overflow etc. is recorded in the status register. Similarly, the other instructions are fetched and executed using ALU and register under the control of the Control Unit. The number and the nature of registers is a key factor that differentiates among computers. For example, Intel Pentium has about 32 registers. Some of these

registers are special registers and others are general-purpose registers. Some of the basic registers in a machine are: All von-Neumann machines have a program counter (PC) (or instruction counter IC), which is a register that contains the address of the next instruction to be executed. Most computers use special registers to hold the instruction(s) currently being executed. They are called instruction register (IR). There are a number of general-purpose registers. With these three kinds of registers, a computer would be able to execute programs. Other types of registers: Memory-address register (MAR) holds the address of next memory operation (load or store). Memory-buffer register (MBR) holds the content of memory operation (load or store). Processor status bits indicate the current status of the processor. Sometimes it is combined with the other processor status bits and is called the program status word (PSW). A few factors to consider when choosing the number of registers in a CPU are: CPU can access registers faster then it can access main memory. For addressing a register, depending on the number of addressable registers a few bit addresses is needed in an instruction. These address bits are definetly quite less in comparison to a memory address. For example, for addressing 256 registers you just need 8 bits, whereas, the common memory size of 1MB requires 20 address bits, a difference of 60%. Compilers tend to use a small number of registers because large numbers of registers are very difficult to use effectively. A general good number of registers is 32 in a general machine. Registers are more expensive than memory but far less in number. From a users point of view the register set can be classified under two basic categories. Programmer Visible Registers: These registers can be used by machine or assembly language programmers to minimize the references to main memory. Status Control and Registers: These registers cannot be used by the programmers but are used to control the CPU or the execution of a program.