Ng i th c hi n : Nguy n Nam Phong Nhm : BKFET

BI 1: M

y Gi i thi u v h V K AVR. y Cc php ton c b n. y Th c hi n ci

t cc ph n m m lin quan. y Lm quen v i Atmega16.

Gi i thi u h V K AVR
Xu t x :
y Do hng Atmel s n xu t. y L 1 trong 3 dng vi i u khi n thng d ng nh t trn th tr ng hi n nay. y C nhi u tnh n ng v

t tr i.

Gi i thi u h V K AVR
c i m chung:
y L dng vi i u khi n kh m nh.
y C c u trc RISC. y C nhi u thanh ghi i u khi n. y C nhi u lo i b nh : Flash , EEPROM , SRAM. y Cc chn vo ra c kh n ng ch u dng l n : 20mA. y C nhi u ch standby

ti t ki m n ng l ng

ng: idle, power- down,

y C kh n ng ho t

nhi u t n s .

Gi i thi u h V K AVR
c i m chung:
y C nhi u ng t trong v ng t ngoi. y Tch h p nhi u ch c n ng : PWM , timer/counter , ADC vv . y Tch h p nhi u chu n giao ti p ngo i vi : UART, USART , TWI , SPI . y D i i n p lm vi c r ng. y Ho t ng n nh ng tin c y. y Ch ng lo i phong ph ph h p v i nhi u m c ch s d ng.

Gi i thi u h V K AVR
M t vi dng v k AVR:
y Dng ATtiny : ATtiny 11 , ATtiny 12 y Dng AT90 : AT90C8515 , AT90S2313 , AT90S8515 y Dng Mega : ATmega8 , ATmega16 , ATmega32 , ATmega128

Cc php ton c b n
Php ton AND ( & ) :
y Cu l nh trong C : Y = A & B ;

A 0 0 1 1

B 0 1 0 1

Y 0 0 0 1

Cc php ton c b n
Php ton OR ( | ) :
y Cu l nh trong C : Y = A | B ;

A 0 0 1 1

B 0 1 0 1

Y 0 1 1 1

Cc php ton c b n
Php ton NOT ( ~ ) :
y Cu l nh trong C : Y = ~A ;

A 0 1

Y 1 0

Cc php ton c b n
Php ton d ch bt ( << , >> ) :
y Cu l nh trong C :

Y = A << B ; // Y = A* 2^B Y = A >> B ; // Y = A/ 2^B

Th c hi n ci t h ng d n s d ng cc ph n m m h tr

Lm quen v i Atmega16

BI 2: Ch c n ng I/O v Ng t ngoi
y Thi t l p ch c n ng I/O cho V K y Thi t l p ch c n ng s d ng ng t ngoi

Ch c n ng I/O
M t :
y Atmega16 c 32 chn vo/ra (I/O) c th l p trnh c y PORTA (c ng A): 8 chn : PA0 PA7 . y PORTB (c ng B): 8 chn : PB0 PB7 . y PORTC (c ng C): 8 chn : PC0 PC7. y PORTD (c ng D): 8 chn : PD0 PD7. y Cc chn ny c i u khi n thng qua cc thanh ghi t ng ng v i cc c ng c a chng.

Ch c n ng I/O
Cc thanh ghi i u khi n ch c n ng I/O:
y V i PORTA (C ng A ) Cc c ng khc t

ng t :
c ghi c.

y Thanh ghi PORTA: Thanh ghi d li u c a cc PORT .

Th c hi n set bit : PORTA |= ( 1<<PAn )

Gi i thch cu l nh : y Php ton |= : A |= B ; ~ A = A | B ; T ng t : A &= B; ~ A = A&B; A += B; ~ A = A+B;

y PAn (n : 0-7 ):

Trong th vi n < avr/io.h > cc chn PA0 n PA7 c nh ngh a t ng ng v i cc s nguyn t 0 7. y V y ta c : PORTA |= (1<<PA2); => PORTA = PORTA | (1*2^2) ;

1*2^2 = 4 => 0000 0100 PORTA = PORTA | 0b00000100 ;

PORTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 0 0 0 0 0 0 0 0 0 0 0

PORTA
PA7 PA6 PA5 0 0 0 0 0 1 0 0

0 0 1 0 0

PA4 PA3 PA2 PA1 PA0

T ng t khi ta mu n t 1 bit v 0: PORTA &= ~ ( 1 << PA2 ); => PORTA &= ~ 0b 0000 0100 ; => PORTA = PORTA & 0b 1111 1011 ;

PORTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 1 1 1 1 1 1 1 1 1 1

PORTA
PA7 PA6 1 1 1 1 1 0 1 1

&

1 1 1 0 1 1

PA5 PA4 PA3 PA2 PA1 PA0

y V y ta c cng th c t ng qut cho vi c set bt c a 1 thanh ghi nh sau

Set ln 1 : Tn_thanh_ghi | = (1 << Tn_bit ); PORTB |= (1<<Pb2); y Clear v 0 : Tn_thanh_ghi &= ~ (1 << Tn_bit ); PORTB&=~(1<<Pb3);
y

Ch c n ng I/O
Cc thanh ghi i u khi n ch c n ng I/O:
y V i PORTA (C ng A ): y Thanh ghi DDRA : Thanh ghi ch h

ng vo/ra .

c ghi

Th c hi n set bit : DDRA |= ( 1<< DDAn ); // v i chn t ng ng l u ra. DDRA &= ~( 1<< DDAn ); // v i chn t ng ng l u vo.

Ch c n ng I/O
Cc thanh ghi i u khi n ch c n ng I/O:
y V i PORTA (C ng A ): y Thanh ghi PINA : Thanh ghi ch dng cho m c ch tr u vo. Ch c c.

c cc gi

Cch ki m tra cc chn vo: if (PINA == 0b0000 0100) // Ki m tra chn 2 c a PORTA c // ph i m c 1 khng. { /*code*/}

Th c hnh s d ng ch c n ng I/O
y H n ch :
y if (PINA = 0x00000100) {}

khi c nhi u phm n ng th i th khng nh n bi t c => c n th c hi n ki m tra c l p theo u vo => if (!( PINA & ( 1<< PA2 ))) {/* code */} y Vi c s d ng phm b m theo d ng ny i h i V K ph i ho t ng lin t c ( ch h i vng )

Ch c n ng ng t ngoi (External Interrupt)

M t :
y Ng t : l m t tn hi u kh n c p c g i n b x l trung tm , yu c u t m d ng t t c cc cng vi c khc u tin th c hi n cng vi c m ng t yu c u. y Khi c tn hi u ng t , cc ch ng trnh ang ch y s c l u vo cc ng n x p , b x l trung tm s g i 1 ch ng trnh ph c v ng t t ng ng v i ng t c yu c u th c hi n cc thao tc x l ng t , sau khi th c hi n xong ch ng trnh con ph c v ng t , ch ng trnh s quay tr v tr ng thi tr c .

Ch c n ng ng t ngoi (Extrenal Interrupt)

M t :
y Atmega16 c 3 chn ng t ngoi l INT0, INT1, INT2 y INT0 (c ng D): chn : PD2 y INT1 (c ng D): chn : PD3 y INT2 (c ng B): chn : PB2 y Ch c n ng ng t c a cc chn ny c i u khi n b i cc thanh ghi : MCUCR , MCUCSR , GICR . y Thanh ghi c : GIFR.

Ch c n ng ng t ngoi (External Interrupt)

MCUCR MCU Control Register

ISC11 ,ISC10 : thi t l p ki u ng t cho chn INT1

ISC11 0 0 1 1 ISC10 0 1 0 1 Ch Ng t m c th p Ng t thay Ng t s Ng t s i m c logic n xu ng n ln

Ch c n ng ng t ngoi (External Interrupt)

MCUCR MCU Control Register

ISC01 ,ISC00 : thi t l p ki u ng t cho chn INT0

ISC01 0 0 1 1 ISC00 0 1 0 1 Ch Ng t m c th p Ng t thay Ng t s Ng t s i m c logic n xu ng n ln

Ch c n ng ng t ngoi (External Interrupt)

MCUCSR MCU Control and Status Register

ISC2 : thi t l p ki u ng t cho chn INT2

ISC2 0 1 Ch Ng t s Ng t s n xu ng n ln

x y ra ng t h n 50ns

chn ny th xung tn hi u vo ph i c

r ng l n

Ch c n ng ng t ngoi (External Interrupt)

GICR General Interrupt Control Register

INT1 : Cho php ng t INT0 : Cho php ng t INT2 : Cho php ng t

chn INT1 chn INT0 chn INT2

Ch c n ng ng t ngoi (External Interrupt)

GIFR General Interrupt Flag Register

INTF1 : c set ln 1 khi x y ra ng t s n ho c thay chn INT1. Lun l 0 khi l ng t m c. INTF0 : c set ln 1 khi x y ra ng t s n ho c thay chn INT0. Lun l 0 khi l ng t m c. INTF2 : c set ln 1 khi x y ra ng t chn INT2.

i m c logic i m c logic

Cc bit ny

c xa v 0 khi cc vector ng t

c g i.

Ch c n ng ng t ngoi (External Interrupt)

Th c hi n xc l p ch
#include <avr/io.h> #include <avr/interrupt.h> #include <util/delay.h> unsigned char x=0; SIGNAL(SIG_INTERRUPT1) { PORTA |= (1<<PA0); _delay_ms(100); PORTA &= ~(1<<PA0); }

ng t ngoi :

void main() { DDRA = 0xFF; DDRB = 0xFF; DDRD = 0x00; PORTD = 0xFF; PORTB = 0x00; MCUCR &=~ ((1<<ISC11)|(1<<ISC10)); // ngat muc thap o chan ngat INT1 GICR |= (1<<INT1); // cho phep ngat ngoai sei(); // cho phep ngat toan cuc while(1) { for(x=0;x<8;x++) { PORTB =(1<<x); _delay_ms(100); } } }

B Timer/Counter
M t :
y Atmega16 c 2 Timer/Counter 8 bits v 1 Timer/Counter 16 bits y Timer/Counter0 : 8 bits. y Timer/Counter1 : 16 bits. y Timer/Counter2 : 8 bits. y Cc b Timer/Counter ny c r t nhi u ch c n ng ng d ng a d ng trong th c t .

B Timer/Counter
Cc chn c a b timer/counter:
y Timer/Counter 0:
y T0 ( PB0 ) y OC0 ( PB3 )

y Timer/Counter 1:
y y y y

T1 ( PB1) OC1A ( PD5 ) OC1B ( PD4 ) ICP ( PD6 )

y Timer/Counter 2:
y OC2 ( PD7 ) y TOSC1 ( PC6) y TOSC2 ( PC7)

B Timer/Counter
Cc v n
y Cc v n

trong bi h c:

c b n c a b Timer/Counter. y S d ng Timer/Counter nh 1 b Timer. y S d ng Timer/Counter nh 1 b Counter. y S d ng Timer/Counter lm b PWM ( Pulse Width Modulation ).

B Timer/Counter
Cc v n
y L Module

c b n:

c l p so v i CPU. y Ch c n ng chnh l lm b nh th i (timer) v b ms ki n (counter). y 3 b Timer/Counter c a ATmega16 u c b canh ch nh th i gian ( Caliration ) s d ng trong cc ng d ng th i gian th c r t ti n l i. y Thng th ng 1 b Timer/Counter s c cc ch ho t ng : Normal Mode , CTC Mode , PWM Mode.

Kh o st Timer/Counter0
Cc nh ngh a quan tr ng c n n m
m

c:
c,

y BOTTOM : gi tr nh nh t m 1 T/C c th gi tr ny b ng 0.

y MAX : gi tr l n nh t m 1 T/C c th m c , gi tr ny ph thu c vo phn gi i c a T/C . VD: T/C0 l T/C 8bits => MAX = 2^8 - 1 = 255.

BOTTOM v MAX l 2 h ng s i v i 1 T/C. y TOP : L gi tr m khi T/C t t i n s thay i tr n thi. BOTTOM TOP MAX . Gi tr TOP c thi t l p thng qua 1 thanh ghi ng v i m i T/C.

Kh o st Timer/Counter0
Cc thanh ghi i u khi n Timer/Counter :
y TCCR0 : Time/Counter Control Register :

Bit 6,3 : WGM00 , WGM01 : Thi t l p ch

ho t

ng c a T/C

Kh o st Timer/Counter0
y TCCR0 : Time/Counter Control Register :

Bit 5,4 : COM01,COM00 : Thi t l p ch

u ra c a chn OC0.

Kh o st Timer/Counter0
i v i cc ch khng ph i PWM

i v i ch

Fast PWM

Kh o st Timer/Counter0
i v i cc ch Phase Correct PWM Mode

Kh o st Timer/Counter0
Cc thanh ghi i u khi n Timer/Counter :
y TCCR0 : Time/Counter Control Register :

Bit 2,1,0 : CS02-0 : Thi t l p ch

chia t n

Kh o st Timer/Counter0
Cc ch chia t n :

Kh o st Timer/Counter0
y TCNT0 : Time/Counter Register :

Thanh ghi ny lm nhi m v l u gi tr m c a b T/C . Gi tr c a thanh ghi ny s t ng 1 n v sau m i kho ng th i gian c nh s n trong qu trnh chia t n. M i khi gi tr c a TCNT b ng v i gi tr c a thanh ghi OCR s x y ra 1 s ki n ng t v chn OC0 s cho ra d ng sng c thi t l p mode .

Kh o st Timer/Counter0
y OCR0 : Output Compare Register :

Gi tr c a thanh ghi ny

c ng

i s d ng thi t l p .

Kh o st Timer/Counter0
y TIMSK : Time/Counter Interrupt Mask :

Bit OCIE0 : Cho php ng t khi thanh ghi OCR = TCNT Bit TOIE0 : Cho php ng t trn Timer/Counter0.

B Timer/Counter
S d ng T/C nh 1 b Timer:
y M t ho t

ng :

( Normal Mode )

Trong ch Normal Mode thanh ghi TCNT t ng gi tr c a n ln 1 n v sau m i 1 kho ng th i gian c nh tr c trong qu trnh chia t n . Khi TCNT t gi tr b ng MAX = 255 , n sinh ra m t ng t. Ta t n d ng ng t ny bi n T/C thnh 1 b Timer.

y V d : Th

c hi n .V i VDK ho t ng

i tr ng thi n LED sau m i 0.1ms t n s 8Mhz.

B Timer/Counter
#include <avr/io.h> #include <avr/interrupt.h> SIGNAL(SIG_OVERFLOW0) { PORTB ^= 1; // dao bit 1 cua PPORTB // 0000 0001 TCNT0 =155; } void main() { DDRB = 0xFF; PORTB = 0x00;

// PORTB la dau ra // khoi tao muc thap

B Timer/Counter
// Mac dinh o Normal mode TCCR0|=(1<<CS01); TCNT0 = 155; TIMSK |= (1<<TOIE0); sei(); while(1) { // vong lap vo tan } } // chia tan 8: 8Mhz/8 = 1Mhz // khoi tao gia tri TCNT // cho phep ngat Overflow // cho phep ngat toan cuc

B Timer/Counter
1us 155 1us 156 157 (255-155) x 1us = 0.1ms 158 159 255

Ch ng trnh con ph c v Ng t : thay i tr ng thi c a LED

B Timer/Counter
S d ng T/C nh 1 b Counter:
y M t ho t y V d : Th

ng : ( Normal Mode )

Cc s ki n c m t chn T0 v l u l i s s ki n trong thanh ghi TCNT. c hi n c ra PORTD. m s ki n v a cc gi tr m

B Timer/Counter
#include <avr/io.h> #include <util/delay.h> void main() { DDRD = 0xFF; // PORTD ra PORTD = 0x00; // muc thap , cho giong voi thanh ghi TCNT0 DDRB = 0x00; // PORTB dau vao cho chn T0 PORTB = 0xFF; // Muc cao TCCR0 |= (1<<CS01)|(1<<CS02); // su dung suon xuong de bat su kien TCNT0 =0;

B Timer/Counter
while(1) { if (TCNT0 == 200) TCNT0 = 0; // cho phep dem den 200 PORTD = TCNT0; } }

B Timer/Counter
S d ng T/C lm b PWM:
y M t ho t
( ch fast PWM ) T chn OC0 c a V K s c xung ra v i r ng xung thay i c b ng cch thay i gi tr c a OCR0 ( 0 255 ). T n s c a chu i xung ny c tnh b ng cng th c: fPWM : T n s xung ra. fclk : T n s ho t ng c a V K. N : H s chia t n.

ng :

Trong :

fPWM = fclk / ( N.256 )

y V d : Th

c hi n nhy n LED b ng ch s nh p nhy c a LED .

PWM , nh n xt

B Timer/Counter
fPWM = 8/(8 x 256) = 0,004 Mhz

TPWM = 1/ fPWM = 250 us

B Timer/Counter
#include <avr/io.h> void main() { DDRB = 0xFF; TCCR0 |= (1<<CS01); //chia tan 8 TCCR0 |= (1<<WGM01)|(1<<WGM00); // che do fast PWM OCR0 = 10; // khoi tao thanh ghi OCR0 TCCR0 |= (1<<COM01)|(1<<COM00); //chon che do OC0 =1 khi TCNT = OCR }

Kh i USART
M t :
y Atmega16 c 1 b USART ( Universal Synchronous/ Asynchronous serial Receiver and Transmitter) . y
y y y y

y l kh i giao ti p n i ti p r t linh ho t :
y Ho t

ng c ch song cng ( truy n nh n c l p ) Truy n thng n i ti p ng b ( Synchronous )ho c khng ng b ( Asynchronous ). ng b giao ti p Master / Slave Gi i t c truy n a c p Cho php s d ng nhi u khung truy n : 5,6,7,8,9 Databits ; 1,2 Stopbit.

Kh i USART
M t :
y C kh n ng t o bit ki m tra ch n l v ki m tra bit ki m tra y y y y

ch n l . C kh n ng pht hi n l i trn C kh n ng pht hi n l i khung truy n C kh n ng x2 t c ch khng ng b C cc ng t pht hi n: k t thc qu trnh nh n , thanh ghi truy n tr ng , k t thc qu trnh truy n

Kh i USART
Cc chn c a kh i USART:
y Chn TXD ( PD1 ) :

Chn xu t tn hi u ra c a kh i USART. y Chn RXD ( PD0 ) : Chn nh n tn hi u vo c a kh i USART. =>> Mu n 2 kh i truy n thng ny giao ti p v i nhau th ph i k t n i TXD c a b ny v i RXD c a b kia. y Chn XCK ( PB0 ) : Chn k t ni xung Clock c a cc b USART . Chn ny ch s d ng trong ch ng b ( Synchronous )

Kh i USART
Khung truy n:

y St : Start bit : lun y y y y

m c th p v ch c 1. Data bits : 5, 6, 7, 8 ho c 9 bits. Khng c Parity bit , Parity bit ch n , Parity bit l . Sp : Stop bit : 1 ho c 2 Stop bit : lun m c cao. IDLE : khng c giao ti p ( m c cao ).

Kh i USART
Gi i thch v khung truy n
y Start bit: y L bt u tin cg i i li u ang c g i t i.

thng bo v i bn nh n l c d

y Stop bit:
y N u

y L bt cu i cng thng bo k t thc 1 khung truy n .

y Parity bit:

c s d ng th bt ny n m gi a data bit cu i cng v Stop bit u tin. y Bit ny c tnh nh sau : y Parity ch n : l k t qu c a php XOR cc databit v bit 0. y Parity l : l k t qu c a php XOR cc databit v bit 1.

Kh i USART
Gi i thch v khung truy n
y Cc data bit:
y Cc data bit s

c ki m tra b ng t c

truy n Baudrate.

y K t lu n : 2 kh i giao ti p c v i nhau th: y C cng 1 khung truy n ( frame format ). y Ph i c cng t c truy n ( baud rate ). Cc v n trn c thi t l p t i cc thanh ghi i u khi n kh i USART

Kh i USART
Cc thanh ghi :
y UDR ( USART Data buffer Register )

Thanh ghi d li u c a kh i USART. Khi truy n thi y l thanh ghi ghi d li u c n truy n. Khi nh n thanh ghi ny ghi d li u nh n. Phn bi t ? Thanh ghi ny ban u m c nh l nh n Mu n ghi d li u g i i th tr c c n UCSRA |= ( 1<< UDRE ). Sau khi ghi d li u xong , b Transmitter c kh i ng th d li u ny s c chuy n vo thanh ghi d ch khi thanh ghi tr ng, r i d li u c truy n i.

Kh i USART
Cc thanh ghi :
y UCSRA ( USART Control and Status Register A)

RXC : Receive complete : Set ln 1 khi trong UDR c d li u ch a c c. Xa v 0 khi b m tr ng. TXC : Transmit complete : Set ln 1 khi ton b d li u trong thanh ghi d ch c y ra ngoi v khng c d li u m i xu t hi n trong UDR. T v 0 khi ch ng trnh con ph c v ng t c g i, ho c ng dng c th xa b ng cch ghi 0 vo.

Kh i USART
Cc thanh ghi :
y UCSRA ( USART Control and Status Register A)

UDRE: UDR is Empty: Set ln 1 khi UDR tr ng v s n sng nh n d li u m i. Xa v 0 khi b m tr ng. FE : Frame Error : Set ln 1 khi x y ra l i khung truy n. 0 khi khng c l i khung truy n Lun t bit ny l 0 khi tc ng vo UCSRA

Kh i USART
Cc thanh ghi :
y UCSRA ( USART Control and Status Register A)

DOR : Data Over Run : Set ln 1 khi x y ra s c trn d li u: ang c d li u trong b m , c d li u trong thanh ghi d ch v ng th i pht hi n 1 start bit m i. Xa v 0 khi c thao tc c d li u t UCR Khi s d ng thanh ghi UCSRA th ph i bit ny l 0 PE : Parity Error : Set ln 1 khi x y ra l i bit ki m tra ch n l . Xa v 0 khi c thao tc c d li u t UCR

Kh i USART
Cc thanh ghi :
y UCSRA ( USART Control and Status Register A)

U2X : Double the USART Transmittion speed : Ch c tc d ng v i ch Asynchronous. MPCM : Multi processor Communication Mode : Khi set ln 1 , t t c cc khung truy n khng c b .

a ch s b lo i

Kh i USART
Cc thanh ghi :
y UCSRB ( USART Control and Status Register B)

RXCIE : RX Complete Interrupt Enable : Cho php ng t khi nh n xong. TXCIE : TX Complete Interrupt Enable : Cho php ng t khi truy n xong. UDRIE : UDR Empty Interrupt Enable: Cho php ng t khi UDR tr ng.

Kh i USART
Cc thanh ghi :
y UCSRB ( USART Control and Status Register B)

RXEN : RX Enable : Cho php nh n. TXEN : TX Enable : Cho php truy n. UCSZ2 : Character size: s l ng databit k t h p cng UCSZ1, UCSZ0 thanh ghi UCSRC s databit.

xc

nh

Kh i USART
Ch s data bit:

Kh i USART
Cc thanh ghi :
y UCSRB ( USART Control and Status Register C)

URSEL: Bit ny l 1 th thanh ghi ny l UCRSC ( chnh n :D ) Bit ny l 0 th thanh ghi ny tr thnh UBRRH s d ng Baudrate. UMSEL : Mode Select : Ch n ch : Set ln 1: ch ng b Synchronous. Set v 0 : ch khng ng b Asynchronous.

set

Kh i USART
Cc thanh ghi :
y UCSRB ( USART Control and Status Register C)

UPM1, UPM0: Parity Mode : Ch n ch cho bt ki m tra ch n l .

Kh i USART
Cc thanh ghi :
y UCSRB ( USART Control and Status Register C)

USBS: Stop Bit Select : 0 : 1 Stop bit. 1 : 2 Stop bits. UCPOL : Clock Polarity : Ch s d ng trong ch Synchronous. Trong ch Asynchronous bit ny l 0. Ch n s n l y m u tn hi u .

Kh i USART
Cc thanh ghi :
y UBRRL v UBRRH ( Baudrate Register )

URSEL : bit ch n = 0 th l UBRRH Khi set baudrate ta tra b ng v gn gi tr cho UBRRH v UBRRL

Kh i USART
M ph ng :
y Th c hi n giao ti p truy n thng n i ti p gi a 2 V K. y Yu c u khung truy n : 8 data bits , 1 stop bit , no parity , Baudrate 9600 bps. y Gi s 2 V K Atmega16 s d ng th ch anh 8Mhz.