Half adder library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity half_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC); end half_adder; architecture Behavioral of half_adder is begin sum <= '1' when ((a='0' and b='1') or (a='1' and b='0'))else '0'; cout <= a and b; end Behavioral; full adder library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity full_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC); end full_adder; architecture Behavioral of full_adder is component half_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; cout : out STD_LOGIC); end component half_adder; signal sum0 : std_logic; signal cout0 : std_logic; signal cout1 : std_logic; begin FA0 : half_adder port map (a=>a,b=>b,sum=>sum0,cout=>cout0); FA1 : half_adder port map (a=>cin,b=>sum0,sum=>sum,cout=>cout1); cout <= cout0 or cout1; end Behavioral;

full adder 3 bit library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fulladd3 is Port ( a0 : in STD_LOGIC; a1 : in STD_LOGIC; a2 : in STD_LOGIC; b0 : in STD_LOGIC; b1 : in STD_LOGIC; b2 : in STD_LOGIC; cin : in STD_LOGIC; s0 : out STD_LOGIC; s1 : out STD_LOGIC; s2 : out STD_LOGIC; cout : out STD_LOGIC); end fulladd3; architecture Behavioral of fulladd3 is component full_adder port( a,b,cin : in std_logic; sum,cout : out std_logic ); end component; signal c0,c1:std_logic; begin fa0 : full_adder port map(a=>a0,b=>b0,cin=>cin,sum=>s0,cout=>c0); fa1:full_adder port map(a=>a1,b=>b1,cin=>c0,sum=>s1,cout=>c1); fa2: full_adder port map(a=>a2,b=>b2,cin=>c1,sum=>s2,cout=>cout); end Behavioral;