Assignment # 02 Last Date of submission: 30-03-2012

Subject: Analog IC Design Semester: Spring 2012

Problem 01. Using the open-circuit and short-circuit time-constant method, find the two poles of the circuit
shown below (assuming that the poles are far apart from each other).
0
= 1uu, I
c
= u.S mA,
1
= 1 0Ez, C

=
u.2 pF, I
1
= 26 mI, R
L
= 1u k, R
L
= 1.S k .


Problem 02 Derive an expression for the voltage gain for the circuit for the given numerical values and plot the
gain in dBs versus frequency on the semilog-graph paper. From the plot, find the half power and frequency.

0
= 1uu, g
m
= 1u mS, C

= 1 pF, C
n
= 1u pF, C
L
= 1u pF R
L
= 1u k, R
I
= 1 k.


Problem 03 Draw the small signal model for the MOS-transistor shown in the figure, at high frequency and
derive the expression the for the voltage gain. Compute the location of the two poles for the numerical values
R
I
= 1 k, R
L
= 1u kobm, g
m
= 1 mS, C
gs
= S pF, C
gd
= 1 pF. Ignore r
ds
.

Problem 04 Find, for given numerical values, the all poles and the midband gain of the transfer function v
out
/v
in

of the differential amplifier shown. Assume that K
N
i
= 11u AI
2
, I
1N
= u.7 I,
N
= u.u4 I
-1
, C
gs
=
u.2 pF, C
gd
= 2u F. Determine also the common mode rejection ratio (CMRR).
C

I
R
L
R
L
C
out
V
v
m
g
C
r

I
R
L
R out
V
1
v
m
g
1
v in
V
v

Problem 05 Derive expressions for output resistance R
o
and currents I
o
for each of the BJT current mirrors:

Problem 06 Repeat problem 05 for the MOS Transistors current sources.

in
I
o
I
in
I
o
I
in
I
o
I
Hint: the equivalent of the half circuit
is shown below, where v
id
= v
in
and
v
od
= v
out
.
R
1
Q
2
Q
1
Q
2
Q
4
Q
3
Q
1
Q
2
Q
3
Q
in
I
o
I
in
I
o
I
in
I
o
I
1
M
2
M
1
M
2
M 4
M
3
M 1
M
2
M
3
M
3
M
6
M
5
M
4
M