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i
d
i
qr
i
dr
E H
i
(s)
E
E
E
abc
dq
H
i
(s)
K
d
K
d
PWM
s
b
s
c
s
a
m
b
m
c
m
a
i
dr
i
qr
u
PLL
Sine & Cosine
Look-up Table
e
PLL
The modulating signals are the output of the
current controller and need to be converted back to the abc-
coordinate frame for comparison with a carrier signal in conven-
tional SPWM implementations. Hence both the forward and
inverse Parks transformations are needed to be realized in the
FPGA, for which look-up tables are a straight-forward method to
implement when the PLL reference angle is made available to the
FPGA. The forward Parks transformation is defined as follows
T u
PLL
( )
2
3
---
u
PLL
( ) cos u
PLL
2t
3
------
\ .
| |
cos u
PLL
2t
3
------ +
\ .
| |
cos
u
PLL
( ) sin u
PLL
2t
3
------
\ .
| |
sin u
PLL
2t
3
------ +
\ .
| |
sin
1
2
---
1
2
---
1
2
---
= (1)
While inverse Parks transformation is given by
T u
PLL
( )
1
u
PLL
( ) cos u
PLL
( ) sin 1
u
PLL
2t
3
------
\ .
| |
cos u
PLL
2t
3
------
\ .
| |
sin 1
u
PLL
2t
3
------ +
\ .
| |
cos u
PLL
2t
3
------ +
\ .
| |
sin 1
= (2)
B. Performance Measurement and Evaluation
Performance of the algorithm presented in this section is illus-
trated by Fig. 3. The spike in the cos(u
PLL
) calculated in FPGA
occurs due to the non-ideal transitions between 2t and 0 radians in
the transmitted PLL angle around its reset instants. The error in
calculation of the trigonometric functions propagates to the
modulating signals fed to the PWM and cause malfunctioning of
the overall controller implementation. Fig. 4 depicts the resulting
error in calculation of the modulating signals. Performance of the
three-phase power converter in Fig. 5 with the presented control
1440
Fig. 3. Error in the calculation of cos(u
PLL
) when u
PLL
is transmitted from
DSP to FPGA.
u
PLL
calculated in DSP
u
PLL
transmitted to FPGA
Error in cos(u
PLL
) calculation in FPGA
Fig. 4. Error in the calculation of modulation signals.
Error in calculation of modulation signals
implementation is depicted in Fig. 6.
+
v
a
v
c
v
b
s
a
s
b
s
c
i
q
i
d
u
PLL
V
dc
C
L
f
R
d
C
d
C
f
R
V
n
i
a
i
c
i
b
Fig. 5. Diagram of a three-phase VSC for standalone operation.
abc
dq
The dq domain current
controllers were implemented using PI current regulators with K
p
= 0.0059 and K
i
= 0.00036. The d-axis current reference i
dr
and q-
axis current reference i
qr
are set to 3 A and 0 A respectively. The
input voltage is V
dc
= 450 V with a 25 resistive load. From Fig.
6, it is observed that the current controller regulates the output
current at 3 A peak, but the spikes in the modulation signals result
in spikes in output phase current i
a
and phase voltage v
a
.
Fig. 6. Spikes in inverter output current and voltage waveforms.
v
a
i
a
m
a
IV. CURRENT CONTROL BY TRANSMISSION OF e
PLL
This section presents implementation of dq-domain current
control in the FPGA when the angular frequency of the PLL is
transmitted from a DSP via an analog channel. Additionally, the
initial phase information is also required to synthesize the PLL
angle. A binary signal state is transmitted using a digital channel at
the reset instants of the PLL reference angle in the DSP.
A. Integrator Reset and Sensitivity to Noise
The control algorithm was modified to transmit e
PLL
calcu-
lated in the DSP to the FPGA as depicted in Fig. 7. The synchro-
nizing signal is represented by RESET_SIGNAL in the block
diagram. Fig. 8 shows the synchronizing RESET_SIGNAL in the
DSP. The synchronizing signal is used to synchronize the u
PLL
calculated in the FPGA by resetting it when the binary state of the
resetting signal changes.
B. Performance Measurement and Comparison
Fig. 9 shows that the cos(u
PLL
) calculated in DSP is in phase
with cos(u
PLL
) calculated in FPGA, thus successfully synchro-
nized with the PLL angle reference frame without incurring in
erroneous calculation at the resetting instants of the PLL reference
1441
Fig. 7. Block diagram for implementation of dq domain control in FPGA by
transmitting e
PLL
and resetting signal from DSP.
k
p
k
i
s
---- +
v
b
v
c
v
a
u
PLL
v
d
v
q
abc
dq 1
s
---
m
b
m
c
m
a
u
PLL
i
q
i
d
i
qr
i
dr
E H
i
(s)
E
E
E
abc
dq
H
i
(s)
K
d
K
d
PWM
s
b
s
c
s
a
m
b
m
c
m
a
i
dr
i
qr
e
PLL
Sine & Cosine
Look-up Table
e
PLL
1
s
---
e
PLL
RESET_SIGNAL
Fig. 8.
PLL
in synchronized with synchronizing signal RESET_SIGNAL.
RESET_SIGNAL
u
PLL
frame.
The time delay associated with the FPGA computation is
quantified in Fig. 10. All power converter current control
functions are programmed in the FPGA including the PWM.
Since the power converter switching frequency for the present
application is 40 kHz, we confirm all required computations are
completed within a single 25 s interrupt interval.
Fig. 9. cos(u
PLL
) synchronized as calculated in DSP and FPGA together with
RESET_SIGNAL.
RESET_SIGNAL
cos(u
PLL
) calculated in DSP
cos(u
PLL
) calculated in FPGA
Fig. 10. Computation time delay for proposed algorithm in FPGA.
21.8 s
C. Other Alternatives and Considerations
It is possible to compute all entries in the forward and inverse
Parks transformation without specifying the angular frequency
and reset instants nor the transformation angle directly. From
straight-forward trigonometric identities, all terms in Parks
transform may be computed from linear combinations of
u
PLL
( ) cos and u
PLL
( ) sin which are also characterized by much
lower signal bandwidth than the sawtooth angle reference. Such
implementation, however, requires one additional analog signal
channel between the DSP and FPGA.
V. SYSTEM PERFORMANCE
Fig. 11 shows a picture of the experimental set-up. Dc power is
provided by a 600 V Sorensen regulated dc power supply. The
filter inductor and capacitor are L
f
= 0.7 mH and C
f
= 10 F
respectively. A damper capacitor and resistor are C
d
= 60 F and
R
d
= 5 O. The inverter switching frequency is 40 kHz and the
current controller was designed with K
p
= 0.0059 and K
i
=
0.00036 with a bandwidth of 400 Hz and a phase margin of 52
o
.
An ADC prefilter is included to avoid aliasing problems in the
discretization. The proposed current control implementation by
transmission of e
PLL
is tested in grid-parallel mode, standalone-
mode and standalone-mode with unbalanced loads.
1442
Fig. 11. Experimental set-up for implementing the dq domain control.
A. Grid-Parallel Mode
For this test, the inverter voltage is first synchronized with the
grid voltage in terms of both amplitude and phase. After the
voltages are matched the inverter is connected to the grid for grid
parallel operation avoiding potential inrush currents at the inter-
connection instant. The current references are set to i
dr
= 4.2 A and
i
qr
= 5.1 A respectively and the input voltage is set to 600 V. Fig.
12 shows the grid voltage when the converter operates in grid-
parallel mode together with the injected current. The resonance of
the inverter current may originate on system interaction problems
between the inverter impedance and the grid impedance.
Fig. 12. Inverter phase voltage and current waveforms for grid parallel mode.
v
a
i
a
B. Standalone Mode
For this test, the inverter is disconnected from the grid but
supplies power to a local resistive load with 25 O. The current
references are set to i
dr
= 5 A and i
qr
= 0 A. The input voltage was
set to 550 V and it can be observed from Fig. 13 that the current
controller regulates the output phase current i
a
at 5 A peak,
resulting in 125 V at v
a
.
The change in implementation of the control algorithm by
transmitting e
PLL
instead of u
PLL
has removed the spikes in the
current and the voltage waveforms due to the sharp PLL angle
transitions.
Fig. 13. Inverter phase voltage and current waveforms for standalone mode with
balanced loads.
v
a
i
a
m
a
The stand-alone system was also tested under unbalanced
load conditions by removing resistor load in phase c. No changes
were introduced to the current control structure and system
currents and voltages are depicted in Fig. 14 and 15 respectively.
Fig. 14. Inverter phase currents for standalone mode with unbalanced loads.
i
a
i
b
i
c
Fig. 15. Inverter phase voltages for standalone mode with unbalanced loads.
v
a
v
b
v
c
1443
VI. SUMMARY
A distributed implementation of grid synchronization by PLL
and dq-domain current control has been presented using DSP and
FPGA. An implementation by direct analog transmission of the
PLL synchronization angle was presented first to illustrate the
problems associated to the sharp resetting of the synchronization
angle. The synchronization algorithm between DSP and FPGA
was then modified to transmit the e
PLL
along with a binary
resetting signal. Since e
PLL
has a much lower signal bandwidth
compared to the sawtooth PLL angle reference, the performance
in the latter implementation has shown better results. Experi-
mental results are included to confirm the improvement of perfor-
mance in the latter realization.
REFERENCES
[1] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, Overview of
control and grid synchronization for distributed power generation
systems, IEEE Trans. Ind. Electron., vol. 53, pp. 1398-1409, Oct. 2006.
[2] E. Monmasson and M. N. Cirstea, FPGA design methodology for indus-
trial control systemsA review, IEEE Trans. Ind. Electron., vol. 54, pp.
18241842, Aug. 2007.
[3] http://focus.ti.com/lit/ds/symlink/tms320f28335.pdf
[4] H. Weng, J. D. DAtre, R. A. Seymour, A. M. Ritter, X. Yuan, R. Dai,
and R. W. Delmerico, Apparatus, method and computer program
product for tracking information in an electric grid, U.S. Patent 7 456
695 B2, Jan. 15, 2009.
[5] P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, D.
Boroyevich, Decoupled double synchronous reference frame PLL for
power converters control, IEEE Trans. Power Electron., vol. 22, pp.
584-592, Mar. 2007.
[6] S. Chung, A phase tracking system for three phase utility interface
inverters, IEEE Trans. Power Electron., vol. 15, pp. 431-438, May
2000.
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