CONFERENCE PROGRAMME 16th EUROPEAN SYMPOSIUM RELIABILITY OF ELECTRON DEVICES, FAILURE PHYSICS AND ANALYSIS Bordeaux - France 10 - 14 October

2005

with the technical co-sponsorship of : IEEE - Electron Devices Society IEEE Reliability Society

in conjunction with : ANADEF - France organised by : Laboratoire IXL CNRS Universit Bordeaux 1 ENSEIRB

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Tuesday, October 11, morning

08:30 09:00 Registration Auditorium Tutorial T1 "Issues in Electromagnetic Compatibility of integrated circuits: Emission and Susceptibility" by Etienne SICARD (INSA Toulouse, France)
The tutorial is focused on the electromagnetic compatibility (EMC) of integrated circuits. The introduction gives general keyword definitions and principles for emission and susceptibility. The second part deals with the evolution of integrated circuit design and technology with its consequences on EMC, with focus on the device scale down, the IC complexity increase, the shift towards higher frequencies, and the synchronous design impact on noise. The third part describes the mechanisms for generating parasitic noise within integrated circuits and the role of the package inductance and on-chip supply network to create resonances and couple with the outside world. Next, the standardized measurement methods are described for both parasitic emission characterization (conducted and radiated) and immunity from 1MHz to 1GHz. Issues and proposals up to 18GHz are discussed. The advances in modelling of emission are also addressed, as well as the issues in immunity prediction. Finally, "golden rules" for low parasitic emission applied in some test circuits and commercial products are presented.

ROOM 3.5, third floor 9:00 Tutorial T3 Basic Principles for Managing Foundry Programs by Arnie LONDON (London Associates, USA)
Since the emergence of foundries in the mid 1980s as a source of supply of IC wafers, their importance in the microelectronics industry has grown steadily. Many small fabless companies have emerged, and even some of the larger manufacturers use foundries to supplement their wafer supply. By having an understanding of how the basic foundry relationship works, it is more likely that a customer will have positive results in terms of product performance and reliability and timely program execution. This is especially true for smaller volume customers. This presentation describes the key organizations and people involved in a typical foundry program and discusses the importance of establishing a strong engineering and logistical interface between foundry and customer. The steps in assessing foundries and making a final selection are discussed. Also covered are the steps in going from an initial design to production status including establishing appropriate yield targets. Case histories of some actual foundry programs are given to illustrate situations in which positive and less than positive results were achieved.

10:30

Coffee break Auditorium

11:00

Tutorial T2 "Negative Bias Temperature Instability (NBTI) in MOS devices" by Jim STATHIS (IBM, USA)
The purpose of this tutorial is to bring together much of the latest information and recent developments in understanding of NBTI. Negative Bias Temperature Instability (NBTI), refers to the generation of positive oxide charge and interface traps in MOS structures under negative gate bias, in particular at elevated temperature. First reported in the 1960s, several effects conspire to bring NBTI back to the attention of device and circuit designers: First, the operating voltage has not scaled as rapidly as gate oxide thickness, resulting in higher fields which enhance the NBTI; second, device threshold voltage scaling has not kept pace with operating voltage, which results in larger percentage degradation of drive current for the same change in Vt; and third, the addition of nitrogen into the gate dielectric for gate leakage reduction and control of boron penetration has had the side effect of increasing NBTI. We will begin with an outline of the basic observations and experimental methods of the early NBTI studies, and proceed to more advanced observations and methods, including recovery or relaxation. Various theories and models will be reviewed. Finally, the impact of NBTI on circuit performance degradation will be discussed.

12:30

Lunch

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Tuesday, October 11, afternoon

14:00 14:20 IP1 Official opening of ESREF 2005 Chairman : A. Touboul (IXL, University of Bordeaux France) Invited Conference : Lifetime Prediction on the Base of Mission Profiles M. CIAPPA (ETH Zrich - Switzerland) Invited Conference : Best Paper at IRPS 2005 Reliability Improvement and Burn in Optimization through the use of die level predictive modeling W. C. RIORDAN, R. MILLER, E. R. St. PIERRE (Intel Corporation - USA) Invited Conference : Best Paper at IPFA 2005 - Singapore Coffee break

15:00

15:20 15:40

SESSION A

Quality and Reliability Techniques for Devices and Systems Auditorium Chairs : V. Loll (Nokia - Denmark) F. Marc (IXL, University of Bordeaux - France)

16:00

A1

16:20 16:40

A2 A3

17:20 17:20

A4 A5

Layout Dependency Induced Deviation from Poisson Area Scaling in BEOL Dielectric Reliability Y. Li1,2, Zs. Tkei1, Ph. Roussel1, G. Groeseneken1,2, K. Maex1 (1 IMEC, 2Katholieke Universiteit Leuven Belgium) Study of Area Scaling Effect on Integrated Circuit reliability Based on Yield Model C. Hong, L. Milor, M. Choi, T. Lin (Georgia Institute of Technology USA) Investigation on Seal-Ring Rules for IC Products Reliability in 0.25 m CMOS Technology S-H. Chen, M-D. Ker* (Industrial Technology Research Institute, *National Chiao-Tung University Tawan) Reliability for Recessed Channel Structure n-MOSFET J.Y. Seo, K.J. Lee, Y.S. Kim, S.Y. Lee, S.J. Hwang, C.K. Yoon (Samsung Electronics Korea) Reliability Prediction in Electronic Industrial Applications G. Cassanelli1, G. Mura2, F. Cesaretti3, M. Vanzi2, F. Fantini1 (1University of Modena, 2 University of Cagliari, 3Thermowatt Italy)

17:40

Presentation of their activity by exhibitors Cocktail courtesy of equipment exhibitors

18:00

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Wednesday, October 12, morning

SESSION E Failure Mechanisms in Microwave, High Bandgap and Photonic Devices Auditorium Chairs: J.M. Dumas (ENSIL-University of Limoges - France) H. Hartnagel (TU Darmstadt Germany) Invited Conference : DC-to-RF dispersion effects in GaAs- and GaN-based heterostructure FETs: performance and reliability issues G. Verzellesi, G. Meneghesso*, A. Chini, E. Zanoni*, C. Canali (Universita di Modena e Reggio Emilia,*Universita di Padova - Italy)
Electroluminescence Spectroscopy for Reliability Investigations of 1.55 m Bulk Semiconductor Optical Amplifier S. Huyghe1, L. Bchou1, N. Zerounian2, Y. Deshayes1, 2 3 3 F. Aniel , A. Denolle , D. Laffitte , J.L. Goudard3, Y. Danto1 ( IXL University of Bordeaux, 2 IEF University Paris-Sud 11, 3AVANEX France) Reliability Investigation on LTG-GaAs Photomixers for THz Generation Based on Optical Heterodyning C. Sydlo, J. Sigmund, B. Mottet, H.L. Hartnagel (TU- Darmstadt Germany) On State Breakdown in PHEMTs and its Temperature Dependence P. Cova, N. Delmonte, R. Menozzi (University of Parma Italy) Safe Operating Area of GaAs MESFET and PHEMT for Amplification in Overdrive Conditions N. Ismal, N. Malbert, N. Labat, A. Touboul, J.L. Muraro*, F. Brasseur*, D. Langrez* (IXL University of Bordeaux, *Alcatel Space Toulouse France)

8:30

IP2

9:10

E1

9:30

E2

9:50 10:10

E3 E4

10:30 SESSION B3

Coffee break Back-end reliability Auditorium G. Groeseneken (IMEC Belgium) N. Stojadinovic (University of Nis - Serbia and Montenegro) Invited Conference : Reliability challenges for low-k dielectrics and copper diffusion barriers Zs. Tkei1, Y-L. Li1,2, G.P. Beyer1 (1IMEC, 2Katholieke Univ. Leuven - Belgium)
Effect of Test Condition and Stress Free Temperature on the Electromigration Failure of Cu Dual damascene Submicron Interconnect Line-Via Test Structures A. Roy, C.M. Tan, R. Kumar*, X.T. Chen* (Nanyang Technological University, *Institute of Microelectronics Singapore) Effect of Vacuum Break after the Barrier Layer Deposition on the Electromigration Performance of Aluminium Based Line Interconnects C.M. Tan, A. Roy, K.T. Tan*, D.S. Kwang Ye*, F. Low* (Nanyang Technological University, *Systems on Silicon Manufacturing Singapore)

Chairs:

10:50

IP 3

11:30

B3-1

11:50

B3-2

SESSION D

Advanced Failure Analysis: sample preparation, case studies Room 3.5, third floor Chairs: Ph. Perdu (CNES - France) M. Vanzi (University of Cagliari France)

11:30 11:50 12:10

D1 D2 D3

Advanced Electrical Analysis of Embedded Memory Cells using Atomic Force Prober (AFP) M. Grtzner (Infineon Technologies Germany) Oxide Charge Measurements in EEPROM Devices C. De Nardi, R. Desplats, P. Perdu, F. Beaudoin, J-L. Gauffier* (CNES/THALES, *LNMO - INSA Toulouse France) Localization and Physical Analysis of Dielectric Weaknesses for State-of-the-Art Deep trench based DRAM Products G. Neumann, J. Touzel, R. Duschl (Infineon Technologies Germany)

12:30

Lunch

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Wednesday, October 12, afternoon

SESSION H MEMS/MOEMS, Sensors and Actuators Reliability Auditorium Chairs: I. de Wolf, (IMEC - Belgium) F. Pressecq, (CNES - France)

14:00

IP4

Invited Conference : Failure Analysis Issues in Microelectromechanical Systems (MEMS) Jeremy Walraven (Sandia lab.- USA)
Out of Plane vs. in Plane Flexural Behaviour of Thin Polysilicon Films: Mechanical Characterization and Application of the Weibull Approach F. Cacchione, A. Corigliano, B. De Masi*, C. Riva* (Politecnico di Milano, * STMicroelectronics - Italy) FTIR Spectroscopy for the Hermeticity Assessment of Micro-Cavities D. Veyri1,2, D. Lellouchi3, J.L. Roux1, F. Pressecq1, A. Tetelin2, C. Pellet2 (1CNES, 2IXL University of Bordeaux, 3NovaMEMS France) Failure Predictive Model of Capacitive RF-MEMS S. Mell, D. De Conto, L. Mazenq, D. Dubuc, B. Poussard, C. Bordas, K. Grenier, L. Bary, O. Vendier*, J.L. Muraro*, J.L. Cazaux*, R. Plana (LAAS-CNRS, *Alcatel Space Industries France) Biaxial initial stress characterization of bilayer gold RF-switches K. Yacine1, F. Flourens1, D. Bourrier1, L. Salvagnac1, P. Calmont1, X. Lafontan2, Q.H. Duong3, L. Buchaillot3, D. Peyrou1, P. Pons1, R. Plana1 (1LAAS-CNRS, 2NovaMEMS, 3IEMN Lille France)

14:40

H1

15:00

H2

15:20

H3

15:40

H4

SESSION B1

Failure Mechanisms in Silicon Devices Room 3.5, third floor Chairs: G. Groeseneken (IMEC Belgium) N. Stojadinovic (University of Nis - Serbia and Montenegro)

14:00

B1-1

14:20

B1-2

14:40

B1-3

15:00

B1-4

15:20

B1-5

Gate Stress Effect on low Temperature Data Retention Characteristics of Split-Gate Flash Memories L.-C. Hu, A.-C. Kang*, E. Chen*, J.R. Shih*, Y.-F. Lin, K. Wu*, Y.-C. King (National TsingHua University, *Tawan Semiconductor Manufacturing Company Tawan) Tunnel Oxide Degradation under Pulsed Stress G. Ghidini, C. Capolupo, G. Giusto, A. Sebastiani, B. Stragliati, M. Vitali (ST Microelectronics Italy) Negative Bias Temperature Instabilities in P-Channel Power VDMOSFETs N. Stojadinovic, D. Dankovic, S. Djoric-Veljkovic, V. Davidovic, I. Manic, S. Golubovic (University of Nis Serbia and Montenegro) Hot-Carrier Reliability of 20V MOS Transistors in 0.13 m CMOS Technology Y. Rey-Tauriac1, J. Badoc1, B. Reynard1, R.A. Bianchi1, D. Lachenal1,2, A. Bravaix2 (1ST Microelectronics, 2L2MP-ISEN France) Hydrogen-related Influence of the Metallization Stack on Characteristics and Reliability of a Trench Gate Oxide M. Nelhiebel, J. Wissenwasser, Th. Detzel, A. Timmerer, E. Bertagnolli* (Infineon Technologies, *TU Wien Austria)

16:00

Coffee break

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Wednesday, October 12, afternoon

SESSION B1 Failure Mechanisms in Silicon Devices Auditorium Chairs: G. Groeseneken (IMEC Belgium) N. Stojadinovic (University of Nis Serbia and Montenegro)

16:20

B1-6

16:40

B1-7

17:00

B1-8

17:20

B1-9

Dielectric Reliability of Stacked Al2O3-HfO2 MIS Capacitors with Cylinder Type for Improving DRAM Data Retention Characteristics J.Y. Seo, K.J. Lee, S.Y. Lee, S.J. Hwang, C.K. Yoon (Samsung Electronics Korea) Degradation of High-K La2O3 gate Dielectrics using Progressive Electrical Stress E. Miranda, J. Molina*, Y. Kim*, H. Iwa* (Universitat Autonoma de Barcelona - Spain, *Tokyo Institute of Technology - Japan) Impacts of the recovery phenomena on the worst case of damage in DC/AC stressed ultrathin NO gate oxide MOSFETs A. Bravaix1, D. Goguenheim1, M. Denais1,2, V. Huard3, C. Parthasarathy2, F. Perrier2, N. Revil2, E. Vincent2 (1L2MP-ISEN, 2STMicroelectronics Crolles 2 Alliance, 3Philips Semiconductors Crolles 2 Alliance France) Radiation Source Dependence of Performance Degradation in Thin Gate Oxide FullyDepleted SOI n-MOSFETs K. Hayama1, K. Takakura1, H. Ohyama1, S. Kuboyama2, S. Matsuda2, J.M. Rafi3, A. Mercha4, E. Simoen4, C. Claeys4,5 (1Kumamoto National College of Technology, 2Japan Aerospace Exploration Agency - Japan, 3Institut de Microelectronica de Barcelona - Spain, 4IMEC, 5 Katholieke Universiteit Leuven Belgium)

SESSION D

Advanced Failure Analysis: sample preparation, case studies (contd) Room 3.5, third floor Chairs: Ph. Perdu, (CNES - France) M. Vanzi (University of Cagliari Italy)

16:20 16:40

D4 D5

17:00

D6

17:20

D7

STEM Role in Failure Analysis Process M.A. Ianello, D. Gobled (Texas Instruments France)) Assessment of the Analytical Capabilities of Scanning Capacitance and Scanning Spreading Resistance Microscopy Applied to Semiconductor Devices M. Stangoni, M. Ciappa, W. Fichtner (ETH Zrich Switzerland) Dynamic Laser Stimulation Case Studies F. Beaudoin1, K. Sanchez1,2, R. Desplats1, P. Perdu1, J.M. Nicot1, J.P. Roux2, M. Otte3 (1CNES/THALES, 2Credence DCG France, 3Texas Instruments Germany) Electrical Performance Evaluation of FIB Edited Circuits through Chip Backside Exposing Shallow Trench Isolations U. Kerst, R. Schlangen, A. Kabakow, C. Boit (Berlin University of Technology Germany)

17:40 to 19:00

Workshop EUFANET : European Failure Analysis Network Room 3.5, third floor Mediator: Romain Desplats, CNES The 5th EUFANET workshop will focus on Diagnostic ATPG and CAD approaches for IC analysis. Issues are linking electrical test with IC diagnostics and manipulation of large CAD files.

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Thursday, October 13, morning Auditorium

SESSION B2 ESD Auditorium Chairs: H. Gieser, (Fraunhofer IZM, Mnchen - Germany) M. Bafleur, (LAAS CNRS - France) Invited Conference Trends and Challenges to ESD and Latch-Up Designs for Nanometer CMOS Technologies Gianluca Boselli, Charvaka Duvvury (Silicon Technology Development, Texas Instruments Inc. USA)
Different Failure Signatures of Multiple TLP and HBM Stresses in an ESD Robust Protection Structure N. Guitard1, F. Essely2, D. Trmouilles1,3, M. Bafleur1, N. Nolhier1, P. Perdu4, A. Touboul2, V. Pouget2, D. Lewis2 (1LAAS-CNRS, 2IXL University of Bordeaux - France, 3 Now with IMEC - Belgium, 4CNES-Thales lab - France) A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits H. Wolf1, H. Gieser1, W. Soldner2, H. Gossner3 (1Fraunhofer Institut of Mnchen, 2 Technische Universiteit Mnchen, 3Infineon Technologies Germany) A 3-D Circuit model to Evaluate CDM Performance of ICs M.S.B. Sowariraj, T. Smedes*, Peter C. de Jong*, C. Salm, T. Mouthaan, F.G. Kuper (University of Twente, *Philips Semidonductors The Netherlands) ESD Circuit Model Based Protection Network Optimisation for Extended-Voltage NMOS Drivers V. Vassilev1, V. Vashchenko3, Ph. Jansen1, G. Groeseneken1,2, M. Terbeek3 (1IMEC, 2 Katholieke Universiteit Leuven Belgium, 3National Semiconductor USA)

08:30

IP5

09:10

B2-1

09:30

B2-2

09:50

B2-3

10:10

B2-4

SESSION N

Noise degradation related to failure mechanisms Room 3.5, third floor Chairs : H. Hartnagel (TU Darmstadt Germany) N. Labat (IXL, University of Bordeaux - France) Invited Conference Accumulation of nonequilibrium phonons in biased channels for microwave power FETs and HEMTs Arvydas Matulionis, Juozapas Liberis (Semiconductor Physics Institute, Vilnius, Lithuania)
Dynamic-Stress-Induced High-Frequency Noise Degradation in NMOSFETs C. Yu, J.S. Yuan, A. Sadat* (University of Central Florida, *Conexant Systems USA) DC and Low Frequency Noise Analysis of Hot-Carrier Induced Degradation of Low Complexity 0.13 m CMOS Bipolar Transistors P. Benoit1,2, J. Raoult1, C. Delseny1, F. Pascal1, L. Snadny1, J-C. Vildeuil2, M. Marin2, B. Martinet2, D. Cottin2, O. Noblanc (1CEM University of Montpellier, 2ST Microelectronics France)

09:10

IP7

09:50

N1

10:10

N2

10:30

Coffee break

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Thursday, October 13, morning

SESSION G Reliability of Power Devices Auditorium Chairs: E. Wolfgang (Siemens - Germany) M. Ciappa (ETH Zrich - Switzerland) Invited Conference Interconnect Reliability in Power Electronic Modules Patrick McCLUSKEY (CALCE-University of Maryland - USA)
Reliability of Contacts for Press-Pack High-Power Devices J. Vobecky, D. Kolesnikov (Czech Technical University of Prague Czech Republic) Effects of Uniaxial Mechanical Stress on IGBT Characteristics M. Usui, M. Ishiko, K. Hotta, S. Kuwano, M. Hashimoto (Toyota Inc. Japan) Automated Setup for Thermal Imaging and Electrical Degradation Study of Power DMOS Devices M. Heer1, V. Dubec1, M. Blaho1, S. Bychikhin1, D. Pogany1, E. Gornik1, M. Denison2, M. Stecher2, G. Groos3 (1Vienna University of Technology Austria, 2Infineon Technologies, 3 University of the Federal Armed Forces Mnich Germany)

10:50

IP6

11:30 11:50 12:10

G1 G2 G3

SESSION C

Electron and Optical Beam Test Room 3.5, third floor Chairs: L. Balk (University of Wuppertal - Germany) R. Cramer (Altis Semiconductor - France)

10:50

C1

11:10

C2

11:30 11:50

C3 C4

NIR Laser Stimulation for Dynamic Timing Analysis K. Sanchez1,2,3, R. Desplats1, F. Beaudoin1, P. Perdu1, J.P. Roux2, G. Woods2, D. Lewis3 (1CNES-TES, 2Credence DCG, 3IXL University of Bordeaux France) Impact of semiconductors Materials on NIR Laser Stimulation Signal A. Firiti1, F. Beaudoin2, G. Haller1, P. Perdu2, D. Lewis3, P. Fouillat3 (1STMicroelectronics, 2CNES-THALES, 3IXL University of Bordeaux France) Photon Emission Microscopy of inter/intra Chip device Performance Variations S. Polonsky, M. Bhushan, A. Gattiker, A. Weger, P. Song (IBM USA) Light Emission to Time resolved Emission for IC Debug and Failure Analysis M. Remmach1, A. Pigozzi1, R. Desplats1, P. Perdu1, D. Lewis2, J. Noel3, S. Dudit3 (1CNES-TES, 2IXL University of Bordeaux, 3STMicroelectronics France)

12:30

Lunch

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Thursday, October 13, afternoon

SESSION G Reliability of Power Devices(Contd) Auditorium Chairs : E. Wolfgang (Siemens - Germany) M. Ciappa (ETH Zrich - Switzerland)
14:00 G4 Extraction of Accurate Compact Models for Fast Electro-Thermal Simulation of IGBT Modules for Hybrid Electric Vehicles M. Ciappa, W. Fichtner, T. Kojima*, Y. Yamada*, Y. Nishibe* (ETH Zrich Switzerland, *Toyota Inc. Japan) Assessment of the Trench IGBT Reliability: Low Temperature Experimental Characterization S. Azzopardi, A. Benansour, M. Ishiko*, E. Woirgard (IXL University of Bordeaux France, *Toyota Inc. Japan) Reliability Enhancement with the Aid of Transient Infrared Thermal Analysis of Smart Power MOSFETs during Short Circuit Operation A. Irace, G. Bregho, P. Spirito, R. Letor*, S. Russo* (Universita degli Studi di Napoli, *ST Microelectronics Italy) Experimental and Numerical Investigation about SEB/SEGR of Power MOSFET G. Busatto, A. Porzio, F. Velardi, F. Iannuzzo, A. Sanseverino, G. Curro* (University of Cassino, *ST Microelectronics Italy) Innovative Methodology for Predictive Reliability of Intelligent Power Devices Using Extreme Electro-thermal Fatigue B. Khong1, P. Tounsi2, P. Dupuy3, X. Chauffeur4, M. Legros1, A. Deram3, C. Levade1, G. Vanderschaeve1, J-M. Dorkel2, J-P. Fradin4 (1CEMES-CNRS, 2LAAS-CNRS, 3Freescale Semiconductors, 4Epsilon Ingnierie, France)

14:20

G5

14h40

G6

15:00

G7

15:20

G8

SESSION C

Electron and Optical Test (Contd) Room 3.5, third floor Chairs: L. Balk (University of Wuppertal - Germany) R. Cramer (Altis Semiconductor - France)

14:00

C5

14:40 15:00 15:20

C6 C7 C8

Electrostatic Discharge Fault Localization by Laser Probing S. Grauby, A. Sahli, W. Claeys, D. Trias*, S. Dilhaire (CPMOH University of Bordeaux, *Serma Technologies France) Seebeck Effect Detection on Biased Device without OBIRCH Distortion Using FET Readout S. K. Brahma, C. Boit, A. Glowacki (Berlin University of Technology Germany) Innovative Packaging Technique for Backside Optical Testing of Wire-Bonded Chips A. Tosi, F. Stellari*, F. Zappa (Politecnico di Milano Italy, *IBM USA) Two-dimensional dopant profiling and imaging of 4H silicon carbide devices by secondary electron potential contrast M. Buzzo1,2, M. Ciappa2, M. Stangoni2, W. Fichtner2 (1Infineon Technologies - Austria, 2ETH Zrich Switzerland)

15:40

Coffee break

16:00 to 17:30 Parallel sessions - Poster Session (second floor) - Annual Power Devices Workshop (Room 5.3, third floor): Lead free solders for power electronics or Thermal interface materials Moderators : E. Wolfgang, Siemens (Germany) M. Ciappa, ETH Zrich (Switzerland) 19:00 Bus departure for the gala diner

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Friday, October 14, morning

SESSION F Packaging, Assemblies and passive components reliability Auditorium Chairs: W. Wondrak, (DaimlerChrysler Germany) Y. Danto (IXL-University of Bordeaux - France) Invited Conference Failure Mechanisms and Qualification Testing of Passive Components H. A. Posta, P. Letullierb, T. Briolatc, R. Humked, R. Schuhmannd, K. Saarinene, W. Wernerf, Y. Ousteng, G. Lekensh, A. Dehbii, and W. Wondraki (aVishay BCcomponents B.V., The Netherlands - b,c Temex SA, France - d EPCOS AG,
Germany - e Evox Rifa OY, Finland - f Vishay BCcomponents Beyschlag GmbH, Germany IXL Universite Bordeaux, France - h IMEC vzw/Division IMOMEC, Belgium i DaimlerChrysler AG, Germany) Prediction of Delamination Related IC & Packaging Reliability Problems W.D. van Driel, M.A.J. van Gils*, R.B.R. van Silfhout*, G.Q. Zhang (Philips Semiconductors, *Philips Applied Technologies The Netherlands) Isolating Failing Sites in IC Packages using Time Domain Reflectometry : Case Studies D. Abessolo-Bidzo, P. Poirier, P. Descamps, B. Domengs (LAMIP-Philips Semiconductors France)
g

09:00

IP8

09:40

F1

10:00

F2

10:20 SESSION F

Coffee break Packaging, Assemblies and passive components reliability Auditorium Chairs: W. Wondrak, (DaimlerChrysler - Germany) Y. Danto (IXL-University of Bordeaux - France)

10:40

F3

11:00

F4

11:20

F5

12:00

F6

New experimental Approach for Failure Prediction in Electronics : Topography and Deformation Measurement Complemented with Acoustic Microscopy I. Richard, R. Fayolle, J-Cl. Lecomte (Insidix France) Correlation between Experimental Results and FE Simulations to Evaluate Lead-Free BGA Assembly Reliability A. Gudon-Gracia, E. Woirgard, C. Zardini (IXL University of Bordeaux France) Vibration Lifetime Modelling of PCB Assemblies using Steinberg Model A. Dehbi, W. Wondrak (DaimlerChrysler Germany) Y. Ousten, Y. Danto (IXL University of Bordeaux France) Moisture Diffusion in Printed Circuit Boards: Measurements and Finite-Element Simulations K. Weide-Zaage1, W. Horaud2, H. Frmont3 (1University of Hannover Germany, 2 Solectron, 3IXL University of Bordeaux France)

12:20 12:40 13:30

Announcement of ESREF 2003 Best Papers Awards Conference closing session Bus departure to Bordeaux Merignac Airport

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POSTERS
The Poster session is scheduled on Thursday, October 13 from 16:00 to 17:30. SESSION A AP1 Quality and Reliability Techniques for Devices and Systems Method for

Robust, Versatile, Direct Low-Frequency Noise Characterization Material/Process Quality Control Using Cross-Shaped 4-Terminal Devices A. Kerlain, V. Mosser (Itron France) Failure Mechanisms in Silicon Devices

SESSION B BP1

BP2

BP3

BP4

BP5

BP6 BP7

Hot Carrier and Soft Breakdown Effects on LNA Performance for Ultra Wideband Communications E. Xiao, P. P. Ghosh, C. Yu*, J.S. Yuan* (University of Texas at Arlington, *University of Central Florida USA) The Impact of Static and Dynamic Degradation on SOI Smart-Cut Floating Body MOSFETs M.A. Exarchos, G.J. Papaioannou, J. Jomaah*, F. Balestra* (National and Kapodistrian University of Athens Greece, *IMEP ENSERG France) Pre- and post- BD electrical conduction of stressed HfO2/SiO2 MOS gate stacks observed at the nanoscale L. Aguilera, M. Porti, M. Nafria, X. Aymerich (Universitat Autonoma de Barcelona Spain) Elimination of Surface State Induced Edge Transistors in High Voltage NMOSFETs for Flash Memory Devices Jin-Wook Lee, Gyoung-Ho Buh, Guk-Hyon Yon, Tsai-su Park, Yu-Gyun Shin, U-In Chung, Joo-Tae Moon (Samsung Korea) Damage Root Isolation about Field Lightning Surge Failure of High Voltage BJT Based Line Driver for ADSL System J. S. Jeong, Jae-Hyun Lee, Jong Shin Ha, Sang Deuk Park (Samsung Electronics Korea) Voltage Stress-Induced Hot Carrier Effects on SiGe HBT VCO Chuangzhao Yu, Enju Xiao*, J.S. Yuan (University of Central Florida, * University of Texas at Arlington USA) Reliability Improvement by the Suppression of Keyhole Generation in W-Plug Vias Jong Hun Kim, Kyosun Kim, Seok Hee Jeon, Jong Tae Park (University of Incheon Korea) Electron and Optical Beam Testing (EOBT)

SESSION C CP1

Circuit-internal signal measurements with a needle sensor C. Hartmann, W. Mertin, G. Bacher (Universitt Duisburg-Essen Germany) Advanced Failure Analysis: sample preparation, case studies

SESSION D DP1 DP2

DP3

DP4

Characterization of a 0.13 m CMOS Link Chip using Time Resolved Emission (TRE) J.F. Stellari, P. Song, J. Hryckowian, O.A. Torreiter*, S. Wilson, P. Wu (IBM USA, *IBM Germany) Localization of Marginal Circuits for Yield Diagnostics Utilizing a Dynamic Laser Stimulation Probing System J.Y. Liao, G.L. Woods*, X. Chen, H.L. Marks, (NVIDIA, *Credence Systems USA) Characterisation of Dopants Distribution using Electron Holography and FIB-Based Lift-off preparation U. Muehle, A. Lenk*, R. Veiland, H. Lichte* (Infineon Technologies, *Dresden University Germany) SRAM Cell Defect Isolation Methodology by Sub Micron Probing Technique
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DP5

DP6

DP7 DP8

F. Sibileau, C. Ali, C. Giret, D. Faure (Texas Instruments France) Intermittent Contact Scanning Capacitance Microscopy An Improved Method for 2D Doping Profiling P. Breitschopf1, G. Benstetter1, B. Knoll2, W. Frammelsberger1,3 (1University of Applied Sciences Deggendorf, 2Infineon Technologies Germany, 3University of the West of England United Kingdom) Non-Destructive Identification of Open Circuit in Wiring on Organic Substrate with High Wiring Density Covered with Solder Resist C. Ming Tan, K. Peng Lim, T. Chong Chai*, G. Cheng Lim, (Nanyang Technological University, *Institute of Microelectronics Singapore) Die Repackaging for Failure Analysis S. Barberan, E. Auvray (ST Microelectronics France) Image alignment for 3D reconstruction in a SEM R. Pintus, S. Podda, M. Vanzi (University of Cagliari Italy) Failure Mechanisms in Microwave, High Bandgap and Photonic Devices

SESSION E EP1 EP2

A 3000 Hours DC Life Test on AlGaN/GaN HEMT for RF and Microwave Applications A. Sozza1,2,3, C. Dua1, E. Morvan1, B. Grimber1, S. Delage1 (1Alcatel-Thales III-V Lab. France, 2Universita Degli Studi di Padova Italy, 3IXL University of Bordeaux - France) Performances and limitations analyses of PHEMT and MHEMT for applications in high bit rate fibre-optic systems O. Pajona, C. Aupetit-Berthelemot, R. Lefevre*, J.M. Dumas, (ENSIL-University of Limoges, *Alcatel-Thales III-V Lab France) Packaging, Assemblies and passive components reliability

SESSION F FP1

FP2

A Simple Moisture Diffusion model for the Prediction of Optimal Baking Schedules for Plastic SMD Packages K. Chooi Lee, A. Vythilingam*, P. Alpern* (Infineon Technologies Germany, *Infineon Technologies Asia Pacific Singapore) Reliability Potential of Epoxy Based Encapsulants for Automotive Applications T. Braun, K.F. Becker, M. Koch, V. Bader, R. Aschenbrenner, H. Reichl (Fraunhofer Institute for Reliability and Microintegration & Technical University Berlin Germany) Power Devices Reliability

SESSION G GP1

GP2 GP3 GP4

GP5 GP6

Reliability Screening through Electrical Testing for Press-Fit Alternator Power Diode in Automotive Application C. Ming Tan1, J. Chiu2, R. Liu3, G. Zhang4 (1Nanyang Technological University, 4Integrated Business and Engineering Pte Singapore, 2Actron Technology Corp., 3Poworld Electronics Co. Tawan) Trench Insulated Gate Bipolar Transistors Submitted to High Temperature Bias Stress C.O. Maga, H. Toutah, B. Tala-Ighil, B. Boudart (LUSAC Cherbourg France) Comparative Analysis of Accelerated Ageing Effects on Power RF LDMOS Reliability M.A. Belad, K. Ketata, K. Mourgues, H. Maanane, M. Masmoudi, J. Marcon (LEMI University of Rouen France) Non Destructive Testing Technique for MOSFET's Characterisation during Soft-Switching ZVS Operations F. Iannuzzo (University of Cassino Italy) The Role of IGBT Module in Electromagnetic Noise Emission of Power Converters C. Abbate, G. Busatto, F. Iannuzzo, L. Fratelli (University of Cassino Italy) A Novel fast and Versatile Temperature Measurement System for LDMOS Transistors A. Tazzoli, G. Meneghesso, E. Zanoni (University of Padova Italy)
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GP7

Specification and use of pulsed current profiles for ultracapacitors power cycling W. Lajnef, J-M. Vinassa, O. Briat, E. Woirgard (IXL University of Bordeaux France) MEMS/MOEMS, Sensors and Actuators reliability

SESSION H HP1 HP2 HP3

Investigation of Charging Mechanisms in Metal-Insulator-Metal Structures M. Exarchos, V. Theonas, P. Pons*, G.J. Papaioannou, S. Mell*, D. Dubuc*, F. Coccetti*, R. Plana* (University of Athens, *LAAS-CNRS France) Failure Analysis of Micro-Heating Elements Suspended on Thin Membranes D. Briand1, F. Beaudoin2, J. Courbat1, N.F. de Rooij1, R. Desplats2, Ph. Perdu2 , (1University of Neuchtel Switzerland, 2CNES-TES lab. France) Thermal and Electrostatic Reliability Characterization in RF MEMS Switches Q.-H. Duong1,2, F. Flourens4, L. Buchaillot1, D. Collard1, P. Schmitt3, X. Lafontan3, P. Pons4, F. Pressecq2 (1IEMN Lille, 2CNES, 3NovaMEMS, 4LAAS-CNRS France)

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