Design Example: Counters

Counter: a sequential circuit that repeats a

specified sequence of output upon clock pulses.
A,B,C,, Z. G, O, T, E, R, P, S, !. 0,1,2,3,4,5,6,7. 7,6,5,4,3,2,1,0. 0,1,0,0,1,2,3,2,3,2,2,1.

Design Example: Counters

Other useful counters:
Decimal counter (e.g. BCD counter)
0000,0001,0010,,1000,1001,0000,0001,

Modulo-k counter
Modulo-5 counter: 0,1,2,3,4,0,1,2,

M-to-N counter
3-to-8 counter: 3,4,5,6,7,8,3,4,

Binary counter: follows the binary sequence.

2-bit (up) binary counter: 0,1,2,3. 3-bit down binary counter: 7,6,5,4,3,2,1,0
ENEE244: Digital Logic Design

Ripple counter Ring counter and Johnson counter

ENEE244: Digital Logic Design

3-Bit Binary Counter

000 001 010 011
0 0 1 1 0 1 0 1

3-Bit Binary Counter

Flip-flop input functions
TA = BC TB = C TC = 1
CP 1

111 110 101 100

T 0 1 1 0 current state next state flip-flop inputs A B C A B C TA TB TC

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 1 1 1 0

0 1 1 0 0 1 1 0

1 0 1 0 1 0 1 0

0 0 0 1 0 0 0 1

0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 1

T Q 0 >

T Q 0 >

T Q 0 >

Q(t) Q(t+1)

Figure 6.32 gives a 4-bit binary counter. When Q0=C, Q1=B, Q2=A, delete Q3, set Count enable bit to be constant 1, it becomes this 3-bit counter.
ENEE244: Digital Logic Design

ENEE244: Digital Logic Design

CP

Binary Counter with JK Flip-Flops

Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 J 0 1 x x K x x 1 0

>
K A1 0 1 0 1 0 1 0 1 0 1 J J

Q Q

A1

Count-Down Binary Counter

A4 A3 1 1 1 1 0 0 0 0 1 1 A2 1 1 0 0 1 1 0 0 1 1 A1 1 0 1 0 1 0 1 0 1 0

CP E
J

>
K

Q Q

A1

A4 0 0 0 0 0 0 0 0 1 1

A3 0 0 0 0 1 1 1 1 0 0

A2 0 0 1 1 0 0 1 1 0 0

>
K

Q Q

A2

when E = 1 and CP goes from 0 to 1:

A1 A2 A3 A4

>
K

Q Q

A3

>
K

Q Q

A4

Exercise: Verify that the circuit is a binary counter that counts down from 15 to 0, and then back to 15 again.

1 1 1 1 1 1 1 1 0 0

>
K

Q Q

A2

>
K

Q Q

A3

>
K

Q Q

A4

ENEE244: Digital Logic Design

ENEE244: Digital Logic Design

Summary
Sequential circuit design example
Shift registers Basic counters

Binary Counter with Parallel Load

2 control signals, 3 modes:
Load (Qi=Di) Load = 1 Count (up) Load = 0, Count = 1 No change Load = 0, Count = 0 (change, load or count, happens only at positive edge of the clock pulse.)
D0 D1 D2 D3 Q0 Q1 Q2 Q3

Next time
Binary counter with parallel load Ripple counter Johnson counter

Next Monday: Exam IV

PLD, Chapter 6, 7.1, 7.2 Discussion on Wednesdays class
ENEE244: Digital Logic Design

Carry Out: 1 if and only if the counter is in count mode with content 1111. Read Figure 6.34 for the detailed implementation.
ENEE244: Digital Logic Design

Load Count

CO

>4-bit count

load
0 1 2 3 4 5 6 7 15

Modulo-7 Counter
0 0 15 14 13 12 11 10 9 8
ENEE244: Digital Logic Design

load
15 14 13 12 11

3-To-8 Counter
0 15 14 13 12 11 10

14 1 13 2 12

modulo-7
(when to load)

1 2 D0 D1 D2 D3 Q0 Q1 Q2 Q3 5 6 7 3 4

0 0 1 1 1

D0 D1 D2 D3

Q0 Q1 Q2 Q3

1 2 3 4 3-to-8 (when and what to load) 5

load 3
11 4 10 5 9 6 8 7

0 0 0 0 1

Load Count

CO

10 9

Load Count

CO

>4-bit count

load
6 9 8

>4-bit count

8 7
ENEE244: Digital Logic Design

modulo-16

modulo-16

Design Example
8-bit counter with two 4-bit counters
D0 D1 D2 D3 0 1 D0 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 0 D1 D2 D3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Exam IV
PLD Timing diagram for basic latch/flip-flop Sequential circuit analysis Sequential circuit design Registers and counters

Load Count

Load Count

CO

CO

>4-bit count

>4-bit count

ENEE244: Digital Logic Design

ENEE244: Digital Logic Design

Ripple Counter
Synchronous counter: the CP signal of all flipflops are from the common clock.

BCD Ripple Counter

Verify the following circuit is a BCD Ripple counter triggered by negative edge.
Q1 Q2 Q4 Q8

Ripple counter: the CP of some flip-flops are

from other flip-flops (and through logic gates). Ripple counter is asynchronous Binary ripple (up) counter (read Figure 6.31) Binary ripple down counter Where the CP signal comes from? (By default, flip-flop is positive edge triggered.)
ENEE244: Digital Logic Design

CP

>
K

Q Q

>
K

Q Q

>
K

Q Q

>
K

Q Q

ENEE244: Digital Logic Design

BCD Ripple Counter

Verify the following circuit is a BCD Ripple counter triggered by negative edge.
CP Q1 Q2 Q4 Q8
0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1

Ring Counter
Ring counter: a circular shift register
(with k flipflops) that at any time, only one flip-flop is set (having value 1) and all others are cleared (with value 0). It is used to generate k (periodic) timing signals.

Example: see Figure 6.37 for circuit.

CP
0

QA QD QC QB

0 0

0 0

0 0

0 0

1 0

1 0

1 0

1 0

0 1

0 1

0 0

0 0

ENEE244: Digital Logic Design

ENEE244: Digital Logic Design

Ring Counter as Counter + Decoder

To generate 4 (periodic) timing signals, we need
a 4-bit ring counter, or a 2-bit counter and a 2x4 decoder.
0 0

Johnson Counter
Johnson counter: a k-bit circular shift register with
the complement of the last flip-flop connected to the input of the first flip-flop, and 2k decoding gates. It is used to generate 2k (periodic) timing signals.

2-bit count
CP CO Load

Count

6 AND gates for decoding 2x4 decoder

3 2 1 0 D Q

S3

D Q

S2

D Q

S1

QD QC QBQA
ENEE244: Digital Logic Design

> CP

>

0 > Q

ENEE244: Digital Logic Design

Johnson Counter
D Q

S3

D Q

S2

D Q

S1

T1 = S3S1 T2 = S3S2 T3 = S2S1 T4 = S3S1 T5 = S3S2 T6 = S2S1

> CP states
S3 S2

>

0 > Q

AND gate for output

S1 T1 T2 T3 T4 T5 T6

1 2 3 4 5 6

0 1 1 1 0 0

0 0 1 1 1 0

0 0 0 1 1 1

1 1 1 1 1 1
ENEE244: Digital Logic Design

6 AND gates for decoding S3 S2 S1