ELEC3250 Notes - Power Electronics1

R.E. Betz School of Electrical Engineering and Computer Science University of Newcastle, Australia. email: Robert.Betz@newcastle.edu.au c 2012 April, 2012

First created: July 20, 2005 Revised on 2012-04-30 00:27:06 +1000 (Mon, 30 Apr 2012) by R.E. Betz SVN Version: 513

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Preface
The notes in this document are for a course in the School of Electrical Engineering and Computer Science at the University of Newcastle, Australia. This course covers a number of topics that can be broadly grouped under the title of power electronics. The rst section of the course will look at switch mode power supplies in their various forms. The main structures for switch mode power supplies will be considered. Again practical issues will be emphasised. Design of the magnetics for switching supplies will be considered, as well as some control issues. The control issues are only briey considered due to the lack of background of some students doing the course. The second part of the course considers high powered converter and inverter topologies. There will be an emphasis on the grid connection of converter technologies. An introduction to matrix converters is presented. Issues such as commutation, modulation strategies, and devices are covered. There are several appendices covering some useful topics which may be useful in the context of the remainder of these notes. It should be noted that these notes are constantly being added to, altered, correctly, clarications added in other words they are a work in progress. The latest version can be downloaded from anonymous ftp at: ftp://vcs2.newcastle.edu.au/Elec3250_Power_Electronics/elec3250_notes. pdf.

Robert E. Betz Newcastle, Australia, April, 2012.

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Revision History
April-May 2012 (REB) Made corrections and added new material on Space Vectors. April-May 2011 (REB) Added new chapter on grid interfacing and renewables. March 11 2011 (REB) Did some minor conversions of the le to allow operation in Subversion. Have also xed up some minor typos that were found last year. July 30 2010 (REB) Made a few wording error corrections in the rst chapter. Minor typos really. July 29 2010 (REB) Typo corrections from last year were made. Added a small section on the linear interpretation of switching poles as a DC-DC transformer. July 23 2009 (REB) Have added a number of sections. A whole section on matrix converters added. A new introductory chapter on Switching Basics added, several Appendices added space vectors, Syncrel inductances, imaginary power. July 25, 2008 (REB) Started adding a section on matrix converters. Still incomplete. July 24, 2008 (REB) Have converted the original Latex notes to Lyx. Complete compilation achieved. August 1, 2005 (REB) The initial distribution version for the students. Some additions have been made for snubbing circuits, but at this stage these additions are incomplete. There have also been some changes made to the Appendix on second order circuits. July 20, 2005 (REB) The initial version of these notes was constructed from the notes that were developed for Elec3230. The main dierence with the current set of notes is that they no longer include the section on digital switching and printed circuit boards. This initial version basically was the Elec3230 notes with the digital switching cut out. As the notes develop new sections will be added with respect to high power power electronics.

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Contents
List of Figures List of Tables Nomenclature xv xxiii xxv

Switched Mode Power Supplies

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1
1-1 1-1 1-2 1-4 1-4 1-6 1-8 1-10 1-18 2-1 2-1 2-1 2-2 2-2 2-4 2-5 2-7 2-9 2-11 2-11 2-11 2-14 2-14 2-16 2-18

1 Switching Basics 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Why Use Switching? . . . . . . . . . . . . . . . . . . . . 1.3 Taxonomy of Power Electronic Systems . . . . . . . . . 1.3.1 Naturally Commutated Systems . . . . . . . . . 1.3.2 Forced Commutated Systems . . . . . . . . . . . 1.3.2.1 Linearising the Non-linear System . . . 1.3.2.2 Basics of PWM and Frequency Spectra 1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Fundamental Topologies 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Taxonomy of Switch Mode Converters . . . . . . . . . . . . . . . 2.3.1 Step-down or Buck Converters . . . . . . . . . . . . . . . 2.3.2 Step-up or Boost Converters . . . . . . . . . . . . . . . . 2.3.3 BuckBoost Converters . . . . . . . . . . . . . . . . . . . 2.3.4 Ck Converters . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 Full Bridge Converters . . . . . . . . . . . . . . . . . . . . 2.4 Basic Analysis of Switch Mode Converters . . . . . . . . . . . . . 2.4.1 Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Basic PWM Generator . . . . . . . . . . . . . . . . . . . . 2.4.3 Simplied Analysis of the Buck Converter . . . . . . . . . 2.4.3.1 Continuous Conduction Mode . . . . . . . . . . 2.4.3.2 Boundary between Continuous and Discontinuous Conduction . . . . . . . . . . . . . . . . . . 2.4.3.2.1 Discontinuous Current with Constant Vd . . . . . . . . . . . . . . . . . . . . .

viii 2.4.3.2.2

CONTENTS Discontinuous Current with Constant Vo . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.3.3 Output Ripple . . . . . . . . . . . . . . . . . . . 2-23 2.4.3.4 Simulation . . . . . . . . . . . . . . . . . . . . . 2-25 2.4.4 Simplied Analysis of the Boost Converter . . . . . . . . 2-28 2.4.4.1 Continuous Conduction Mode . . . . . . . . . . 2-28 2.4.4.2 Boundary between Continuous and Discontinuous Conduction . . . . . . . . . . . . . . . . . . 2-28 2.4.4.2.1 Discontinuous Current with Constant Vd .2-31 2.4.4.3 Simulation . . . . . . . . . . . . . . . . . . . . . 2-33 2.4.5 A Brief Look at the Buck-Boost Converter . . . . . . . . 2-36 2.4.6 A Brief Analysis of the Ck Converter . . . . . . . . . . . 2-36 2.4.7 Full Bridge dc-dc Converter . . . . . . . . . . . . . . . . . 2-38 2.4.7.1 Bipolar Switching . . . . . . . . . . . . . . . . . 2-39 2.4.7.2 Unipolar Switching . . . . . . . . . . . . . . . . 2-42 2.4.8 Comparison of Basic Converter Topologies . . . . . . . . . 2-44 2.4.8.1 Switch Utilisation . . . . . . . . . . . . . . . . . 2-44 2.4.8.1.1 Buck Converter . . . . . . . . . . . . . 2-45 2.4.8.1.2 Boost Converter . . . . . . . . . . . . . 2-45 2.4.8.1.3 Buck-Boost Converter . . . . . . . . . . 2-46 2.4.8.1.4 Full Bridge Converter . . . . . . . . . . 2-47 2.4.9 Synchronous Rectiers . . . . . . . . . . . . . . . . . . . . 2-49 2.4.10 Switching Losses and Snubber Circuits . . . . . . . . . . . 2-50 2.4.10.1 Diode Snubbers . . . . . . . . . . . . . . . . . . 2-51 2.4.10.2 Snubbers for Thyristors . . . . . . . . . . . . . . 2-58 2.4.10.3 Snubbers and Transistors . . . . . . . . . . . . . 2-58 2.4.11 Resonant and Soft-Switching Converters . . . . . . . . . . 2-65 2.4.11.1 Why One Should Not Use Resonant Converters 2-67 2.4.11.2 Why One Should Use Quasi-Resonant Converters 2-67 2.4.12 Example: ZVS Converter Design and Analysis . . . . . . 2-68 3 Switch Mode Power Supplies 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Isolated Converter Topologies . . . . . . . . . . . . . . . . . . . . 3.2.1 The Forward Converter . . . . . . . . . . . . . . . . . . . 3.2.1.1 Other Forward Converter Topologies . . . . . . . 3.2.1.1.1 Two Switch Converter . . . . . . . . . . 3.2.1.1.2 Push-Pull Converter . . . . . . . . . . . 3.2.2 The Flyback Converter . . . . . . . . . . . . . . . . . . . 3.2.3 Utilisation of Magnetics . . . . . . . . . . . . . . . . . . . 3.3 Introduction to Control Techniques for Switching Power Supplies 3.3.1 Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Protection Issues . . . . . . . . . . . . . . . . . . . . . . . 3.3.2.1 Soft Start . . . . . . . . . . . . . . . . . . . . . . 3.3.2.2 Voltage Protection . . . . . . . . . . . . . . . . . 3.3.2.3 Current Limiting . . . . . . . . . . . . . . . . . . 3.3.3 Control Architecture of a Switch Mode Power Supply System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.1 Voltage Mode Control . . . . . . . . . . . . . . . 3.3.3.2 Voltage Feed-forward PWM Control . . . . . . . 3-1 3-1 3-1 3-1 3-7 3-7 3-7 3-12 3-18 3-22 3-25 3-27 3-27 3-28 3-28 3-30 3-30 3-33

CONTENTS 3.3.3.3 Current Mode Control . . . . . . . . . . . . . . . 3-33 3.3.3.3.1 Slope Compensation . . . . . . . . . . . 3-37 Sup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-1 4-1 4-2 4-2 4-2 4-3 4-3 4-3 4-4 4-4 4-5 4-6 4-6 4-7 4-7 4-8 4-8 4-8 4-9 4-9 4-9 4-9 4-10 4-12 4-12 4-13 4-13 4-14 4-14 4-14 4-15 4-15 4-16 4-16 4-17 4-19 4-20 4-20 4-20 4-21 4-22 4-22 4-23 4-23 4-24

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4 Introduction to Practical Design of Switch Mode Power plies 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Component Selection . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1.1 Values . . . . . . . . . . . . . . . . . . . . . 4.2.1.2 Resistor Types . . . . . . . . . . . . . . . . 4.2.1.3 Tolerance . . . . . . . . . . . . . . . . . . . 4.2.1.4 Selecting Values . . . . . . . . . . . . . . . 4.2.1.5 Maximum Voltage . . . . . . . . . . . . . . 4.2.1.6 Temperature Coecient . . . . . . . . . . . 4.2.1.7 Power Rating . . . . . . . . . . . . . . . . . 4.2.1.8 Shunts . . . . . . . . . . . . . . . . . . . . 4.2.1.9 PCB Track Resistors . . . . . . . . . . . . 4.2.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . 4.2.2.1 Types of Capacitors . . . . . . . . . . . . . 4.2.2.2 Standard Values . . . . . . . . . . . . . . . 4.2.2.3 Tolerance . . . . . . . . . . . . . . . . . . . 4.2.2.4 ESR and Power Dissipation . . . . . . . . . 4.2.2.5 Aging . . . . . . . . . . . . . . . . . . . . . 4.2.2.6 dv/dt Rating . . . . . . . . . . . . . . . . . 4.2.2.7 Series Connection of Capacitors . . . . . . 4.2.3 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3.1 Schottky Diodes . . . . . . . . . . . . . . . 4.2.3.2 PN diodes . . . . . . . . . . . . . . . . . . 4.2.4 The BJT . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 The MOSFET . . . . . . . . . . . . . . . . . . . . . 4.2.5.1 Bi-directional Conduction . . . . . . . . . . 4.2.5.2 Power Losses . . . . . . . . . . . . . . . . . 4.2.5.3 MOSFET Gate Resistors . . . . . . . . . . 4.2.5.4 Maximum Gate Voltage . . . . . . . . . . . 4.2.6 Operational Ampliers . . . . . . . . . . . . . . . . . 4.2.6.1 Osets . . . . . . . . . . . . . . . . . . . . 4.2.6.1.1 Input Oset Voltage . . . . . . . . 4.2.6.1.2 Input Oset Current . . . . . . . . 4.2.6.1.3 Input Bias Current . . . . . . . . 4.2.6.2 Limits on Resistor Values . . . . . . . . . . 4.2.6.3 Gain-Bandwidth Product . . . . . . . . . . 4.2.6.4 Phase Shift . . . . . . . . . . . . . . . . . . 4.2.6.5 Slew Rate Limits . . . . . . . . . . . . . . . 4.2.7 Comparators . . . . . . . . . . . . . . . . . . . . . . 4.2.7.1 Hysteresis . . . . . . . . . . . . . . . . . . . 4.2.7.2 Comparator Interfacing . . . . . . . . . . . 4.3 Introduction to Magnetics Design . . . . . . . . . . . . . . . 4.3.1 Review of the Fundamentals . . . . . . . . . . . . . 4.3.1.1 Amperes Law . . . . . . . . . . . . . . . . 4.3.1.2 Faradays Law . . . . . . . . . . . . . . . .

x 4.3.1.3 4.3.1.4 4.3.1.5

CONTENTS Inductance . . . . . . . . . . . . . . . . . . . . . A Note on Units . . . . . . . . . . . . . . . . . . The Three Rs . . . . . . . . . . . . . . . . . . . 4.3.1.5.1 Reactance . . . . . . . . . . . . . . . . 4.3.1.5.2 Remanence . . . . . . . . . . . . . . . . 4.3.1.5.3 Reluctance . . . . . . . . . . . . . . . . The Ideal Transformer . . . . . . . . . . . . . . . . . . . . Real Transformers . . . . . . . . . . . . . . . . . . . . . . 4.3.3.1 Core Materials . . . . . . . . . . . . . . . . . . . 4.3.3.2 Saturation . . . . . . . . . . . . . . . . . . . . . 4.3.3.3 Other Core Limitations . . . . . . . . . . . . . . 4.3.3.3.1 Curie Temperature . . . . . . . . . . . 4.3.3.3.2 Core Losses . . . . . . . . . . . . . . . . Optimal Design Issues . . . . . . . . . . . . . . . . . . . . Design of an Inductor . . . . . . . . . . . . . . . . . . . . 4.3.5.1 Key Magnetic Parameters . . . . . . . . . . . . . 4.3.5.1.1 Initial Permeability . . . . . . . . . . . 4.3.5.1.2 Eective Permeability . . . . . . . . . . 4.3.5.1.3 Amplitude Permeability . . . . . . . . . 4.3.5.1.4 Incremental Permeability . . . . . . . . 4.3.5.1.5 Eective Core Dimensions . . . . . . . 4.3.5.1.6 Inductance Factor . . . . . . . . . . . . 4.3.5.2 Details of Inductor Design . . . . . . . . . . . . 4.3.5.3 Issues in Forward Converter Transformer Design 4.3.5.3.1 Turns Ratio = 1:1 . . . . . . . . . . . . 4.3.5.3.2 Turns Ratio = 2:1 . . . . . . . . . . . . 4.3.5.3.3 Turns Ratio = 3:1 . . . . . . . . . . . . 4.3.5.3.4 Turns Ratio = 4:1 . . . . . . . . . . . . Design of Manufacturable Magnetics . . . . . . . . . . . . 4.3.6.1 Wire Gauge . . . . . . . . . . . . . . . . . . . . 4.3.6.2 Wire Gauge Ratio . . . . . . . . . . . . . . . . . 4.3.6.3 Toroidal Core Winding Limits . . . . . . . . . . 4.3.6.4 Tape versus Wire Insulation . . . . . . . . . . . 4.3.6.5 Layering of Windings . . . . . . . . . . . . . . . 4.3.6.6 Number of Windings . . . . . . . . . . . . . . . 4.3.6.7 Potting . . . . . . . . . . . . . . . . . . . . . . . 4.3.6.8 Safety Requirements . . . . . . . . . . . . . . . . 4-24 4-26 4-26 4-26 4-26 4-27 4-27 4-29 4-30 4-32 4-32 4-32 4-32 4-33 4-35 4-38 4-38 4-38 4-38 4-38 4-39 4-39 4-40 4-46 4-47 4-47 4-47 4-47 4-48 4-48 4-48 4-48 4-49 4-49 4-50 4-50 4-50

4.3.2 4.3.3

4.3.4 4.3.5

4.3.6

II Line Commutated Converters and High Power Inverters 4-53

5 Introduction to High Power Converter Technology 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Applications of Power Converter Technology 5.2 Review of Power Semiconductor Devices . . . . . . . 5.2.1 Diodes . . . . . . . . . . . . . . . . . . . . . . 5.2.1.1 Series Diodes . . . . . . . . . . . . . 5.2.2 Thyristors . . . . . . . . . . . . . . . . . . . . 5.2.2.1 Turn-on Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-1 5-3 5-3 5-8 5-8 5-11

CONTENTS 5.2.2.2 Turn-o Transient . . . . . . . . . . . . Gate Turn-o Thyristors . . . . . . . . . . . . . . 5.2.3.1 Snubbers and GTO Thyristors . . . . . 5.2.3.2 GTO Turn-on . . . . . . . . . . . . . . 5.2.3.3 GTO Turn-o . . . . . . . . . . . . . . Insulated Gate Bipolar Transistors (IGBTs) . . . 5.2.4.1 IGBT Operation . . . . . . . . . . . . . 5.2.4.2 IGBT Turn-on . . . . . . . . . . . . . . 5.2.4.3 IGBT Turn-o . . . . . . . . . . . . . . Other Devices and Developments . . . . . . . . . 5.2.5.1 Power Junction Field Eect Transistors 5.2.5.2 Field Controlled Thyristor . . . . . . . 5.2.5.3 MOS-Controlled Thyristors . . . . . . . 5.2.5.4 New Semiconductor Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5-13 5-15 5-17 5-17 5-21 5-22 5-24 5-25 5-26 5-26 5-26 5-26 5-27 6-1 6-1 6-1 6-2 6-3 6-5 6-11 6-11 6-11 6-13 6-15 6-19 6-25 6-30 6-31 6-32 6-34

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5.2.3

5.2.4

5.2.5

6 Line Frequency Uncontrolled Rectiers 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Some Mathematical Preliminaries . . . . . . . . . . . . . . . . . . 6.2.1 Fourier Analysis of Repetitive Waveforms . . . . . . . . . 6.2.1.1 Measures of Waveform Distortion . . . . . . . . 6.2.1.2 Power and Power Factor . . . . . . . . . . . . . 6.3 The Half Wave Rectier Circuit . . . . . . . . . . . . . . . . . . . 6.3.1 Pure Resistive Load . . . . . . . . . . . . . . . . . . . . . 6.3.2 Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Inductive Load with Back EMF . . . . . . . . . . . . . . . 6.4 The Concept of Current Commutation . . . . . . . . . . . . . . . 6.5 Practical Uncontrolled Single Phase Rectiers . . . . . . . . . . . 6.5.1 Unity Power Factor Single Phase Rectier . . . . . . . . . 6.5.2 Eect of Current Harmonics on Line Voltages . . . . . . . 6.5.3 Voltage Doubler Single Phase Rectiers . . . . . . . . . . 6.5.4 The Eect of Single Phase Rectiers on Three Phase, Four Wire Systems . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Three Phase, Full Bridge Rectiers . . . . . . . . . . . . . . . . .

7 Introduction to Other Power Electronic Devices and Applications 7-1 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 Inverters and Applications . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2.1 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . 7-4 7.2.1.1 Space Vectors and PWM . . . . . . . . . . . . . 7-8 7.2.2 Dead-time Issues . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.2.3 Some Inverter Applications . . . . . . . . . . . . . . . . . 7-15 7.2.3.1 Variable Speed Drives . . . . . . . . . . . . . . . 7-15 7.2.3.2 Grid Connected Applications . . . . . . . . . . . 7-17 7.3 Multilevel Converters and Applications . . . . . . . . . . . . . . 7-20 7.4 Basic Introduction to Matrix Converters . . . . . . . . . . . . . 7-20 7.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.4.2 Switching Rules . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7.4.3 Switching Some More Detail . . . . . . . . . . . . . . . 7-22 7.4.3.1 Alesina/Venturini Modulation Algorithm . . . . 7-22

xii 7.4.3.2 Space Vector Modulation Techniques Implementation Issues . . . . . . . . . . . . . . 7.4.4.1 Bidirectional Switches . . . . . . . . . 7.4.4.2 Current Commutation . . . . . . . . . 7.4.4.3 Input Filters . . . . . . . . . . . . . . 7.4.4.4 Over-voltage Protection . . . . . . . . Comments . . . . . . . . . . . . . . . . . . . . .

CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 7-37 7-37 7-40 7-44 7-44 7-46

7.4.4

7.4.5

8 Grid Connected Converters and Renewable Energy Systems 8-1 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 Wind Power . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.2 Photovoltaics . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.3 Outline and Scope of this Chapter . . . . . . . . . . . . . 8-2 8.2 Photovoltaic Inverters . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1 Review of Power Electronic Congurations for Grid Connected Converters . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1.1 How do photovoltaic devices work? . . . . . . . 8-5 8.2.1.2 Equivalent Circuit of a Solar Cell . . . . . . . . 8-8 8.2.1.3 Traditional PV Inverter Topologies . . . . . . . 8-14 8.2.2 New PV Inverter Topologies . . . . . . . . . . . . . . . . . 8-26 8.2.2.1 H5 Inverter (SMA) . . . . . . . . . . . . . . . . 8-26 8.2.2.2 HEIRC Inverter (Sunways) . . . . . . . . . . . . 8-32 8.2.2.3 Full Bridge with DC Bypass (Ingeteam) . . . . . 8-33 8.2.2.4 Neutral Point Clamped (NPC) Half-Bridge Inverter . . . . . . . . . . . . . . . . . . . . . . . . 8-35 8.2.2.5 Some Other Topologies and Issues . . . . . . . . 8-37 8.2.3 Grid Requirements for PV Systems . . . . . . . . . . . . . 8-41 8.2.3.1 Discussion of the International Standards . . . . 8-42 8.2.3.2 Anti-islanding Standards . . . . . . . . . . . . . 8-49 8.2.3.3 Australian Standards . . . . . . . . . . . . . . . 8-51 8.2.4 Grid Synchronization and Related Control for PV Systems 8-53 8.2.4.1 Brief review of PLLs . . . . . . . . . . . . . . . . 8-54 8.2.4.2 Brief Review of Synchronisation Techniques for Power Systems . . . . . . . . . . . . . . . . . . . 8-60 8.2.5 Islanding Detection Techniques . . . . . . . . . . . . . . . 8-73 8.3 Wind Turbine Converter Systems . . . . . . . . . . . . . . . . . . 8-73 8.3.1 Grid Requirements for Wind Turbine Systems . . . . . . . 8-73 8.3.2 Grid Synchronization for Three Phase Systems . . . . . . 8-73 8.3.3 Brief Overview of Wind Turbine Converter Control . . . . 8-76

III

Appendices

8-77

A Review of Second Order Circuits A-1 A.1 Series RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1.1 Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . A-4 A.1.2 Time Domain Response . . . . . . . . . . . . . . . . . . . A-5 A.1.2.1 Forced Response of Series RLC Circuit with Initial Inductor Current . . . . . . . . . . . . . . . A-7 A.2 Parallel RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . A-8

CONTENTS A.2.1 Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . A-10 B Introduction to Space Vectors B-1 B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.2 The Sinusoidal Assumption . . . . . . . . . . . . . . . . . . . . . B-1 B.2.1 Winding Interaction with Spatial Flux Density DistributionB-2 B.2.2 Winding Interaction with Temporal Flux Density VariationB-6 B.3 dq Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 B.3.1 Stationary Frame Transformations . . . . . . . . . . . . . B-9 B.3.1.1 MMF transformations . . . . . . . . . . . . . . . B-9 B.3.1.2 Current Transformations . . . . . . . . . . . . . B-11 B.3.1.3 Voltage Transformations . . . . . . . . . . . . . B-12 B.3.1.4 Impedance Transformations . . . . . . . . . . . . B-13 B.3.1.5 Flux Linkage Transformations . . . . . . . . . . B-14 B.3.2 Rotating Frame Transformations . . . . . . . . . . . . . . B-14 B.3.3 Example SYNCREL Linear dq Model . . . . . . . . . . B-17 B.4 Space Vector Model . . . . . . . . . . . . . . . . . . . . . . . . . B-21 B.4.1 Current Space Vectors . . . . . . . . . . . . . . . . . . . . B-22 B.4.1.1 Stationary Frame Current Vectors . . . . . . . . B-22 B.4.1.2 Rotating Frame Current Vectors . . . . . . . . . B-24 B.4.2 Flux Linkage Space Vector . . . . . . . . . . . . . . . . . B-25 B.4.3 Voltage Space Vector . . . . . . . . . . . . . . . . . . . . . B-27 B.4.4 Example SYNCREL Space Vector Model . . . . . . . . B-27 B.4.5 Space Vector Power Expression . . . . . . . . . . . . . . . B-28 B.4.6 Space Vector Expression for SYNCREL Torque . . . . . . B-29 B.4.7 Relationship Between Space Vectors and dq Models . . . B-32 C Calculation of Inductances for chine C.1 Calculation of Inductances . . C.1.1 Self Inductances . . . C.1.2 Mutual Inductances . C.1.3 Summary . . . . . . . a Synchronous Reluctance MaC-1 . . . . . . . . . . . . . . . . . . . . C-1 . . . . . . . . . . . . . . . . . . . . C-3 . . . . . . . . . . . . . . . . . . . . C-11 . . . . . . . . . . . . . . . . . . . . C-14

xiii

D Introduction to Instantaneous Imaginary Power D-1 D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1.1 Single Phase Reactive Power . . . . . . . . . . . . . . . . D-1 D.1.2 Three Phase Instantaneous Imaginary Power . . . . . . . D-3 E Introductory Exercise using Saber Simulator E.1 Introduction . . . . . . . . . . . . . . . . . . . E.2 Circuit Schematic Capture . . . . . . . . . . . E.3 Executing the Transient Analysis . . . . . . . E.4 Plotting and Processing Results . . . . . . . . E.4.1 Manipulating Results . . . . . . . . . E.4.2 Fourier Analysis . . . . . . . . . . . . E.5 A Practice Exercise . . . . . . . . . . . . . . . E-1 E-1 E-2 E-6 E-7 E-9 E-11 E-13

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xiv F PV F.1 F.2 F.3

CONTENTS Related Information SunnyBoy Transformerless PV Inverter . . . . . . . . . . . . . . . Tianwei PV Array Datasheet . . . . . . . . . . . . . . . . . . . . Australian Standards for PV Inverter Connections . . . . . . . . F.3.1 AS4777.2-2005: Grid connection of energy systems via inverters Part 2: Inverter Requirements . . . . . . . . . . F.3.2 AS4777.3-2005 Grid connection of energy systems via inverters Part 3: Grid protection requirements . . . . . . . F-1 F-2 F-4 F-6 F-6 F-17 G-1 G-21

G Python Listing for Two Phase PLL Bibliography

List of Figures
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 Conceptual diagram of a traditional linear DC linear power supply. 1-3 Simple half wave rectier circuit with LR load. . . . . . . . . . . 1-4 Plots for a half wave rectier with an LR load L = 200mH and R = 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Forced commutated switching pole. . . . . . . . . . . . . . . . . . 1-7 Output of the switching pole. . . . . . . . . . . . . . . . . . . . . 1-7 Example buck converter with waveforms. . . . . . . . . . . . . . 1-9 Conceptual diagram of a H-bridge. . . . . . . . . . . . . . . . . . 1-10 Conceptual diagram showing how to generate double edge naturally sampled PWM. . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Close-up of naturally sampled PWM process. . . . . . . . . . . . 1-13 Equivalence between a switching pole and a variable turns ratio DC-DC transformer. . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Saber circuit used to simulate double edged naturally sampled PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Saber simulation output for double edged naturally sampled PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Component waveforms for double edged naturally sampled PWM. 1-17 Spectrum when the triangular modulation waveforms are 180 out of phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14

Block diagram of the structure of a typical DC-DC converter. . . 2-2 A basic buck or step-down converter. . . . . . . . . . . . . . . . . 2-4 A basic boost or step-up converter. . . . . . . . . . . . . . . . . . 2-5 Two switch buckboost converter. . . . . . . . . . . . . . . . . . . 2-6 Single switch Buckboost converter circuit. . . . . . . . . . . . . 2-7 The Ck converter. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Ck converter with the switch open. . . . . . . . . . . . . . . . . 2-8 Ck converter with the switch closed. . . . . . . . . . . . . . . . 2-9 Full bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Denition of the terms related to duty cycle. . . . . . . . . . . . 2-12 Waveforms in a sawtooth based PWM modulator. . . . . . . . . 2-13 Simple PWM generator circuit. . . . . . . . . . . . . . . . . . . . 2-14 Currents and circuit congurations for a buck converter. . . . . . 2-15 Current waveform at the point of discontinuous current in the inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.15 Current waveform for a buck converter with discontinuous current.2-18

xvi

LIST OF FIGURES 2.16 Voltage ratio of the buck converter for continuous and discontinsV uous operation modes and constant Vd . NB. ILBmax = T8Ld . . . 2.17 Characteristics of the buck converter with constant Vo . NB. sV ILBmax = T2Lo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.18 Output voltage ripple for a buck converter. . . . . . . . . . . . . 2.19 Circuit used in simulation of the buck converter. . . . . . . . . . 2.20 Waveforms for a buck converter with D = 0.5, RL = 100, and continuous inductor current. . . . . . . . . . . . . . . . . . . . . . 2.21 Initial startup waveforms for a buck converter with D = 0.5, RL = 40k, and discontinuous inductor current. . . . . . . . . . 2.22 Currents and circuit congurations for a boost converter. . . . . 2.23 Voltage ratio of a boost converter versus duty cycle. . . . . . . . 2.24 Current waveform on the edge of continuous current. . . . . . . . 2.25 Plot of the normalised continuous current boundary for the boost converter (Vo constant). . . . . . . . . . . . . . . . . . . . . . . . 2.26 Current waveforms for the boost converter with discontinuous current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.27 Duty cycle versus normalised output current for the boost converter with constant Vo . . . . . . . . . . . . . . . . . . . . . . . . 2.28 Boost converter simulated using Saber . . . . . . . . . . . . . . . 2.29 Simulated waveforms for a boost converter with D = 0.5 and continuous current. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.30 Output of a boost converter in continuous current mode with several dierent duty cycles. . . . . . . . . . . . . . . . . . . . . . 2.31 Steady state currents and voltages in a Ck converter. . . . . . . 2.32 Waveforms for a full bridge converter with a bipolar switching strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.33 Waveforms for a full bridge converter with a unipolar switching strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.34 The input current into a buck-boost converter with a large input inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.35 Plot of switch utilisation for the common converter types. . . . . 2.36 (a) Conventional non-synchronous rectier based boost converter. (b) Synchronous rectier based boost converter. . . . . . . . . . . 2.37 (a) Step-down converter circuit with a RC snubber; (b) The diode reverse recovery current [2]. . . . . . . . . . . . . . . . . . . . . . 2.38 Equivalent circuit of the snubber used to protect diodes. (a) Full equivalent circuit; (b) simplied circuit with Rs = 0. . . . . . . . 2.39 Waveforms for the simplied (Rs = 0) snubber circuit. . . . . . . 2.40 Plot of the normalised capacitor voltage versus Cbase /Cs . . . . . 2.41 Turn-o snubber circuit for a transistor step-down converter. . . 2.42 Stray inductances that are important in a transistor switching circuit during turn-on [2]. . . . . . . . . . . . . . . . . . . . . . . 2.43 Current and voltage trajectories during turn-on and turn-o for a step-down transistor converter. . . . . . . . . . . . . . . . . . . 2.44 Equivalent circuit for the turn-o RCD snubber and approximate waveforms for dierent values of capacitance [2]. . . . . . . . . . 2.45 Switching trajectories for dierent turn-o capacitor values. . . . 2.46 Typical turn-on snubber for a transistor step-down converter. . . 2.47 Over-voltage snubber for a transistor step-down converter. . . . .

2-20 2-22 2-24 2-26 2-27 2-27 2-29 2-29 2-30 2-31 2-32 2-34 2-35 2-35 2-36 2-37 2-41 2-43 2-47 2-48 2-50 2-52 2-54 2-55 2-56 2-59 2-60 2-61 2-62 2-63 2-63 2-64

LIST OF FIGURES 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60 Undeland snubber for a step-down converter circuit. . . . . . . . 2-65 A zero current switching (ZCS) resonant buck converter. . . . . . 2-66 A zero voltage switching (ZVS) resonant buck converter. . . . . . 2-67 A quasi-resonant forward converter. . . . . . . . . . . . . . . . . 2-68 Zero Voltage Switching quasi resonant buck converter for example.2-69 Waveforms in the ZVS circuit (scanned from [2]) . . . . . . . . . 2-70 Voltage across the freewheeling diode in the ZVS circuit. . . . . . 2-72 Final design of the resonant buck ZVS circuit. . . . . . . . . . . . 2-77 ZVS circuit without output lter but with an ideal current source load at 6 Amps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78 ZVS circuit with output lter and ideal current source load at 6 Amps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79 Saber circuit used for the 6 Amp full simulation. . . . . . . . . . 2-80 ZVS circuit with output lter and resistive load at 6 Amps. . . . 2-80 ZVS circuit with lter circuit and resistive load, output current 20 Amp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81 Basic circuit of the forward converter. . . . . . . . . . . . . . . . A practical forward converter. . . . . . . . . . . . . . . . . . . . . Equivalent circuit for a practical forward converter. . . . . . . . . Current waveforms for a practical forward converter. . . . . . . . Circuit diagram of a two switch forward converter. . . . . . . . . Push-pull forward converter. . . . . . . . . . . . . . . . . . . . . . Currents owing in the push-pull forward converter with SW1 closed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents owing in the push-pull forward converter with SW1 and SW2 open. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flux imbalance in the push-pull circuit. . . . . . . . . . . . . . . Connection between the Buck-Boost and Flyback converter. . . . Flyback converter with the switch closed. . . . . . . . . . . . . . Flyback converter with the switch open. . . . . . . . . . . . . . . The voltage, current and ux in the ideal Flyback Converter. . . Typical BH loop for a magnetic material. . . . . . . . . . . . . . Core excitation waveforms. (a) forward converter. (b) full bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of a typical switch mode power supply. . . . . . . Feedback circuit using a small forward converter. . . . . . . . . . Example of a simple bootstrap power circuit for a PWM generator chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap circuitry modied for increased hysteresis range. . . . Block diagram of the Unitrode high speed PWM generator. . . Operation of a constant current limit. . . . . . . . . . . . . . . . Operation of a fold-back current limit. . . . . . . . . . . . . . . . Conceptual diagram of a control system for a switch mode power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linearised model of a switch mode power supply. . . . . . . . . . Block diagram of a nested loop control system for a switch mode power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms for tolerance band current control. . . . . . . . . . . . Waveforms for constant o time control. . . . . . . . . . . . . . 3-2 3-3 3-3 3-5 3-7 3-8 3-9 3-10 3-12 3-13 3-14 3-15 3-16 3-18 3-19 3-23 3-24 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-32 3-34 3-35

xvii

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27

xviii

LIST OF FIGURES 3.28 Waveforms for constant frequency with turn-on at clock time control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.29 Open loop instability of current mode control. (a) stability with duty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stability with duty cycle > 0.5 and slope compensation. . . . . . . . . 3.30 Geometrical relationship of the current waveform slopes when there is a current perturbation. . . . . . . . . . . . . . . . . . . . 3.31 Inductor current response of current mode converter. . . . . . . . 3.32 Optimal slope compensation to eliminate RLC type oscillations. . 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 Equivalent circuit model of a current shunt . . . . . . . . . . . . Method of voltage sharing for series capacitors. . . . . . . . . . . Reverse recovery in a converter secondary circuit. . . . . . . . . . Reverse recovery in a boost converter circuit. . . . . . . . . . . . Operational amplier circuit for discussion of osets. . . . . . . . Conventional inverting Op Amp circuit with a gain of 1000. . . . Inverting Op Amp circuit with alternative feedback network. . . Gain-bandwidth product of an Op Amp. . . . . . . . . . . . . . . Comparator with hysteresis. . . . . . . . . . . . . . . . . . . . . . Interfacing a comparator to an NPN transistor. . . . . . . . . . . A loop of wire enclosing an area of time varying ux density. . . A BH loop for a magnetic material. . . . . . . . . . . . . . . . . Circuit symbol for a transformer. . . . . . . . . . . . . . . . . . . Simplied model of a real transformer. . . . . . . . . . . . . . . . Ferrite choice (from [9]). . . . . . . . . . . . . . . . . . . . . . . . Initial permeability with respect to frequency for 2P iron powder Ferroxcube material (from [8]). . . . . . . . . . . . . . . . . . . . Incremental permeability as a function of magnetic eld strength for 2P iron powder Ferroxcube material (from [8]). . . . . . . . . Core type selection table (from [8]). . . . . . . . . . . . . . . . . Core data for toroidal cores using powdered iron (from [8]). . . . Typical BH characteristic for 2P magnetic material (from [8]). . Losses in 2P material with respect to ux density and frequency (from [8]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Winding interleaving for high-dielectric isolation and good primary to secondary coupling. . . . . . . . . . . . . . . . . . . . . . A transformer design to satisfy safety requirements. . . . . . . . The current-voltage characteristic of a diode. . . . . . . . Conceptual structure of a conventional diode. . . . . . . . Conceptual structure of a power diode. . . . . . . . . . . . Typical reverse recovery characteristic for a diode. . . . . Series connection of diodes to support higher voltage. . . Conceptual diagram of a thyristor. . . . . . . . . . . . . . Transistor model of the thyristor. . . . . . . . . . . . . . . Typical characteristic of a thyristor. . . . . . . . . . . . . Typical turn-on waveforms for a thyristor. . . . . . . . . . Typical thyristor turn-o waveforms. . . . . . . . . . . . . An example of a dc chopper circuit using a GTO thyristor Turn on waveforms for a GTO thyristor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-36

3-38 3-39 3-40 3-40 4-5 4-10 4-10 4-11 4-15 4-17 4-18 4-19 4-21 4-22 4-24 4-26 4-28 4-30 4-36 4-36 4-37 4-40 4-42 4-44 4-44 4-50 4-51 5-4 5-5 5-5 5-7 5-8 5-9 5-10 5-11 5-12 5-14 5-16 5-18

LIST OF FIGURES 5.13 5.14 5.15 5.16 Turn-o waveforms for a GTO thyristor. . . . . . . . . . . . . . . GTO thyristor circuit with additional crowbar SCR . . . . . . A schematic diagram of the basic structure of the IGBT. . . . . . The IGBT voltage and current transfer characteristics and circuit symbol: (a) output characteristic; (b) transfer characteristic; (c) and (d) n-channel IGBT circuit symbols. . . . . . . . . . . . . . . Current ows in the IGBT. . . . . . . . . . . . . . . . . . . . . . Equivalent circuits for the IGBT: (a) approximate equivalent circuit for normal operating conditions; (b) more complete equivalent circuit showing the parasitic thyristor. . . . . . . . . . . . . . Typical turn-on waveforms for an IGBT. . . . . . . . . . . . . . . Turn-o waveforms for an IGBT. . . . . . . . . . . . . . . . . . . Schematic and circuit symbol for the P-MCT. . . . . . . . . . . . 5-19 5-21 5-22

xix

5.17 5.18

5-23 5-28

5.19 5.20 5.21 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19

5-29 5-30 5-31 5-31

6.20 6.21 6.22

Line current waveform distortion. . . . . . . . . . . . . . . . . . . 6-3 Phasor relationship for complex power. . . . . . . . . . . . . . . . 6-6 Diagram of the normalised single phase power components with a 30 phase angle the power is normalised by dividing by Vrms Irms . 6-7 Half wave rectier with a resistive load. . . . . . . . . . . . . . . 6-11 Half wave rectier with an LR load. . . . . . . . . . . . . . . . . 6-12 Plots for a half wave rectier with an LR load L = 200mH and R = 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Half wave rectier circuit with an inductor and back emf. . . . . 6-14 Plots for a half wave rectier with an inductor and back emf as a load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Test circuit used for current commutation discussion. . . . . . . . 6-15 Circuit congurations during current commutation of the circuit in Figure 6.9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Plots of the currents in the test circuit of Figure 6.9 vs = 50 sin t, Ls = 5mH, Id = 1 Amp. . . . . . . . . . . . . . . . . . . 6-18 A practical single phase rectier. . . . . . . . . . . . . . . . . . . 6-19 Equivalent circuit of the single phase rectier when the diodes are conducting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Waveforms for the practical single phase rectier circuit of Figure 6.12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Input current and output voltage harmonics in a single phase rectier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Real and imaginary components of the harmonic phasors for the harmonics single phase rectier harmonics plotted in Figure 6.14. 6-23 Single phase rectier with input and dc link lters. . . . . . . . . 6-26 Circuit for the a single phase rectier with current wave shaping boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 Waveforms for a single phase rectier with active current waveshaping (a) the input current and voltage; (b) the boost converter input voltage and inductor current. . . . . . . . . . . . . . 6-28 Block diagram of the control system for a single phase rectier with active current wave-shaping. . . . . . . . . . . . . . . . . . . 6-30 Single phase rectier showing the point of common coupling. . . 6-31 Single phase rectier voltage doubler. . . . . . . . . . . . . . . . . 6-32

xx

LIST OF FIGURES 6.23 Single phase rectiers loads in a three phase, four wire distribution system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6.24 Basic three phase, six pulse, full wave rectier circuit. . . . . . . 6-35 6.25 Waveforms of a three phase rectier with a constant current source load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 Denition of rectier and inverter modes of operation [2]. . . . . Generic power processing block [2]. . . . . . . . . . . . . . . . . . Block diagram of a generic AC drive system. . . . . . . . . . . . Specic implementation of an inverter. . . . . . . . . . . . . . . . Single leg of inverter and the PWM waveforms. . . . . . . . . . . Switch positions and the resultant voltage space vectors. . . . . . Switching waveforms for double edge pulse width modulation. . . Switching time determination. . . . . . . . . . . . . . . . . . . . . Voltage limit hexagon. . . . . . . . . . . . . . . . . . . . . . . . . Inverter showing the initial and nal current ow after a leg is red. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of dead-time induced switching error in an inverter. . . Generic non-battery based photo-voltaic supply system. . . . . . Some grid connected FACTS units oered by Siemens. . . . . . . Conceptual diagram of a matrix converter. . . . . . . . . . . . . . Recongured conceptual diagram of the matrix converter. . . . . General form of switching pattern [16]. . . . . . . . . . . . . . . . (a) Direction of the output line-to-neutral voltage vectors for the active switch congurations. (b) Directions of the input line current vectors generated by the active switch congurations. . . . . Derivation of the voltage components for a desired voltage space vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double sided switching sequences for a matrix converter over one control cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode bridge bidirectional switch cell. . . . . . . . . . . . . . . . Common emitter and common collector back-to-back bidirectional switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short and open circuit situations that can occur during commutation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two phase switching matrix example. . . . . . . . . . . . . . . . Four step commutation process between bidirectional switch cells in Figure 7.23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Matrix converter input lters and damping resistors. . . . . . . . Matrix converter with over-voltage diode clamp protection. . . . 7-2 7-2 7-3 7-4 7-5 7-9 7-9 7-11 7-13 7-15 7-16 7-18 7-19 7-20 7-21 7-24

7-31 7-33 7-38 7-38 7-39 7-41 7-42 7-43 7-45 7-45

7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9

Block diagram of a generic PV system [21] . . . . . . . . . . . . . 8-6 Band gap diagram of a solar cell (pn junction). . . . . . . . . . . 8-7 Optical generation of carriers in a pn junction. . . . . . . . . . . 8-9 Equivalent circuit of an ideal solar cell. . . . . . . . . . . . . . . . 8-11 Equivalent circuit of a non-ideal solar cell. . . . . . . . . . . . . . 8-11 Circuit symbols for a solar cell and a series array of solar cells. . 8-12 Maximum power diagram for a solar cell. . . . . . . . . . . . . . 8-13 Relative merits of dierent inverter topologies for PV systems [24].8-15 Single-phase multi-string converter [25]. . . . . . . . . . . . . . . 8-17

LIST OF FIGURES 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 8.28 8.29 8.30 8.31 8.32 8.33 8.34 8.35 8.36 8.37 8.38 8.39 8.40 8.41 Detailed view of a single single phase output module [25]. . . . . Multi-string converter with a three phase output stage [25]. . . . A transformerless bridge converter interface for a PV system. . Equivalent circuit for the H-bridge PV converter with S1 and S4 turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent circuit for the H-bridge PV converter with S2 and S3 turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent circuit for the H-bridge PV converter with S1 and S3 turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Switching H-bridge converter. . . . . . . . . . . . . . . . Hybrid Switching H-bridge converter equivalent circuit for the two positions of the low frequency switches. . . . . . . . . . . . . H5 H-bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . H5 H-bridge equivalent circuit for Vg > 0. . . . . . . . . . . . . . H5 H-bridge equivalent circuit for Vg < 0. . . . . . . . . . . . . . The HERIC PV inverter topology (Sunways) . . . . . . . . . . . The full bridge DC bypass PV inverter (Ingeteam). . . . . . . . . Basic NPC single phase leg. . . . . . . . . . . . . . . . . . . . . . NPC with Vg > 0 and i > 0. . . . . . . . . . . . . . . . . . . . . . NPC with Vg < 0 and i < 0. . . . . . . . . . . . . . . . . . . . . . Basic structure of a single phase PV interface with a high frequency isolated boost converter. . . . . . . . . . . . . . . . . . . Basic structure of a single phase PV interface with a low frequency transformer and non-isolated boost converter. . . . . . . . Test set up for testing the compliance of a distributed resource with the IEEE 1547 standard in anti-islanding. . . . . . . . . . . VDE 0126-1-1 anti-islanding standard test circuit. . . . . . . . . Lightning impulse test waveform. . . . . . . . . . . . . . . . . . . Classic PLL block diagram. . . . . . . . . . . . . . . . . . . . . . Block diagram of a PLL control system when in lock. . . . . . . . Root locus and Bode plot for a 1st order classic PLL. . . . . . . Root locus and Bode plot for the 2nd order PLL. . . . . . . . . . Open loop Bode plots for a 2nd order PLL with zero added. . . . Closed loop magnitude response of a 2nd order PLL with zero added. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic in-quadrature PLL. . . . . . . . . . . . . . . . . . . . . . . Xcos simulation model of the basic in-quadrature PLL. . . . . . . Xcos simulation result input waveform and feedback sine waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xcos simulation result the error between the input waveform and the sine feedback waveform. . . . . . . . . . . . . . . . . . . Xcos simulation result the output of the PI controller which indicates the dierence between the input frequency and the loop centre frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . In-quadrature PLL implemented with a Park transformation. . . The three phase quadrature PLL using a Park Transformation. . Space vector representation of the convergence process of a Park Transformation based quadrature PLL. . . . . . . . . . . . . . . . Space vector representation when the Park Transformation quadrature based PLL is locked. . . . . . . . . . . . . . . . . . . . . . . 8-18 8-19 8-20 8-21 8-21 8-24 8-26 8-27 8-28 8-29 8-31 8-33 8-34 8-37 8-38 8-39 8-40 8-41 8-50 8-51 8-53 8-54 8-56 8-58 8-59 8-60 8-61 8-62 8-64 8-65 8-65

xxi

8.42 8.43 8.44 8.45

8-66 8-67 8-68 8-69 8-70

xxii

LIST OF FIGURES 8.46 Two phase PLL implemented in Python showing the estimated waveform versus the actual waveform. . . . . . . . . . . . . . . . 8.47 Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL. . . . . . . 8.48 Two phase PLL implemented in Python showing the estimated waveform versus the actual waveform when there is a 30% 5th input harmonic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.49 Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL when there is a 30% 5th input harmonic. . . . . . . . . . . . . . . . . . . . . 8.50 Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL when there is a 30% 5th input harmonic and lter. . . . . . . . . . . . . . . . A.1 A.2 A.3 A.4 B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 C.1 C.2 C.3 C.4 Series RLC circuit . . . . . . . . . . . . . . . . . . . Series RLC circuit pole positions. . . . . . . . . . . . Time response of a series RLC circuit with Q = 6.3. Parallel RLC circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-71 8-72

8-73

8-74

8-75 A-2 A-3 A-7 A-9 B-3 B-6 B-9 B-16 B-18 B-20 B-23 B-24 B-25 C-2 C-5 C-6 C-11

MMF calculation integration path. . . . . . . . . . . . . . . . Dimensions of a single coil. . . . . . . . . . . . . . . . . . . . Three phase to two phase transformation. . . . . . . . . . . . Two phase stationary to two phase rotating transformations. Conceptual diagram of a three phase SYNCREL. . . . . . . . Ideal dq equations. . . . . . . . . . . . . . . . . . . . . . . . . Resolving the current space vector onto the abc axes. . . . . . Relationship between the dq-axes and current space vectors. . Space vector rotating frame transformations. . . . . . . . . . Two pole three phase Syncrel conceptual Developed diagram of a Syncrel. . . . . . d axis developed diagram for Syncrel . . . a phase inductance plot. . . . . . . . . . diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.1 Phasor relationship for complex power. . . . . . . . . . . . . . . . D-2 D.2 Space vector diagram. . . . . . . . . . . . . . . . . . . . . . . . . D-6 E.1 E.2 E.3 E.4 E.5 E.6 E.7 E.8 E.9 E.10 E.11 Simple single phase, half wave rectier, with an LR load. . . . . . E-2 Initial screen upon invoking SaberSketch. . . . . . . . . . . . . . E-3 An example of a parts gallery screen. . . . . . . . . . . . . . . . . E-4 The wire attributes window. . . . . . . . . . . . . . . . . . . . . . E-7 An example of SaberSketch with the Saber guide toolbar activated.E-8 An example dc/transient simulation set-up window. . . . . . . . E-9 The input-output table of the dc/transient analysis window. . . . E-10 The initial SaberScope window. . . . . . . . . . . . . . . . . . . . E-11 A signal plotted in SaberScope. . . . . . . . . . . . . . . . . . . . E-12 An example of a waveform calculation in SaberScope. . . . . . . E-13 Fourier analysis dialogues in Saber. . . . . . . . . . . . . . . . . . E-14

List of Tables
1.1 4.1 4.2 4.3 4.4 6.1 6.2 7.1 7.2 7.3 7.4 7.5 7.6 Switch congurations and output voltages for a generic H-bridge. 1-11 Resistor application selection guide Capacitor application guide . . . . Core materials and their uses. . . . Inductor specications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-7 4-31 4-35

Fourier coecient formulae with symmetry. . . . . . . . . . . . . 6-3 Current harmonic amplitudes. . . . . . . . . . . . . . . . . . . . . 6-25 Switching combinations and associated phase and line-to-line voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching combinations and associated phase and phase-to-neutral voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM ring times for various sectors . . . . . . . . . . . . . . . . . Voltage limit s . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching values used in SVM. . . . . . . . . . . . . . . . . . . . Selection of switching congurations for combinations of output voltage and input current vectors. . . . . . . . . . . . . . . . . . EN50160 European standards for public distribution grid voltage harmonics limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of US and European Standards on disconnection times for PV inverters under abnormal voltage variations. . . . . Comparison of European and US standard for disconnection with respect to frequency deviations. . . . . . . . . . . . . . . . . . . . European and US reconnection conditions for PV inverter systems after a trip [21]. . . . . . . . . . . . . . . . . . . . . . . . . . European and US DC current injection limitations . . . . . . . . IEC and IEEE standards for injected current harmonics . . . . . IEC61000-3-2 current harmonic limits. . . . . . . . . . . . . . . . Australian Standard voltage and frequency limits. . . . . . . . .

7-6 7-7 7-12 7-14 7-30 7-32

8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8

8-45 8-45 8-46 8-47 8-47 8-48 8-48 8-52

B.1 Summary of Stationary Frame Transformations . . . . . . . . . . B-14 B.2 Summary of Rotating Frame Transformations . . . . . . . . . . . B-17 E.1 Number magnitude speciers in Saber . . . . . . . . . . . . . . . E-6

xxiv

LIST OF TABLES

Nomenclature
D gop I0 isw itr k Ln Lp q T ton TK Vd vsw vtr BJTs EHP GTO Duty cycle =
ton T .

Optical generation rate (EHP/cm3 /sec) Diode reverse saturation current. Current through a semiconductor switch. Current through a pass transistor in a linear power supply. Boltzmanns constant (1.38 1023 J/K ). Mean diusion length of electrons in p materials. Mean diusion distance of holes in n materials. Charge of an electron (1.6 1019 C). Switching period. On-time of a switch. On means that the switch is closed. Temperature in Kelvin. DC input voltage to a linear or switching power supply. Voltage across a semiconductor switch. Voltage across a pass transistor in a linear power supply. Bipolar Junction Transistors Electron-hole-pairs. Gate Turn O Thyristor.

IBGT Insulated Gate Bipolar Junction Transistor. MOSFET Metal Oxide Semiconductor Fiedl Eect Transistor. PWM Pulse Width Modulation. SCR Silicon Controlled Rectier or Thyristor.

SMPS Switch Mode Power Supplies.

xxvi

Nomenclature

Part I

Switched Mode Power Supplies

Chapter 1

Switching Basics
1.1 Introduction

Power electronics is an enabling technology for a carbon constrained world. Power electronic systems allow the very ecient conversion of electrical energy to forms which can be more easily utilised. For example, photovoltaic collectors naturally generate DC output voltages, the level of the voltage being dependent on the number of series cells. In order to utilise photovoltaics in the power system as it currently exists, the DC voltage needs to be converted to AC voltage of the correct magnitude. Without the use of power electronics this conversion is very dicult to achieve at reasonable cost. Power electronics is essential to power all electric and hybrid electric vehicles, allow ecient air-conditioning, drive new technology lighting systems, allow interfacing of wind turbines to the grid and so on. Another major use of power electronics is in variable speed drives. AC electrical machines are normally constant speed systems, with the shaft rotational speed being related to the AC supply frequency and the number of pole pairs in the machine. In order to change the speed of an AC machine one needs a variable frequency, variable voltage supply. Prior to the advent of power electronics, this was achieved by the use of electrical machine based frequency converters. This was a very expensive solution, which meant the variable speed AC systems were almost never used. If one wanted a variable speed electrical machine one used the DC machine, where the shaft speed can be controlled by the magnitude of the DC armature voltage. Power electronics, coupled with microprocessors has allowed the development of completely static (i.e. no rotating parts) power electronic variable frequency, variable voltage supplies for AC electrical machines (know as inverters). Inverters can be built using current technology up to the several megawatts. The variable speed AC machine drive market is now worth tens of billions of dollars per year on a global basis. Power electronics is also embedded in many consumers products as well most home electronic systems, for example, are powered by a switch mode power supply (computers, LCD and plasma TVs, video recorders etc). The reason for the switch mode power supplys ubiquitous use is related to their light weight, eciency, and multi-voltage capabilities. The remainder of this chapter will examine the basic switch building blocks

1-2

Switching Basics for power electronic systems. These will be examined in a very generic way initially, and then some specic implementations will be considered throughout the remainder of the course.

1.2

Why Use Switching?

One question that needs to be answered before looking at how switching is implemented is: Why bother using switching in electronic circuits? Clearly the answer depends on what one is trying to achieve. One can use switching to implement a classic switch function i.e. connect one part of a circuit to another part. One can use a mechanical or a semiconductor based switch for this. Usually once a switch of this type is closed or opened it tends to remain this way for a long period of time. Whilst this is a valid use of switching, it is not the focus of the switching discussed in this course. The switching that will be discussed here is relatively high frequency switching that occurs continuously whilst the circuit is operating. This means that the electronic circuits operation is in a constant transient state. Switching is used in power electronic systems because the power conversion is very ecient. This is due to the fact that if a device is switched then ideally the voltage across the device is zero. Therefore the power dissipated in the switching element is: p = vsw isw = 0 isw = 0 (1.1) where vsw is the voltage across the switch, and isw is the current through the switch. Obviously the power dissipated in the switch is zero regardless of isw . Similarly one can have voltage across a device, and due to external circuit conditions the current through the device can be zero, and again the power dissipated in the switch will be zero. Remark 1.1 The previous paragraph is simply a statement as to why switches are in general used in electrical systems. The trick to using switching electronic elements in power electronic systems is that by using high frequency switching (which can only be obtained electronically), together with specic external circuit conditions, one can obtain a linearly controllable output from the system without dissipating any power. Remark 1.2 Switches used in real systems do have resistance and oset voltages across them. Therefore the switches do dissipate power when they switch is closed, but the power dissipated is often very low compared to the amount of energy being controlled by the switching circuit. Remark 1.3 Another advantage of power conversion using switching is that the size and weight of the power conversion device is far less than power conversion techniques that do not use switching. This is largely due to the fact that inductors and capacitors are frequency dependent devices, and the switching frequency in power electronics systems are high which means that these components can be made smaller.

Power dissipated in the switch is zero.

1.2 Why Use Switching?

1-3

vtr = (Vd vout )

itr

vout

Vd

vref

Control

Cout

RL

Figure 1.1: Conceptual diagram of a traditional linear DC linear power supply. The benets of switching can clearly be seen if one considers the traditional linear DC power supply. These power supplies take a DC input voltage and convert it to a lower DC voltage. This are implemented by using a circuit of the general conguration shown in Figure (1.1). As can be seen from this gure, there is a substantial voltage across the pass transistor, and therefore the power dissipated in the transistor is: ptr = vtr itr = (Vd vout )itr (1.2)

traditional linear DC power supply

where vtr is the voltage across the pass transistor, itr is the current through the pass transistor, and Vd is the DC input voltage to the power supply. The pass transistor is essentially behaving as an electronically controlled resistor, its value being dynamically changed by the control circuit to maintain the output voltage at the desired output voltage. Remark 1.4 As can be seen from (1.2) if Vd vout is a large value and there is a reasonable current ow, itr through the device, the power dissipated can be very large. Therefore the eciency of these power supplies is usually very low. The pass transistor requires a large heat sink under these conditions, making the supply bulky.

Remark 1.5 The key point to note in Figure 1.1 is that the NPN transistor is operating in its linear region of operation. This is similar to Class A ampliers that one may be familiar with from linear electronics. As with the Class A amplier, operation in the linear region means that a lot of power is being dissipated in the transistor.

1-4

Switching Basics

+ +
vs

v diode

vL

iL

L R

+
v out

Figure 1.2: Simple half wave rectier circuit with LR load.

1.3

Taxonomy of Power Electronic Systems

Power electronic systems fall into two broad categories, depending on how the switches in the system are switch o: naturally commutated systems; and forced commutated systems. We shall briey consider these, in a very generic sense, below. Both these switching strategies will be further developed later in the course.

1.3.1

Naturally Commutated Systems

Naturally commutated power electronic devices are very common a diode rectier consists of naturally commutated devices called diodes (which the readers should be very familiar with). Natural commutation means that the power device is turned o by a natural process derived from the external circuit conditions. For example consider a simple half wave rectier circuit with an LR load as shown in Figure 1.2. In this circuit the diode will switch (or turn) on when the voltage vd across the diode becomes positive, and it will naturally turn o when the current attempts to reverse through the diode this is the point of natural commutation or transition from the conduction mode of the diode to the turned o state. Note that this point of turn-o is determined by the external circuit conditions (i.e. the input voltage waveform and the specic values of the load resistor and inductor). Figure 1.3 on page 1-5 shows the waveforms for this particular circuit, and one can see that when the current through the load attempts to reverse the diode turns o and the diode voltage becomes that of the supply waveform.

Remark 1.6 One can see that with this circuit the turn-on time of the diode is determined by the properties of a diode i.e. turns on immediately it becomes

1.3 Taxonomy of Power Electronic Systems

1-5

t1
0.8 0.6

t2

t3

iL
(A)
0.4 0.2 0.0 -0.2 60.0 40.0 20.0

Due to simulation numerics

vs

v out

vL

(V)

Area A
0.0 -20.0 -40.0 -60.0 0.0 0.005 0.01 0.015 0.02 t(s) 0.025 0.03 0.035 0.04

Area B

v diode

Figure 1.3: Plots for a half wave rectier with an LR load L = 200mH and R = 50. forward biased. The turn-o time is determined by the load and supply properties only, and the fact that a diode cannot conduct current in the reverse direction. We shall see that the turn-on time of some naturally commutated circuits can be controlled. A variant of the basic diode rectier circuit can be obtained by replacing the diode with a thyristor or Silicon Controlled Rectier (SCR). These devices are similar to a diode in that it turns o, or commutates, when the current attempts to reverse through the device. However it is dierent from the diode because it does not turn on immediately it becomes forward biased, but must have a ring pulse put into it via a third gate terminal, assuming that it is already forward biased. There are a variety of systems that fall under the category of naturally commutated single and three phase rectiers, and thyristor rectiers or converters. Remark 1.7 One of the main problem application areas with naturally commutated devices is DC. Because these devices require a reverse of current and voltage across them to turn o, DC systems are a problem. It is possible to turn o naturally commutated devices in DC systems, but it requires complex auxiliary circuitry. Summary 1.1 Naturally commutated switching devices are characterised by the property that they turn o or commutate from the conducting mode to the nonconducting mode due to external circuit conditions. There is not an explicit

1-6

Switching Basics input under the designers control that results in the device turning o. The turn on time may or may not be a controlled time.

1.3.2

Forced Commutated Systems

Power electronic systems are categorised as forced commutated if the turn on and turn o times are determined by an externally generated ring pulse, the timing of which is completely controlled by the system designer. From a hardware perspective, the devices used for such systems are bipolar junction transistors (BJTs), MOSFETs, Insulated Gate Bipolar Junction Transistors (IBGTs), Gate Turn-o thyristors (GTOs) etc. Remark 1.8 Forced commutated systems are more exible than naturally commutated systems because they can more easily handle DC input voltages. Naturally commutated systems have problems with DC inputs because without special provision the circuit conditions cannot reverse the current ow through the switching device to facilitate a natural commutation. Switch mode power supplies (SMPS), which are the subject of this section of the course, almost exclusively use forced commutation. An alternative name to indicate this that is often used in the SMPS literature is hard switched. This refers to the fact that the device can be switched o regardless of the current and voltage conditions across the switching element. Remark 1.9 It should be noted that not all SMPS are forced commutated. There is a strategy for switching, what would normally be forced commutated switching devices, called soft switching, or resonant mode switching. This switching strategy has many aspects similar to natural commutation, where extra circuitry is used to force conditions that allow zero voltage or zero current through the switching device at the time of switching. However, even under this condition, the device switching gate has to be activated to turn o the device it does not do it naturally. The fundamental element of a forced commutated system is the switching pole, which is shown conceptually in Figure 1.4 on page 1-7. As can be seen from this gure, the switch is modeled as a single pole double throw switch. The connection of the switch is controlled by the S/W ctrl input to the switch. The output voltage is either v or 0 volts depending on the switch connection.

By its very nature, the switching pole is a non-linear element the output can only take one of two dierent values. Assuming that the control circuit is switching the output from v to 0 at a particular frequency then the output of the circuit appears as shown in Figure 1.5 on page 1-7. The non-linearity of the output of the circuit is clearly evident.

From a control perspective non-linear behaviour is undesirable. In most electronic circuits it is desired that the output of the circuit is related to the input of the circuit in a linear fashion e.g. in amplier or attenuator applications. Therefore the output of Figure 1.5 needs to be modied in some way so that the switching system behaves linearly.

1.3 Taxonomy of Power Electronic Systems

1-7

vout

S/W ctrl
Figure 1.4: Forced commutated switching pole.

vout

Vd

ton

Figure 1.5: Output of the switching pole.

1-8

Switching Basics Remark 1.10 The upshot of the linearisation of the converter system is that it allows the use of conventional and familiar linear control theory on the converter systems. Remark 1.11 Another consequence of the quest for linearisation of switching systems is that the control rates and switching frequencies have to be high. This allows the overall control for these systems to be organised as a nested hierarchy of control loops, with the inner most loops having the highest bandwidth. The inner control loops, as far as the slower outer control loops are concerned, appear to be algebraic in nature. This approach allows a decoupled control design approach to be used, and greatly simplies the design. Remark 1.12 There is a move in the control of power electronic systems to embrace the non-linearity of the system by the use of non-linear control strategies such as Model Predictive Control (MPC). It should be noted that the application of such control methodologies to power electronic systems has only been made possible because of the availability of low cost powerful microprocessor systems. 1.3.2.1 Linearising the Non-linear System

To linearise the basic switching pole one needs rstly to dene what the input/output relationship is. An examination of Figure 1.5 shows that the switching waveform average value over the period T is controlled by the time that the voltage is at Vd and at 0 volts. A way of capturing this is to dene the duty cycle of the waveform: ton (1.3) D= T where 0 D 1 and ton is the on-time of the switch which means that the switch is closed so that the output is connected to the input voltage. The average voltage output of the waveform is: vave = = 1 T
ton

Vd dt
0

(1.4) (1.5) (1.6)

1 DT Vd dt T 0 = DVd

...what is required is a lter on the output of the switching pole.

As can be seen from (1.6) the relationship between the average output voltage and the input voltage is linear with respect to the duty cycle i.e. vave Vd when the constant of proportionality is D the duty cycle.1 One could also consider that the relationship is vave D, where the constant of proportionality is the input voltage magnitude, and D is regarded at the input to a linear system. However, if the waveform of Figure 1.5 is fed into a resistive load the current would look like the output voltage waveform. What is usually required in real world applications is a DC current through the load that is related to the average output voltage vave . Most readers will see that what is required is a lter on the output of the switching pole. The lter will only respond to the low frequency components in
1 The switching pole, in an average sense, behaves like an electronically controlled attenuator.

1.3 Taxonomy of Power Electronic Systems

1-9

iL
IL
vL

t
vout
vout

L Vd

iL
Cout

RL

S/W ctrl Filter

Figure 1.6: Example buck converter with waveforms. the output waveform of Figure 1.5, the lowest frequency being DC. Therefore if the lter has a lower enough role o frequency the AC components in the waveform will be attenuated, and the DC component will be predominant. Figure 1.6 shows the previous switching pole with the output lter added. The waveforms for the inductor current and the output voltage are also shown. As can be seen, the inductor current waveform and the output voltage waveforms are smoothed compared to the square wave voltage and current waveforms at the switch. This particular circuit is a basic switched mode power supply circuit known as a buck converter. We shall examine this circuit in much more detail in Chapter 2 on page 2-1.

Remark 1.13 The amount of ripple on the current and voltage waveforms depends on the values of the ltering components in Figure 1.6. For example, if the inductor is made larger then the peak-to-peak ripple on iL can be decreased, and similarly if Cout is made larger then the ripple on the output voltage can be made smaller. The other parameter that aects the magnitude of both ripples is the frequency of switching (i.e. fs = 1/T ). The higher the frequency, then for given values of L and Cout , the smaller the ripple on iL and vout respectively. Remark 1.14 The observations and remarks in Remark 1.13 above are another way of saying that the frequency characteristics of the output lter are the determining factor for minimising the ripple on the output for a given switching frequency. Remark 1.15 If it is desired to have vout as a variable quantity i.e. the output can move to dierent reference outputs vref , then the dynamics associated with the output lter are very important. If the ripple is to be kept low, then the switching frequency should be very high, this allowing the ltering components to be kept small to achieve a low output ripple. The small lter components will allow rapid transient output voltage changes with set-point changes.

1-10

Switching Basics

S=W1
Vd

vout

S=W2

Load
vsw1
vsw2

S=W1 ctrl

S=W2 ctrl

Figure 1.7: Conceptual diagram of a H-bridge. 1.3.2.2 Basics of PWM and Frequency Spectra

...frequency characteristics of Pulse Width Modulation

From the previous section one can deduce that the linearisation of the nonlinear switching waveforms from the switching pole is related to the relationship between the frequency characteristics of the switching pole output waveforms and the frequency characteristics of the output lter. Given this relationship, we shall introduce some basic theory on the frequency characteristics of Pulse Width Modulation (PWM), which is the main technique used to generate the output waveforms for most forced commutated power electronic systems. In order to introduce PWM we shall consider a basic building block for many power electronic systems the H-bridge. A basic schematic of this building block can be seen in Figure 1.7. One can see that the name of the topology is derived from the shape of the circuit when drawn.

The outputs of this circuit can be easily tabulated by considering that a 1 is when the switch is connected to the top terminal in Figure 1.7, and a 0 is when a switch is connected to the bottom terminal. The possible switch congurations and the vout voltages are shown in Table 1.1. As can be seen this particular circuit is capable of producing three dierent output voltages.

The simplest way of switching the H-bridge is to use the 10 and 01 switching strategies to produce a Vd output voltage waveform. The average voltage is then determined by the length of time that waveforms spend on each of the voltages. For example, if the time spent at Vd is equal to the time spent at Vd then the average output voltage is obviously 0 volts.

1.3 Taxonomy of Power Electronic Systems S/W1 0 0 1 1 S/W2 0 1 0 1 vout 0 Vd Vd 0

1-11

Table 1.1: Switch congurations and output voltages for a generic H-bridge.

Remark 1.16 The H-bridge circuit is a very versatile power electronic circuit. With the addition of one more parallel switching pole it becomes an inverter module capable of three phase output waveforms. As presented in Figure 1.7 on page 1-10 it is capable of positive and negative output voltages by simply changing the eective duty cycle of the output waveforms. As noted later in the course in Section 2.4.7 on page 2-38 one can develop more sophisticated switching strategies to produce less ripple in the output (when the output is ltered) without an increase in the switching frequency of the devices. I will not preempt this material here, but instead present a more general consideration of PWM switching strategies, their harmonic implications, and implementation approaches. We shall consider a form of PWM called double edge naturally sampled PWM[1]2 . A conceptual diagram of how this PWM is implemented is shown in Figure 1.8. Consider the top part of the diagram. As can be seen the basic idea is that the sinusoidal reference waveform is compared to a triangular modulating waveform of the same amplitude using a comparator. The output of the comparator is a digital waveform. If one takes the average of this digital waveform it is 1/2 and the peak-to-peak value is 1 (since it is digital). Therefore the waveform has a DC component in it of 1/2. The widths of the pulses in this waveform vary, and over each interval corresponding to one period of the triangular carrier the average output is a scaled value of the reference waveform with the 1/2 DC oset added to it. A similar argument can be made for the waveform at the bottom part of the diagram. The dierence here is that the reference waveform is an inverted version of the reference for the top half of the circuit, therefore the this comparator is trying to PWM the output to produce a voltage that is the opposite of the top half of the circuit. These two oset waveforms are then subtracted, which removes the DC component from the output, and doubles the average output voltage compared to the DC oset waveforms. This also means that the output waveform is now bipolar.

...double edge naturally sampled PWM

Let us consider a little theory associated with this. Consider Figure 1.9 which shows a close up of the modulation process. This is a simplied situation in that the reference waveform Vref is considered to be a DC level. Nevertheless one can see the basic idea by analysing this situation.
2 Note that there are a variety of forms of PWM, and this is but one. It does happen to have some nice properties with respect to the spectrum though.

1-12

Switching Basics

vref

t
+ -

vref

PWM output

t
+ -

Figure 1.8: Conceptual diagram showing how to generate double edge naturally sampled PWM. Carrying out some simple geometry on these waveforms we can write: Vref ton = = Vtri T 4 4Vtri (ton t0 ) T Vref 1 + t0 Vtri (1.7) (1.8)

Similarly one can also write: Vref t1 to It is simple to see that: t = to ton = T 2 1+ Vref Vtri (1.12) = Vtri + = t0 + = T 4 4Vtri T (to t1 ) (1.9) (1.10) (1.11)

T 2 Vref + 3 + t0 Vtri

and therefore the average voltage over one cycle of the triangular modulating waveform is: 1 vave = [t Vd ] (1.13) T Vref Vd 1+ (1.14) = 2 Vtri

1.3 Taxonomy of Power Electronic Systems

1-13

m=
Vtri
Vref

4Vtri T

m = 4Vtri T

Vtri

Vd

t
t0 ton t1

to

Figure 1.9: Close-up of naturally sampled PWM process.

1-14

Switching Basics

vL

vL vout

L Vd
iL

L Vd

vout

1
Cout

iL
v sw Cout
RL

vsw

RL

S/W ctrl
Vref
1 2Vtri

+
1 2

Figure 1.10: Equivalence between a switching pole and a variable turns ratio DC-DC transformer. If we let Vtri = 1 and normalise to Vd then we can write the average voltage as: vave 1 1 = + Vref Vd 2 2 (1.15)

Remark 1.17 One can see from (1.15) that there is a DC oset in the output waveform that is unrelated to Vref . Remark 1.18 Equation (1.14) can be broken into two components; the DC V oset Vdc = Vd ; and the component related to the reference signal 2Vd Vref = 2 tri V kpole Vref , where kpole = 2Vd can be considered to be the gain of the switching tri pole. Now equate (1.6) and (1.14): DVd D = = Vd Vd + Vref 2 2Vtri 1 1 + Vref 2 2Vtri (1.16) (1.17)

Figure 1.10 shows the equivalence between the switching pole and a variable turns ratio transformer. The switching pole, in an average sense behaves as a DCDC transformer with an innite turns ratio. When analysing the performance of the system from a control perspective, the ripple in the currents and voltages can be ignored because of the averaging eect of the lter, and the switching pole can be consider to be a linear transformation with a ratio of D. If a similar analysis is carried out for the negative reference waveform and the 180 phase shifted triangular waveform then one one will get a similar expression: vave 1 1 = Vref (1.18) Vd 2 2 and therefore if these two expressions are subtracted then the dierence waveform will eliminate the DC component, and the average dierence waveform will be Vref . A simulation of the PWM scheme of Figure 1.8 was set up in the Saber . This simulation also allows the Fourier components of the waveform to be easily

1.3 Taxonomy of Power Electronic Systems

1-15

rel_oper_gte in1 out in2 conv_d2var diff

d2var

combined_output

c_sin ZeroPhaseDelay amplitude:2 offset:1 frequency:10000 amplitude:0.9 frequency:50 delay:0 rel_oper_gte in1 k:1 in2 out conv_d2var

d2var

c_saw3 amplitude:2 offset:1 frequency:10000 delay:0

Figure 1.11: Saber PWM.

circuit used to simulate double edged naturally sampled

obtained. The Saber circuit appears in Figure 1.11. As can be seen this circuit essentially mirrors the conceptual diagram of Figure 1.8.

Figure 1.12 shows the output of the modulator along with its spectrum. In this simulation the triangular waveform has a frequency of 10kHz, and the reference waveform is a 50Hz sine wave with an amplitude of 0.9. Several observations can be made from this gure: Fundamental component of the output is at 50Hz and its amplitude is 0.9. The rst appreciable harmonics in the PWM output waveform are sidebands of the 10kHz triangular wave frequency. There are no harmonics at the switching frequency of 10kHz.

Let us examine the PWM generated in a little more detail. The absence of the harmonics at the triangular wave frequency (which is the eective switching frequency if a H-bridge converter is being driven) is a direct consequence of the 0 phase shift in the triangular wave for the bottom modulation stream in Figure 1.8 on page 1-12. This results in a 0 phase dierence between the 10kHz harmonic produced in either leg in the H-bridge. Therefore when the harmonic components are implicitly subtracted by the H-bridge one is subtracting two waveforms that are in phase, and the net result is zero. Figure 1.13 shows the component waveforms for the simulation that produced the results of Figure 1.12. One can see that the ZeroPhaseLegSwWaveform and DelayedPhaseLegSwWaveform have a DC oset this is evident from the time domain waveforms and the spectrum where the DC component can be seen in the spectrum of both signals as 0.5. The other interesting observation is that the spectrum of the ZeroPhaseLegSwWaveform and DelayedPhaseLegSwWaveform both have the 10kHz

1-16
Graph0

Switching Basics

Mag() : f(Hz)
1.0

combined_output

0.8

0.6 Mag() 0.4 0.2 0.0 0.0 1.0k 2.0k 3.0k 4.0k 5.0k 6.0k 7.0k f(Hz) 8.0k 9.0k 10.0k 11.0k 12.0k 13.0k 14.0k 15.0k

() : t(s)

1.0

combined_output

Reference
0.5

()

0.0

0.5

1.0

20.0m

21.0m

22.0m

23.0m

24.0m

25.0m

26.0m

27.0m

28.0m

29.0m

30.0m t(s)

31.0m

32.0m

33.0m

34.0m

35.0m

36.0m

37.0m

38.0m

39.0m

40.0m

Figure 1.12: Saber PWM.

simulation output for double edged naturally sampled

switching harmonic, but in the combined_output waveform this component is missing. As mentioned previously this is due to the 180 phase shift in the triangular modulating waveforms and the leg reference waveforms.

Given the above cancellation, it is informative to consider the case where the triangular modulation waveforms are 180 out of phase, as compared to in phase. Figure 1.14 shows the spectrum in this case, and as expected the 10kHz switching frequency in each of the leg switching waveforms is no longer cancelled and appears in the combined output waveform. The real and imaginary components of the Fourier components were taken. As can be seen the real 10kHz components in the leg switching waveforms are opposite in magnitude indicating that when they are subtracted they will add together to give a resultant in the output waveform. The imaginary component is only present in the fundamental as it is a sine wave and hence at 90 to the assumed cosine waveforms for the Fourier series in Saber .

Remark 1.19 The main point to note from the above harmonic analysis is that when triangular PWM is used the phase angle between the triangular carrier waveforms can have important implications on the harmonic content of the output waveforms. The PWM sampling strategy presented above is called naturally sampled because the switching occurs at the natural cross-over points of the triangular

1.3 Taxonomy of Power Electronic Systems

1-17

Graph0
() : t(s)
1.0

Reference

0.5 ()

0.0

0.5

1.0

() : t(s)

1.0

ZeroPhaseLegSwWaveform

0.5 () 0.0 0.5

() : t(s)

1.0

DelayedPhaseLegSwWaveform

0.5 () 0.0 0.5

19.5m
0.6

20.0m

20.5m

21.0m

21.5m

22.0m t(s)

22.5m

23.0m

23.5m

24.0m

24.5m
Mag() : f(Hz)

ZeroPhaseLegSwWaveform

Mag()

0.4

0.2

0.0 0.6

Mag() : f(Hz)

DelayedPhaseLegSwWaveform

Mag()

0.4

0.2

0.0 1.0 0.8 Mag() 0.6 0.4 0.2 0.0 2.0k 0.0 2.0k 4.0k f(Hz) 6.0k 8.0k 10.0k

Mag() : f(Hz)

combined_output

12.0k

Figure 1.13: Component waveforms for double edged naturally sampled PWM.

Graph0
Mag() : f(Hz)
0.6

Leg1

Mag()

0.4

0.2

0.0 0.6 0.4 () 0.2 0.0 0.2 0.4 0.2 0.0 () 0.2 0.4 0.6 0.5 0.4 Mag() 0.3 0.2 0.1 0.0 0.6 0.4 () 0.2 0.0 0.2 0.6 0.4 () 0.2 0.0 0.2 1.0 0.8 Mag() 0.6 0.4 0.2 0.0 0.0 1.0k 2.0k 3.0k 4.0k 5.0k 6.0k 7.0k f(Hz) 8.0k 9.0k 10.0k 11.0k 12.0k 13.0k 14.0k

() : f(Hz)

Real_Leg1

() : f(Hz)

Imag_Leg1

Mag() : f(Hz)

Leg2

() : f(Hz)

Real_Leg2

() : f(Hz)

Imag_Leg2

Mag() : f(Hz)

combined_output

15.0k

Figure 1.14: Spectrum when the triangular modulation waveforms are 180 out of phase.

1-18

Switching Basics waveform and the reference waveform. This form of modulation is particularly suitable to analogue implementation, and indeed many early analogue modulators used this strategy or variants of it. However, this particular technique is dicult to implement digitally because the times for switching at the crossover points can only be calculate by solving a transcendental equation, which is time consuming in a microprocessor system. To make the strategy amenable to digital implementation, a regular sampled double edge PWM strategy can be employed. This is achieved by sampling the reference waveform at the peak of the triangular waveform and then holding this sample constant until the next peak of the triangular waveform. It is this constant sampled value that it compared to the triangular wave to determine the switching time. The use of this constant sample means that the cross point of the triangular waveform is easy to compute digitally. Sampling at the peak of the triangular waveform prevents multiple switching due to the reference step changing at in inappropriate time.

regular sampled double edge PWM

1.4

Summary

This chapter has outlined the following: 1. Why use switching? it allows very ecient control of electrical energy. 2. The basic taxonomy of power electronic converter systems into naturally commutated systems and forced commutated systems. The fundamental dierences in the operational principles of these two dierent approaches are presented, and the semiconductor devices that are associated with them are briey discussed. 3. The fundamental operational element of forced commutated systems, the switching pole, was introduced. 4. Discussion of the use of ltering on the output of forced commutated power electronic systems to hide the inherent non-linearity of the system is introduced. 5. Finally some of the basic concepts of PWM and its frequency spectra are presented.

Chapter 2

Fundamental Topologies
2.1 Introduction

This course part will not attempt to cover every issue related to the design and operation of switch mode power supplies there is more than enough work in this area to ll a whole course by itself. Instead, the material shall seek to emphasise the main types of switch mode converter structures, their fundamental operational principles, the various areas where the dierent structures are useful, and nally aspects of the design and control of the switch mode converters. Before looking at the dierent structures for switch mode converters, we should rstly dene what we mean by switch mode converters. Denition 2.1 Switch Mode Converters (SMCs) are converters which accept a DC input and generate a DC output. Switched mode converters are usually only operating at powers up to 10s of kilowatts. The switched mode converter usually nds application as a power supply regulator in such items as computers, television sets, stereo systems etc., in fact almost all modern electronic consumer devices use some form of switch mode converter. One of the other areas of application of switch mode converters are aerospace systems, where weight is a very important consideration. The switch mode inverter, on the other hand accepts a DC input and generates an AC output. These are treated in their own section of this course, since these devices tend to nd application in the high power industrial systems area, and are most often used for the control of electrical machines (although they are not exclusively used for this).

2.2

References

References to switch mode power supplies are often contained in texts on electronics and power electronics. There are some specialised book written on the design of switching power supplies. Tutorial references that readers may nd useful are [2, 3, 4, 5]. One can nd a lot of material in the IEEE Transactions on Industrial Electronics, and the IEEE Transactions on Power Electronics. This information

2-2

Fundamental Topologies tends to be of a more detailed nature on specic design issues with converters, or new converter topologies.

2.3

Taxonomy of Switch Mode Converters

There are literally hundreds of dierent circuit congurations for switch mode converters. However, one can classify most of the them into two basic categories: buck converters boost converters Step-down or buck converters. Step-up or boost converters. Many of the other topologies that are in the literature are combinations of these two basic topologies. The basic layout of a SMC system is shown in Figure 2.1 below. The input to the converter is usually the mains. Since this is AC the rst step is to convert this to DC via a rectier. Notice that one can also feed DC, from a battery, directly in at the output point of the rectier. The unregulated DC is usually ltered with a capacitor, before feeding the DC-DC converter electronics. The output of this stage then feeds the load.

Battery

AC line voltage Uncontrolled Filter DC-DC capacitor converter (1 or 3 diode rectifier DC DC DC phase) (unregulated) (unregulated) (regulated) Desired output voltage

Load

Figure 2.1: Block diagram of the structure of a typical DC-DC converter.

In the following diagrams the switches are assumed to be unidirectional. The direction of current ow is indicated by the arrow on the switch.

2.3.1
output voltage is always less than input voltage

Step-down or Buck Converters

The step-down or buck converter is distinguished by the fact that the output voltage is always less than the input voltage. This means, that regardless of the switching strategy, it is impossible to get the output at a higher voltage than the input. The distinguishing circuit feature of the buck converter is that one cannot get any current to ow in the circuit when the power device is turned on, if the output voltage is greater than or equal to the input voltage. Figure 2.2 shows a basic circuit for a buck converter. Before analysing the circuit, let us look at it heuristically to determine its basic operation. When

2.3 Taxonomy of Switch Mode Converters the switch SW closes, current will ow to the resistive load via the inductor L. The capacitor C will charge up during this process. Note that there is a transient involved in the inductor current building up and the voltage being established on the capacitor. When the switch is opened the current through the inductor cannot stop instantly (if it does then the voltage across the inductor will become very large and the circuit will most probably be destroyed). The diode in the circuit will become forward biased, allowing the current in the inductor to continue owing in the same direction (towards the load). During this phase of operation the energy that was stored in the eld of the inductor during the switch on time is being transferred to the load. If the switch remains open for a long time the inductor current gradually decreases to zero, and at the same time the current drawn from the capacitor increases. If the switch is closed before the inductor current decreases to zero, then the current begins to increase again. Remark 2.1 Note that the maximum current that can ow through the inductor if the switch is left closed is Vd /RL . Remark 2.2 If the inductor current goes to zero then the converter is said to be operating in discontinuous mode. If it does not go to zero, then the converter is operating in continuous current mode. Generally speaking, it is desirable to operate the converter in one mode or the other, without a change of mode. Changes in mode can result in diculties in controlling the output voltage of the converter. A change of mode can occur depending on load changes. Remark 2.3 If the lter were not present in Figure 2.2 then the output voltage would exactly mirror the input voltage i.e. if the switch is opened an closed then the output would be a square wave voltage. The lter has to be designed so that the cuto frequency is signicantly below the switching frequency. If this is the case then the lter will reject most of the AC components present at the vod , so that the output voltage will essentially be a DC value equal to the average value of the voltage vod . Remark 2.4 One of the distinguishing features of this type of circuit is that when the switch is closed the input is connected to the output, but when the switch is open the input is disconnected from the output. Another distinguishing feature of the buck converter is that the inductor is not placed across the input voltage when the switch is closed. The inductor has a voltage imposed across it that is usually somewhat lower than the input voltage. This means that the inductor does not store all the energy being supplied by the input.

2-3

buck converter distinguishing features

Remark 2.5 If multiple output voltages are required then the buck converter as depicted here is not the topology to use. Other converters, such as the forward converter, that are related to the buck converter can be used. Remark 2.6 Since the switch is at the input to the converter, then the input current is discontinuous. Therefore the input lter to this circuit is more complicated compared to other converter types.

2-4

Fundamental Topologies

Energy storage inductor

id Vd

SW

Low pass filter iL L

vod

io

vL

RL Load

Vo

Figure 2.2: A basic buck or step-down converter. Practical issue 2.1 Driving the gate of a buck converter can be a problem. If we assume that the switching element is a n-channel MOSFET (as it would be for many designs), then the gate voltage often has to be 5V, and in some cases 10V above the supply voltage. This complicates the gate drive, since one has to fabricate the higher voltage using a transformer based gate drive circuit.

2.3.2
output voltage that is always greater than the input voltage

Step-up or Boost Converters

As the name implies, the boost or step-up converter has an output voltage that is always greater than the input voltage. The boost converter also has the added advantage that the output can isolated from the input (using transformer isolation). Figure 2.3 shows a conceptual diagram of a non-isolated boost converter. The basic operation mechanism is that when the switch is closed the load is isolated from the input by the diode, and current builds up in the inductor. This current build is eectively storing energy in the eld of the inductor. When the switch is opened, the current in the inductor wishes to continue to ow in the same direction and with the same magnitude. Therefore the diode will turn on and the current will immediately ow into the lter capacitor and any connected load.

Remark 2.7 If the voltage on the capacitor is larger than the supply voltage, the inductor will produce what ever voltage is required so that Vd + vL = Vo . This is required in order for the current to continue to ow in the inductor. One can see that because the polarity of vL shown in Figure 2.3 always has to reverse for this situation, then the output voltage must always be greater than the input voltage (except under initial start-up conditions). Remark 2.8 The main feature of the boost converter is that current can ow through the switch regardless of the relationship between the input and output voltages. This usually occurs because the input to the circuit is disconnected from the output when the switch is closed. It is this feature that one must look for when one is trying to ascertain what category a particular topology falls into.

boost converter distinguishing features

2.3 Taxonomy of Switch Mode Converters

2-5

Energy storage

iL

L +
vL

io

SW C

+
Vo

Vd

Figure 2.3: A basic boost or step-up converter. When the switch is opened, the input is connected to the output because the diode switches on. Another distinguishing feature is that when the switch is closed the input voltage is placed across the inductor (so that it stores all the energy being supplied by the input), and when the switch is opened the inductor is placed in series with the load. and this stored energy is transferred to the load. Remark 2.9 In a boost converter the inductor fullls an energy storage function, whereas in the buck converter the inductor forms a ltering function. Therefore, one can view the boost converter as not having a lter capacitor. This distinction is not very clear for the non-isolated converter, but when we look at isolated converters in the next chapter we shall see that there is a clear distinction. Remark 2.10 There is a maximum power that is practical to build for converters that rely on the energy storage principle. This is especially true for low input voltages. As we shall see in the next chapter a related converter is the yback converter, which operates using the same principle, and hence suers from the same power limitations. In order to cater for high power output with an energy storage converter, one needs to have a very small energy storage inductor (since E = 1 Li2 , and therefore the current contributes most signicantly to the stored 2 energy). It turns out that for powers much above 50W when the input voltage is low, the inductance becomes very small and is comparable with the parasitics of the circuit. Therefore, the circuit becomes very dicult to manufacture.

2.3.3

BuckBoost Converters

The buckboost converter seeks to combine the properties of the previous two converters. This converter type allows the output to be less than or greater than the input voltage. Furthermore, this type of converter also allows a negative polarity output to be generated. The most obvious way of generating a buckboost converter is to cascade the buck and the boost converter. In practice, however, this is not usually done, since one can obtain the same performance from the system using a single switch

2-6

Fundamental Topologies arrangement. In this case one must really consider the circuit conguration to be a new one, and not a combination of the previous two.1 In order to understand the operation of this circuit let us rstly look at a two switch implementation. Figure 2.4 shows the conceptual circuit for this. In this circuit both switches are either closed at the same time, or they are open at the same time. If both the switches are closed, then the circuit takes on the classic boost converter conguration. If the output voltage is higher than the input voltage, current can still ow through the inductor. When both the switches are opened, then the inductor is positioned in the circuit as in the classic buck converter, and the current built up during the switch closed stage circulates via the diodes through the output capacitor. Remark 2.11 The key to the circuit of Figure 2.4 is that the switches eectively change the circuit conguration, from a boost circuit during the energy storage phase, to a buck circuit when energy is transferred to the load.

SW1

iL

io

+
Vd

L vL

SW2 C
Vo
RL

Figure 2.4: Two switch buckboost converter. Figure 2.5 shows a simplied circuit for a buck-boost converter circuit using only one switch. The crucial change in this circuit is the swap of the inductor and the switch and the reversal of the diode as compared to the boost converter of Figure 2.3. The swapping of the inductor and the switch and reversing the diode means that the full input voltage is applied across the inductor when the switch is closed (as in the boost converter). This means that the inductor is essentially a energy storage element, as in the boost converter. However, when the switch is opened the input is no longer connected to the supply (as is the situation in the buck converter), and therefore the constraint that the output must be larger than the input is removed. The resultant voltage across the capacitor is simply related to the amount of energy stored in the inductor, and the current required by the load resistor. If one wishes to increase the output voltage then the switch is closed for a longer period of time, and it the voltage is to be decreased then the switch is closed for a shorter period of time. Remark 2.12 One can see from the above explanation that the operation of this circuit has characteristics of both the buck and the boost converter. Reiterating, the energy storage in the inductor is from the boost converter (when the switch
1 One must consider the buck-boost converter to be a conguration in its own right, since it is very dicult to see the separate buck or boost converters in the single switch circuits.

2.3 Taxonomy of Switch Mode Converters

2-7

id

SW +

Vd

vL L

iL

Vo

RL

io
Figure 2.5: Single switch Buckboost converter circuit. is closed), and the disconnection of the input from the output when the switch is open is the same as the buck converter. One can therefore identify a buckboost topology by looking for the fact that the inductor is placed across the supply and disconnected from the load during the energy storage phase when the switch is closed, and the inductor is disconnected from the supply and placed in the output circuit when the switch is opened. Remark 2.13 One should note that the voltages one can obtain from the buck boost converter are related to the relationship between the load, the capacitor, and the inductor . Remark 2.14 The limitations on the performance of the buck-boost converter are very similar to those of the buck and the boost. In addition the presence of two diodes in the circulating current path can lead to ineciency (even when Schottky diodes are used).

2.3.4

Ck Converters

This converters peculiar name arises from its inventor (pronounced Ch-ooo-k). It was arrived at by essentially forming a dual of the buckboost converter. Similarly to the buckboost converter it is capable of producing voltages that are larger and smaller than the input voltage, and the output voltage is negative relative to the same reference as the input voltage. One fundamental dierence is that the primary storage element is a capacitor, as opposed to the inductor in the buckboost converter. Figure 2.6 shows a basic Ck converter. This circuit is slightly more dicult to understand. Therefore we shall consider two situations: one when the switch is closed, and the other when the switch is open. Consider Figure 2.7, which shows the situation when the switch is open. For the sake of the discussion it shall be assumed that the current in the inductors

2-8

Fundamental Topologies

iL

vC 1 + -

iL

+
Vd

L1 vL
1

SW

C1

L2 vL

+ C
Vo
RL

io

Figure 2.6: The Ck converter. is continuous. In this case the capacitor is charged by the current iL1 owing from the input. The current iL2 owing on the load side of the circuit continues to deliver energy to the load. Note that both iL1 and iL2 would be decreasing under this circuit condition. Remark 2.15 The input current, iL1 , would be decreasing because the capacitor voltage is greater than the input voltage. This can be deduced from the fact that: vc1 = Vd + Vo (2.1)

Remark 2.16 Equation (2.1) results from the fact that the average voltage across the inductors in the circuit must be zero under steady state conditions the total volt-seconds change across an inductor must be zero over a complete switching cycle under steady state conditions.

iL

vC 1 + -

iL
L2 vL

+
Vd

L1 vL

+ C
Vo
RL

io

Diode is short circuit

Figure 2.7: Ck converter with the switch open.

Let us consider the situation when the switch is closed. The circuit under this condition is shown in Figure 2.8. Clearly the diode is reverse biased under this condition, and the input inductor, L1 is storing energy with the input voltage

2.3 Taxonomy of Switch Mode Converters

2-9

iL

vC 1 + -

i L2

+
Vd

L1 vL

C1

L2 vL

+
C2 Vo RL

io

Switch is closed circuit

Figure 2.8: Ck converter with the switch closed. appearing across it. The current, iL2 is also owing through the switch. This current to will be increasing with the capacitor voltage driving it. Therefore, the energy that has been stored in the capacitor is being transferred to the load. Remark 2.17 The important point to note about the operation of the Ck converter is that the capacitor C1 is the element that is actually transferring the energy to the output (and not the inductor as in the other converters that we have looked at). The inductors in the circuit are essentially performing a ltering function on the input currents. Remark 2.18 Examination of Figures 2.7 and 2.8 indicate that the switch simply transfers the capacitor from the input where it receives energy from the supply, to across the load where it supplies energy to the load. Remark 2.19 The capacitor in the Ck converter has to be able to handle high ripple currents.

2.3.5

Full Bridge Converters

This is the most complex of the converters, in terms of the number of semiconductor components, that we shall look at. It is also the most versatile, in that it can nd application in everything from SMCs to dc-to-ac drives. We shall only be considering the former of these two applications. Figure 2.9 shows a conceptual diagram of the full bridge converter circuit. Notice that it has a total of eight semiconductors, with four of them being unidirectional switches. The application of a full bridge circuit depends on the control applied to the bridge. One of the most important properties of the full bridge is that it operates in all four quadrants of the io vo plane. This means that the converter can produce positive and negative output voltage and positive and negative current. The previous converters could only operate in one quadrant (positive or negative voltage, and only positive current). This fact also means that the full

2-10
Leg A Leg B

Fundamental Topologies

DC machine load

SWA+

DA+

SWB +

DB +

La
i0

Vd

v 0 = v AN - v BN

Ra
ea

v AN
SWADASWBDB- v BN

+ -

Figure 2.9: Full bridge converter. bridge converter can accept a dc input and produce an ac output (this mode of operation is known as inversion, and will not be discussed further at this stage). One can see from Figure 2.9 that the switches have diodes in parallel with them. This acknowledges the fact that the switches shown in the diagram are considered to be constructed of a technology that only conducts current in one direction. It also means that if a switch is closed and the current is in the reverse direction then the current will ow through the diode and not through the switch. There are two main switching strategies that can be adopted using the full bridge inverter: Bipolar switching. Unipolar switching. Bipolar switching is the name given to the switching strategy when the A+ and B are switched together, and the B+ and A are switched together. Therefore the voltage applied to the load is Vd . There are no other voltages that can be applied. One can deduce that it the switching is such that 50% of the time the A+, B is in force, and the remainder of the time the B+, A state in in force, then the average voltage across the load is zero. By varying the switching around this the voltage can be varied from zero to Vd (when only A+, B are in force) to Vd (when only B+, A are in force). Remark 2.20 The full bridge converter can only produce output voltages that are in the range of Vd vo Vd . Unipolar switching, on the other hand, exploits another degree of freedom available in the full bridge to gain a lower current ripple in the output. One can

2.4 Basic Analysis of Switch Mode Converters also switch two devices in dierent legs but on the same rail. For example, one could switch the A+, B+ devices. This eectively places zero volts on the load, and allows the current to freewheel through one of the switches and the diode paralleling the other device. The mode of operation clearly changes the rate of change the current as compared to the bipolar switching mode.

2-11

2.4

Basic Analysis of Switch Mode Converters

In this section we shall do some basic analysis of the converters mentioned in the previous section. Before carrying out this analysis we shall rstly dene the concept of duty cycle, also known as mark-space ratio. We shall also introduce the concept behind the development of the switching waveforms. This work has already been presented in a general way in Section 1.3.2.2 on page 1-10, so some of what is below is a refresher of this presentation with an emphasis on this particular application of PWM.

2.4.1

Duty Cycle

Consider Figure 2.10, which shows a switching waveform. The duty cycle of this waveform is dened as: ton (2.2) D= Ts Considering the waveform in Figure 2.10 we can work out the average voltage produced: vave = = = 1 Ts 1 Ts
Ts

vo dt
0 ton Ts

Vd dt +
0 ton

0dt

ton Vd Ts = DVd

(2.3)

From (2.3) one can see that the average voltage is directly proportional to the duty cycle of the switching.

2.4.2

Basic PWM Generator

In the previous section we dened the concept of a duty cycle. The next question that arises is: how does one generate the switched output in a manner that a desired average output voltage is produced?. The simplest technique, that actually arose from the days of complete analogue PWM generators is to use a sawtooth or triangular waveform. This concept is shown schematically in Figure 2.11. One can see from Figure 2.11 that the slope of the sawtooth is: m= vst Ts

2-12

Fundamental Topologies

SW

Vd

v0

v0

ON
Vd

OFF

V0

0
t on Ts
t off

Figure 2.10: Denition of the terms related to duty cycle.

2.4 Basic Analysis of Switch Mode Converters Therefore one can say that: ton = Vcontrol m Vcontrol = Ts vst Vcontrol vst Vcontrol Vd vst (2.4) (2.5)

2-13

One can see from (2.5) that: D= and hence: vave = DVd = or vave Vcontrol where the constant of proportionally is Vd /vst .
Sawtooth waveform

(2.6)

(2.7)

v st
Vcontrol

ON
Vd

OFF

ton Ts

toff

Figure 2.11: Waveforms in a sawtooth based PWM modulator. Remark 2.21 Note that if Vd = vst then the constant of proportionality is one. Therefore the average output voltage is the same as the control voltage. In most PWM generators this is not the situation. The circuitry required to perform the PWM generation using the waveforms of Figure 2.11 is very simple. Figure 2.12 shows a conceptual diagram of the required circuit.

Remark 2.22 The PWM generator circuit shown in Figure 2.12 is usually implemented using analogue circuitry. This can be done at a very low cost. It can also be implemented in a digital system.

2-14

Fundamental Topologies

Vdesired

+ Amplifier

v control

+
Comparator

V0

Switch control

Sawtooth waveform
Figure 2.12: Simple PWM generator circuit.

2.4.3

Simplied Analysis of the Buck Converter

In this section we shall carry out a simplied analysis of the characteristics of the buck converter. The assumptions used are detailed later. However, one observation that can be made about the circuit is that the inductor/capacitor combination in Figure 2.2 eectively form a low pass lter. This lter lters out the harmonics in the switching waveform, which is of the form of Figure 2.10. For the ltering action to be eective, the -3db roll-o of the LC circuit has to be substantially lower than the switching frequency of the inverter (i.e. fs = 1/Ts ). This means that the eect of the switching on the output current is largely eliminated, and the switching current is essentially dc. This fact forms the basis of one of the assumptions made later. As mentioned Section 2.3.1 the buck converter can operate in continuous conduction mode or discontinuous mode. This term refers to the current in the inductor. In continuous mode, the current in the inductor never goes to zero, whereas in discontinuous mode the current will go to zero at some point in the switching time Ts . Let us now consider each of these modes separately. 2.4.3.1 Continuous Conduction Mode

We shall assume that the circuit is in steady state for the development of the expressions. If the circuit is in steady state then we immediately know that the sum of the volt-seconds applied across the inductor when the switch is closed plus the volt-seconds when the switch is open must equal zero.2 The waveforms and circuit congurations for the buck converter are shown in Figure 2.13. Note 2.1 The following analysis assumes that the capacitor voltage essentially remains constant over a complete PWM cycle. This in turn implies that the value of the capacitor is large enough that it can absorb the charge supplied from the inductor current without signicant voltage rise.
2 This is true because = vdt, and the ux in the inductor must not increase over a complete period for the circuit to be in steady state.

2.4 Basic Analysis of Switch Mode Converters Remark 2.23 A consequence of the previous note is that over a complete cycle of the PWM the average current supplied by the inductor must be equal to the average current supplied to the load. If this were not the case then the capacitor voltage would continually rise or fall over time as the circuit operated, thereby violating the steady state assumption. Notation 2.1 The capitalised currents and voltages in Figure 2.13 and the following analysis refer to the average values of the currents, and not the instantaneous values.

2-15

vL
Vd -Vo

0
- 0 V iL IL

A t B

Ts

Io

0
t on
iL t off iL

io

io

Vd

L vL

Vo

Vd

L vL

Vo

Figure 2.13: Currents and circuit congurations for a buck converter.

Remark 2.24 As stated above the average inductor voltage over the complete PWM interval has to be zero for steady state operation. Therefore, by inspection of the inductor voltage plot in Figure 2.13 we can say that the volt-seconds applied must be zero.3 Therefore: (Vd Vo )ton = Vo (Ts ton ) This expression can be rearranged to give: Vo ton = = D (duty cycle) Vd Ts (2.9) (2.8) linear voltage gain

3 Note the dc output voltage assumption appears in Figure 2.13 as the constant voltages over each of the switching intervals.

2-16

Fundamental Topologies Remark 2.25 Keeping in mind the assumptions in the above analysis, this (2.9) means that the output voltage varies linearly with the duty cycle, given a xed input voltage. Remark 2.26 One could also obtain the relationship of (2.9) by averaging the vo voltage shown in Figure 2.10, realising that this voltage waveform is the form of the input waveform. The output is then obtained since the average input voltage has to be the same as the average output voltage for steady state to exist in the circuit (else the current through the inductor would be increasing or decreasing over a number of cycles.) By using conservation of energy one can also calculate the ratio of the input and output currents. Assuming that the circuit is essentially lossless, then we can say: Pd = Po (2.10) This can be clearly expanded as: Vd Id = Vo Io or Vd 1 Io = = Id Vo D (2.11)

(2.12)

Remark 2.27 As can be seen from (2.12) the buck converter acts the same as an electronic transformer when in continuous current mode. Remark 2.28 Even though the current iL is fairly smooth, the input current id is jumping from some peak value to zero every time the switch is opened. Depending on the source for the converter, the input may have to be ltered to smooth out these current uctuations. 2.4.3.2 Boundary between Continuous and Discontinuous Conduction

In this section we shall establish the condition for the converter to move from continuous to discontinuous conduction. Discontinuous conduction occurs when the current iL goes to zero at or before the end of the control period. Consider the current waveform shown in Figure 2.14. One can formally work out that the average value of such a waveform is 1 iLpeak , which is also obvious using geometric arguments based on 2 the fact that the waveform is made up of triangles. Therefore one can derive the following expression for the minimum average current that must be owing in the circuit to sustain continuous conduction: ILB = 1 DTs 1 iLpeak = [(Vd Vo )ton ] = (Vd Vo ) = IoB 2 2L 2L (2.13)

current required for continuous inductor current

where ILB is the minimum average inductor current, and IoB the minimum output current value (remember the two are the same given the steady state assumption). Equation (2.13) can be further manipulated using the expression (2.9) to eliminate V0 , and assuming that Vd is constant, giving:

2.4 Basic Analysis of Switch Mode Converters Ts Vd (D D2 ) 2L

2-17

ILB = IoB =

(2.14)

On can dierentiate (2.14) to nd the duty cycle for the maximum ILB for given Vd , Ts , D, and L: dILB Ts Vd = (1 2D) (2.15) dD 2L Clearly from (2.15), the maximum value occurs at D = that value is: Ts Vd ILBmax = 8L
1 2

Therefore using (2.14) (2.16)

iL
v L = (Vd -Vo )

peak

Current is zero here

iL

0
I LB = I oB

- o V t on Ts
Figure 2.14: inductor. Current waveform at the point of discontinuous current in the

t off

Remark 2.29 Equation (2.14) denes the value of the average current required in the inductor to just allow continuous conduction. Therefore, the maximum value for this average current, which is the value dened in (2.16) occurs when the duty cycle is 1/2. This means that the onset of discontinuous current operation occurs rst if the duty cycle is around this value (which implies that the output voltage is 1 Vd ). 2 Remark 2.30 The previous remark implies that one can design the converter so that the minimum load current is larger than ILBmax in order to ensure continuous conduction (assuming that continuous conduction is the desired operation mode). Note that one of the main design parameters is the inductance value itself. Another point to note is that the input voltage is a parameter in (2.16), so if this voltage varies over a range then this must be taken into consideration. Finally, the load of the system will dene the load current required, and via the other considerations mentioned above it will dene the parameters of the converter.

2-18

Fundamental Topologies Remark 2.31 There are two main cases to investigate in relation to discontinuous current the constant Vd case and the constant Vo case. Let us now consider each of these. 2.4.3.2.1 Discontinuous Current with Constant Vd . In many applications the input voltage remains constant, and only the output voltage is varied. We are interested in what the voltage gain of the inverter is under the condition of discontinuous current. Note that we found that with continuous current the voltage gain of the converter was D, and hence it operated linearly. However, as we shall see if the converter operates in discontinuous mode then the voltage gain of the converter becomes non-linear. The following discussion is with reference to Figure 2.15.

iL

peak

Current is zero here

iL

I L = Io

v L = (Vd -Vo )

- o V DTs Ts
Figure 2.15: Current waveform for a buck converter with discontinuous current. voltage conversion ratio In order to calculate the voltage conversion ratio, we rstly start by using the volt-seconds condition i.e. the total volt-seconds over a control interval must be zero for steady state operation: (Vd Vo )DTs + (Vo 1 Ts ) = 0 which leads to the following relationship for the voltage ratio: D Vo = Vd D + 1 (2.18) (2.17)

D1Ts

D2Ts

The next relationship to establish is the value of the average current in the inductor under this condition depicted in Figure 2.15. We shall use a technique similar to that used for (2.13). We must rstly get an expression for the peak inductor current. It can be seen from Figure 2.15 that iLpeak can be written as: iLpeak = Vo 1 Ts L

2.4 Basic Analysis of Switch Mode Converters We are now in a position to calculate the average inductor current over a period. This is most easily carried out by calculating the area under the iL current in Figure 2.15 for a complete control cycle and dividing by Ts . Therefore we can write: Io = =
1 2 iLpeak (DTs

2-19

+ 1 Ts )

Ts

(2.19) (2.20) (2.21) average inductor current discontinuous mode

1 iL (D + 1 ) 2 peak 1 Vo 1 Ts (D + 1 ) = 2 L

Substituting for Vo using (2.18) one can manipulate (2.21) to give: Io = 1 Ts Vd D1 2 L (2.22)

Clearly this can also be expressed in terms of the minimum load current that results in discontinuous conduction using (2.16) to give: Io = 4ILBmax D1 (2.23)

We can now nd an expression for 1 in (2.18) by rearranging (2.23) to give: 1 = Io 4ILBmax D (2.24)

Substituting (2.24) into (2.18) and rearranging we get the nal expression for the voltage ratio: Vo D2 = (2.25) Io Vd D2 + 1
4 ILBmax

Remark 2.32 The most notable feature of (2.25) is that the voltage ratio is now non-linear. In other words there is a non-linear gain through the converter. Clearly this complicates the design of the control. Furthermore, the onset of nonlinearity with the onset of discontinuous current would make the control even more dicult if the converter moved from continuous current to discontinuous current operation. Figure 2.16 is a plot of (2.25) in the discontinuous region, and (2.9) in the continuous region. Remark 2.33 As noted in the previous remark, the voltage ratio to duty cycle relationship for discontinuous operation can be seen, from Figure 2.16, to be very non-linear .

voltage ratio is now non-linear

2.4.3.2.2 Discontinuous Current with Constant Vo . In many applications the output voltage should be kept constant whilst the input voltage varies. An example of this type of application is a traditional switch mode power supply (SMPS), where the power supply should keep a constant voltage output despite variations of the mains supply voltage.

constant output

voltage

2-20

Fundamental Topologies

Boundary for onset of discontinuous current

D =10 . D = 0.9 D = 0.8 D = 0.7

0.8

Vo 0.6 Vd

D = 0.6

0.4

DISCONTINUOUS CURRENT REGION

D = 0.5

CONTINUOUS CURRENT REGION

D = 0.4 D = 0.3 D = 0.2 D = 01 .

0.2

0.2

0.4

0.6

0.8

1 Io
I LB
max

1.2

1.4

1.6

D = 0.0 1.8 2

Figure 2.16: Voltage ratio of the buck converter for continuous and discontinsV uous operation modes and constant Vd . NB. ILBmax = T8Ld

2.4 Basic Analysis of Switch Mode Converters If one uses (2.14) and the linear voltage ratio (2.9), one can calculate the value of the current at the edge of continuous current conduction in the inductor. Substituting for Vd in (2.14) one gets: ILB = Ts Vo (1 D) 2L (2.26)

2-21

which clearly has a maximum at D = 0, giving: ILBmax = Ts Vo 2L (2.27)

Remark 2.34 Note that (2.27) is the expression for ILBmax in terms of Vo whereas the expression (2.14) is in terms of Vd . In (2.27) the assumption is that Vo is constant (held there by the control of D), and Vd is totally variable. Remark 2.35 Operation at D = 0 for a constant nite Vo is a mathematical artifact, since this would imply that Vd = (given that D = Vo /Vd in continuous current mode). Using (2.26) and (2.27) we can write: ILB = (1 D)ILBmax (2.28)

Using (2.18), (2.21), and (2.27) one can write the following expression (note that both (2.18) and (2.21) are valid regardless of the constraint on Vd or Vo ). Now from (2.18) we have: DVd (2.29) Vo = D + 1 Substituting into (2.21) one can write: Io = Using (2.27) we can write: ILBmax Ts = 2L Vo Substituting this into (2.30) we get: Io = which can be manipulated to give: 1 = Io ILBmax Vo DVd (2.33) ILBmax Vd D1 Vo (2.32) (2.31) Ts Vd D1 2L (2.30)

which can be substituted back into (2.18) and manipulated to give: Vo D= Vd

Io ILBmax Vo 1 Vd
1 2

(2.34)

2-22

Fundamental Topologies

1
Vd = 125 . = 15 . = 2.0 = 3.0 = 4.0

0.8

Vo Vd Vo

0.6 D 0.4 DISCONTINUOUS CURRENT REGION

CONTINUOUS CURRENT REGION

Vd Vo Vd Vo Vd Vo

0.2
Vd Vo

= 5.0

0 0 0.2 0.4 0.6 Io I LB 0.8 1 1.2

max

Figure 2.17: Characteristics of the buck converter with constant Vo . NB. sV ILBmax = T2Lo .

2.4 Basic Analysis of Switch Mode Converters Remark 2.36 As can be seen from (2.34) the relationship between D and Vo /Vd is again highly non-linear. As in the constant Vd case, the control for constant Vo would be much simpler if operation is maintained in the continuous current mode.

2-23

Remark 2.37 The ILBmax in Figure 2.17 is dierent from that in Figure 2.16. Figure 2.17 shows the inter-relationship between the duty cycle, load current and inverse voltage ratio for the buck converter. The non-linearity in the discontinuous current region of operation is very evident from the gure. Remark 2.38 Figures 2.16 and 2.17 are actually equivalent. For example, at Vo = 1. The corresponding D = 0.5 in Figure 2.16 Vd = 0.5 and ILB Io
max(D=0.5)

point in Figure 2.17 is

Vd Vo

= 2 (i.e.

Vo Vd

= 0.5), D = 0.5 and

Io ILBmax(D=0)

= 0.5.

The latter can be seen from (2.27) and (2.16) as follows. From (2.16): ILBmax(D=0.5) = Ts Vd Ts Vo Vo = (using Vd = ) 8L D8L D Ts Vo (for D = 0.5) = 4L 1 = ILBmax(D=0) 2 (2.35) (2.36) (2.37)

Correspondence can be found for all the other points. 2.4.3.3 Output Ripple

In the analysis thus-far we have assumed that the capacitor is large enough that the voltage at the output does not change substantially. This was an approximation that made the analysis simpler, but in reality is not true. In many applications that ripple at the output is important for example, in power supply applications many circuits cannot tolerate signicant ripple. In order to get a feel for the voltage ripple we shall assume that the current is continuous. A further simplication is that the impedance of the capacitor is very much lower than the load resistance, and therefore we can assume that the ac component of the current ripple all ows into the capacitor, and the average current over a switching interval ows into the resistor. The following analysis is with reference to Figure 2.18.

voltage ripple

Remark 2.39 One can immediately see from Figure 2.18 that we are assuming that the ripple is small enough to be insignicant compared to the voltage across the inductor hence the inductor voltages are drawn as piecewise constant. Remark 2.40 One could also carry out a complete circuit analysis for the buck converter and get very precise voltage ripple waveforms. The equations for this are straight forward, but just a little messy.

2-24

Fundamental Topologies

vL
Ts
Vd - vo

0
-vo

iL

DI L 2

I L = Io

DQ
Ts 2

0
vo

Vo

DVo

t
Figure 2.18: Output voltage ripple for a buck converter.

2.4 Basic Analysis of Switch Mode Converters The output voltage ripple expression can be developed using a capacitor charge approach: Q 1 1 IL Ts Vo = = (2.38) C C 2 2 2 The next step is to get an expression for IL . From the denition of the voltage across an inductor we can say the following: IL = vL t L (2.39)

2-25

Considering the o time, we can carry out the following calculations. If t = to , and we can write to = Ts ton , and ton = DTs (from (2.2)) then we get t = to = (1 D)Ts . Using this expression, and the fact that vL = Vo we can write: Vo (1 D)Ts (2.40) IL = L Substituting this expression into (2.38) we can write the following expression for the voltage ripple: Ts Vo (1 D)Ts 8C L 2 Vo 1 Ts (1 D) = Vo 8 LC Vo = (2.41) (2.42)

This expression can be further manipulated into a form that highlights the ltering requirements of the LC combination. Realising that: fc = then (2.42) can be written as: Vo 2 (1 D) = Vo 2 where fs = 1/Ts . Remark 2.41 Equation (2.44) emphasises that fact that making the lter pole of the LC lter circuit much smaller than the frequency of the PWM results in a lower output voltage ripple. Remark 2.42 Note that (2.44) indicates that the ripple is independent of the average inductor current (in continuous conduction mode). Therefore, keeping in mind the assumptions made in the analysis, the load on the inverter does not inuence the amount of ripple. The most relevant of these assumptions in relation to this issue is that the capacitor impedance is much lower than that of the load. 2.4.3.4 Simulation fc fs
2

1 2 LC

(2.43)

(2.44)

One can set up a computer simulation of the buck converter circuit. The particular simulator used for this exercise is the Saber by Analogy. The circuit set up in the simulator is shown in Figure 2.19. The switching device is modeled

2-26

Fundamental Topologies by a switch which has a very high o resistance, and a very low on resistance. The diodes in the circuit are essentially ideal, in that they have a zero turn on voltage.
prbit_l4 BIT STREAM prbit_l4 BIT STREAM 100

sw1_l4

switch_output_voltage 50e-3

v_o

v_dc

10

pwld

pwld

100e-6

40000

Figure 2.19: Circuit used in simulation of the buck converter. If the load is set at 100, the switching duty cycle to 0.5, and the switching frequency to 100kHz, then the plot of Figure 2.20 results. Note that this low value of load resistance ensures that the current is continuous in the inductor. The plots shows the initial startup transient (that was missing from the steady state analysis that we have carried out above). Once the transient has died away then the output voltage settles to the 5 Volt level that is predicted from the theory. The inductor current settles to the load current, which is Io = 5/100 = 0.05 Amp. Notice that the capacitor current is essentially zero. If one magnies the graph it can be seen that the capacitor is absorbing the ac currents resulting from the high frequency switching.

Remark 2.43 One can also simulate the performance of the buck converter if there is discontinuous current ow in the inductor. However, the simulation time required for the system to go into steady state is very long due to a problem with the initial transient. This phenomena can be seen in Figure 2.21 which shows the currents for a 50% duty cycle and a load resistance of 40k. Notice that we get an initial LC transient which leaves the capacitor with a charge of approximately 9 Volts (i.e. about twice the applied average voltage of 5 Volt). Once this voltage has appeared on the capacitor it can only dissipate via the load resistor. Therefore the time for the voltage to decay to the steady state value is of the order of 4 to 5 seconds. Remark 2.44 The slow transient that is evident in Figure 2.21 would not occur in a practical discontinuous mode buck converter. It occurs in the example case because the converter control is open loop. In a practical converter the duty cycle is varied depending on the error between the output voltage and the desired output voltage, so as to force the output voltage to the desired.

sw1_l4

2.4 Basic Analysis of Switch Mode Converters

2-27

(A) : t(s) 0.2 Capacitor cur

(A)

0.0

-0.2 0.4

(A) : t(s) Inductor cur

0.2

(A)
0.0 -0.2 10.0 8.0 6.0

(V) : t(s) v_o

(V)
4.0 2.0 0.0 0.0 0.025 0.05 0.075 0.1 t(s) 0.125 0.15 0.175 0.2 0.225

Figure 2.20: Waveforms for a buck converter with D = 0.5, RL = 100, and continuous inductor current.
(A) : t(s) 0.2 Capacitor cur

(A)

0.0 (0.11243, 167.57u)

-0.2 0.2

(A) : t(s) Inductor cur

(A)

0.0 (0.11243, 70.099u) -0.2 10.0 8.0 (0.11243, 8.8035)

(V) : t(s) v_o

(V)

6.0 4.0 2.0 0.0 0.0 0.025 0.05 0.075 0.1 t(s) 0.125 0.15 0.175 0.2 0.225

Figure 2.21: Initial startup waveforms for a buck converter with D = 0.5, RL = 40k, and discontinuous inductor current.

2-28

Fundamental Topologies

2.4.4

Simplied Analysis of the Boost Converter

In a manner similar to the analysis of the buck converter we shall also analyse the basic properties of the boost converter. The converter analyzed is that shown in Figure 2.3. As with the buck converter there are two cases to consider the continuous inductor current case, and the discontinuous inductor current case. 2.4.4.1 Continuous Conduction Mode

The following discussion is in relation to Figure 2.22. Using the same approach as with the buck converter, we can say that in steady state that the time integral of the voltage across the inductor over a complete switching period is zero. Therefore, by inspection of Figure 2.22 we can write: Vd ton + (Vd Vo )to = 0 boost converter voltage ratio Rearranging this gives the voltage ratio of the converter: Ts 1 Vo = = Vd to 1D Assuming a lossless circuit we can say that Pd = Po , and hence: Vd Id = Vo Io boost current ratio which can be rearranged to give the current ratio of the converter: Io = (1 D) Id (2.48) (2.47) (2.46) (2.45)

Remark 2.45 Equation (2.46) indicates that the voltage ratio goes to innity if D = 1. This arises from the fact that the steady state assumption means via (2.45) that the output voltage becomes increasingly large as D 1. Remark 2.46 Equation (2.46) indicates that the voltage ratio is not linear for a boost converter. A plot of the voltage ratio is shown in Figure 2.23. Note the very large increase in the voltage ratio as D 1. In reality this increase does not occur. The analysis that lead to (2.46) involved ideal components. However, if one includes resistance in the inductors and capacitors, and accounts for the very poor switch utilisation under large duty cycles, then as D 1, then Vo /Vd 0, and not .

2.4.4.2

Boundary between Continuous and Discontinuous Conduction

inductor current continuous current boundary

The following discussion is with reference to Figure 2.24. This gure shows the current waveform at the edge of continuous conduction. Following an analysis technique similar to that for the buck converter, we can write that the average value of the inductor current at this boundary is:

2.4 Basic Analysis of Switch Mode Converters

2-29

vL
Vd

A t B

Vd -Vo iL IL

Ts

0
t on
iL t off iL

io

io
Vd

Vd

L vL

Vo

L vL

Vo

Figure 2.22: Currents and circuit congurations for a boost converter.

100 90 80 70 60
Vo 50 Vd

40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

D (Duty Cycle)

Figure 2.23: Voltage ratio of a boost converter versus duty cycle.

2-30 1 iL 2 peak 1 Vd = ton 2 L Ts Vo D(1 D) = 2L

Fundamental Topologies

ILB =

(2.49) (2.50) (2.51)

output current continuous current boundary

Equation (2.51) can be further manipulated by realising that the inductor current and the input current in this converter are the same (i.e. id = iL ). Therefore using (2.48) we can say that Io = (1 D)IL , and hence: IoB = Ts Vo D(1 D)2 2L (2.52)

iL

peak

Current is zero here

v L = Vd iL I LB t

Vd -Vo

t on Ts

t off

Figure 2.24: Current waveform on the edge of continuous current. If we consider that the output voltage of the boost converter is kept constant, then one can dierentiate (2.51) and equate to zero to get the value of D = 0.5 for the maximum value of inductor current at the edge of continuous conduction. This value of current is: Ts Vo ILBmax = (2.53) 8L Similarly, one can dierentiate (2.52) and equate to zero to get the maximum value of IoB at D = 1/3. The value of IoB is: IoBmax = 2 Ts Vo Ts Vo = 0.074 27 L L (2.54)

maximum inductor continuous current boundary maximum output continuous current boundary

Both ILB and IoB can be expresses as follows in terms of their maximum values: ILB = 4D(1 D)ILBmax 27 IoB = D(1 D)2 IoBmax 4 (2.55) (2.56)

2.4 Basic Analysis of Switch Mode Converters If we normalise (2.51) and (2.52) using (2.53) we can get the plot shown in Figure 2.25.
I LB

2-31

1 0.9 0.8 0.7 0.6

I I LB
I oB
max

max

I LB

= 0.59I LB

max

0.5
max

0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3

1 3

I oB

0.4

0.5 D

0.6

0.7

0.8

0.9

Figure 2.25: Plot of the normalised continuous current boundary for the boost converter (Vo constant).

Remark 2.47 Figure 2.25 can be interpreted in the following way. If the current in the inductor is less than ILB then the converter will begin to operate with discontinuous inductor current. This translates to the output current being less than IoB , since the inductor current is not the output current for this type of converter. Notice that the largest value of the continuous output current boundary occurs at D = 0.33, which does not correspond to the point where the largest value of the continuous inductor current boundary occurs. This is due to the fact that the inductor current does not linearly relate to the output current. Remark 2.48 Figure indicates that for continuous current ow in the inductor, either keep the inductor current above ILB , or the output current above IoB . If the output is above IoB , then IL is above ILB , and vice-versa. 2.4.4.2.1 Discontinuous Current with Constant Vd . We shall assume that Vd and D remain constant as the output load varies. Under normal operating conditions there would be a controller that would vary D so as to maintain

2-32

Fundamental Topologies Vo constant despite load variations. However, the above assumptions allow an easier understanding of the discontinuous current condition. The following discussion is with reference to Figure 2.26 which shows the current under the discontinuous current condition.

iL
v L = Vd

peak

Current is zero here

iL

IL

Vd -Vo

DTs Ts
Figure 2.26: current.

D1Ts

D2Ts

Current waveforms for the boost converter with discontinuous

discontinuous voltage ratio

The integral of the voltage over one control interval must be equal to zero for the circuit to be in steady state. Therefore we can write the following equation: Vd DTs + (Vd Vo )1 Ts = 0 Vo 1 + D = Vd 1 (2.57) (2.58)

discontinuous current ratio

Again using the fact that the converter is assumed to be lossless, then we can say Pd = Po , and hence the current ratio under discontinuous operation is: 1 Io = Id 1 + D (2.59)

If we consider Figure 2.26, and using the fact that the current waveform can be broken down into a number of triangles, we can calculate the average input current. The peak current is: iLpeak = discontinuous average input current Vd DTs L (2.60)

and hence the average input current can be deduced to be: Id = Vd DTs (D + 1 ) 2L (2.61)

2.4 Basic Analysis of Switch Mode Converters discontinuous average output current Using (2.59) one can write the average output current expression as: Io = Ts Vd 2L D1 (2.62)

2-33

We can use (2.58), (2.62) and (2.54) to get an expression for the duty cycle in terms of the voltage ratio and the output current. From (2.54) we can write: 27 Ts = IoBmax L 2Vo and from (2.58) one can write: 1 =
Vo Vd

(2.63)

D 1

(2.64)

Substituting both of these into (2.62) and manipulating one can get the expression: 4 Vo Vo Io (2.65) D= 1 27 Vd Vd IoBmax Using (2.65) we can develop a plot of D versus Io /IoBmax for various Vo /Vd . The normal operating mode would be that Vo is constant, and Vd is varying. The development of this plot is slightly complicated due to the fact that the Io /IoBmax for discontinuous current is a function of the duty cycle. Using (2.56) and (2.65) it is possible to get the following expression for the limit on the duty cycle for discontinuous conduction, for a given value of Vd /Vo : 2 Dlim =
1
1 1 x (1 x )

discontinuous duty cycle

1
1 1 x (1 x )

4 (2.66)

where x = Vd . The negative of the two solutions gives a value of D in the valid Vo range of 0 1. This sets the limit on the D values, and therefore a limit on the Io /IoBmax range via (2.56). The characteristics of the boost converter with a constant Vo are shown in Figure 2.27. Remark 2.49 One can see from Figure 2.27 that the duty cycle has a highly non-linear relationship to the output current in the discontinuous region of operation. Once outside this region the duty cycle is constant for a particular voltage ratio output.

2.4.4.3

Simulation

To complete this section on the boost converter we shall construct a simulation of the circuit shown in Figure 2.28. The circuit simulated has the switch output switch closed, therefore the load resistance is approximately 100. The voltage output of the circuit, inductor current, load current, and energy stored in the output capacitor and with a 50% duty cycle is shown in Figure 2.29. Notice that the output voltage is 2Vd , as one would predict from (2.46). After the initial startup transient the energy in the capacitor settles

2-34

Fundamental Topologies

1 0.9 0.8 0.7 0.6 D 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 Io
I oB
max

Vd Vo Vd Vo

= 0.1

= 0.25

CONTINUOUS CURRENT REGION Vd

Vo = 0.5

DISCONTINUOUS CURRENT REGION

Vd Vo Vd Vo = 0.75

= 0.9

0.8

1.2

Figure 2.27: Duty cycle versus normalised output current for the boost converter with constant Vo .

2.4 Basic Analysis of Switch Mode Converters to a dc value, indicating that the circuit is now in steady state. The inductor current is essentially constant, which means that the current being pulled from the supply is very close to constant. The eect of applying several dierent duty cycles when there is continuous conduction is shown in Figure 2.30. Again the simulation output conforms almost exactly to the predicted values of the output using (2.46).
prbit_l4 BIT STREAM prbit_l4 BIT STREAM pwld v_o 100

2-35

sw 1_l4

v_dc

10

100e-6

40000

Figure 2.28: Boost converter simulated using Saber .

(J) : t(s) 0.04 Cap energy

(J)

0.02

0.0 0.4

(A) : t(s) I_o

(A )

0.2

0.0 0.8

(A) : t(s) Inductor cur

0.6

(A )

0.4 0.2 0.0 40.0 (V) : t(s) v_o

(V)

20.0

0.0 0.0 0.02 0.04 0.06 0.08 0.1 t(s) 0.12 0.14 0.16 0.18 0.2 0.22

Figure 2.29: Simulated waveforms for a boost converter with D = 0.5 and continuous current.

sw 1_l4

50e-3

2-36

Fundamental Topologies

(V) : t(s) 60.0 v_o;D=0.5

v_o;D=0.8 50.0 v_o;D=0.2

40.0

(V)

30.0

20.0

10.0

0.0 0.0 0.025 0.05 0.075 0.1 t(s) 0.125 0.15 0.175 0.2 0.225

Figure 2.30: Output of a boost converter in continuous current mode with several dierent duty cycles.

2.4.5

A Brief Look at the Buck-Boost Converter

buck-boost ratio

voltage

We shall not carry out a complete analysis of the buck-boost converter. We can consider the buck-boost converter can be considered to be a cascade of a buck converter and a boost converter. Therefore, assuming that both converters are operated with the same duty cycle, that the current conduction is continuous, then the output voltage ratio is simply the cascade of the two expressions already derived for the buck and boost converters: Vo D = Vd 1D (2.67)

buck-boost current ratio

As with the previous converters, if we use the lossless converter assumption we can get the current ratio for the buck-boost converter as: Io 1D = ID D (2.68)

Equation (2.67) can easily be shown to hold for the single switch version of the converter as in Figure 2.5. The situation with discontinuous current is more complex, and cannot be considered to be a cascade of the individual converters under this condition.

2.4.6

A Brief Analysis of the Ck Converter

The following analysis is with reference to Figures 2.6, 2.31, 2.7 and 2.8. It is assumed in the following analysis that the voltage on the capacitor VC1 is constant. This implies that the capacitor is fairly large.

2.4 Basic Analysis of Switch Mode Converters

2-37

vL

Vd

0 OFF
Vd -VC = - o V
1

ON t

vL

VC -Vo
1

0 OFF
- o V

ON

iL

IL

0
iL

t
2

IL

0
(1 - D ) s T (= t on )

t
DTs (= t off )

Figure 2.31: Steady state currents and voltages in a Ck converter.

2-38

Fundamental Topologies

Under the constant VC1 and steady state operation assumptions, the integral of the voltages across the inductors must be zero. Therefore we can write: Vd DTs + (Vd VC1 )(1 D)Ts = 0 VC1 and (VC1 Vo )DTs + (Vo )(1 D)Ts = 0 1 VC1 = Vo (for L2 ) D Ck voltage ratio Using (2.70) and (2.72) we can write: Vo D = Vd 1D Ck current ratio (2.73) (2.71) (2.72) 1 = Vd (for L1 ) 1D (2.69) (2.70)

As with the previous converter analysis, if we assume that the converter is lossless, then we can develop the current ratio: Io 1D = Id D (2.74)

Remark 2.50 Equations (2.73) and (2.74) are the same as those for the buckboost converter. One can calculate the current and voltage ratios using an alternate technique based on the charge transferred by the capacitor. This technique is illuminating in that it emphasises the fact that it is the capacitor that is storing the energy that is being transferred from the source to the load. It shall be assumed that the inductors, L1 and L2 , are large enough that the ripple in the currents can be ignored i.e. iL1 = IL1 and iL2 IL2 . If the circuit is in steady state then the total charge delivered to the capacitor over a complete control interval is zero. This can be expressed mathematically as follows: IL1 (1 D)Ts IL2 DTs = 0 IL Io 1D 2 = = IL1 Id D Using the lossless argument once again (Po = Pd ), then one gets: Vo D = Vd 1D (2.77) (2.75) (2.76)

2.4.7

Full Bridge dc-dc Converter

We shall now consider the calculation of the output voltage ratio and currents for the full bridge dc-dc converter. As was previously noted, this converter is capable of producing both ac and dc outputs, but in this analysis we shall only consider dc output. The following discussion is with respect to Figure 2.9.

2.4 Basic Analysis of Switch Mode Converters Assuming that the switches are switched in such a way that the current is continuous in the load, then the output voltage is only a function of the switch states. Let us consider Leg A in Figure 2.9. If switch SWA+ is closed and if io is positive then the current will ow through SWA+ . If io is negative then the current will ow through DA+ . In either case, the Leg A load connection is connected to the positive rail of the dc supply. Therefore: vAN = Vd (for SWA+ on and SWA o) (2.78)

2-39

Remark 2.51 The assumption stated above essentially means that one of the switches in a leg is switched on at a particular instant of time. As we shall see later, if both switches are open in a leg, then the output voltage is no longer a function of the switch states, but depends on the direction of the load current from the leg. The alternative switching position for Leg A is SWA+ o and SWA on. In this case a positive current ows through DA and a negative current through SWA . Hence in both cases the Leg A load connection is connected to the negative of the supply, which is also the reference point for the voltage measurements. Therefore: vAN = 0 (for SWA on and SWA+ o) (2.79) Remark 2.52 Expressions (2.78) and (2.79) indicate that the output voltage is dependent only on the status of the switches, and not on the direction of the current. Given Remark 2.52 then the output voltage of Leg A averaged over a complete switching cycle Ts , depends only on the input voltage Vd and the duty ratio of SWA+ . Therefore the average Leg A voltage is: VAN = Vd ton + 0 to = Vd duty cycle of SWA+ Ts (2.80)

Similar arguments apply to Leg B. Therefore VBN is: VBN = Vd duty cycle of SWB+ (2.81)

independent of io . Given VAN and VBN , then we can calculate the output voltage for the converter as follows: Vo = VAN VBN (2.82) Equation (2.82) is a general expression for the output voltage. It was mentioned in Section 2.3.5 that there are two main strategies for arranging the switching in full bridge converters. We shall now investigate these strategies in detail. 2.4.7.1 Bipolar Switching

This is a switching strategy where the top switch in one leg is closed and the bottom switch in the other leg is closed. Therefore the switches are grouped as diagonal pairs in Figure 2.9.

2-40

Fundamental Topologies In a manner similar to that shown in Section 2.4.2, the PWM for bipolar switching is implemented conceptually by comparing a reference voltage with a triangular waveform. We can work out the output voltage of the converter with this type of switching with the aid of Figure 2.32. In the bipolar converter the basic algorithm is that when the control voltage is greater than vtri then SWA+ and SWB are turned on. If the control voltage is less than vtri then SWA and SWB+ are turned on. The logic behind this switching algorithm, is that the triangular switching waveform can be considered to be a scaled version of the integral of the leg waveform with respect to the voltage reference point. Therefore, for a particular leg voltage one has to simply nd the scaling factor for the control voltage or the triangular wave. From Figure 2.32A we can see that: vtri = Vtri 1
Ts 4

(2.83)

At the switching time t1 one can see that vtri = vcontrol . Substituting this into the above expression we can write: t1 = vcontrol Ts Vtri 4 (2.84)

Leg A duty cycle

Again referring to Figure 2.32A we can see that the total on time for Leg A of the inverter is: 1 (2.85) ton = 2t1 + Ts 2 We can now use (2.2) to give the duty cycle for the SWA+ and SWB switch pair: ton 1 vcontrol D1 = = 1+ (2.86) Ts 2 Vtri The duty cycle for the SWB+ SWA leg (i.e. leg B) is therefore: D2 = (1 D1 ) Using (2.82) we can write: Vo = D1 Vd D2 Vd = (2D1 1)Vd (2.88) (2.87)

Leg B duty cycle

full bridge bipolar output voltage

which becomes, substituting (2.86) : Vo = Vd v = kvcontrol tri control V (2.89)

Remark 2.53 Equation 2.89 indicates that the output voltage is linear with respect to the control voltage. This makes the control of the converter fairly simple. Remark 2.54 From Figure 2.32 it can be seen that the voltage across the load is bipolar in nature, hence the name of this switching strategy. It should also be noted that the fact that the voltage is going from positive to negative will result in higher ripple in the output current, as compared to any strategy that keeps the voltage unipolar.

2.4 Basic Analysis of Switch Mode Converters

2-41

v tri

$ Vtri

v control

A
t1 t1 Ts / 2

Ts

v AN
Vd

10 B

01

10

01

10 t

v BN
Vd

10 C

01

10

01

10 t

vo = v AN - v BN
Vd Vo

D
- d V

10

01

10

01

10

I o + ve io

Io
SWA + D ASWB - D DA + DB SWA-

SWA + SWB -

B+

I o - ve

SWB +

io

-I o
SWA + SWASWB - SWB +
DADB +

t
DA + DB SWA + SWB -

Figure 2.32: strategy.

Waveforms for a full bridge converter with a bipolar switching

2-42

Fundamental Topologies Remark 2.55 From (2.88) it can be seen that as the duty cycle D1 is varied from 0 to 1 the output voltage varies from Vd to Vd . This variation is independent of the direction of the current, although dierent switching components are responsible for the conduction of the current depending on the current direction. This can be seen from Figure 2.32E and F, where the various conduction devices are shown. 2.4.7.2 Unipolar Switching

An alternative switching strategy to the bipolar strategy is the unipolar strategy. This switching strategy takes into account another degree of freedom as compared to the bipolar strategy. The basic idea of this switching strategy is to keep the voltage across the load unipolar if the desired voltage is unipolar. This is achieved by the voltage switching from Vd to 0. Examination of Figure 2.9 indicates that there are two basic strategies for obtaining unipolar operation. For example, assuming that the current direction is positive, then one can have switch SWB switched on, and then open and close SWA+ depending on the average voltage that one desires. This would result in the voltage across the load going from Vd with SWA+ closed, and 0 with SWA+ open (and hence SWA closed). The other strategy is to switch leg B. For example, assuming the same current direction, one could open SWB (and hence close SWB+ ), the current then circulating through via SWA+ and DB+ . Both of the above switching strategies are employed in the switching algorithm drawn in Figure 2.33. One could use a switching scheme similar to that of the bipolar case, where one has a unipolar control voltage. In this case only one of the two switching patterns could be easily incorporated. This would result in a larger output voltage for unipolar switching as compared to bipolar switching. Both of the switching strategies could be used however, if one has the bipolar control voltage shown in Figure 2.33. The switching times are determined as follows: SWA+ closed if: vcontrol > vtri (2.90) and SWB+ closed if: vcontrol > vtri i.e. vtri < vcontrol (2.91) (2.92)

This switching strategy allows both the positive and negative parts of the triangular waveform to be utilised. The net result of switching using this strategy is shown in Figure 2.33C. As compared to the bipolar strategy, or a unipolar strategy where only one of the switching options are used, the switching frequency has eectively been doubled without actually changing the switching frequency of the switches themselves. Remark 2.56 The eective doubling of the switching frequency means that the ripple in the current using the unipolar strategy is less than the ripple using the bipolar strategy. Examination of the waveforms in Figure 2.32B and C and Figure 2.33B and C indicate that the duty cycles are the same for the unipolar case and the bipolar

2.4 Basic Analysis of Switch Mode Converters

2-43

v tri
$ Vtri

v control

A
-v control v AN
Vd t1 t1 t1 t1 t1

Ts

10 B

00

10

11

10

00

10

11 t

v BN
Vd

10 C

00

10

11

10

00

10

11 t

vo = v AN - v BN
Vd Vo

2t 1

2t 1

10

00

10

11

10

00

10

11 t

D
- d V

I o + ve
DA + SWA + SWB D
B-

io

Io
SWA + SWB DASWADB -

I o - ve

SWB SWADB -

io

-I o

t
SWA + SWB DA + DB DA-

DA + DB -

SWB -

Figure 2.33: strategy.

Waveforms for a full bridge converter with a unipolar switching

2-44

Fundamental Topologies case (the VAN and VBN waveforms are the same in both cases). Rewriting these for convenience: 1 vcontrol +1 (2.93) D1 = 2 Vtri and D2 = 1 D1 (2.94)

full bridge duty cycle

full bridge unipolar output voltage

Clearly then in this case the output voltage is exactly the same as that of the bipolar case i.e.: Vd Vo = (2D1 1)Vd = v (2.95) control Vtri Remark 2.57 Because of the eectively higher switching frequency of the unipolar strategy, it is the preferred method of switching for these types of converters.

2.4.8

Comparison of Basic Converter Topologies

In this section we shall attempt to compare the basic converter topologies introduced in this chapter. This comparison is somewhat limited, as there are a great many topologies that fall into these general categories of those introduced, that in particular applications have advantages over others. Nevertheless this somewhat theoretical comparison is benecial in that it highlights some of the fundamental structural dierences between the converters, and in addition introduces some of the metrics used for carrying out comparisons. One of the rst points to notice about most of the converter structures that we have looked at is that they produce unipolar output voltages. There is one exception to this the full bridge converter. In addition to the unipolar operation, all except the full bridge converter can only handle current in one direction; into the load. Therefore the buck, boost, buck-boost and Ck converters are said to operate in one quadrant of the io vo operation plane. The full bridge converter on the other hand can operate on all four quadrants of the io vo plane. 2.4.8.1 Switch Utilisation

One of the important metrics of power electronic devices is the switch utilisation. This refers to how well a particular converter topology uses the voltage and current ratings of the semiconductor switches used. If a switch is poorly utilised then a larger semiconductor switch must be used for a given power output for the converter. This corresponds to more expensive switches. In order to calculate the switch utilisation for the previous converters we rstly need a few assumptions: 1. The average current is at its rated value of Io . The ripple in the current can be ignored. 2. The output voltage is ripple free and is at a constant rated value of Vo . 3. The input voltage is allowed to vary and the duty cycle is varied by a control algorithm to keep the output voltage at its xed rated value.

2.4 Basic Analysis of Switch Mode Converters Given these assumptions the peak switch voltage VT and current IT are calculated. The switch peak power rating is then calculated as PT = VT IT . The switch utilisation is then calculated as: Us = where Po = Vo Io . Remark 2.58 The low ripple assumption used in the following analysis implicitly allows one to remove the particular value of inductance used in the circuit from the switch utilisation expressions i.e. the expressions are circuit value independent. It also serves to simplify the analysis whilst still capturing the essential character of the expressions. Let us now consider the switch utilisation of the generic converter types that we have considered in this chapter. 2.4.8.1.1 Buck Converter The peak voltage across the switch is: VT = Vd (2.97) Po PT (2.96)

2-45

switch utilisation denition

This can be written in terms of the output voltage using (2.9) allowing the peak switch voltage to be written as: VT = Vo D (2.98)

Examination of Figure 2.2 reveals that the peak current through the switch must be the same as the average load current, since when the switch is closed the two currents have to be the same (via the no inductor current ripple assumption). Therefore: IT = Io (2.99) Using these two expressions for VT and IT we can write the expression for the switch rating power: V o Io PT = VT IT = (2.100) D Therefore: Po V o Io Us = (2.101) = Vo Io = D PT D 2.4.8.1.2 Boost Converter A similar analysis for the boost converter can also be carried out. Again the basic equations for the voltage ratio, (2.46), and the current ratio, (2.48) can be used. The key to getting the switch utilisation in this case is to realise that the average input current id and the inductor current iL are the same. Since we are assuming that the inductor is large enough that there can be little ripple in the inductor current, then the switch current must also equal the inductor current. The same assumption also means that we can replace the instantaneous currents with their average values (since they will be the same). Therefore id = Id and iL = IL . We can therefore write: IT = Id (2.102)

buck converter switch utilisation

2-46

Fundamental Topologies Using (2.48) we can relate the Id and Io , therefore we have: Io (2.103) 1D From Figure 2.3 one can see that the peak voltage across the transistor is the output voltage i.e.: VT = Vo (2.104) IT = Id = allowing the switch peak power to be written as: PT = VT IT = Vo Io 1D =1D (2.105)

boost converter switch utilisation

and the switch utilisation as: Us = Po = PT Vo Io

Vo Io 1D

(2.106)

2.4.8.1.3 Buck-Boost Converter The determination of the switch utilisation for the buck-boost converter is a little more complicated than the previous cases. This complication occurs due to the fact that the average current ID is not the peak current value owing through the switch device (as was the case in most of the above). This occurs due to the fact that the switch disconnects the input from the output. The waveform for the input current (which is also the switch current in this case) is shown in Figure 2.34. Note that the constant value of the current from 0 to DTs is due to the large inductance assumption. It can be seen that that average input current is: iD DTs ID = = iD D (2.107) Ts and therefore the peak current through the switch is: ID D Using (2.68) and (2.108) we can write: iD = IT = iD = 1 1D Io (2.108)

(2.109)

The maximum voltage across the switch (from Figure 2.5) can be seen to be: VT = Vd + Vo and using (2.67) we can write: 1D Vo Vo + Vo = D D Using (2.109) and (2.111) we can now write the peak switch power: VT = PT = VT IT = buck-boost utilisation switch 1 V o Io D(1 D) (2.111) (2.110)

(2.112)

and hence the switch utilisation factor is: Po Us = = D(1 D) = D D2 PT

(2.113)

The Ck converter has the same switch utilisation as the buck-boost converter.

2.4 Basic Analysis of Switch Mode Converters

2-47

Input current

iD ID

t
DTs
(1 - D ) s T

Figure 2.34: The input current into a buck-boost converter with a large input inductance. 2.4.8.1.4 Full Bridge Converter When we consider the switch utilisation for the full bridge converter we shall look at SWA+ and then divide the result by four, because there are four switches in this converter. In other words we require fours times the amount of semiconductor material in this converter, and hence we consider then the peak power is divide across these four devices. Remark 2.59 The division of the single switch utilisation is a technique for saying that the converter is using more silicon than other converters. However, it should be noted that each individual switch has to satisfy the peak power prior to being divided by four. From Figure 2.9 it is obvious that the peak voltage across a switch is: VT = Vd Similarly it is clear that the peak current is the load current: IT = Io Therefore the peak switch power is: PT = VT IT = Vd Io (2.116) (2.115) (2.114)

We need to get the output power. Since we have expressed the peak switch power in terms of Vd we need to get the output power in terms of this as well. This can be achieved by using (2.89) in conjunction with (2.86) which allows us to write: vcontrol = Vtri (2D1 1) (2.117)

2-48 and hence: Vo = Vd (2D1 1) and therefore the output power is:

Fundamental Topologies

(2.118)

Po = Vo Io = Vd (2D1 1)Io Therefore the switch utilisation for SWA+ is: USWA+ = full bridge switch utilisation Po = (2D1 1) PT

(2.119)

(2.120)

In order to get the nal value we divide then single switch value by four: Us = 0.5D1 0.25 (2.121)

The best way to get an overall comparison of the switch utilisation for the various converters is to plot the switch utilisation versus duty cycle for them. This plot is shown in Figure 2.35. Remark 2.60 One can see from Figure 2.35 that the buck-boost converter, the Ck and the full bridge converter do not have good switch utilisation as compared to the buck or the boost converter. Therefore, where possible it is better to use these converters, since a lower cost switch can be used for a given application.

1 0.9 Boost 0.8 0.7 0.6

Po PT 0.5

Buck

Buck-boost and Cuk Full bridge

0.4 0.3 0.2 0.1 0 0

0.1

0.2

0.3

0.4

0.5 D

0.6

0.7

0.8

0.9

Figure 2.35: Plot of switch utilisation for the common converter types.

2.4 Basic Analysis of Switch Mode Converters Remark 2.61 If both higher and lower voltages than the supply are required then one has to use either the buck-boost or the Ck converters. A signicant advantage of the Ck converter is that the front end of the converter looks like that of the conventional boost converter. Therefore it shares the property of this inverter that the input current is reasonable constant, and hence the ltering of the input is signicantly simplied as compared to the buck-boost converter where the input (and output) currents are highly discontinuous. Similarly the output current of this converter can also be kept almost constant. A disadvantage of the Ck converter is that the capacitor has to have a high ripple current capacity. Remark 2.62 The full bridge converter should only be used if four quadrant operation is required.

2-49

2.4.9

Synchronous Rectiers

In a switching power supply is being used in very low voltage applications the drop of voltage across the rectier diodes can be signicant. This voltage drop obviously results in less eciency from the converter. In some of the more demanding applications eciency takes precedence over other considerations. One halfway solution to the eciency problem is to use of Schottky diodes for the rectier. These devices have an on voltage of approximately 0.2 volt, as compared to the 0.60.7 volt of the conventional diode. However, in the very demanding applications this drop is still too much. The solution employed is the use of the so-called synchronous rectier. This uses a MOSFET instead of the diode. The reader should be aware that a MOSFET has a conventional diode intrinsically built into its structure. This is not the diode that is being used in the synchronous rectier. The synchronous rectier uses the fact that a MOSFET is a symmetric structure, and consequently conducts current from the Drain to the Source and vice-versa. This means that when the internal diode is reverse biased the MOSFET is not turned on (thereby operating as a reverse biased diode). But when the diode is forward biased the MOSFET is turned on. This eectively shorts out the internal diode since the on voltage of a MOSFET is signicantly lower than the on voltage of the internal diode. This is due to the fact that the MOSFET essentially functions as a resistance when turned on hard, and the on state resistance of many modern MOSFETs is very very low of the order of 103 m. This principle is shown in Figure 2.36 which shows a conventional boost converter circuit with and without a diode rectier. One feature in Figure 2.36 is the parallel Schottky diode with the MOSFET. This diode is required to carry the current when the bottom MOSFET turns o, and the rectier MOSFET is o. This gap is required so that shoot through from the load cannot occur (and from the supply for the buck converter). The body diode of the MOSFET should not be allowed to carry this current because of the very high reverse recovery time.

Remark 2.63 One other advantage of using synchronous rectiers is that one can make sure that there is continuous conduction under all load conditions. This occurs because the current can ow in either direction through the inductor with a series MOSFET as opposed to a diode.

2-50

Fundamental Topologies

+V

+V

Synchronous rectifier

(a)

(b)

Figure 2.36: (a) Conventional non-synchronous rectier based boost converter. (b) Synchronous rectier based boost converter.

2.4.10

Switching Losses and Snubber Circuits

It has been shown that the losses in power electronic switches due to the switching process itself and be between two and four times the static losses when the switch is conducting [4] depending on the switching frequency. Clearly these losses will increase in proportion to frequency. The switching losses are switching device and topology dependent. Switching losses occur primarily because as a device switches on or o there may be both substantial voltage and current across the device. Consequently there is a spike of power dissipation during this interval. Specically the purpose of snubber circuits are [2]: 1. Limit voltages applied across semiconductor devices during turn-o and/or turn-on transients. 2. Limit the rate of rise of current through devices (di/dt) during turn-on. 3. Limit the rate of rise of voltage across devices during turn-o or re-applied forward blocking voltages. 4. Shape the switching trajectory so that the device remains in the safe operating area (SOA)4 under all switching circumstances. transistor switches Topologies, which use transistor switching devices, and have a transformer pri4 The SOA is the area in the VI plane for devices operation where the manufacturer will guarantee that the device will not be damaged. The device must remain within this area under static and dynamic conditions.

2.4 Basic Analysis of Switch Mode Converters mary in series with the switching device tend to have their switching losses concentrated in the turn-o switching cycle (as compared to the turn-on switching cycle). This is because the leakage inductance of the transformer limits the rate of rise of current upon switching device turn-on, and therefore there is little current owing the device whilst the voltage is at a substantial level across the device. Remark 2.64 Any topology where there is an inductor in series with the power device will have a lower turn-on loss because of the slow rise of current at turnon. Remark 2.65 The non-isolated buck converter, at rst sight, would appear to fall into the low turn-on loss category of converters. However, in the case of this converter there is a free wheeling diode at the junction point of the inductor and the switching device which completely changes the situation. In fact the stored charge in the free wheeling diode exacerbates the situation by providing a short circuit to ground upon switching device turn-on. This results in a very high current spike with a very rapid rise time. Therefore in this case there are signicant turn-on losses. During turn-o the transistor is protected by the same types of snubber circuits as other topologies. If the switching device is a MOSFET the switching losses tend to be concentrated at turn-on. This is due to the devices own self capacitance Co , which is in parallel with the device. At turn-on one gets a large spike of current due to this capacitance being charged, often to the level of twice the supply voltage. The turn-o losses of the MOSFET tend not be be very high because of the very rapid turn-o of this type of device. Remark 2.66 Snubbers are often required with MOSFETs, not because of the turn-o losses as with transistors, but because of inductive spikes across the drain-source due to parasitic inductance. The fact that MOSFETs can turn-o very quickly exacerbates this inductive spike issue. Not only do active switching elements need snubbers, but so do naturally commutated elements such as diodes and thyristors. As a starting point to this analysis we shall consider diode snubbing. 2.4.10.1 Diode Snubbers

2-51

MOSFET switches

This section is still in development and is far from complete at the moment. Currently it only introduces the various applications of snubbers but does not include comprehensive analysis. The simplest situation to analyse is the diode in a buck converter situation [2]. Consider the diagram in Figure 2.37. A snubber circuit is required across the diode because of the large voltage that can occur across it as a result of the reverse recovery current and the parasitic inductance. In Figure 2.37 the L is the leakage inductance in the diode recovery path. The highly inductive load is being modeled as an ideal current source, Io . When the switch T is opened the current owing in the load is allowed to ow up

2-52

Fundamental Topologies

Ls

iLs
Rs

Io

Vd

iDf

Df

vD +

Cs

(a)
diDf V =- d dt Ls iDf
Io t0

tSW

t
I rr ts

(b)

Figure 2.37: (a) Step-down converter circuit with a RC snubber; (b) The diode reverse recovery current [2].

2.4 Basic Analysis of Switch Mode Converters through the diode Df , therefore preventing the large voltage spike that would otherwise result from the highly inductive load. This is shown in Figure 2.37(a), where IDf = Io . When the switch T is closed again at time tSW then the current iDf remains initially at Io and starts to decrease. It remains at this level because of the inevitable parasitic inductance of the circuit associated with the diode. The voltage Vd is applied across the leakage inductance, hence the linear decrease of the current. At time t0 the current through the diode (and the L inductor) becomes zero. After this time the current owing through the diode begins to ow in the reverse direction of normal forward bias current ow. This will continue until the stored charge in the diode is exhausted, and at time ts the diode snaps o. At ts the current through L is Irr and if nothing is done, the voltage produced by di/dt through L in order to keep Irr owing would be enormous. Hence the requirement of a snubber circuit Rs Cs . In order to analyse the snubber circuit consider the equivalent circuit of Figure 2.38. This shows the full equivalent circuit for the snubber section of the circuit, as well as a simplied circuit when the resistor is zero. We shall use the later initially to carry out the analysis, even though this circuit is not used in practice. Nevertheless the basic principles of operation are shown by using this circuit. Not that the following analysis is based on this presented in [2]. The circuit in Figure 2.38(b) is a simple LC circuit, and therefore can be solved using the standard dierential equation. It can be shown that the solution to this circuit is: Vd VCs 0 sin 0 (t t0 ) (2.122) iL (t) = IL0 cos 0 (t t0 ) + Z0 vCs (t) = Vd (Vd VCs 0 ) cos 0 (t t0 ) + Z0 IL0 sin 0 (t t0 )(2.123) where: 0 Z0 = = 2f0 = L Cs 1 L CS

2-53

In this particular case, we shall assume that the t = 0 time is at the point where the diode snaps o. Therefore the initial conditions for the inductor current and the capacitor voltage are iL0 = Irr and vCs = 0. Figure 2.39 shows the waveforms that are generated for the simplied circuit of Figure 2.38(b). Note that the capacitor voltage is the negative of the diode voltage. Let us dene a base capacitance value: Cbase = L Irr Vd
2

(2.124)
1 2 2 C s vC s ,

2 (this is derived from the expression 1 L Irr = 2 capacitor voltage is the input voltage).

and saying that the

Substituting L = Cbase

Vd Irr

into (2.123) and manipulating we can write: Cbase sin 0 t Cs (2.125)

vCs = Vd 1 cos 0 t +

2-54

Fundamental Topologies

Ls I rr

iC

(a) Vd

Diode Snap-off

K A

Rs

Cs

vCs

Rs = 0

Ls
iLs

(b) Vd

Cs

vCs

Figure 2.38: Equivalent circuit of the snubber used to protect diodes. (a) Full equivalent circuit; (b) simplied circuit with Rs = 0.

2.4 Basic Analysis of Switch Mode Converters

2-55

vCsmax

vCs

Irr

L diL = Vd dt

Vd

Figure 2.39: Waveforms for the simplied (Rs = 0) snubber circuit.

Taking the derivative of this expression we and equating the result to zero (the nd the extremum) we can write: Cbase cos 0 t Cs

sin 0 t = or

(2.126)

tan 0 t =

Cbase Cs

(2.127)

where 0 t is the optimal value for . Note that due to the properties of the tan function, we can also write: tan(0 t ) = Cbase Cs

(2.128)

We shall make us of the following trigonometric identities: sin x cos x = = tan x 1 + tan2 x 1 1 + tan2 x (2.129) (2.130)

where x denotes the optimal value for the phase in the expressions (note that x can equal 0 t or 0 t ). Due to the ambiguity of the x value, then the above two expressions can be positive or negative depending on whether x = 0 t or

2-56

Fundamental Topologies

3.0 2.8 Normalised v_Cs 2.6 2.4 2.2 2.0 0.0

0.5

1.0

1.5 C_base/C_s

2.0

2.5

3.0

Figure 2.40: Plot of the normalised capacitor voltage versus Cbase /Cs . x = 0 t . Using these expressions we can write from(2.125): vCsmax = Vd 1 = Vd 1 = Vd 1 1 1 + tan x 1 1+ 1+
Cbase Cs 2

Cbase tan x Cs 1 + tan2 x base CCs Cbase Cs 1 + Cbase

Cs

(2.131)

(2.132)

Cbase Cs Cbase Cs

(2.133)

1+ 1+

Vd 1

Cbase Cs

(2.134)

The negative solution does not make sense the maximum voltage would be less than the input voltage. Therefore chose the positive solution, which gives: vCsmax = Vd 1 + 1+ Cbase Cs (2.135)

Remark 2.67 One can see from (2.135) that if Cs < Cbase that vCsmax increases, and for small values very large values of voltage would occur. The maximum capacitor voltage is impressed across the diode, and therefore has to be kept under control. Figure 2.40 shows a plot of this normalised capacitor voltage versus the Cbase /Cs value. As can be seen, if Cbase /Cs > 1 then the capacitor voltages

2.4 Basic Analysis of Switch Mode Converters become quite large. However, one can also see that the Cs has to be fairly large to reduce the voltage to any signicant margin. The above analysis was only approximate in that we neglected the Rs resistance in the circuit to get an approximate feel for the eect of the capacitance. However, in reality there is a resistor there, and it is required in order to prevent large currents from owing into the switching transistor when the switch is turned back on. The dierential equation for the circuit under this condition is: dvCf d2 vDf + Rs C s + vDf = Vd (2.136) L Cs dt2 dt where vDf is the diode voltage after t = 0 which is the instant that the diode snaps o. The initial conditions at this point are the initial inductor current of Irr and the initial capacitor voltage is zero (as was the case for the previous analysis). These conditions then lead to the boundary condition for the dierential equation of vDf (0+) = Irr Rs and:
2 Irr Rs Vd Irr R2 dvDf (0+) = dt Cs L L

2-57

(2.137)

Using standard solution techniques one can show that the solution is: vDf (t) = Vd where: = = = = 1 Rs 2 tan1 tan1 Vd Irr2Rs L Irr 2 2 0 L Irr t e cos( t ) Cs cos (2.138)

As in the previous case the maximum value can be found by taking the derivative, and then setting to zero and solving for the time. If this is done then the time at which the maximum voltage occurs can be found to be: tm = +
2

(2.139)

If this is substituted into (2.138) then the normalised maximum reverse voltage across the diode is: 2 Vmax Cbase Rs Rs =1+ 1+ + 0.75 etm (2.140) Vd Cs Rbase Rbase where Rbase =
Vd Irr

and Cbase is as dened previously.

2-58 2.4.10.2 Snubbers for Thyristors

Fundamental Topologies

RC snubbers, similar to those used for diodes, are also required for thyristor circuits. For example, when thyristors are being used in the controlled rectier applications, when only thyristor is turned o by another being turned on, then there is a reverse recovery current that ows through the thyristor that is being turned o. This current will snap-o very rapidly when the reverse recovery is complete. The inductance of the circuit that this reverse recovery current is owing through will result in a large voltage occurring across that device that is commutating o (i.e. undergoing the reverse recovery). If nothing is done about this the device may suer failure due to over-voltage. Details of design to be presented later. In the meantime information can be found in [2].

2.4.10.3

Snubbers and Transistors

This section is incomplete the analysis has not been completed. Refer to [2] for more details. Snubbers are required for transistor switches in order to improve their switching trajectory. Transistors (regardless of whether they are BJTs, MOSFETs etc) experience stresses during turn-on and turn-o. These stresses are due to either higher than normal current through the device while there is substantial current across of the device (this usually occurs at turn-on due to diode reverse recovery), or higher than normal voltage across the device while there is substantial current owing in the device (this usually occurs are turn-o due to stray inductances). Both of these situations can be managed by judicious use of snubber. A typical turn-o snubber circuit for a transistor switch in a step-down converter is shown in Figure 2.41. It is fairly obvious how this circuit works when the transistor turns o the voltage across the capacitor cannot change instantly. Therefore as the current through the transistor falls it is transferred to the capacitor via the snubber diode. Whilst the voltage across the capacitor is less than the supply voltage the freewheeling diode around the current source remains o. Therefore this circuit keeps the voltage across the transistor near zero as the current through the device falls. Therefore the power dissipation in the transistor during the switching transient is low. Note 2.2 Note that most snubbers are essentially transferring energy from the silicon switching device to a passive component (e.g. a resistor). Therefore they may not improve the eciency of a circuit, but the power dissipation may be easier to handle in a passive device as opposed to a transistor where critical function temperatures are of vital importance with respect to lifetime. Remark 2.68 Note that the turn-o snubber also helps prevent over-voltages on the transistor due to stray inductances. When diode Df turns on an equivalent LC circuit is formed with the leakage inductances in the circuit and the snubber capacitor. Normally a high voltage could be induced in the leakage inductance as the current changes when the freewheeling diode turns on, but with

turn-o snubber

2.4 Basic Analysis of Switch Mode Converters the snubber capacitor there an LC circuit is formed that limits the voltage rise across the device.

2-59

I Df

I0

Vd

DS

RS

iC S

Figure 2.41: Turn-o snubber circuit for a transistor step-down converter. When the transistor switches back on, the diode DS in Figure 2.41 will be reverse bias. Hence the capacitor CS will discharge through the resistor RS . Providing the capacitor is largely discharged before the transistor is next turned o the circuit will function as described above. Remark 2.69 The discharge current through Rs resistor is added to the turnon current through the transistor. The turn-on current through the transistor can be quite large under some circumstances due to the stored charge in the freewheeling diode. This is the main reason for a turn-on snubber discussed later. Let us look in more detail at the reasons for the turn-on and turn-o snubbers. Figure 2.42 shows the various stray inductances in a transistor circuit that can inuence the switching of the circuit. The L1 to L5 inductors are eectively in the switching path during turn-on and turn-o, and the aect the switching trajectories of the device (i.e. the v versus i relationship during the switching of the transistor).

Figure 2.43 shows a conceptual diagram of the turn-on and turn-o switching trajectories under the inuence of the stray inductances. At t0 the transistor is on, and at t+ the turn-o of the device begins. As the process proceeds the 0 current through the device begins to fall and the voltage across the device begins to rise. The trajectory moves towards the point on the graph that is denoted

2-60
L1

Fundamental Topologies

L2 L5 Io

Vd

L3

L4

Figure 2.42: Stray inductances that are important in a transistor switching circuit during turn-on [2]. with t1 . As the switching trajectory moves towards this point there is clearly power being dissipated in the device as there is simultaneously substantial current and voltage through and across the device. The over-voltage at t1 is due to the inductances in the circuit i.e. L = L1 + L2 + + L5 and the diC of dt the switch current as the device turns o. Note 2.3 The over-voltage at t1 would result in considerable extra power dissipation in the switching device, since there can often still be considerable current owing in the device at the time of this over-voltage.

The device nally turns o at point t3 when it supports the full supply voltage and has zero current owing through it. When the device turns back on, it follows the trajectory from t3 to t4 and up to t5 and nally t6. . The bump above the rated current at t5 is due to the reverse recovery of the freewheeling diode that has been taking the load current whilst the transistor has been turned o. As with the turn-o situation clearly one has considerable voltage across the device simultaneously with a more than rated current through the device at this point, which indicates that there will be considerable power dissipation due to this. In addition to this, the reverse recovery current could, in some cases, cause damage to the device over time. This is especially true if the switching device is a minority carrier based switch such as a bipolar junction transistor (BJT). These devices suer from secondary break down due to a negative temperature coecient resulting in hot spots in the device under circumstances similar to those just describe. Remark 2.70 During the turn-on phase the current being handled by the transistor is Io + irr where irr is the reverse recovery current of the diode. When the diode snaps o, it is only the irr component of this current that is undergoing a rapid rate of change, and consequently only the energy stored in 1 L i2 has to rr 2 be handled by any snubbering circuitry.

2.4 Basic Analysis of Switch Mode Converters

2-61

iC
t6 t0

t5

Idealised switching loci

Turn-off
t1

Turn-on

t4

t3
L diC dt

0
iC Io

vCE

C L idt

Vd

Io

vCE
t0 t1

t3

t4 L = L1 + L2 +

t5 t6

Figure 2.43: Current and voltage trajectories during turn-on and turn-o for a step-down transistor converter.

2-62
Model of transistor switch during turn-o

Fundamental Topologies

tfi iC

tfi iC

tfi iC
Io

Io
iDf iDf iDf

Vd

iCS
Vd

Vd

Vd

iC

CS

vCS

CS small

CS = CS1

CS big

iCS = Io iC

Figure 2.44: Equivalent circuit for the turn-o RCD snubber and approximate waveforms for dierent values of capacitance [2]. If one now considers the operation of the turn-o snubber with dierent values of capacitor Cs we get the plots in Figure 2.44. One can see that if the capacitor is small then the voltage across it does not stay low during the turn-o, and there can still be substantial current and voltage across the switch. The CS = CS1 is characterised by the fact that the capacitor charge time is exactly the fall time of the current. For the large value of capacitor the charge time is far longer than the fall time of the current. Consequently for the whole of the turn-o period the voltage across the switch has a very low value. Remark 2.71 Clearly, from a switch power dissipation perspective, the large value of CS is superior. However, the down side of this approach is that the energy stored in CS has to be dissipated in the RS resistor on the next turn-on of the switch. Therefore it is best, for eciency reasons to choose a sensible compromise based on a balance between switch losses and RS losses. An optimum value can be found to minimise the total losses in the circuit [2].

Figure 2.45 shows the switching trajectories for the dierent values of capacitor shown in Figure 2.44. This simply conrms the comments in Remark 2.71.

turn-on snubber

A typical turn-on snubber is shown in Figure 2.46. As mentioned in a previous remark, the function of turn-on snubbers is to alleviate the large currents that can ow at turn-on due to reverse recovery currents from diodes that are conducting at the time of turn-on. As can be seen from Figure 2.46 the turn-on snubber works by using the inductance of the series inductance LS to limit the rate of rise of current during the turn-on phase. Therefore, since the diode Df will be a short circuit due to

2.4 Basic Analysis of Switch Mode Converters

2-63

iC
SOA

Io CS = 0

CS small CS = CS1

CS large
vCE

Vd

Figure 2.45: Switching trajectories for dierent turn-o capacitor values.

Df

I0

Vd LS

DLS

RLS

Figure 2.46: Typical turn-on snubber for a transistor step-down converter.

2-64

Fundamental Topologies reverse recovery during for a period of time during the turn-on the LS inductor will be supporting approximately Vd volts across it, and hence the voltage across the transistor will almost be zero. The price paid for the turn-on snubber is that the energy stored in the LS inductor must be dissipated. In order to do this additional components RLS and DLS are included to provide a path for the current to ow when the transistor is turned o. When the current ows through this path there will be a slight over-voltage impressed across the transistor. The resistor RLS is chosen so that the current in the inductor will be dissipated in a reasonable time after turn-o i.e. before the next turn-on. In addition it also has to be chosen so that the voltage rise on the transistor is not too great during turn-o as the inductor current ows through it. The nal type of snubber we shall consider is the over-voltage snubber. This type of snubber is specically designed to prevent over-voltage on the transistor due to the stray inductances in the circuit. It does not prevent voltages from appearing across the device during turn-o, and does not add any current at the turn-on of the device. The over-voltage snubber and the turn-o snubber should not be used at the same time. The basic structure for the over-voltage snubber is shown in Figure 2.47.

over-voltage ber

snub-

Ls

Df

I0

Rov

Vd Dov C ov

Figure 2.47: Over-voltage snubber for a transistor step-down converter.

In this circuit the voltage across the capacitor is at Vd when the switch is closed (diode Dov is reverse biased). When the transistor is switched o then diode Df turns on and the stray inductance L causes diode Dov to turn on forming a resonant circuit with Cov . This allows the energy to ow into Cov pushing its voltage above Vd . The amount the voltage goes above Vd depends on the relative values of L and Cov . The over-voltage across the capacitor then dissipates through the resistor back to the supply during the transistor o time.

2.4 Basic Analysis of Switch Mode Converters

2-65

Cov

Df

Io

Cd
Vd

CS

RS

LS

Figure 2.48: Undeland snubber for a step-down converter circuit. Remark 2.72 As noted previously turn-o snubbers can perform the function of over-voltage protection. The question then arises why bother with the overvoltage snubber? The main reason is that there is more freedom to address the over-voltage problem without running into diculties with the discharge time and subsequent resistance dissipation of the turn-o snubber. Also, in some other circuit congurations that employ turn-on snubbers, the over-voltage cadi pacitor serves to capture the energy from the dt limiting turn-on inductor. A snubber that attempts to combine aspects of all the previous snubbers, but with reduced component count is the Undeland Snubber. This combines characteristics of the turn-on, turn-o and over-voltage snubbers. Figure 2.48 shows an Undeland snubber for a step-down converter circuit.

2.4.11

Resonant and Soft-Switching Converters

This section of the notes will be undergoing a major revision during course presentation in 2005. The material below is still correct as far as it goes, but it is only a very brief and not particularly erudite presentation of some aspects of resonant converters. These notes will not look at resonant converters in any detail. These types of converters are not in the mainstream of converter technology at this time, and in fact some people in the switch mode power supply area think that they

2-66

Fundamental Topologies are a fad [5]. Nevertheless one should know what they are and what are their limitations. By the way I think that over time resonant converter technologies will certainly have increased application in specialist areas. Currently they are being used in areas where weight and losses are of particular importance (e.g. aerospace). A resonant converter is a converter that intentionally has a resonant LC tank circuit as a fundamental part of its operation. This tank circuit is excited by the switching of the converter, so that the resonance is maintained during operation. There are a variety of dierent topologies to achieve this operation. The reason for having this resonance is that if the switching of the main power devices occurs at the time when the voltage across, or the current through the device is zero. This means that the power dissipated in the device ideally is zero. Consequently it is possible to increase the switching frequency of the converter, without incurring excessive losses in the switching devices. In order to have some idea of the congurations of a resonant converters consider Figures 2.49 and 2.50. Figure 2.49 shows a resonant buck converter that is designed to switch when the current through the switch reaches zero. Figure 2.50 is a resonant buck converter which switches when the voltage is zero across the switch. We shall not look at the details of the operation of these (for details look in [2, 4]), but one can see that both circuits have the extra LC components represented by Cr and Lr . These are the components that represent the resonant circuit that is used to assist the switching of the power devices.
SW
Lr
Lf

Io
Vd

+ Cr

Cf

RL

Figure 2.49: A zero current switching (ZCS) resonant buck converter.

Remark 2.73 We shall see that the concepts used in resonant converters are actually very old. These ideas were originally used in forced commutated silicon controlled rectier (SCR) circuits from as far back as the 1960s. Before considering the pros and cons of resonant converters we need to distinguish between them and the so-called soft switching converters (a name often used in the literature to mean a resonant converter). Soft switched converters are also known as quasi-resonant converters. A resonant converter is one in which the power waveforms (current and voltage) are sinusoidal, and switching occurs when the voltage and/or current go through zero. Therefore the switching losses (ideally) should be zero. The quasi-resonant converter on the other hand is intermediate between the resonant converter and the conventional PWM converter. The circuit of these converters is so arranged that it creates a tank circuit for a portion of the switching period so that the switch transitions are nearly lossless.

2.4 Basic Analysis of Switch Mode Converters

Cr Dr

2-67

SW

Lr

Lf

Io
Vd

+ D Cf

RL

Figure 2.50: A zero voltage switching (ZVS) resonant buck converter. 2.4.11.1 Why One Should Not Use Resonant Converters switching frequency is a function of the load parasitic capacitances

Resonant converters have several problems in practice. The rst major one is that the switching frequency is a function of the load. This causes problems in the design of the EMI lters. A more serious problem is that it is common to use the parasitic capacitances as one of the elements in the resonant tank circuit. This makes is virtually impossible to build units that behave the same on the production line. The obvious solution to the problem is to parallel the parasitics with a capacitor that swamps its eects. However, this has the eect of lowering the oscillation frequency of the tank circuit, which is the whole objective of having the resonant converter in the rst place. In addition to the above problems, resonant converters still have problems with large line voltage changes, short-circuited or unloaded outputs, and component tolerances in general. They also operate mainly at higher peak transistor currents for the same output power compared to conventional PWM inverters, and in some congurations at larger voltage stresses. 2.4.11.2 Why One Should Use Quasi-Resonant Converters

Before discussing the benets of using these converters it may be benecial to review the operation of a quasi-resonant converter. Consider Figure 2.51, which is a conceptual diagram of a quasi-resonant forward converter. Notice that the main dierence between this converter and that of Figure 3.1 is the addition of the capacitor across the switch. The presence of the capacitor across the switch forms an LC circuit together with the magnetising inductance of the transformer. When the switch is opened, the voltage across the capacitor is zero. The current through the magnetising inductance will continue owing into the capacitor, and a resonant ring begins. This ring will continue until the voltage on the capacitor falls back to the supply voltage. At this point the voltage on the magnetising inductance will be positive at the dot end of the primary. This will cause the diode rectier in the secondary to turn on, and the remainder of the energy stored in the magnetising

2-68

Fundamental Topologies
iL

D1

L +
vL

C
RL

N1 Vd

N2

D2

Vo

SW

C SW

Vd

t Switch voltage

Figure 2.51: A quasi-resonant forward converter.

zero voltage switching

inductance is transferred to the load. One can see that the quasi resonant converter essentially forms a zero voltage switching (ZVS) device, since the voltage across the capacitor cannot change instantaneously when the switch is opened. One must be sure to choose the LC components so that the LC ring is complete before the start of the next control interval. However, this is not too limiting, and there is usually a reasonable range of components that can be chosen. Another possible problem is the presence of a charged capacitor across the switching device when it is turned on. However, a few calculations for practical situations show that the energy dissipated in a MOSFET switch due to this is very small. The major advantage of the quasi-resonant converter is the fact that it essentially works the same as the standard hard switched PWM converters, and the switching rate is determined by the PWM controller chip. Therefore the design of the ltering and EMI circuits is greatly simplied compared to frequency wild converters such as many of the pure resonant designs.

2.4.12

Example: ZVS Converter Design and Analysis

This example comes from a previous assignment in this course. Figure 2.52 is a diagram of a Zero Voltage Switching (ZVS) quasi resonant buck converter. The key equations for LC series circuits are as follows [2]. The equation for the current through the inductor is: iL (t) = IL0 cos 0 (t t0 ) + Vd Vc0 sin 0 (t t0 ) Z0 (2.141)

and the equation for the voltage across the switch capacitor is: vCr (t) = Vd (Vd VC0 ) cos 0 (t t0 ) + IL0 Z0 sin 0 (t t0 ) (2.142)

2.4 Basic Analysis of Switch Mode Converters

iLr
vC r Cr Dsw Lr iL Lo io I o

2-69

isw

+
Vin

C bulk

Df

Co

RLoad

vo

Figure 2.52: Zero Voltage Switching quasi resonant buck converter for example. where: 0 = Z0 = 1 Lr Cr (2.143) (2.144) (2.145) (2.146) (2.147)

Lr Cr iL (t0 ) = IL0 (the initial inductor current) vCr (t0 ) = VC0 (the initial capacitor voltage) t t0

a. Explain how the circuit of Figure 2.52 works. Use the above equations above appropriately to augment your explanation. Provide sketches of the current through the Lr inductor, and the voltage across the capacitor vCr as the circuit moves through its very states of operation. b. Carry out a design of the circuit assuming 24V input, a 5 Volt output, 30100 Watt output power range, 100mV output ripple, and continuous output current conduction. Make the resonant frequency 100kHz. c. Simulate the design to show that it works as designed. Solution Answer to Part (a) The fundamental assumption made in the following discussion is that the output can be modeled over one switching period as a constant current sink. Usually this assumption, for most realistic values of the output lter inductor, is reasonable. The following discussion is taken almost directly from Mohan[2]. This book gives a very clear explanation of the operation and behaviour of this circuit. The following explanation is with respect to Figure 2.53 from Mohan[2]. This diagram has been scanned from the text book, and therefore the quality is a little compromised. There are ve main areas of operation is this gure. Each of these areas shall be discussed in turn.

2-70

Fundamental Topologies

Figure 2.53: Waveforms in the ZVS circuit (scanned from [2]) . Interval t0 t1 The assumed starting point of the switching cycle is that the switch is opened at t0 (it has been closed up until this time), and that vCr = 0 and the current through the Lr inductor is the load current Io . The fact that vCr = 0 when the switch is opened means that this is a zero voltage switch operation. Since this current is constant then there will be no voltage across the inductor. Consequently the freewheeling diode will have a voltage across it of Vd Volts and hence will be o. This in turn implies that all the current will be owing through the capacitor. Therefore as time progresses from t0 the capacitor will be linearly charging in the polarity shown in Figure 2.53. The equivalent circuit at this time is shown in the Figure. Therefore the expression for the voltage on the capacitor is: t Io vc = dt t t1 (2.148) Cr t0 Interval t1 t2 The next interval can be divided into several sub-intervals.

2.4 Basic Analysis of Switch Mode Converters We shall discuss these in detail with the appropriate supporting equations. At time t1 the voltage across Cr becomes equal to Vd Volts, and therefore the voltage across the diode is 0 Volts. As t becomes greater that t1 then the voltage across the diode will attempt to go forward bias, and hence the free wheel diode will turn on and the load current will begin to transfer to it. The Lr current will also continue to ow in the Cr Lr part of the circuit. Since the right hand side of Lr is now connected to ground, the Cr Lr circuit now becomes a resonant circuit, where the initial condition in the circuit for the inductor current is Io . The inductor current for t1 t t2 is can be found by using the appropriate initial conditions in (2.141). In this case at t1 we have IL0 = I0 and Vc0 = Vd hence (2.141) can be written as: iL (t) = I0 cos 0 (t t1 ) t1 t t2 (2.149)

2-71

Similarly, for the capacitor voltage. We already know that the initial condition on the Cr capacitor at the beginning of the t1 time is Vd . Therefore we can write the expression for the voltage on the capacitor from (2.142) as: vc (t) = Vd + IL0 Z0 sin 0 (t t1 ) t1 t t2 (2.150) As can be seen from (2.150), the capacitor voltage is essentially that of a resonant circuit with a Vd voltage oset. Therefore the peak capacitor voltage is Vd + Z0 IL0 , and this occurs when the inductor current is zero. This is also the time when all of the load current is owing through the freewheeling diode. At t = t1 the resonant current in the circuit will attempt to reverse in direction. There is no current in the inductor, and therefore no energy to keep the current owing in the same direction. The voltage on the capacitor is in such a polarity to begin to make the current ow in the negative direction through the inductor. Consequently, as per (2.150) the voltage across the capacitor begins to decrease. The resonant pulse continues to t1 , at which point the voltage on the capacitor has reached the initial value at the start of the resonant cycle, and therefore in an oset sense is starting to reverse the voltage across it. This continues until time t2 when the voltage across the capacitor attempts to go negative. This is prevented by the diode Dr across the switch, which turns on. The situation at t2 is that freewheeling diode is still on, diode Dr has just turned on, the Lr inductor has a negative current owing through it, and the freewheeling diode has both the load current and the negative Lr current owing through it. Interval t2 t3 During this interval the current through the Lr inductor, which is initially negative at t2 , will start to increase linearly. One can see from the equivalent circuit in Figure 2.53 that the rate of change of current through the Lr inductor is: Vd diL = dt Lr (2.151)

2-72

Fundamental Topologies

vio

vio
V0 Vd t0 t1 t2 t3 t4

Ts =

1 fs

Figure 2.54: Voltage across the freewheeling diode in the ZVS circuit. This linear increase in the Lr current will continue whilst ever the switch diode and the freewheeling diode are on. Immediately after t2 (between t2 and t2 ) the switch should be closed, and this will allow the current to ow through the switch when it attempts to reverse direction through the Lr inductor. If this is not done, then there will be a dierent resonant cycle through the Cr Lr components. This is undesirable, as one can end up with a non-zero voltage across the Cr capacitor, and there would be a non-zero voltage switch on of the switch in the next complete cycle. Interval t3 t4 The switch is closed , therefore vCr is clamped at zero. The freewheeling diode is on and the Lr current at Io and freewheeling diode is o. At this point the whole sequence can now repeat if the switch is opened. Remark 2.74 The average output voltage for this circuit is controlled by controlling the period t3 t4 . The period t0 t3 is determined by the load current and the resonant circuit parameters, and is therefore not under the control of the circuit controller. Therefore if one wishes to have a lower average output voltage then t3 to t4 has to be made very short. Figure 2.54 shows the voltage waveform across the freewheeling diode. If the circuit is in steady state then the average voltage on the diode side of the Lf lter inductor has to be equal to the average output voltage. I Remark 2.75 It should be noted that the circuit has to be designed so that Z0 I0 > Vd . If it isnt the resonant ring will not have sucient amplitude to cause the voltage across the switch to become zero at time t2 . Therefore there would be a non-zero voltage switching if this occurs. This means that it is important to understand the minimum output current in order to make sure that zero voltage switching occurs under all load conditions. I Answer to Part (b) The rst part of the design is to work out the resonant circuit components. There are two factors that must be taken into account when designing these components:

2.4 Basic Analysis of Switch Mode Converters The resonant frequency required in this case 100kHz. The minimum current that will be pulled through the converter. This value will determine the Z0 I0min value. This must be larger than all values of Vd in order to ensure ZVS under all circumstances. These two constraints can be used to determine the two circuit parameters. The specications say that the minimum power the circuit has to supply is Po = 30 Watts at a voltage of 5 Volts. Therefore Iomin = 6Amps. We only have to cope with a constant input voltage of 24 Volts. The key equations are: 1 2 Lr Cr 1 Lr C r = 2 4 2 fr fr = In relation to the minimum power requirement we have: Z0 Iomin Vd Now Z0 = Lr Cr
P

2-73

(2.152) (2.153)

(2.154) Lr Cr Vd Iomin
2 2

(2.155) (2.156)

Now Iomin = omin = 30 = 6Amps. Therefore IoVd = 16. We shall choose Vo 5 min this value to be 20, so that it is well above the minimum value. Using (2.156) we can write Lr = 20Cr . Using this expression in (2.153) we can after a little manipulation write: Cr = 1 = 2 80 2 fr 1 = 0.3559F 80 2 (100e3 )2 (2.157)

Therefore using Lr = 20Cr we have that Lr = 7.112H. As a check these values give: Z0 Iomin = 26.83 (2.158)

which is clearly greater than the 24 Volt supply. In order to have continuous conduction the output lter inductor must be able to supply the energy for the whole of the period whilst the switch is open. As noted previously, the time that the switch is open in this circuit is not a controllable quantity, but is dependent on the circuit parameters and the output current. The precise answer to this question could be quite complex due to the fact that the output current varies the time that the switch is open in the circuit. In order to make the design robust to variations in design parameters and variations in circuit operational conditions that occur in real life, I will take a conservative approach to the design of the lter inductor. This conservative approach manifests itself in the calculation of the time that the switch is open. When the switch is open, ignoring the ramp slope

2-74

Fundamental Topologies shown in Figure 2.54 and assuming the output voltage is constant, we can write the following expression under steady state conditions for the voltage across the lter inductor: Vo topen + (Vd Vo )tclosed = 0 (2.159)

where topen is the eective time that the switch is open, and tclosed is the eective time that the switch is closed. The word eective relates to the fact that the actual time that the switch is open and closed is not related to the true time that these switches are open and closed for this converter. This is due to the fact that the voltage appearing across the output lter inductor does not correspond to the actual points where the switch is switched. Clearly equation (2.159) implies that for the system to be in steady state: tclosed = Vo Vd Vo topen (2.160)

Remark 2.76 Note that this expression contains an implicit assumption because the slope on the diode voltage waveform when the switch is rst opened is being ignored. The expression in its full form becomes a function of the resonant capacitor and the load current since these determine the time for the slope. I In addition we require that the average current over the total switching cycle is is equal to the Iomin = 6Amp current. Since the current waveform in the lter inductor (Lo ) is a triangular waveform, this implies that the average over half the period also equals the same value. The next question to resolve is the value of the topen time. This is where the worst case analysis comes in. One could calculate from the resonant waveform and the current value what the precise time is for the capacitor voltage to go to zero at t2 . The time from t2 t3 could then be calculated. This together with the linear charge time of t0 t1 gives the total eective open time for the switch. A more conservative approach is to assume the maximum possible eective open time for the resonant frequency chosen. For the resonant part of the cycle this is the time to the negative peak of the resonant capacitor voltage plus the linear charge time of the capacitor and the linear current increase time from t2 t3 . If the circuit is continuous for this time it will be continuous under all contingencies for ZVS for this circuit design. We shall now calculate topen . The linear charge time t0 t1 is given by: t01 = Cr Iomin Vd = 0.3559e6 24 = 1.4236e6 secs 6 (2.161)

Three quarters of the resonant period is 7.5secs this is the time to when the resonant capacitor voltage has reached its maximum negative value in the worst case. As mentioned above we are assuming that this is the time when the total voltage across the capacitor is zero. The nal time to calculate is the time it takes the current in the Lr to again reach Iomin from zero. This time is: t23 = Lr Iomin Vd 7.112e6 6 = = 1.778e6 secs 24 (2.162) (2.163)

2.4 Basic Analysis of Switch Mode Converters Therefore the total eective time that the switch is open is, adding to the times calculated above, equal to topen = 10.7016secs. The actual physical maximum switch open time is: tphy open = 1.4236e6 + 7.5e6 = 8.9236secs (2.164)

2-75

where tphy open is the actual true physical time that the switch is open. Note again that this is NOT the eective open time. These times give the time axis in calculation of the average current under the inductor ripple current. Assuming that this current is on the verge of discontinuity, then it is a triangle that starts at zero, goes to a maximum value and then back to zero at the end of the switching interval. Remark 2.77 This is an interesting situation. In the analysis for the converter we make the assumption that the current through the output lter inductor is more or less continuous and constant at the average current value. Indeed we sometimes model it as a current source. However in the situation of being the verge of discontinuity and the Lr inductor current reaching zero at the negative maximum voltage of the Cr capacitor, both the current in Lo and Lr are zero. Therefore the eective inductor for the current build-up is Lr + Lo . A situation completely violates the assumptions we made to establish the operation of the circuit. The waveforms applied to the output side of the circuit do not appear as shown in Figure 2.54. I Keeping in mind the limitations of the analysis from the previous remark, we still need to make some sort of an estimate for the Lo lter inductor value. During the topen time we shall assume that the current is freewheeling through the diode. If the output side of the circuit is on the verge of discontinuity, then this current will approximately reach zero during this period. If the iLo current is assumed to be triangular in shape then the average current is iave = 1 ipeak . 2 Therefore, since iave = Iomin = 6A then ipeak = 2Iomin = 12A. So this is the value of current that has to decrease to zero during topen when the voltage applied to the inductor is Vo . ipeak = Vo Lo topen (2.165)

and the average current for a triangular waveform such as this is 1 ipeak . Since 2 the average current has to be Iomin = 6Amps the ipeak = 2Iomin and using the fact that tclosed =
Vo Vd Vo Vd Vo

topen from equation (2.160) and realising that

5 24

= 0.2083 allows us to write5 : Lo = = Vo 2Iomin Vo 2Iomin topen = 5 8.92e6 = 3.71H 26 (2.166) (2.167)

The nal section to the design is capacitor design for the output. The specication says that the ripple has to be less than 100mV. The equation developed
5 See

remark below with respect to the meaning of the following value of inductance.

2-76

Fundamental Topologies in the notes for working out ripple can be used for this situation. This equation uses the concept of duty cycle. As can be seen from Figure 2.54 the eective waveform across the output is similar to that of a conventional hard-switched converter. Therefore the same relationships hold with respect to duty cycle. One of the main results we found previously when considering hard-switched converters is that the output voltage is a function only of the duty cycle in steady state, regardless of the load current. A similar property applies in this case. Notwithstanding the approximations with respect to the wave-shapes in5 volved, the switching period is Ts = topen +tclosed = topen (1+ 245 ) = 13.518secs. 5 The switch closed time is tclosed = 245 topen = 2.8162secs. Therefore the switching frequency is fs = 73975Hz under steady state conditions for all load currents. Using the traditional denition of the duty cycle we can write: De = 2.8162 tclosed = = 0.2083 topen + tclosed 2.8162 + 10.7016 (2.168)

Remark 2.78 We have to use the eect duty cycle, because the switch is actually closed after 8.9secs, but voltage is not applied at the output until the iL = Io i.e. the resonant inductor (Lr ) current has reached the load output current. Consequently duty cycle cannot be dened by the true on and o times of the switch as in other converters. I The expression for the ripple form the notes is: Co = 1 De
2 8fs Lo vo Vo

1 0.2083 8 739752 3.71e6

0.1 5

= 244F

(2.169)

Remark 2.79 The values for the lter inductor and capacitor are very much the worst case values. In fact the inductor has been chosen so that the ripple current is the maximum possible value before the current becomes discontinuous. As can be seen from the value it is smaller than the value of the inductance in the resonant circuit. One of the key approximations made in the above analysis was that the current through the Lo inductor could be considered constant over a switching cycle. Clearly if the ripple current is of the order of the average current itself then the Lo inductor cannot be considered to be a virtual current sink. If this assumption is not correct then all of the previous calculations will be thrown out by a signicant amount. Therefore a value of Lo should be chosen that is much larger than the minimum value chosen, and also much larger than the resonant inductor value as well so that it sees this inductor as a current sink. We shall choose a value for the lter inductor of Lo = 300H. This value is somewhat arbitrary but is two orders of magnitude above that previous calculated, and, more importantly is signicantly larger than the resonant inductor. It is not a ridiculously large value that would make it dicult or expensive to manufacture. I If we use the value of Lo = 300H then we can recalculate the value of the lter inductor. Substituting this value of Lo into (2.169) we get: Co = 3F (2.170)

2.4 Basic Analysis of Switch Mode Converters

iLr
vC r
C r = 0.3559mF

2-77

Dsw
Lr = 7.112mH Lo = 300mH

isw

iL

io I o
C o = 3m F

+
Vin

C bulk

Df

RLoad

vo

Figure 2.55: Final design of the resonant buck ZVS circuit. This completes the design calculations for the power supply under minimum current conditions. The completed design is show in Figure 2.55 with the circuit parameters shown. If the circuit is operating at maximum power the operational frequency of the converter will change. This is due to the fact that in the t2 t3 time will be longer. You may recall from (2.151) that the rate of increase of the iL current is only related to the input voltage and the value of Lr . Since the negative current starting point when the switch is re-closed is a large value, then clearly this time will be much larger. This means that the eective topen time of the switch will be much longer, and consequently the tclosed time will need to be longer to compensate for this increase in time. Remark 2.80 The point made in the previous paragraph is a negative for the ZVS resonant converter. It appears to be much more susceptible to load eects with respect to the switching frequency as compared to the ZCS form of the converter. I The worst case rise time of the current is: t23 = Lr 7.112e6 iL = 40 = 11.85secs Vd 24 (2.171)

Therefore the total worst case time for there to be no voltage applied to the output inductor is: topen = 10.7016e6 + 11.85e6 = 22.5516secs (2.172)

Remark 2.81 This value is likely to be quite inaccurate because it was derived using worst case assumptions we used you may recall the three quarters point in the resonant cycle for the worst case resonant time. In the high current case this will be more in error because of the large amplitude of the resonant pulse. I The eective duty cycle has to be such as to produce the correct average output voltage. As in the previous analysis we have: tclosed = 5 topen = 5.93secs 24 5 (2.173)

2-78

Fundamental Topologies
ZVS Resonant Buck Ideal current sink load at 6 Amp

M
Switch sig

period: 12.8u

7.5 5.0 2.5 0.0 2.5 5.0 7.5

60.0 50.0 40.0 30.0 20.0 10.0 0.0 10.0 40.0

(A) : t(s)
Lr inductor current

(A)

(V) : t(s)

locmax: (0.0016679, 50.81)

Cr cap voltage

(V)

(V) : t(s)
Diode voltage

30.0

20.0 (V)

10.0

Ave: 5.0797

0.0

10.0

1.66m

1.67m

1.68m

t(s)

1.69m

1.7m

1.71m

Figure 2.56: ZVS circuit without output lter but with an ideal current source load at 6 Amps. Therefore the eective duty cycle becomes in this case: De = tclosed 5.93 = 0.2083 = topen + tclosed 22.5516 + 5.93 (2.174)

as was found previously. The new switching frequency is: fs = 1 1 = = 35110 Hz 6 + 5.93e6 topen + tclosed 22.5516e (2.175)

Remark 2.82 One can see that the frequency of operation has dropped signicantly. This will therefore aect the output lter components dramatically if the same ripple is to be obtained. I Answer to Part (c) In this section we consider the simulation results. The rst set of results in Figure 2.56 are for the light load case where the load is modeled as an ideal current sink of 6 Amps. As can be seen the frequency of operation and the waveform amplitude are as predicted in the design. If we include the load lter in the circuit, but still with an ideal current sink as the load, then we can the results shown in Figure 2.57. As can be seen the results are largely the same as those in Figure 2.56.

2.4 Basic Analysis of Switch Mode Converters

VS resonant buck I_o = 6Amp, LoCo filter, Current Source Load.

2-79

M
n_15
period: 12.8u

7.5 5.0 2.5 0.0 2.5 5.0 7.5

70.0 60.0 50.0 40.0 (V) 30.0 20.0 10.0 0.0 10.0 5.1 5.075 5.05 5.025 (V) 5.0 4.975 4.95 4.925 4.9 PK2PK: 0.0838 X_Max: (0.008055, 50.79)

(A) : t(s)
Lr inductor curret

(A)

(V) : t(s)
Cr voltage

(V) : t(s)

Vo

8.035m

8.04m

8.045m

8.05m t(s)

8.055m

8.06m

8.065m

Figure 2.57: ZVS circuit with output lter and ideal current source load at 6 Amps. Finally if we include a resistor in circuit. The Saber model appears in Figure 2.58, and the results of the simulation with a 6 Amp output current appear in Figure 2.59. As can be seen the results are very similar to the ideal cases. The ripple current is within specication. If we increase the output current to the full load value of 20 Amps then we have to make a change in the frequency and the timing in the circuit. The result of the simulation of this circuit appears in Figure 2.60. As can be seen the frequency of operation at 45872Hz is dierent from that calculated, mainly due to the dierent time for the resonant pulse. This was noted as a point of inaccuracy above. The rise time of the inductor current is virtually exactly as calculated. The waveforms have again the correct form as discussed earlier. Remark 2.83 In order to get a more accurate design one would need to precisely calculate the resonant pulse width for the Cr capacitor voltage. I Remark 2.84 One very interesting observation from the results in Figure 2.60 is that the output ripple has not increased as we had predicted. The reason for this is subtle. When we calculated the ripple we were assuming a normal buck converter operating in continuous current mode. However, in the ZVS resonant converter case during the period of t2 t3 the Lr inductor current is building up, and therefore not all the current being supplied to the the load is having to be supplied from the Lo inductor. Therefore it does not use as much stored energy, and hence it is able to keep more continuous current ow. Therefore the ripple specication is satised without having to change the output lter capacitor. I

2-80

Fundamental Topologies

period:12.8u bits:[(tx=0,bit=_1),(tx=1n,bit=_1),(tx=1.1n,bit=_0),(tx=8.5u,bit=_0),(tx=8.5001u,bit=_1)] prbit_l4

BIT STREAM

sw1_l4 pwld pwld 0.3559u ref:c3

ref:l1 7.112u

ref:l2 300u

pwld ref:pwld2

v_dc 24

ref:c2 3u 0.8333

gnd

Figure 2.58: Saber circuit used for the 6 Amp full simulation.

ZVS resonant waveforms, with output filter and resistor 6 Amp output

M
n_15
period: 12.8u

(V) : t(s)
5.05

V_o
PK2PK: 0.06894

5.025

5.0 (V) 4.975 4.95 4.925 60.0 50.0 40.0 30.0 20.0 10.0 0.0 10.0

(V) : t(s)
Cr voltage

Maximum: 50.82

(V)

7.5 5.0 2.5 0.0 2.5 5.0 7.5 (A)

(A) : t(s)
Lr current

4.305m

4.31m

4.315m

4.32m

4.325m

t(s)

4.33m

4.335m

4.34m

4.345m

4.35m

Figure 2.59: ZVS circuit with output lter and resistive load at 6 Amps.

2.4 Basic Analysis of Switch Mode Converters

2-81

ZVS resonant buck Io=20Amp, Output filter and R load

M
n_15
period: 21.8u

20.1 20.0 19.9 19.8 19.7

40.0 Delta X: 17.276u Delta X: 4.224u

(A) : t(s)
Lo current

(A)

(V) : t(s)
Diode voltage

(V)

20.0

0.0

20.0 5.02 5.0 (V) 4.98 4.96 4.94 4.92 150.0 X_Max: (0.0063686, 112.83) 100.0 (V) PK2PK: 0.062998

(V) : t(s)
Vo ripple

(V) : t(s)
Cr voltage

50.0 Delta X: 5.9446u 0.0

40.0 (A) 20.0 0.0 20.0

Delta X: 11.85u

(A) : t(s)
Lr current

6.33m

6.34m

6.35m

t(s)

6.36m

6.37m

6.38m

Figure 2.60: ZVS circuit with lter circuit and resistive load, output current 20 Amp.

2-82

Fundamental Topologies

Chapter 3

Switch Mode Power Supplies

3.1 Introduction

In the previous chapter we looked at some fundamental topologies for switch mode converters. In this chapter we shall build on this basic information by considering some topologies that are used for commonly available switch mode power supplies (SMPSs). Towards the end of the chapter we shall consider some aspects of the control of these power supplies.

3.2

Isolated Converter Topologies

The converters presented in the previous chapter were all non-isolated converters. However, in practice isolated converters are very common. This is due to the fact that these converters do oer electrical isolation, but more importantly that allow the simple production of a number of voltages that are all electrically isolated. In this section the isolated converters will be related back to the basic topologies of the previous chapter. We do not look at all possible isolated topologies, since there are far too many to do this. Instead we concentrate on the basic types, from which all the others have common features. The fundamental principles of operation are emphasised.

simple production of a number of voltages

3.2.1

The Forward Converter

Figure 3.1 shows the basic idealised circuit for the forward converter. The forward converter is derived from the buck converter shown in Figure 2.2. The connection between the two converters is not obvious at a rst glance. One may recall that the main distinguishing feature of the buck converter is that when the switch is closed the input is connected to the output. In the case of the forward converter this is not literally true due to the isolation of the transformer. However, when the switch is closed the secondary side of the transformer is reected to the primary, so in eect this connection exists. When the switch in the buck converter is opened then the input is disconnected from the output. In the forward converter this occurs due to the fact that the voltage across the transformer reverses (because of the trapped ux in

3-2

Switch Mode Power Supplies the transformer), and the diode D1 is reversed biased and disconnects the load from the transformer secondary. Remark 3.1 The above-mentioned trapped ux in the magnetising inductance of the transformer is a new problem that does not exist in the conventional buck converter. If one were to operate the forward converter as described in the paragraph above then the switch would be destroyed by the very high voltages created as the ux in the magnetising ux attempts to maintain the current through the open switch.

D1

L +
vL

iL

C
RL

N1 Vd

N2

D2

Vo

SW

Figure 3.1: Basic circuit of the forward converter. practical converter forward Figure 3.2 shows a practical forward converter circuit. In this circuit we introduce a third winding to transfer the energy trapped in the magnetising inductance back to the supply. This winding plays no part when the switch is turned on, but when the switch is turned o and the voltage across the magnetising inductance reverses then, due to the turn direction of the third winding, diode D3 turns on and current ows back into the supply. This limits the rate at which the ux collapses in the magnetising inductance, and therefore the voltage induced by this collapse is controlled. The operation of the circuit can be better understood by referring to the equivalent circuit in Figure 3.3. This circuit is based on using the concept of the ideal transformer that does not require any mmf to operate.1 Ignoring the leakage inductances, the ux is stored in the Lm inductance. When the switch is closed current builds up in this inductance, and at the same time current, i1 ows into the transformer. The voltage v1 appears across the magnetising inductance, and this is reected via the transformer voltage ratio to
1 The transformer has a magnetic structure with innite permeability and consequently the coupling between the windings is one. This also implies that the primary winding has innite inductance.

3.2 Isolated Converter Topologies

3-3

D1 N3 N1 Vd D3 N2 D2

L +
vL

iL

C
RL

Vo

SW

Figure 3.2: A practical forward converter.

Ideal transformer
i3 Ll1 i2 N3 Ll 2 iL

i1

D1

L +
vL

RL

Lm
Vd

im v 1 N 1

N2

D2

Vo

D3
v sw

SW

Figure 3.3: Equivalent circuit for a practical forward converter.

3-4

Switch Mode Power Supplies winding 2 (the secondary). Similarly the current i1 is reected as i2 in winding 2 via the transformer current ratio. This current then feeds the load via the output LC lter. When the switch is opened then the current im owing in the magnetising inductance cannot stop instantaneously. As can be seen from the equivalent circuit the current can ow in a loop via the ideal transformer. The dot relationship between the primary and ternary winding means that the voltage Vd appears across the ternary winding. This voltage is reected to the primary winding voltage as v1 = Vd . This implies that vsw = 2Vd . Therefore, the presence of the third winding keeps the voltage across the switch to a reasonable and controllable value, and essentially returns the energy trapped in the magnetic eld of the magnetising inductance to the supply. The above discussion omitted the inuence of the leakage inductance. Unfortunately the presence of leakage disrupts the ideal operation. If we again consider Figure 3.3, we can see that the leakage inductance carries im + i1 , and 1 therefore it would store the energy 2 Ll1 (im + i1 )2 . As with the magnetising current this stored energy will attempt to maintain the current in the same direction. Therefore when the switch is opened a large voltage can be produced across this inductance, which would also result in a high vsw voltage. Even for fairly small values, the voltage produced could result in the destruction of the switch. Remark 3.2 In order to minimise the leakage inductance the primary and ternary winding are often bilar wound i.e. they are both wound on the same arm of the transformer. The secondary may not be wound like this as large voltage isolation between the primary and secondary is often very important. Remark 3.3 In order to catch any voltage spikes associated with the leakages one may need some snubbers across the switch. Remark 3.4 The wire used for the ternary winding can be much smaller gauge than the secondary winding as it only has to carry the magnetising current of the transformer. Now let us consider the operation of this forward converter in a little more detail. Assuming for the moment that we are dealing with the ideal forward converter as depicted in Figure 3.1, and assuming that the transformer is ideal. If the switch is turned on, then there will be current owing through the transformer primary, and hence the secondary. Since the voltage ratio of a transformer is: v2 N2 = v1 N1 then we can deduce that: vL = N2 Vd Vo N1 for 0 < t < ton (3.2) (3.1)

inuence of leakage inductance

which is a positive value, causing iL to increase in value. When the switch is turned o then the diode D1 is reverse biased, eectively disconnecting the transformer from the remainder of the secondary side

3.2 Isolated Converter Topologies circuit. The trapped energy in the lter inductor causes the diode D2 to turn on, allowing current to circulate. In this case the inductor voltage is: vL = Vo for ton < t < Ts (3.3)

3-5

which is negative, resulting in a decreasing current in the lter inductor. If one integrates the inductor voltage over one complete period and equate to zero one gets: N2 Vo = D (3.4) Vd N1 Remark 3.5 One can see from (3.4) that the voltage ratio is the same, in principle, as that for the buck converter. However, whilst a buck converter can only produce voltages less than the input voltage, the forward converter can produce voltages that are greater than the input voltage with an appropriate turns ratio for the transformer. As we have previously noted, in a practical forward converter one must account for the energy trapped in the magnetising inductance. Let us now consider how this requirement alters the operational range of the converter output voltages. The following discussion is with reference to Figures 3.3 and 3.4.
v1
Vd

forward converter voltage ratio

t
N1 N3
tm t on Ts isw
t off

Vd

i1

im

t
iL i1 = im

Figure 3.4: Current waveforms for a practical forward converter.

3-6 When the switch is closed then: v1 = Vd

Switch Mode Power Supplies

for 0 < t < ton

(3.5)

and the current through the magnetising inductance, im , increases at a linear rate (as can be seen in Figure 3.4). When the switch is opened at time ton , the imton must instantaneously keep owing. This is achieved via the primary coil of the ideal transformer. Note 3.1 The capacity for the magnetising current to ow through the primary of the ideal transformer is due to a property of transformers. The circuitry connected to the secondary winding of the transformer is reected (via a turns ratio relationship) to the primary. Therefore, the current is actually owing in the secondary circuit, but reects in such a way as to create the illusion that it is owing in the primary. From this point of view Figure 3.3 is a little deceptive. When the switch is opened, as previously mentioned, the voltage induced in winding 2 is such that the diode D1 is reversed biased, thereby disconnecting the secondary circuit. At the same time, diode D3 turns on due to the voltage induced in winding 3. Therefore this winding eectively becomes the secondary under this condition. Under this condition the currents owing in the circuits are: i1 = im , i2 = 0 and i3 becomes (from the normal current ratio for an ideal transformer): N1 im (3.6) i3 = N3 During the time tm , when the i3 current ows, the voltage across the transformer primary is: N1 for ton < t < ton + tm (3.7) v1 = Vd N3 since Vd is the voltage across winding 3. When the transformer demagnetises, then im = 0 and v1 = 0. The time can be obtained by realising that the time integral of the voltage across the magnetising inductance must be zero over a complete time period (for steady state operation). Considering Figure 3.4 one can see that: Vd DTs N1 V d tm = 0 N3 tm N3 = D Ts N1 (3.8) (3.9)

Forward converter maximum duty cycle

If the transformer has to be totally demagnetised before the start of the next control interval, then the maximum value of tm /Ts = 1 D. Therefore the maximum duty cycle, using (3.9) is: (1 Dmax ) = Dmax N3 Dmax N1 1 = 1 + N3 N1 (3.10) (3.11)

Remark 3.6 Equation (3.11) indicates that the maximum duty cycle is 0.5 if N1 = N3 (a common choice in many designs).

3.2 Isolated Converter Topologies 3.2.1.1 Other Forward Converter Topologies

3-7

We shall not go into detail into the other forward converter topologies, but shall simply show the basic design and highlight a few pertinent properties. Only a subset of the available of forward converter topologies will be presented. 3.2.1.1.1 Two Switch Converter This topology is shown in Figure 3.5. In this converter each of the switches are turned on and o simultaneously. Consequently each switch only has to stand a maximum voltage of Vd . One of the other nice features of the circuit is that the magnetising and leakage currents can ow via the diodes to the supply, thereby eliminating the ternary winding on the transformer, and negating the requirement for snubbing across the switches. A Dmax = 0.5 limitation applies to this converter.

SW1

Vd

N1

N2

Vo

SW2

Figure 3.5: Circuit diagram of a two switch forward converter.

3.2.1.1.2 Push-Pull Converter This topology is shown in Figure 3.6. The salient feature of this topology is the centre tap transformer used. One of the main limitations of the previous forward converters was that the duty cycle was limited to a maximum value of 0.5. This limitation occurred due to the need to demagnetise the transformer prior to the start of the next switching cycle. The push-pull form of the forward converter eectively allows one to get a full duty cycle range, at the cost of a more elaborate transformer and two switching devices. We shall spend a little more time investigating this circuit because a few important concepts can be gleaned from this that are of use in Power Electronics and circuits in general. One can see from Figure 3.6 that only one half of the transformer is active at any one time, since only one of the switches is turned on at any one time. For example, if SW1 is closed then current will ow from the supply via the

3-8

Switch Mode Power Supplies

D1

N1

N2

RL

Vo

Vd

N1

N2

D2

SW1

SW2

Figure 3.6: Push-pull forward converter.

top half of the primary through SW1 . This will result in a voltage developing across the top half of the secondary winding consistent with the dot convention of the windings. The resultant current ows via diode D1 to the load. If SW2 is closed (then SW1 is open) a similar pattern occurs. In this case the current ows from the source via the bottom half of the primary through SW2 . The dot convention with this half of the primary in relation to the secondary means that diode D2 is forward biased (and D1 is reverse biased). Therefore again current ows to the load. The diode arrangement on the secondary is a conventional full wave rectier circuit. As with the previous cases one ends up with magnetic energy trapped in the magnetising inductance of the primary. In this particular case the other half of the primary winding that is not conducting current when the corresponding switch is closed corresponds to the ternary winding shown in Figure 3.2. The two halves of the primary essentially form an autotransformer. If we operate the circuit so that there is a period of operation when both of the switches are o, then a question that immediately arises is what happens to the trapped magnetic energy in the core of the transformer?. This turns out to not be an easy answer in the sense that the solution takes a deal of insight into how transformers work. We shall consider the operation of the circuit if both switches are in the o state using two approaches the rst is the conventional equivalent circuit approach, and the second is based on realising that the total mmf in the circuit cannot change instantaneously. Consider the situation where switch SW1 has been closed and then it has been opened. Switch SW2 is left open. When SW1 was closed then the top half of the secondary transformer would be positive, and consequently the diode D1 is forward biased. We shall assume that the lter inductor L is large enough that the current iL is constant. Hence the current iL ows through D1 . When SW1 is opened then there is ux in the core of the transformer. This ux must be maintained by a current. This current is often called the magnetising current, and it is assumed to ow through a ctitious circuit element called

3.2 Isolated Converter Topologies the magnetising inductance. This element is usually placed in the primary side of a transformer. From Figure 3.7 one can see that the current owing through SW1 is composed of two components the load current (with the appropriate turns ratio) and the magnetising current. Normally the magnetising current is small compared to the load component. We are assuming that the transformer is ideal i.e. it does not require any mmf to magnetise it. The magnetising current is owing through the magnetising inductance to produce the ux that is present in any real transformer. When SW1 is opened then we have the situation shown in Figure 3.8. On the primary side of the transformer there are two main eects to consider. The current shown in Figure 3.7 owing through the leakage inductance of the primary (Ll ) wishes to continue owing. Therefore a voltage is developed across the leakage in an eort to achieve this. This voltage appears in conjunction with the supply voltage across SW1 this is voltage vLl +Vd in Figure 3.8. A snubber is often required across the transistors to cope with this voltage spike.
Ideal transformer
N2 N1

3-9

Vd

Ll

iL

D1

L
iL

N2 N1

i L + im

im

Lm Vd

N2
N1 N2 N 1

Vd

RL

Vo

N1 SW1

N2 N2 V N1 d

D2

Diode is open circuit.

Figure 3.7: Currents owing in the push-pull forward converter with SW1 closed.

The second salient point on the primary side of the circuit is that the current owing through the magnetising inductance cannot be changed instantaneously. Therefore a voltage would normally develop across the magnetising inductance in an eort to maintain this current. This voltage has a polarity with the positive on non-dotted terminal of the top half of the transformer. However, this is coupled by the ideal transformer to the secondary. This would produce a positive voltage on the non-dotted terminals of the secondary. Consequently the diode D2 would become forward biased. Diode D1 also remains forward biased as well, meaning that the (constant) iL current splits between D1 and D2 . This then provides a path for the magnetising current to ow. If this circuit was a normal push-pull inverter circuit then the diode across SW2 would turn

3-10
Vd

Switch Mode Power Supplies

Ideal transformer

Ll

im

D1

L
iL

vL

iL
im Lm
N1 N2

N1 N2

im
iL

RL

Vo

+
SW1

N1

N2 i L

v L +Vd
l

N1 N2

im

D2

Both diodes short circuit

Figure 3.8: Currents owing in the push-pull forward converter with SW1 and SW2 open. on and clamp the voltage across the top half of the winding to Vd . However, the presence of the full wave rectier circuit on the secondary side of the circuit changes this normal scenario. One point that is not obvious in Figure 3.8 is why does the current iL split between the two secondary windings? When D2 becomes forward biased why doesnt D1 become reverse biased? The answer to these questions is that the constant load inductor current prevents this from happening. If D1 attempts to turn o, then the load current would immediately be diverted into the lower half of the secondary. This would mean that a voltage would be induced in this part of the winding (since a rate of change of ux in the core would result) such that diode D2 would turn o, and D1 would turn on. Therefore the stable situation is that shown in Figure 3.8. Note that due to the dots on the secondary, the iL /2 current in each half of the windings would produce uxes that cancel each other. Therefore the only component of ux producing current is the magnetising component reected into the secondary which circulates around the loop comprising the two diodes and the transformer secondaries. Another way of reasoning this is to realise that when SW1 is opened the reected iL current must become zero. Consequently the eective iL current through the secondary of the transformer must also be zero (else we cannot have zero reected iL on the primary side). Given that iL is held constant by the lter inductor, the only way that this can be achieved is if there is net zero ux produced by the secondary winding due to iL . This is achieved by D1 and D2 both being on, since this results in ux cancellation in the secondary winding. There is an alternative way of reasoning the splitting of the inductor current between the two secondary windings. This technique is simple, and can be applied to very complex coupled winding situations. For the moment consider the transformer to be ideal i.e. the magnetising inductance is innite. With SW1 closed all the current owing in the primary is reected into the secondary. In terms of mmf, an ideal transformer does not require any mmf to set up the

3.2 Isolated Converter Topologies ux in the core. Therefore we have: N1 i1 + N2 iL = 0 (3.12)

3-11

i.e. no net mmf in the transformer. When SW1 opens the net mmf in the core cannot change since the transformer is ideal i.e. it has to remain zero. The current in the load inductor is constant, therefore this current must split between the two secondary windings so that the ux produced by one is cancelled by that produced by the other, thereby keeping mmf in the core zero i.e. when the switch is opened i1 = 0, therefore the second term in the mmf expression must also be zero. This occurs if the other term is 1 N2 iL + ( 1 N2 iL ), which implies the above-mentioned 2 2 splitting of the currents. The overall result of D1 and D2 being on simultaneously is that the secondary windings are short circuited. This value is mirrored to the primary, and its voltage will be zero (if D1 and D2 are ideal). It can be shown that the voltage ratio [2] for this converter is: N2 Vo =2 D Vd N1 (3.13)

push-pull ratio

voltage

where 0 < D < 0.5. Therefore, even though the range of the duty cycle is limited to 0.5, the output voltage can achieve values as if the duty cycle has a range from 0 to 1. Remark 3.7 One potential problem with the push-pull converter is that the switches are subject to maximum voltages of 2Vd . For low voltage applications this is of little consequence, but for mains line applications with 240VAC this means that the devices will be subject to minimum voltages of 700V. Therefore, 1000V MOSFETs are required to ensure that there is sucient over voltage capacity. Remark 3.8 One of the potential problems with the push-pull circuit is that small dierences in the timing of the duty cycles of the two switches can lead to osets in the ux of the transformer. These timing dierences can occur because of dierences between the turn-on times of the transistors, or dierences in the speeds of the ring circuits. Consider Figure 3.9 which shows a typical BH curve for a ferro-magnetic material. As the ideal push-pull circuit operates it normally moves from B1 to B2 via the hysteresis loop shown. If the on transistor is driving the ux density to B2 , and its on-time is a little less than the other transistor, then the ux density may not quite get to B2 , but instead only gets to B2a . Therefore, when the other device turns on it will drive the ux density to a value a little higher than B1 , B1a . This process will continue, and the maximum ux density B1a will creep up higher on the BH characteristic. If the process continues then the core will saturate at the higher ux densities and the magnetising inductance of the core will become very small and excessive currents will ow through the transistor that is on when this occurs. This often results in transistor failure. Current mode control is often used to x this problem. MOSFET transistors also help, as they have a positive temperature coecient, and as they heat up more of the voltage is dropped across the device, thereby robbing volt seconds from the magnetising inductance. The resistance of the primary also helps via a similar mechanism.

3-12

Switch Mode Power Supplies

Loop with flux imbalance Normal operation loop

B1a B1

B 2a B2

B1 = B 2

Figure 3.9: Flux imbalance in the push-pull circuit.

Practical issue 3.1 One very nice feature of the push-pull converter is that both of the transistors are referenced to the same ground rail. This simplies the drive circuits for transistors as compared to other topologies where one has transistors oating at dierent voltage levels.

3.2.2

The Flyback Converter

The Flyback converter is an isolated converter that is derived from the buckboost converter described in Section 2.3.3 of the previous chapter. Figure 3.10 diagrammatically shows this connection. Recall from Section 2.3.3 that the important properties of the buck-boost were that when the switch is closed it performs similarly to a boost converter, with the input disconnected from the output and the current owing through an inductor storing energy. When the switch is opened then the energy stored in the inductor is then transferred to the secondary winding, and in the process of doing this the energy storage inductor eectively becomes the lter inductor in the load section of the circuit. This inductor connects the input to the output when the switch is open. If we compare the buck-boost shown in Figure 3.10 with the Flyback converter, then we can see that the magnetising inductance of the transformer carries out the same function as the storage inductor in the traditional circuit. During the phase when the switch is closed current ows through the magnetising inductance. During the time the output circuit is disconnected from the input because the diode is reversed biased. When the switch is opened, the current through the magnetising inductance wishes to keep owing in the same direction. It therefore produces a positive voltage on the non-dot end of the primary, resulting in a corresponding positive voltage on the non-dot end of the secondary. Consequently the diode in the secondary becomes forward biased,

3.2 Isolated Converter Topologies and the magnetising current in the primary is reected (via the turns ratio) in the secondary. This current ows into the output capacitor. In eect the magnetising inductance in the primary has been reected into the secondary, and it performs the same function as the lter inductor in the classical buck converter circuit.

3-13

Vo
N1 Vd Vd N2

Vo

SW

Buck-Boost Converter

Flyback Converter

Figure 3.10: Connection between the Buck-Boost and Flyback converter. Now let us consider the operation of the Flyback converter in more detail. Again we shall assume steady state operation, and the output voltage is considered constant. We shall look in some detail at the variation of the ux in the core, since it is the ux that stores the energy that is transferred to the load. One can calculate the ux in an inductor by using Faradays Law: N d dt 1 t (t) = vL ( )d + (0) N 0 vL = (3.14) (3.15)

In the case when the switch is closed, as shown in Figure 3.11, there is a constant voltage of Vd applied across the magnetising inductance, Lm . The secondary side of the circuit may as well not be there, since the diode in the secondary eectively disconnects the load from the primary. The load current Io is supported by the capacitor. It is therefore important that the capacitor be large enough to support the current and voltage appropriately during the switch on period. Equation (3.15) can therefore be written as: (t) = (0) + Vd t N1 for 0 < t < ton (3.16)

and clearly the peak ux in the magnetising inductance at the end of the on period is: Vd = (0) + ton (3.17) N1 At the end of the time ton the switch is opened. Because the current owing in the magnetising inductance cannot change instantaneously, or alternatively

yback peak ux

3-14

Switch Mode Power Supplies

Diode reverse biased

iD = 0

Io

im Lm

v1 N 1

N2

RL

Vo

Vd

N2 N1

v1 =

N2 N1

Vd

SW

Figure 3.11: Flyback converter with the switch closed.

the total mmf in the transformer cannot change instantaneously, then a voltage is induced on the secondary (the polarity determined by the dot convention), in such a manner as to turn on the diode in the secondary. The circuit conguration then changes to that shown in Figure 3.12. As can be seen from the gure a voltage of Vo is produced across the sec1 ondary so that the diode turns on. The voltage N2 Vo is produced across the N primary, with a polarity that will cause the magnetising current to decrease. Another way to look at this is to realise that the secondary circuit is reected to the primary by the transformer, and therefore the magnetising current can ow in this reected circuit. During the o stage of operation, the ux in the transformer core will decrease from the peak value calculated in (3.17). Therefore the time evolution of the ux during this time is again given by applying Faradays Law:
N1 N2 V o

(t ton ) N1 Vo (t ton ) for ton < t < Ts (t) = N2

(t) =

(3.18) (3.19)

yback ux at Ts

From (3.19) one can deduce, using (3.19) and (3.17), that the ux at the end of the control interval:

3.2 Isolated Converter Topologies

3-15

Diode forward biased

iD

Io

im Lm

N1

N 2 Vo

RL

Vo

Vd

v1 =

N1 N2

Vo

SW open
Figure 3.12: Flyback converter with the switch open. Vo (Ts ton ) (Ts ) = N2 Vd Vo = (0) + ton (Ts ton ) N1 N2

(3.20) (3.21)

We are again assuming that the system is in steady state, therefore the ux at the beginning and end of a control interval must be the same. This means that: (Ts ) = (0) which, using (3.21) allows us the write: (0) + Vd Vo ton (Ts ton ) = (0) N1 N2 Vo Vd ton = (Ts ton ) N1 N2 (3.23) (3.24) yback voltage ratio (3.25) (3.22)

Rearranging this, and using (2.2) we can write: Vo N2 = Vd N1 D 1D

Remark 3.9 The voltage ratio in (3.25) is identical to the voltage ratio calculated for the buck-boost converter, as shown in (2.67). The currents owing in the circuit under the switch on and o conditions are shown in Figure 3.13

3-16

Switch Mode Power Supplies

v1
Vd

0
N1 N2 Vo
t on f Ts
t off

f(0)

t
iD

N1 N2

im
Io

t
Figure 3.13: The voltage, current and ux in the ideal Flyback Converter.

3.2 Isolated Converter Topologies

3-17

Let us calculate the currents owing in the Flyback converter. This analysis basically follows the same procedure as the calculation of the magnetising ux. Assume that the current at the beginning of a control interval has an initial value of im (0). Therefore during the ton period the magnetising and switch current is: Vd t for 0 < t < ton (3.26) im (t) = im (0) + Lm As with the ux, the peak magnetising current at the end of the on period is: m = im (0) + Vd ton i Lm (3.27) peak magnetising and switch current

Remark 3.10 Note that m is also the peak current owing through the switch. i During the o period the switch current is obviously zero. During this time the voltage across the magnetising inductance is of a polarity so that the current decreases. The current during this period is: im (t) = m i
N1 N2 Vo

Lm

(t ton )

(3.28)

The current in the diode during this period is simply a scaled version of the inductor current (by the transformer turns ratio). i.e.: iD (t) =
1 Vo N1 N1 im (t) = im N2 (t ton ) N2 N2 Lm

yback diode current

(3.29)

Using the equations that we have derived it is now possible to get the peak magnetising current in terms of the load current and voltage and the duty cycle. This is an important equation for this type of converter, since the peak magnetising current needs to be known so that saturation of the core can be avoided, and the switches can be sized. The rst step is to work out the average expression for the diode current, which is also equal to the average load current (in steady state). Taking the average of (3.29) and rearranging we can get the expression for the peak current in terms of the average load current and the output voltage: Io 1 V o N2 m = N2 i + (1 D)Ts N1 (1 D) 2 Lm
N1

peak switch current

(3.30)

The peak voltage across the switch can be seen to be the supply voltage plus the voltage produced by the transformer: vsw = Vd + which can be written, using (3.25), as: vsw = Vd (1 D) (3.32) N1 Vo N2 (3.31)

3-18

Switch Mode Power Supplies

3.2.3

Utilisation of Magnetics

One important factor in the performance of converters is the utilisation of the magnetic material. Converters such as the boost and yback converter are storing energy in the magnetic eld and then transferring this stored energy to the load when the switching device is turned o. A converter such as the forward converter is transferring energy via direct transformer action the stored energy is a nuisance in that it has to be transferred somewhere when the power device is turned o. Despite this two dierent modes of operation, both these converter types are only magnetising the core in one direction. The full bridge converter, on the other hand, is really a variant of the forward converter, but it is dierent in that the core is magnetised on both directions during normal operation. This bidirectional magnetisation has implications on the utilisation of the core material. One of the main motivations for the use of SMPSs is their low weight and volume. Therefore it is essential that the magnetic material is well utilised to achieve these objectives. Consider Figure 3.14 which shows a typical BH curve for a magnetic material. The ux density Bm is the maximum ux density that can be achieved when the material is saturated. The ux density Br1 is the remnant ux density when the core is not being subject to an mmf.
B Original magnetic material (no air gap)
Bm

Br 1 Br 2

H Magnetic material with air gap

Figure 3.14: Typical BH loop for a magnetic material. Figure 3.15 shows the excitation waveforms for a forward converter with a feedback winding such that N1 = N3 (Figure 3.15(a)), and a full bridge converter (Figure 3.15(b)) with the same primary turns. The voltage v1 is the voltage across the primary winding. We shall assume that both converters are operating with D = 0.5. Bmax is the excursion of the ux density from the average value of the ux density. Note 3.2 It should be noted that the use of a full bridge converter in this mode is entirely articial. Under a duty cycle of 0.5 the average output voltage of this converter is zero. The output could be used to drive a transformer connected

3.2 Isolated Converter Topologies to a rectier to get a dierent output voltage. If a modulation strategy using zero voltage application is used then control of the DC output voltage could be obtained. The reason for the articial D = 0.5 restriction is that this will force the ux in the core (under appropriate start up conditions) to be bidirectional. Remark 3.11 A better converter to use for this example is the push-pull converter. This converter can perform all the functions of the full bridge if a DC output is required, only involves two switches, and can be made to operate with symmetric bidirectional ux in the core of the transformer (with modied ring of the switches using a combination of current control and zero voltage application).

3-19

v1 Vd

v1 Vd

0
t on
- d V t off

0
t on
- d V t off

DB

DB

(DB )max

(DB )max

0
Ts (= 1 ) fs

Ts (=

1 ) fs

(a)

(b)

Figure 3.15: Core excitation waveforms. (a) forward converter. (b) full bridge converter. Let us consider the expression for the maximum deviation of the ux density away from the average value. We know from Faradays Law, (3.14), and the relationship = BAc , where Ac the area of the core, that ux density can be written as: ton 1 B= v1 d + B(0) (3.33) N1 Ac 0

3-20

Switch Mode Power Supplies We are interested in the total change in B from whatever initial condition there is. We shall call this B. This allows us to ignore the initial condition B(0) in the following evaluation.2 Assuming that D = 0.5 (which implies that ton = Ts /2), and v = Vd then we can write:
2 1 Vd d B = N1 Ac 0 Vd Vd Ts = = 2N1 Ac 2N1 Ac fs Ts

(3.34) (3.35)

This value corresponds to the peak value of the ux in Figure 3.15(a). To evaluate the average value we calculate the area under the B curve and divide by the time (since in Figure 3.15(a) the B waveform is triangular). Therefore using (3.35) the expression for Bave is:
Vd 2N1 Ac fs Ts 2

Bave = =

Ts Vd 4N1 Ac fs for D = 0.5

(3.36) (3.37)

We can now nd Bmax , the maximum deviation of the ux from the average ux, by subtracting (3.37) from (3.35) to give: Bmax = Maximum ux excursion. Vd 4N1 Ac fs for D = 0.5 (3.38)

which is valid for both converters. A little earlier we mentioned that we had ignored the initial value of the ux density, but in the footnote we noted that this would be important. Referring to Figure 3.14, one can see that when there is no excitation of the core that the remnant ux density is Br . Therefore this point on the BH characteristic is the starting point for any unidirectional ux excursion i.e it is the initial condition B(0) in (3.33). Therefore, using the denitions in Figure 3.14 the forward converter ux excursion Bmax becomes: Bmax = 1 (Bm Br ) 2 (3.39)

i.e. the ux excursion is limited by the remnant ux density in the core. Because the ux is starting o with the Br oset, then the ux cannot undergo large ux excursions. In the case of the full bridge converter, the ux undergoes symmetric ux density excursions about the zero ux density point in Figure 3.14.3 Therefore Bmax is limited only by the saturation ux of the core i.e.: Bmax = Bm
2 Note

(3.40)

the the initial condition is very important when it comes to evaluating the magnetic utilisation, as we shall see. 3 This is achieved because of the switch drive circuits are designed to produce these ux excursions. Note that it is not intrinsic in the design of these converters that this would happen.

3.2 Isolated Converter Topologies What are the implications of these dierences in the maximum ux density that can be achieved with these converters? These can be gleaned by considering (3.38) in the light of the above comments. Rearranging (3.38) we get: Ac = Vd 4N1 (B)max fs (3.41)

3-21

We can see from this expression that if Bmax is large then Ac can be smaller. Therefore, given the same applied voltages, duty cycle and switching frequency, and for the same number of turns on the primary, the full bridge converter will have a signicantly smaller core for the magnetics as compared to the forward converter. Remark 3.12 Equation (3.41) assumes that fs is the same and N1 is the same under the condition of smaller core cross-sectional area. However, as can be seen from (4.23) in the following chapter, reproduced here for convenience: L=
2 N1 Ac lc

(3.42)

where lc is the magnetic path length of the core, the inductance of the core is much less. This should also be obvious from the denition of inductance: L= N1 BAc = i i (3.43)

If Ac is smaller, then for the same current i the B will be the same (via Amperes Law), and therefore will be smaller. Therefore implicit in (3.41) is the fact that the current is allowed to increase when we have the smaller core area, since the same voltage is applied by the converter across the winding for the same time, but the inductance is less. Remark 3.13 As can be gleaned from Remark 3.12 there is a trade-o for the reduced size magnetics under the condition specied for the same power output we have a larger magnetising current, therefore higher losses, and larger switching devices. Remark 3.14 The fact that one does not have to demagnetise the core in the push-pull converter means, without considering the maximum ux density issue, one can produce more power from the same magnetic core. The eective maximum duty cycle is 1, whereas for the forward converter it is 0.5 (depending on the relative turns ratio of the ternary winding). Remark 3.15 In general a bidirectional ux density change type of converter uses the magnetic material more eectively than a unidirectional ux density converter. Remark 3.16 One can see from (3.39) that the maximum excursion of the ux in the forward converter is limited by the remnant ux in the core. Therefore one way to utilise the magnetics better in these types of converters is to reduce the remanence. This can be achieved by putting an air gap in the core. This to a large degree linearises the core operation, and also dramatically lowers the remnant ux density. This eect is shown diagrammatically by the dashed BH characteristic in Figure 3.14.

3-22

Switch Mode Power Supplies Under the condition of identical duty cycle, identical turns in the primary winding and identical core area (i.e. the magnetising inductance of both cores is the same), then ux in the cores is: Forward converter: Bmax = Bave + Bmax + Br Bave = Bmax (2Bmax )Ts 2Ts = 2Bmax + Br (3.44) (3.45) (3.46)

For the push-pull converter, assuming appropriate control (i.e. current control), then: Bave = 0 Bmax = 0 + Bmax = Bmax (3.47) (3.48)

Therefore the push-pull converter has less than half the peak ux density in the core. This would means that the core losses in this converter would be lower than those of the forward converter (see below on core losses). The other issue that can limit the utilisation of magnetic cores in switching power supplies are core losses. The general expression for the core loss per unit volume or weight is of the form:
a Core Loss density = kfs [(B)max ] b

(3.49)

where the k, a, and b are determined from the particular material. One can see from this expression that the core losses are a complex function of frequency of switching and the maximum ux density excursion. If, for example, the switching frequency is increased, then the maximum ux density becomes less, with everything else the same. Therefore, depending on the specic values of a and b, the overall losses will be smaller. Also the total core volume will be smaller, since the maximum ux density is less. On the other hand, the switching losses in the active devices will increase with increased frequency. One can see that the optimisation of the core losses must be carried out for each specic device.

3.3

Introduction to Control Techniques for Switching Power Supplies

Now that we have looked in detail at several idealised converter topologies suitable for switching power supplies, we shall now look at overall topological and control issues. Due to the varying background of the students doing this subject we shall not delve deeply into the control issues, but instead, an overview of the concepts involved will be presented. There are many references on issues related to the control of switching supplies, both in books and in several of the IEEE Transactions, namely Power Electronics, Industrial Electronics, and Industry Applications. Some of the books on these issues are [2, 5, 4]. Before looking at the control issues, we shall consider some broader topological and practical issues of switching supplies. Consider Figure 3.16 which is a block diagram of a typical switching power supply (from [2]).

3.3 Introduction to Control Techniques for Switching Power Supplies

Isolation barrier DC-DC power convertion Rectifier and filter EMI filter DC HF Power Transformer Rectifier and filter
Vo

3-23

Mains Supply AC

Switches

HF Signal Transformer Base and gate drive circuitry Small Mains Transformer PWM Controller DC Error Amplifier

Rectifier and filter Feedback circuitry

Vo -ref

Figure 3.16: Block diagram of a typical switch mode power supply.

As can be seen from Figure 3.16 we have looked at the detail of the dc-dc conversion section of the power supply in the rst part of this chapter. The lower half of the diagram is related to sensing of the feedback signals and the control circuitry. The important point to note here is that the feedback signals have to be isolated from the input if we are to have an isolated power supply. This complicates the design of the supply considerably. The circuit of Figure 3.16 is a conceptual diagram of one way of designing the isolated feedback. In this conguration the control circuitry and PWM generation is on the output side of the isolation. The other alternative is to have this circuity on the supply side of the isolation, and only the output voltage is feedback in an isolated fashion. The relative merits of the control circuitry on the supply side and the output side are not clear cut. Having the control circuitry on the output side (as in Figure 3.16) has the advantage that one is transmitting pulsed signals (basically ring pulses) across the isolation. This would also allow one to use an optocoupler instead of a signal transformer. On the negative side the base drive circuitry is a little more complicated. If the PWM and control circuitry is on the supply side then the base drive circuitry is usually a little simpler compared to the output side circuitry. On the negative side, getting the output voltage and/or current in an isolated fashion can be dicult. One technique is to use a voltage-to-frequency converter on the output side, and a frequency-to-voltage converter on the supply side. Some power supplies attempt to use opto-couplers in a linear mode of operation. However, opto-couplers are an inherently non-linear device, and this is dicult to do. To complicate the issue even further they are subject to temperature

feedback isolation

3-24 variations.

Switch Mode Power Supplies

One rather nice and simple technique of getting isolated feedback variables with the control on the supply side is the circuit shown in Figure 3.17 which was proposed in [5]. This circuit uses a small forward converter to transfer the analogue voltage value of the output voltage across the isolation barrier. The BJT is connected to the output of the main power converter, and is turned o and on by the pulsating voltage here. This then operates a low power forward converter that transfers the main converter output voltage via the transformer to main converter primary reference. The small transformer would have a turns ratio so that the output voltage is higher than the main converter output voltage. By doing this any voltage drop across the rectifying Schottky diode is insignicant. One crucial aspect of the performance of this circuit is that the duty cycle of the main converter (which is used to control the small feedback forward converter) does not aect the output voltage. This is achieved because the output circuit is a peak detector, and the precise duty cycle does not aect the peak detected. The peak is related to the output voltage of the main converter. The forward feedback converter output voltage is then resistive divided to give a voltage that is appropriate for the error amplier. It is claimed that this circuit is capable of giving an accuracy of 2% and has a bandwidth that is controlled by the RC time constant of the capacitor/resistive divider network at the output of the feedback circuit.

Isolation barrier

Main converter output

Vo

R1

v feedback

R2

S Feedback circuitry Forward converter

Figure 3.17: Feedback circuit using a small forward converter.

3.3 Introduction to Control Techniques for Switching Power Supplies

3-25

3.3.1

Start-Up

Another interesting practical aspect of a SMPS is how to start it up. The dilemma takes the form of a chicken or egg argument one needs power to start the switching, and one needs switching to get power. The solution to this problem could take the form of that shown in Figure 3.16, where we have a separate power transformer for the control logic. Power is therefore immediately available for the PWM and feedback circuitry when the main power is applied. However, in many situations this would be considered to be an expensive solution. Another much lower cost solution is to use a control logic power winding, a resistor and a capacitor [5]. This is suitable for converters where the control logic is referenced to the primary. A circuit for this is shown in Figure 3.18. Initially the transformer section of the circuit is inoperative. When power is applied to the power supply the unregulated DC supply comes on-line. Consequently the electrolytic capacitor in Figure 3.18 will charge up. The zener diode is to limit the voltage to a value safe for the PWM generator IC. The PWM generator now has enough voltage to operate. Unfortunately many PWM generator ICs only have a small hysteresis band of operation around the nominal voltage of operation. For example, the UC3825 PWM generator IC by Unitrode Semiconductor Products (now owned by Texas Instruments ) operates with voltages from 9 Volts to a maximum of 30 Volts. There is a 400mV hysteresis around the 9 Volt minimum voltage. Therefore, once the circuit starts operating (at 9 Volts) then it will continue to operate until the voltage falls to (9 - 0.4) Volts. This implies that the capacitor voltage in Figure 3.18 cannot fall by the 0.4 Volt hysteresis value during the time that the main power circuit starts to supply power to the PWM generator. If the voltage does fall by this amount then the PWM generator will stop working, and the resistive charging process will cause the cycle to repeat. The circuit will therefore operate in a type of limit cycle. In order to make the onset of limit cycle behaviour less likely during startup of the power supply, one needs to create a larger hysteresis in the operating supply of the PWM IC. The PWM IC is designed limited to a certain hysteresis, so the increased range must be obtained by circuitry external to the chip. Figure 3.19 shows one way of achieving this [5]. This circuit eectively allows the capacitor to charge up to a higher voltage before the PWM IC is allowed to operate. The capacitor charges up as described for Figure 3.18. When the voltage on the capacitor reaches a value equal to the value of the breakdown voltage of zener Z2 plus the threshold voltage of the MOSFET, then the MOSFET will turn on. This then allows the PNP transistor to turn on and voltage is applied to the PWM IC, which begins to operate. The resistor RG feeds back voltage to the gate of the MOSFET so that it will remain on, even if the voltage across zener Z2 drops below its threshold voltage. The feedback will remain active while the voltage on the gate of the MOSFET remains above the threshold voltage. As a specic example of the operation of this circuit, consider zener Z2 to be 12 Volt and the gate threshold of the MOSFET to be 2 Volt. Therefore when the voltage on the capacitor reaches approximately 14 Volt, zener both Z2 and the MOSFET will be on. Consequently the PNP will turn on, and the 14 Volt on the capacitor will appear on the Vcc pin of the PWM IC. The capacitor

improved power start-up circuit

3-26

Switch Mode Power Supplies

Initial charging resistor

Unregulated DC supply

Vcc

PWM Generator Chip

Power winding when running

Figure 3.18: Example of a simple bootstrap power circuit for a PWM generator chip.

3.3 Introduction to Control Techniques for Switching Power Supplies

Unregulated DC supply Hysteresis circuit

3-27

Initial charging resistor

Vcc

Z1

Z2

RB

RG

PWM Generator Chip

Power winding when running

RG

Figure 3.19: Bootstrap circuitry modied for increased hysteresis range. will then begin to discharge. The PWM IC will continue to operate until the capacitor voltage falls below its minimum operating voltage, which in the case of a UC3825 is 9 Volt. Therefore, the circuit has created a voltage hysteresis for 14 9 = 5 Volt. Remark 3.17 The increased hysteresis created by the circuit shown on Figure 3.19 means that the capacitor can be a smaller size and still be able to keep the PWM IC running long enough to allow the auxiliary winding to start to supply the power to the PWM IC. Remark 3.18 The charging resistor shown in Figures 3.18 and 3.19 is constantly connected on the circuit. Therefore, even when the switch mode supply is running, it will still dissipate power. However, this resistor can be made quite large so that the power dissipated can be made small the charging time of the capacitor is not that important (within reason). The resistor is no longer really supplying the current in the turn on phase, as it was with the previous circuit. Alternatively one can use auxiliary circuitry to switch the resistor out, thereby allowing a smaller resistor to be used.

3.3.2
3.3.2.1

Protection Issues
Soft Start

Soft starting refers to generating voltage output very slowly when power is rst applied. This is required because when power is rst applied the control

3-28

Switch Mode Power Supplies circuitry will apply the maximum duty cycle to the power stage. This can result in excessive current ow in the components which can be potentially destructive. In order to prevent this a special mode of operation is required so that the duty cycle ramps up from a very small value to the value required by the control circuitry. Soft starting is also used to recover a SMPS from fault conditions. Soft starting is handled internally in most PWM ICs, therefore it does not require any specic action by a designer. 3.3.2.2 Voltage Protection

Most SMPS integrated control circuits have a pin which can be connected to an external circuit. This circuit will generate a voltage into the pin of the IC when the input voltage rises above a certain value. Most ICs also contain circuitry that detects under voltage conditions. Internally the shutdown circuitry usually stops the internal latch from functioning and sets the outputs into a non-driving state. A block diagram of the Unitrode 1825 switch mode PWM generator chip is shown in Figure 3.20. Notice that the Output Inhibit is activated for low voltage to the chip itself, as well as from the Ilim/SD input (i.e. pin 9). The later is activated by external circuitry to detect over voltage/under voltage to the power circuit.
BLOCK DIAGRAM

U DG-92030-2

3/97

Figure 3.20: Block diagram of the Unitrode

high speed PWM generator.

3.3.2.3

Current Limiting

Current limiting is included in most PWM control ICs to protect the power supply under short circuit conditions. There are two types of current limiting: Constant current limiting.

3.3 Introduction to Control Techniques for Switching Power Supplies Fold-back current limiting. Constant current limiting, as the name implies, is a form of current limit where the current can only go to a particular value and then it will not increase any more, regardless of the load. Therefore, even under short circuit conditions the current will not increase appreciably above this limit value. This concept is shown in a V0 I0 diagram in Figure 3.21. One point to note about this diagram is that the voltage at the output of the converter can be appreciable under this condition, depending on the impedance of the load. Remark 3.19 The constant current limit may not be satisfactory in many applications, since the limit current may, over time, result in the thermal rating of the inductor or transformer windings being exceeded. Therefore, if such a limit is to be used, then one must ensure that the windings and power devices can support the limit current indenitely. constant limit

3-29

current

Vo

Load lines
Vo, rated

RL = R1

Vo1 Vo2 RL = R2

I o, rated

I limit

Io

Figure 3.21: Operation of a constant current limit.

A slightly dierent limit is the fold-back current limit. This limit is motivated by the desire of reducing the currents owing in abnormal short circuit or near short circuit conditions. The operation of this current limit philosophy is shown in Figure 3.22. In this case when the current reaches a limit value of Io, limit then the current limit drops with the output voltage. Therefore under short circuit conditions the current is reduced to a much lower value than in the previous case. The power that is being supplied to the external circuit under this condition is not nearly as high as in the constant current limit situation. Remark 3.20 The fold-back current limit does not solve the overheating problem mentioned in the previous remark. If the circuit is operating at Io, limit then the problem is the same as in the constant current limit case.

fold-back limit

current

3-30

Switch Mode Power Supplies

Vo

Load lines
Vo, rated

RL = R1 RL = R2 Vo1 Vo2
I o, foldback I o,rated I o,limit

Io

Figure 3.22: Operation of a fold-back current limit. Most PWM ICs implement a two stage current limit. The current through the switch is fed through a sense resistor, and the fed into the current limit pin of the PWM IC. If the voltage on this pin reaches a certain value the switch turn on pulse is turned o until the next control cycle. Therefore the current limiting is carried out on a switching interval basis. If the voltage goes higher and reaches a second limit, then the controller stops switching and restarts in soft start mode. The power supply can then oscillate in this mode until the short or the fault is rectied. Current limiting is actually a little more complicated than has been made out so far. Consider the situation when one has a converter with a transformer and multiple output windings. If the current sensing is set up on the primary, then the current limit has to be set for the current pulled under full load from all the windings. However, if all the secondaries, except one, are unloaded, then if there is a short on this winding the full current of the inverter can go through this winding before there is a trip. This situation could result in the destruction of this winding, or destruction of the rectier components on this winding. There is no easy way out of this problem. Probably the most economical solution is to sense the current limit of each winding individually, and then take the output of these limit circuits and OR them together. This forms the trip signal to the PWM chip.

3.3.3
3.3.3.1

Control Architecture of a Switch Mode Power Supply System

Voltage Mode Control

Figure 3.23 shows a conceptual diagram of a SMPS system from a control perspective (as opposed to an implementation perspective). The compensating

3.3 Introduction to Control Techniques for Switching Power Supplies amplier is shown with generic feedback components Z1 and Z2 . These components can contain reactive circuit elements, which allow a variety of dierent transfer functions to be set up in the feedback loop.
Compensating amplifier
Zf

3-31

Vd

Zi

vc

PWM Controller

Power stage and output filter

vo

Vo,ref

Figure 3.23: Conceptual diagram of a control system for a switch mode power supply. In general the main objective of the control system of Figure 3.23 is to control the output voltage to be a specic value under varying load conditions. In order to design the feedback compensation, one needs to obtain a model of the system suitable for control analysis. This is achieved by using an approach called state space averaging. This allows one to obtain a state space model of the system, accounting for the switching in the circuit in an average sense [2]. We shall not look at the detail of the process. The net result of this modeling process is that one can obtain a small signal linearised model of the converter and its control of the form shown in Figure 3.24. This gure shows each of the converter components as a transfer function. In this form one can apply standard classical control system design techniques to the system. Whilst switching power supplies seem to be very simple circuits, their operation from a control viewpoint is more complex than one might initially expect. Consider, for example, the yback and boost converter. Because these two converters store energy in the magnetic eld of an inductor before transferring it to the load they exhibit an eect caused by having a right half plane zero in their transfer function. Such systems are known as non-minimum phase systems. For the non-control literate reader, a right half plane pole corresponds to a response that tends to go in the wrong direction to correct a disturbance. Consider the following example of a right half plane zero eect. If we have a yback converter, and there is a sudden decrease in the output voltage due to an increased output load on the converter. The natural reaction of the control system is to increase the duty cycle, D, so that more energy is transferred to the load to restore the voltage. However, due to the above-mentioned energy storage operation principle of this converter, the initial increase in the duty cycle can result in a further decrease in the output voltage. This is due to the

non-minimum phase

3-32

Switch Mode Power Supplies

~ v (s ) T1 (s ) ? ~o vc (s ) ~ d (s ) Tm (s ) ? ~ vc (s )
~ vo,ref (s )+
~ v err (s ) Compensating
error amplifier

~ vo (s ) Tp (s ) ? ~ d (s )
~ d (s )

~ v c (s )

PWM controller

Power stage and output filter

~ vo (s )

Figure 3.24: Linearised model of a switch mode power supply. fact that increasing D instantaneously delays the next delivery of energy from the magnetic eld to the load, as compared to what would have happened if there had been no change in D. One can see that if the feedback is very high bandwidth then this will result in a further increase in D, and the process will repeat. We eectively have positive feedback. Of course the process will stop when we get to the limit of the duty cycle (this is a non-linear eect that is not accounted for in our linear explanation). The presence of a right half plane zero in these converters limits the control bandwidth of these types of converters. Figure 3.23 shows a basic diagram for a switch mode control system. Many real systems actually use a hierarchical control system consisting of two nested control loops. The inner most of the control loops is a current control loop, and the outer control loop is the traditional voltage control loop. The advantages of using the current control loop will be discussed in detail in a following section. Suce to say that the disturbance rejection properties of the controller are improved using this structure. A block diagram of this hierarchical control system appears in Figure 3.25. Notice that the voltage vc appears as a current reference to the section of the circuit that controls the current.
Switching signal
H (s ) G(s )

vo,ref

S
vo

vo,err

Voltage loop feedback compensator

vc

Comparator and latch

iL

Power stages and output filters

vo

iL

Figure 3.25: Block diagram of a nested loop control system for a switch mode power supply.

3.3 Introduction to Control Techniques for Switching Power Supplies 3.3.3.2 Voltage Feed-forward PWM Control

3-33

All of the diagrams for control of the SMPSs thus-far have relied totally on feedback control. However, in the case of input voltage uctuations one can feedforward the change of input voltage to the controller so that it can be accounted for before it would aect the output. This is usually achieve in practice by feeding the input voltage into the PWM IC. This chip usually accounts for the supply variation by altering the amplitude of the triangular waveform that is used internally to generate the PWM. One can see from (2.7) that if vst is increased (corresponding to an increase in the peak of the triangular waveform) then the duty cycle decreases. Therefore if this value is controlled by the input voltage then it is possible to get near perfect input disturbance rejection. 3.3.3.3 Current Mode Control

input disturbance rejection

Current mode control is a term used in the SMPSs literature to refer to a nested loop control system, such as that depicted in Figure 3.25, where the inner loop controls the inductor current, and the outer loop controls the output capacitor voltage. There are a number of very good reasons for complicating the control structure of the addition of the current control loop: Switch current limiting. It was mentioned in Section 3.2.1.1.2 that one of the problems with the push-pull converter was that small dierences in the switching times of the switching devices could cause eventual saturation of the transformer. Employing current mode control the peak switching currents in the two switches of such converters can be balanced so that this phenomena does not occur. Note that the current mode control in this situation would be from each of the two switches. Simplied converter dynamics. Current control eectively removes the pole introduced by the output inductor. This simplies the dynamics of the converter system, eectively allowing the bandwidth of the control loop to be increased (because of the increased gain and phase margin achieved). This is especially useful in converters that have a right half plane zero in their response. Simplied paralleling of converters. The presence of the current control loop allows the possibility of paralleling of several SMPSs, with each power supply contributing the same amount of current to the load. This is achieved by feeding each of the supplies with the same control voltage. Automatic voltage feed-forward. The desirable properties of voltage feedforward are implicitly achieved when current mode control. If the input voltage increases, the current will reach the current limit sooner. Therefore the duty cycle will decrease with out the delay of waiting for the voltage to vary at the output. In a current mode controlled SMPS, as depicted in Figure 3.25, the control voltage vc , which is derived from the error between the desired output voltage and the actual output voltage, represents a desired inductor output current, or a switch current. This is achieved in a number of dierent ways [2]:

3-34 a. Tolerance band control. b. Constant o time control.

Switch Mode Power Supplies

c. Constant frequency control with turn-on at clock time. tolerance band control Let us look at how each of these schemes works in a little more detail. In tolerance band control the inductor current is kept within a band, and the control voltage is eectively controlling the average value of the current. The width of the band is a design parameter, and by choosing it the designer is also inuencing the switching frequency of the converter (which is also related to other parameters of the converter). Tolerance band control is essentially a classical hysteresis or bang bang type of control strategy. The operation of tolerance band control is depicted in Figure 3.26. The iL value is one of the design parameters for the controller. If iL is very small then, for the same converter parameters, the frequency of switching will be much larger. The other important point to note is that the switching frequency is related to the voltage appearing across the inductor (which changes the slope of the currents). Therefore if the input voltage increases, then so will the switching frequency. This is not a desirable property it makes the losses of the switch dicult to predict.

iL

vc

Di L / 2

Di L / 2

IL

t
t on

Switch turns on

t off

Switch Switch turns turns off on

Figure 3.26: Waveforms for tolerance band current control. Another problem with the tolerance band controller is that it only really works properly in continuous mode operation. If the current becomes discontinuous, then the desired average inductor current can become negative. If the current is discontinuous then the lower switch on limit would have to be zero the circuit has to be designed to handle this. If the controller is not specially designed, the controller will respond to driving the inductor current to zero, and it will then stay there. There is also a problem of very high switching frequencies at low current values, this corresponding to a very small hysteresis band.

3.3 Introduction to Control Techniques for Switching Power Supplies Constant o time control controls the peak current in the inductor. In this strategy the control voltage species the maximum or peak current. When this peak current is reached the switch is opened for a xed period of time. It is then closed again and the process repeats. This situation is depicted in Figure 3.27. This control strategy also suers from the problem that the switching frequency is dependent on the input voltage and the converter parameters.

3-35

constant o time control

vc

iL

I$L

t
t on t on
t off Switch turns off Switch turns on t off

Switch turns on

Constant t off

Figure 3.27: Waveforms for constant o time control. The constant-frequency with turn-on at clock time control is the control strategy most commonly used. This is due to the fact that the switching frequency is user denable in the strategy. One is eectively trading o the ripple control achievable with tolerance band control for the constant switching frequency. This allows one to control more accurately the losses in the switching devices, and makes the design of the output lter much simpler. Figure 3.28 shows the waveforms that occur with this control. The switch is closed at a time determined by a clock signal. The switch remains on until the current limit is reached, and then it turns o until the beginning of the next control period. The process then repeats. The fact that the switch only turns on at the beginning of a clock pulse means that the frequency is xed by the clock period (which of course is user denable). There is a problem with straight current mode control that we have not mentioned in the discussion thus-far. If the converter duty cycle exceeds 50% the converter output will possibly oscillate at a subharmonic of the switching frequency specically at half the switching frequency. This occurs because the current control loop works by turning o a switch when the current reaches constant frequency with turn-on clock time control

subharmonics

3-36

Switch Mode Power Supplies

vc

iL

I$L

t
t on
t off

t on
t off

Ts

Ts

Clock

Clock

Clock

Constant period between clock pulses

Figure 3.28: Waveforms for constant frequency with turn-on at clock time control.

3.3 Introduction to Control Techniques for Switching Power Supplies a particular value. It is possible if the duty cycle is larger than 50% that the current will not return to the value at the beginning of the control interval. Therefore in the next control interval the current will reach the desired value sooner (since it is starting o with an oset). Therefore the switch will turn o sooner than it otherwise would, and consequently the o time will be longer. Therefore at the end of this interval the current may be lower than the desired value. This would result in the control deciding to turn the switch on longer, since we are now starting from a negative oset compared with the correct value if this phenomena were not occurring. One can see that the period of the oscillation caused by this jitter in the duty cycle results in a frequency that is half the switching frequency. In addition to the subharmonic oscillation problem, one also has a form of open loop instability with current mode control [6]. The following discussion is with reference to Figures 3.29(a), (b) and (c). Consider Figure 3.29(a) shows the eect of a perturbation of the inductor current (dashed line) away from the nominal current (the solid line). Notice that the perturbation dies away in this case. The eective duty cycle changes due to the way that current mode control works. Figure 3.29(b) shows a similar situation, but in this case the duty cycle is larger than 0.5. One can see that instead of the error between the nominal inductor current and the perturbed version getting less, it actually increases with each successive control interval. Therefore, there is eectively positive feedback in this case.

3-37

open loop instability

3.3.3.3.1 Slope Compensation Many of the problems with current mode control can be overcome by using the technique called slope compensation. This technique involves adding a sawtooth waveform to the current feedback waveform, or alternatively subtracting a sawtooth from the voltage error signal fed to the current mode controller comparator. Figure 3.29 shows the eect of slope compensation. In this case the sawtooth waveform is subtracted from the error voltage, Ve coming from the voltage error amplier. This eectively forms a new reference for the current control section of the loop. In this case, even though the duty cycle is larger than 0.5 the perturbed current returns to the nominal current (as was the case for D < 0.5). The added ramp has a constant value, and therefore the sensitivity of the feedback to variations in the current measurement becomes less. To understand how this works one can look at the extreme case when the current in the load is very low and the ramp is added to the current measurement. In this situation the control voltage from the error amplier is being compared to the slope compensation voltage, and hence the circuit is essentially operating in the normal triangular wave comparison mode of voltage control. Therefore, the addition of the slope compensation brings in some features of voltage control into the current mode loop, and under the situation of low currents it eectively behaves as voltage control (and therefore would have the dynamics of voltage control). Let us consider this situation in a little more detail. One can see from Figure 3.30 that the current perturbation error at the beginning of a control interval, i0 , is related to the current perturbation error at the end of the next

3-38

Switch Mode Power Supplies

iL

Ve

m2 m1
Di 0 Di L

t D (a) Duty cycle < 0.5

Ve

m1
Di 0

m2
Di L

t D (b) Duty cycle > 0.5 Compensated voltage reference

Ve
-m

m1
Di 0

m2

t D (c) Duty cycle > 0.5, slope compensation

Figure 3.29: Open loop instability of current mode control. (a) stability with duty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stability with duty cycle > 0.5 and slope compensation.

3.3 Introduction to Control Techniques for Switching Power Supplies control interval, i1 , as follows: i1 = i0 m2 m1 (3.50)

3-39

Remark 3.21 Equation (3.50) shows that if |m2 | > |m1 | then |i1 | > |i0 | i.e. the error has increased after one control interval. This situation would continue. This situation correlates to D > 0.5, since for the circuit to be in steady state, i at the beginning of the interval, must be equal to the value at the end. This implies that |m2 | > |m1 |. Therefore the two conditions are synonymous.

m2
Di 0

m1
Di1

x=

Di 0 m1

x=

-Di1 m2

Figure 3.30: Geometrical relationship of the current waveform slopes when there is a current perturbation. As mentioned above the compensation can be carried out by adding the slope compensation waveform to the current, or subtracting from the voltage. The techniques can be shown to be equivalent. Therefore, assuming that we are adding to the current we can modify (3.50) by adding the slope compensation to give: m2 + m i1 = i0 (3.51) m1 + m If the duty cycle is near 100% then the slope m1 0. Furthermore, we wish that i1 < i0 for the error to be decreasing over successive control intervals. Using these facts we can write the following: i0 m2 + m m1 + m m2 + m m1 + m < i0 <1 (3.52) (3.53) (3.54)

1 implying m > m2 2

3-40

Switch Mode Power Supplies Remark 3.22 Equation 3.54 shows that the slope of the ramp that must be added to the current or subtracted from the voltage error must be greater than half the magnitude of the down slope of the inductor current. If one considers (3.51), and consider it to be a discrete iterative expression, then the inductor current behaves as though it is an underdamped RLC circuit. This is shown in Figure 3.31. This RLC response can be damped out (akin to critical damping) by choosing m = m2 . The eect of this is shown graphically in Figure 3.32.

Din = -Di(n -1)

Fm GH m

2 1

I +m J K
+m

1 T

2T

3T

4T

5T

Figure 3.31: Inductor current response of current mode converter.

Ve

-m = m 2

Dio

m2 m1

Figure 3.32: Optimal slope compensation to eliminate RLC type oscillations.

Chapter 4

Introduction to Practical Design of Switch Mode Power Supplies

4.1 Introduction

In this chapter we shall briey look at the most important aspects of the physical component design of a switch mode power supply (SMPS). The approach taken is a very practical one, with some theory where appropriate. The design of a switch mode power supply, like most electronics design, is complicated because of the large number of design trade-os that are available. This fact means that this presentation is far from exhaustive, nevertheless the salient issues in making design choices will be emphasised. The design of SMPSs is complicated even further by the fact that virtually all SMPSs use magnetics in their design. Consequently much of this chapter will be concerned with the design of these magnetics. The rst section of this chapter will consider issues related to the selection of the electronic components of a SMPS. The second section of the chapter will look in some detail at the design of SMPS magnetics. Much of the material in this chapter is closely based on [5].

4.2

Component Selection

The information on the selection of components for SMPSs is usually material that ends up in vendors application notes (if one is lucky), or in the mind of a designer. This information therefore is often very inaccessible to a new designer, and is often attained by many disappointing design exercises. In this section we shall attempt to highlight some of these hard-to-nd selection criteria for a variety of components: resistors, capacitors, Schottky diodes, rectier diodes, BJTs, MOSFETs, op amps, and comparators.

4-2

Introduction to Practical Design of Switch Mode Power Supplies

4.2.1

Resistors

The resistor is probably the most ubiquitous of all electronic components. Consequently most electronic designers dont pay a lot of attention to details other than its value and power rating. 4.2.1.1 Values

There is a practical maximum value for a resistor that is used on a PCB. This practical limit occurs for several reasons: Large resistor values are not commonly available (although they can be obtained for specialised applications). If a very large value of resistor is used, then the resistance across the PCB between the resistor legs may be comparable or less than the resistor value. Therefore the resistor is ineective. Using large resistor values makes the circuit very susceptible to electrical noise. A large value of resistance means that very small capacitively coupled currents can result in large coupled voltages. Remark 4.1 Dont use large values of resistance in your designs if at all possible. Even values of 220k can cause signicant noise pickup problems, especially in switching applications which are inherently noisy in any case. 4.2.1.2 carbon composite Resistor Types

metal lm

wire wound

Obviously choosing the correct resistor for the job is necessary in electronics design. There are several resistor choices, depending on the application. The oldest style of common resistor is the carbon composite resistor. One can usually tell these resistors by the large size for their power rating. One may still nd these resistors in a hobbyist store, but for professional circuit design they are no longer used, as there are much smaller, lower cost, and more reliable resistors available.Another interesting point about carbon resistors is that the preferred values made were far fewer than the more modern resistors (only 12 per decade). The most commonly used resistor today is the metal lm resistor. These are available in a wide range of values, and low to moderate power ratings (several watts).As noted in the previous paragraph, there are a lot more preferred values in these resistors (48 to 96 values per decade, depending on tolerance). For higher power rating applications there are several choices. The wire wound resistor is the one that most people would be familiar with (a heating radiator element is an extreme form of this type of resistor). They are generally available in power ratings from 1W to approximately 1kW (and sometimes larger values for special applications such as regeneration banks in large inverter systems). One problem with wire wound resistors is that they have high inductance, which makes a conventional wire wound resistor unsuitable for high frequency applications. Fortunately, it is possible to wind the resistor with equal turns in two dierent winding directions so that the inductance can almost be eliminated (the ux produced from each winding direction cancels). Variable

4.2 Component Selection resistance wire wound resistors are called Rheostats. These are most commonly used in laboratories for experiments, rather than in commercial products. Another common type of resistor used for current sensing applications is the current shunt. This resistor type usually has a very low, but precisely known value. One can detect the voltage across the resistor, and then use Ohms Law to deduce the current through the shunt. The shunt itself is made of metals that have a very low temperature coecient. A low cost shunt can be created using a PCB track itself. This should only be considered where cost is the primary consideration, since the accuracy of such a shunt is not very good. It should be noted that shunts provide a non-isolated measurement of current. In many applications this is all right, but in other applications where isolation is important then additional measures must be used to gain isolation of the measurement. Table 4.1 summarises these comments.

4-3

shunt

Type Carbon composite Metal lm Wire wound (inductive) and rheostat Wire wound (non-inductive) Shunt PCB track

Suggested Applications Not commonly used anymore General purpose replace carbon Used for high power load resistors Used in high frequency applications Used for measuring large currents Used for low cost measurement of currents

Table 4.1: Resistor application selection guide

4.2.1.3

Tolerance

One important attribute of a resistor is its accuracy. Many years ago the garden variety resistor had a tolerance of 5%, and the exotic resistors had a tolerance of 1%. These days the default tolerance of resistors is 1%, and at slightly higher price one can have resistors with 0.1% tolerance. 4.2.1.4 Selecting Values

In many designs the specic value of a resistor does not matter (although in some it does as well). If this is the case then only the ratio between resistors is important. Therefore, in order to minimise the number of components that need to be ordered it is better to try an choose the same values of resistor where possible. For example, if sections of the circuit rely on resistor ratios, then choose one resistor out of the two to be say, 10k. One can then choose the other to satisfy the ratio requirement. 4.2.1.5 Maximum Voltage

Voltage ratings are not a parameter that immediately comes to mind when thinking of resistors. However, in the case of surface mount resistors, the spacing between the ends of the resistor means that voltage rating must be considered. In SMPS circuits one can be dealing with voltages anywhere from 10s of volts

4-4

Introduction to Practical Design of Switch Mode Power Supplies to 100s of volts, and at the top end of this range resistor voltage rating can be important. 4.2.1.6 Temperature Coecient

Most modern metal lm resistors have a very small temperature coecient of the order of 50250ppm/ C. Wire wound resistors however, depending on the material they are made from, can exhibit substantial changes of resistance with temperature. This is especially a problem with these resistors, since by denition they will undergo large temperature changes. Shunt resistors, as mentioned in Section 4.2.1.2, are purpose designed to exhibit very low temperature coecients. They also usually have a very low value so that power dissipation is low in the resistor, and hence temperature rise is kept to a minimum. 4.2.1.7 Power Rating

half power operation

All resistors have a maximum power rating. However, a resistor should not be operated at its maximum power rating, since it is severely stressing the component. This severe stress usually results in a high failure rate of components. In order to ensure high reliability of resistors it is recommended that a resistor, at worst, is operated at half its nameplate power rating. It is probably better to be even more conservative than this and operate the resistor at approximately 1/3rd of its power rating. Practical issue 4.1 Select resistor power ratings so that they are operating at approximately 1/3rd of the device specied power rating.

pulsed power The above comments are implicitly for continuous power dissipation. However, one can modify them in relation to pulses of power, especially for wire wound resistors. Manufacturers of these resistances will sometimes give a table of pulsed powers for pulses of less than 100msec. Practical issue 4.2 Power ratings for non-wire wound resistors should be strictly adhered to. It is alright to have power pulses up to the maximum rating of the resistor for short durations (say less than 100msec) providing the repetition rate is not too high. Rheostat A Rheostat is a variable power resistor, as opposed to a Potentiometer which is a variable signal level resistor. Rheostats usually consist of a wire wound resistor that has a sliding contact. The power rating for the device is for the whole resistor. Therefore if the sliding contact is halfway along the resistor, so that only half the resistor is being used, then the power rating is half the nameplate value (so that the maximum temperature of each of the wire turns is the same as for the full resistor). One must be particularly careful with using these resistors on a voltage source, as it is easy to move the slide around so that the maximum power rating of the active section of the Rheostat will be exceeded. One can put a current meter in the circuit to make sure that the current rating of the device is not exceeded as adjustments are made, or alternatively another resistor can be put in series with the Rheostat to prevent overload.

4.2 Component Selection 4.2.1.8 Shunts

4-5

Whilst a shunt is a resistor, it is not used for the normal application of the resistor, which is to somehow limit current ow. With a shunt one wishes to impede the current ow as little as possible. A shunt is generally constructed of a near zero coecient metal such as manganin, attached to heavy duty terminal blocks made of brass. Shunts come in a variety of sizes, ranging from very low current shunts, up to shunts that can handle thousands of amps. Typically a shunt is designed to produce either 50mV or 100mV at its rated current. Shunts are generally used if one wishes to measure low frequency or DC currents. In AC applications, current transformers are often used instead since they oer isolation. Remark 4.2 It should be noted that the use of shunts in high power Power Electronic applications is not very common these days. For example, it is not common for shunts to be used to measure the currents in inverter systems. Instead Hall Eect transducers are used, since they have good frequency response and oer isolation. Consider a 100A shunt with a 100mV output. This means that the resistance of the shunt is 100mV / 100A = 1m. In addition to the resistance of the shunt there is a parasitic inductance. For a 1in shunt, this inductance is of the order of 1020nH. If we assume 20nH, then we have an AC model for the shunt as shown in Figure 4.1. Obviously the impedance of this circuit is Rshunt +jLshunt which is frequency dependent. Clearly there is a zero in the impedance frequency response, and hence above a certain frequency the voltage across the shunt will increase due to the eect of the inductance.

Rshunt

Lshunt

Figure 4.1: Equivalent circuit model of a current shunt inductance eects We found above that the value of resistance for a shunt is usually low. Therefore, even though the parasitic Lshunt is low, the frequency at which the zero occurs can also be relatively low. If we use the specic values from the previous paragraph, then we have that the zero in the impedance occurs when Lshunt /Rshunt = 1 which gives f = 1m/(2 20nH) = 8kHz. In many real applications for shunts the currents will contain frequencies above 8kHz, and hence one would be getting erroneous current readings. Remark 4.3 One way to raise the frequency at which the impedance zero occurs with the shunt is to raise the resistance of the shunt. However, in high current applications this is not feasible. An alternative strategy is to lower the inductance of the shunt by making it from stacked layers of metal, instead of a single piece. There are practical limits on how far this can be taken. A control person would immediately think of another solution to the shunt frequency response problem try and arrange a pole-zero cancellation so that

4-6

Introduction to Practical Design of Switch Mode Power Supplies innite frequency response can be obtained. The obvious way to do this is to place a capacitor in parallel with the shunt i.e. in parallel with the equivalent circuit of Figure 4.1. The impedance function with the capacitor can be easily sown to be: Rshunt + jLshunt (4.1) Zeq = (1 2 Ccomp Lshunt ) + jCcomp Rshunt where Ccomp the compensating capacitor value. If we make the assumption in (4.1) that 2 Ccomp Lshunt Zeq
L Rshunt (1 + j Rshunt ) shunt

1 then: (4.2)

1 + jCcomp Rshunt

Clearly for pole zero cancellation we require: Ccomp Rshunt = which means that: Ccomp = Lshunt 2 Rshunt (4.4) Lshunt Rshunt (4.3)

Substituting in the values for the 1m shunt one gets: Ccomp = 20nH = 20, 000F (1m)2 (4.5)

Clearly this is not a practical value of capacitance. Fortunately there is a way to achieve the same eect in the op amp amplier circuit that is required to amplify the current shunt voltage signals. The value of capacitance used in this circuit are much more reasonable values (usually in the nF range) [5]. 4.2.1.9 PCB Track Resistors

If one is looking for a budget priced version of the shunt one can use the resistance of a PCB track. This type of shunt will have poor accuracy because it relies on the accuracy of the track width and thickness, and the temperature coecient for copper is very poor (0.4%/ C). However, this type of current sense can be used for over-current protection. Practical issue 4.3 The resistance of a trace is approximately given by the formula [5]: length R = 0.5m (1 oz. copper) (4.6) width at room temperature. Two-ounce copper has half this value.

4.2.2

Capacitors

Just as there are dierent types of resistors, there are dierent types of capacitors. In any design it is usually not possible to use just one type of capacitor the correct capacitor technology must be used for the application.

4.2 Component Selection 4.2.2.1 Types of Capacitors

4-7

Capacitor types are dened by their construction technology. The main types of capacitors in common use are: Electrolytic This is one of the most common types of capacitors used for large capacitance. There are a variety of choices available, with the most common being the aluminum electrolytics. These capacitors can have very large values well into the millifarad range, and many hundreds of volts. Note that these capacitors are physically very large. There are also tantalum electrolytic capacitors, which are available in solid and wet varieties. These capacitors tend to have maximum sizes that are smaller than those attainable in the aluminum electrolytic variety, but they have better high frequency performance. A distinguishing feature of all electrolytic capacitors is that they have a polarity. Ceramic These are the at, disc like capacitors that home hobbyists would be familiar with. They are used for timing and bypass purposes. They are available in values from a few picofarads to 1F. New in this range of capacitors are the multilayer ceramic (MLC) variety, which have very low eective series resistance and larger maximum values (several hundred microfarads) as compared to the older ceramics. Plastic These capacitors can withstand very high dv/dt across them, particularly the polypropylene variety. They are used in circuits such as quasiresonant SMPSs. Another variety, Polystyrene, are more specialised, and are used where very low leakage is required, such as in sample-hold applications.

Type Aluminum Electrolytic Tantalum Electrolytic Ceramic Multilayer ceramic Plastic

Suggested Applications Used when large capacitance needed. Low frequencies. Bulky. Use for moderate capacitances. Medium frequencies. Less bulk. Timing and bypass applications. High frequency bypass, low leakage applications. Use for high dv/dt applications. Low leakage current applications.

Table 4.2: Capacitor application guide The information in the above description is summarised in the Table 4.2. 4.2.2.2 Standard Values

Capacitors do not have the same range of values as modern resistors do in fact the preferred values are basically the same as those available in the old carbon resistor ranges: 1.0, 1.2 1.5, 1.8, 2.2, 2.7, 3.3, 4.7, 5.6, 6.8, 8.2. Note that 5.6 and 8.2 are not always available. One can get away with this crudely spaced set of values because the tolerances for capacitors are generally not all that accurate anyway. Also, in many applications, it is the value of a capacitor in relation to a resistor that is the

4-8

Introduction to Practical Design of Switch Mode Power Supplies important quantity. Therefore, one can adjust the resistor to get the desired result. Practical issue 4.4 Just as large resistor values should be avoided, one should also avoid the use of capacitor values less than approximately 22pF. The reason for this is that capacitance exists between any parallel plates, and consequently parasitic capacitances on a PCB can swamp out the designed low values of capacitance. 4.2.2.3 Tolerance

The tolerances on capacitors are usually very poor typically 20%. Electrolytic capacitors can have even worse tolerances than this. The other variable to consider is the temperature range that the capacitor will operate over. The capacitance value can vary substantially with temperature, e.g. some types of capacitors can loose 80% of their capacitance at -40 C. 4.2.2.4 ESR and Power Dissipation

The equivalent series resistance (ESR) of a capacitor is a very important variable, since it determines the performance of the capacitor in many applications, and is also closely related to the power dissipation in the capacitor. Most manufacturers quote the ESR at 100 or 120Hz. The reason for this is that they imagine that the capacitor is being used in power supply smoothing applications. These values of ESR are useless in determining the ESR at say 100kHz (which is necessary in power electronics applications). Therefore, if you are using a capacitor in a power electronic application with high frequency currents, make sure that you have a relevant value of ESR. Remark 4.4 The ESR resistive can have a very important eect on the voltage ripple from a capacitor. For example, if one is pulling 1 Amp of ripple current at 100kHz from a capacitor, and the ESR is 100m, then there is 100mV of ripple introduced by the voltage drop across this internal resistance. Therefore, if one requires 50mV of ripple maximum, then one would need at least two capacitors in parallel, and we have not even taken into account the amount of capacitance required to supply the charge to the load. The situation in relation to the ESR could be even worse if the capacitor has to operate over a wide temperature range. 4.2.2.5 Aging

Aging of capacitors, especially in relation to electrolytics, can be very important. Electrolytic capacitors may have a life time gure associated with a certain temperature of operation. Values could be 1000 hours, 2000 hours, or even better 5000 hours. When a capacitor approaches its design age the capacitance decreases, and the capacitor will be out of specication. In the worst circumstances the capacitor may fail. Fortunately, for every 10 C drop in temperature, a capacitors life doubles. For example, is a capacitor is rated at 2000 hours at 85 C, then if it is operated at an average temperature of 25 C, then it will last 2000 26 = 128, 000 hours, or 16 years.

4.2 Component Selection Remark 4.5 The use of the average temperature the capacitor is subjected in the above calculation is important. 4.2.2.6 dv/dt Rating

4-9

There are two forms of dv/dt rating for capacitors depending on the application and the technology of the capacitor. Electrolytic capacitors, for example, usually have a rating on the amount of rms ripple current that they can tolerate. This rating is related to the average i2 R lose in the ESR resistor, and the thermal properties of the capacitor package. Metallised plastic capacitors used in resonant and quasi-resonant converters have a dv/dt rating. In these applications these capacitors can sometimes be subject to very rapid rates of change of voltage across them. This in turn leads to very large current ows via the expression i = C(dv/dt). These large peak currents can cause instantaneous heating in the capacitor, which can result in the destruction of the capacitor if the rating is exceeded. Remark 4.6 Depending on the application the ripple current or the dv/dt rating may be important. Ripple current tends to be the appropriate measure when the capacitor is being used in an application where the voltage across the capacitor is relatively constant. dv/dt is relevant with the voltage across the capacitor undergoes large and rapid transients. 4.2.2.7 Series Connection of Capacitors

Sometimes capacitors are series connected in order to get the required voltage rating. However, if precautions are not taken one will nd that one of the capacitors will be supporting more of the voltage than the other. This is due to the fact that the capacitance of so-called identical capacitors are not the same. Since the same current ows into each capacitor, then one will inevitably have a higher voltage than the other. The way to force better sharing of the voltage across the capacitors is to parallel resistors with the capacitors, as shown in Figure 4.2. This arrangement will keep the capacitor voltages equal at DC, but depending on the values of the resistors and capacitors, there may be some degree of imbalance in a situation where there is a large ripple.

4.2.3

Diodes

There are two main types of diodes used in SMPS circuits normal rectier diodes, and Schottky diodes. We shall see in Section 5.2.1 that there are special PN junction diodes required for very high powered applications, but we shall not be considering these here. 4.2.3.1 Schottky Diodes

Schottky diodes are constructed using a metal-semiconductor junction, as compared to a normal diode which has a semiconductor-semiconductor PN junction. The special property of the Schottky diode is that it does not have the charge storage problems that normal PN diodes have. Consequently these diodes will

4-10

Introduction to Practical Design of Switch Mode Power Supplies

Figure 4.2: Method of voltage sharing for series capacitors. turn o almost instantly when a reverse voltage is applied to them. The other advantage if the Schottky diode, as compared to the PN diode, is that the forward voltage drop is much lower approximately 0.2V for the Schottky, and 0.6V for the PN diode. There are a few caveats associated with Schottky diodes they can only operate at fairly low voltages, up to about 100V; the higher voltage Schottky diodes tend to have a forward voltage that is approaching a PN diode; the internal space charge capacitance of a high voltage Schottky diode can be high, thus resulting in reverse current when the capacitance is charging as the diode is reverse biased. 4.2.3.2 PN diodes

reverse recovery

These are the conventional diodes. They are available in many dierent types, from slow rectier diodes, to ultrafast signal diodes. The latter are more akin to the diodes used in SMPS circuits. The ultrafast refers to the reverse recovery characteristics of the diode. The fast diodes have the ability to get the stored minority charge out of the diode very rapidly when the device is reverse biased. Whilst the stored charge is disappearing the diode is able to conduct current in the reverse direction. This phenomenon is known as reverse recovery.
v + v +

i Forward current

i Reverse recovery current

Figure 4.3: Reverse recovery in a converter secondary circuit.

4.2 Component Selection

4-11

Forward current

Reverse recovery current

Figure 4.4: Reverse recovery in a boost converter circuit. Reverse recovery can have a variety of eects from poor converter eciency, to destruction of power devices. These two situations are illustrated in Figures 4.3 and 4.4. In Figure 4.3 one can see that when the voltage across the diode reverses, the diode will conduct current for a short period of time. This current could potentially be very large since the impedance opposing it would be small, and the voltage driving it large (a combination of the output lter capacitor voltage in series with the voltage appearing across the secondary of the transformer winding, which would now aid the reverse current ow). Clearly this situation is not good for converter eciency, and the rapid rate of change of the reverse owing current through the diode would result in a lot of EMI being produced. Figure 4.4 is a basic schematic of the boost converter circuit. When the MOSFET turns on energy is stored in the inductor, and the diode is reverse biased. When the MOSFET turns o the current has to continue owing, and the diode immediately becomes forward biased. The current then ows through the the load and its lters. The reverse recovery problem occurs in the next event. The MOSFET again turns on to store more energy in the inductor. However, because the inductor has been forward biased it has stored minority carriers in it. When it becomes reverse biased, these minority carriers result in the diode conducting reverse current as well as it did when forward biased. The only limitation to the current ow is the impedance of the circuit, which is very low in this case. Consequently, in some circumstances the MOSFET may receive too much current and destroy itself. Even if this does not happen there will be excessive power dissipated in the device, and large amounts of EMI generated. Practical issue 4.5 Most converters will use either ultrafast diodes, or Schot-

4-12

Introduction to Practical Design of Switch Mode Power Supplies tky diodes to prevent reverse recovery problems. Remark 4.7 Synchronous rectiers are a very low loss rectier employing a MOSFET. Even with these devices a Schottky diode is placed in parallel with the MOSFET to take the instantaneous currents that need a path when the MOSFET is not on during the forward bias period. The body of a MOSFET has a parasitic diode around the device, but this diode is very slow. A Schottky diode in parallel with the device prevents the internal diode from being used. Remark 4.8 Ultrafast diodes themselves generate a lot of EMI. This occurs because an ultrafast diode still has reverse recovery current, the ultrafast bit being that it only last for a short period of time. However, as the diode rapidly decreases the reverse current, it generates a very rapid rate of change of current, and consequent EMI.

4.2.4

The BJT

I shall not spend much time on describing the practical issues of using Bipolar Junction Transistors (BFTs), since they are not commonly used today. For small to medium power SMPSs MOSFETs have large enough current and voltage range for most applications. For very high power applications, Insulated Gate Bipolar Junction Transistors (IGBTs) are more commonly used. We shall not look at these devices here since they will be described in detail in Section 5.2.4. Power BJT transistors were the device of choice for SMPS applications some 15 to 20 years ago. They are not used today because of the diculty in using the devices. For example, power BJT transistors have a very low current gain (typically known as the of the device), especially in higher voltage applications. This means that considerable current must be supplied to the base of the device if there is a large current from the collector to emitter. This may not be a problem for small converters, but it is an issue at larger powers. The consequence of this high current is a complex and expensive base drive circuit. A second problem is the voltage drop across the device. Even when a transistor is turned hard on the collector to emitter voltage is approximately 0.2 volt. Therefore the power lost in the device is approximately ic vce . A MOSFET on the other hand would have a much lower voltage drop, and therefore much lower power loss. A nal problem with the BJT is turning the device o. As with the diode, the BJT is a minority carrier device. Therefore it also suers from charge storage problems. Consequently, when the device is turned o it will continue to conduct current from the collector to the emitter until the stored charge disappears. Special base drive circuitry must be used to get rid of the stored charge as quickly as possible.

4.2.5

The MOSFET

As mentioned in Section 4.2.4, the MOSFET is by far the most common transistor used in SMPS systems. There are two main types of MOSFETs used n-channel devices (the most common ones), and p-channel devices useful in certain situations. The n-channel device turns on when there is a positive voltage exceeding the threshold voltage, between the source and gate of the device.

4.2 Component Selection The p-channel device is the dual of this, and turns on when the gate has a voltage that is negative compared to the source. If the source of the p-channel device is connected to the positive supply rail of a system, then the device can be turned on by simply connecting the gate to ground. Remark 4.9 One could consider the p-channel MOSFET to be a device that turns on with an active low signal, whereas the n-channel device requires an active high signal. Remark 4.10 The n-channel device is more commonly used because the resistance of these devices is less for the same size die. Consequently the cost for a given current rating is less. 4.2.5.1 Bi-directional Conduction

4-13

It should be noted that MOSFETs can conduct current in both directions i.e. from drain to source, and source to drain. We have seen this fact used in synchronous rectiers in Section 2.4.9. 4.2.5.2 Power Losses

There are three sources of losses in MOSFETs used in switching applications: Conduction losses These are the losses in the MOSFET resistance when it is on. The calculation of this loss is simple P = I 2 RDSon . However, one should be aware that the MOSFET has a positive temperature coefcient, so as the device heats up its RDSon increases based on the typical expression: R(T ) = R(25 C) 1.0078e(T 25) (4.7) Therefore to calculate the power, one must rst work out an initial power using the 25 C value of RDSon , and then work out the temperature rise (using the package thermal resistance), and recalculate the power. This procedure is carried out iteratively until the power value converges to a value.1 Gate Charge Losses This is not really a loss in the MOSFET, but a lose in the gate drive circuitry driving the MOSFET. This is due to the fact that the gate of a MOSFET looks like a capacitor. Therefore in order to get the voltage of the gate to rise quickly a substantial current must momentarily ow into the gate. Many data sheets give the total charge to bring the gate voltage to a certain voltage level, Qg . If the voltage level you are using is dierent then a reasonable approximation is to multiply the Qg data value by the ratio of your voltage to the data sheet voltage. The power can then be calculated by using P = Qg V fs where fs is the switching frequency. Switching Losses This is a loss that is dissipated in the MOSFET itself. When a hard switching converter is turned o there is a period of time where the MOSFET is conducting a substantial current and is supporting a substantial voltage. During this period there is substantial power dissipation
1 Usually this calculation only requires one or two iterations. The thermal resistance is a poorly known parameter, and if convergence does not occur then one is probably dissipating too much power.

4-14

Introduction to Practical Design of Switch Mode Power Supplies in the device. Clearly the more times the device is switched per unit time, then the more average power will be dissipated in the device. In order to roughly calculate the losses due to switching one can assume that as the device turns o or on that the voltage rises or falls as a linear function of time. Whilst this is happening the current through the device is more or less constant. Therefore the expression for the power dissipation for one on-o event would be the average voltage times the current i.e. P = Ipk Vpk ts /2, where ts is the time for the on-o switching event. Therefore the total power dissipated over a one second interval (i.e. the total energy dissipated in the device per second) is the energy dissipated per switching event multiplied by the number of switching events per second i.e. P = Ipk Vpk ts fs /2 Remark 4.11 By calculating the conduction and switching losses, and using the thermal resistance of the MOSFET package one can come up with an estimate of the temperature rise of the device. This estimate is a good measure of whether the device is going to run hot or cool. 4.2.5.3 MOSFET Gate Resistors

You should always put a resistor in series with the gate of a MOSFET. This is required because the gate capacitance in series with the gate lead inductance forms a high Q series LC resonant circuit. These circuits can oscillate at frequencies in the 100s of MHz range. They result in excessive heating of the MOSFET and the emission of copious EMI radiation from the circuit. The inclusion of the gate resistor provides the necessary damping to lower the Q of the resonant circuit so that any oscillations are damped out quickly. Practical issue 4.6 If you have two MOSFETs in parallel you should put an individual resistor in series with each of the gates. If a single resistor is shared between two gates then oscillations can occur between the two MOSFET gates. 4.2.5.4 Maximum Gate Voltage

Some designers decide to make the gate-source voltage very high in order to get the gate voltage past the threshold voltage of the MOSFET in the minimum time. If the gate-source voltage exceeds approximately 20 volt, then the MOSFET is likely to be damaged. To turn a device on the most important thing is to have a very low impedance gate drive so that the current can be sourced to charge up the gate capacitance.

4.2.6

Operational Ampliers

Operational ampliers are used extensively in SMPS control systems. We have briey considered control aspects of SMPS in Section 3.3. This discussion however, did not consider some of the practical issues involved in using Op Amps. These practical issues are related to the non-ideal behaviour of Op Amps. Much of the following discussion is relevant to general usage of Op Amps, and is not particular to their use in SMPSs.

4.2 Component Selection 4.2.6.1 Osets

4-15

There are two main types of osets in Op Amps: a. Input Oset Voltage. This is eectively a voltage between the + and terminals of the Op Amp. It is a result of manufacturing dierences between the electronics of the input circuitry of the Op Amp. The oset voltage is usually a small value i.e. mV or V. b. Input Oset Current. The input impedance of a real Op Amp is not innity. Therefore current will ow into the terminals. Due to manufacturing tolerances, the current in the + and terminals can be dierent. The input oset current is very small in absolute terms usually of the order of nAmp. Considering the small values for the oset voltage and current one might be tempted to say; What is the problem?. The problem with the osets is due to the fact that an Op Amp has a very high open loop gain, which is usually greater than 106 . Therefore, if one has, say a 2mV oset voltage at the input, then the output would be 2 103 106 = 2 103 . Most Op Amps operate on a power supply of 12 to 15 volt. Therefore the oset voltage would result in the output of the Op Amp being saturated to the supply rail. The immediate retort to the above paragraph is that Op Amps are never operated in open loop, but have feedback around them that lowers the eect gain. However, even with feedback, the gain can still be quite high, resulting in signicant output oset voltage. Similar arguments can be mounted with oset current when there are resistances in series with the inputs.

LM2902 100k 9.09k 10k

Figure 4.5: Operational amplier circuit for discussion of osets. 4.2.6.1.1 Input Oset Voltage The following discussion is with reference to the circuit of Figure 4.5. This shows a typical Op Amp circuit, with the noninverting input shorted to ground. If the Op Amp was ideal then the output voltage would be zero under these conditions. However, the oset voltage for a LM2902 Op Amp is approximately 2mV. This means that there is eectively

4-16

Introduction to Practical Design of Switch Mode Power Supplies 2mV between the + and terminals. The gain of the amplier is 10 in this case, making the output with a zero input voltage equal to 2mV 10 = 0.02 volt. In many applications this may not be a problem. However, if the gain was 1000 then the output oset would be 2 volt, which is clearly unacceptable. Remark 4.12 Note that the output oset due to input oset voltage is not a direct function of the resistors used, but is related to the gain of the amplier. 4.2.6.1.2 Input Oset Current The following discussion is also with respect to Figure 4.5. In this case we shall assume that the oset voltage is zero. Because the inputs to a real Op Amp take slightly dierent currents, then the voltage at each of the input pins can be slightly dierent due to the diering voltage drops across the resistors. For example, in the case of the LM2902, the dierence between the input currents can be as much as 5nA. Therefore the voltage dierence between the two terminals can be 9.09 103 5 109 = 45V. This voltage, in turn, is amplied by the gain of the amplier to give 450V output voltage. As with the oset voltage case, in many applications this is not serious, but if the gain is high, or very high precision is required, then the eect of the input current oset may cause signicant output voltage oset. Remark 4.13 The eects of input current oset occur simultaneously with input voltage oset, therefore the output osets have to be added together. Remark 4.14 Input current oset will become more pronounced if larger resistance values are used. Remark 4.15 More expensive ampliers are laser trimmed internally in order to lower the input oset current. 4.2.6.1.3 Input Bias Current The input bias current is the current that ows into the input terminals even if there is no input oset current eect. The input bias current can cause oset problems if the resistances in the input terminal leads are mismatched. In the case of Figure 4.5 we have been careful to choose the resistors so that the eective resistance through which the bias currents ow is the same. However, if there is a mismatch in the resistance values due to resistor tolerances, or alternatively due to other external circuit considerations, then there will be dierent voltage drops across the input circuit resistors. This results in the generation of dierent voltages on the input pins to the Op Amp. As a specic example, if we assume that the resistor to ground from the non-inverting terminal is 19.09k, and the input bias current for the LM2902 is 90nA, then the dierence in the resistance seen by the two bias currents is 10k. Consequently the bias current oset voltage is V = 90nA10k = 900V. This voltage in turn is amplied by the amplier gain of 10, giving an output oset of 9mV. Remark 4.16 Clearly, one should try and get the resistance in series with the Op Amp inputs to be the same values to eliminate the eect of bias currents on the output.

4.2 Component Selection Summary 4.1 Given the above discussion, we can develop and expression for the output oset: V = [Vos + Ios R + Ib R]Acl (4.8) where Vos the input oset voltage, Ios the input oset current, Ib the input bias current, R the average value of the input resistors, R the dierence between the values of the resistors, and Acl the closed loop gain of the amplier. Remark 4.17 One can see from (4.8) that in order to minimise the output oset one must: Keep the resistor values as small as feasible to minimise the eect of the Ios current. Make sure the input resistor values are closely matched so that R 0 . Choose an amplier with a very small Vos . Note that a low Vos Op Amp often has a lower gain-bandwidth product. 4.2.6.2 Limits on Resistor Values

4-17

10MW 10kW
+

10kW

Figure 4.6: Conventional inverting Op Amp circuit with a gain of 1000. It has been previously mentioned in Section 4.2.1.1 that it is not desirable in general to choose large values of resistors. In Op Amp circuits there is often a temptation to do this when one is endeavoring to get a high gain feedback amplier. Let us consider the specic example circuit shown in Figure 4.6. This is a conventional inverting Op Amp circuit, and the resistors have been chosen so that the feedback gain of the circuit is 1000. The other requirement is that the input impedance of the circuit is 10k. Consequently the feedback resistor is 10M. This value of resistor is far too large to be practical. Besides the problem that it will pick up a lot of electrical noise, it may not even be eective since the leakage impedance across the PCB is probably lower than this value.2

4-18

Introduction to Practical Design of Switch Mode Power Supplies

R2

R4

R3 R1 vin
-

vo
+

R1

Figure 4.7: Inverting Op Amp circuit with alternative feedback network.

An alternative circuit that can be used in this situation is shown in Figure 4.7. In this case the feedback voltage is lower by the inclusion of the voltage divider network comprised of R3 and R4 . This result of this network is that the output voltage has to be higher in magnitude than it otherwise would be to get the full input current (vin /R1 ) to ow through the R2 resistor. The benet that one obtains is that there is much more freedom to choose the resistors so that one can keep reasonable values and obtain the required gain. If one calculates the gain of the Op Amp circuit of Figure 4.7 then it can be shown that it is: vo R2 R4 + R3 R4 + R2 R3 = (4.9) vin R1 R3 Let us consider the specic example of a gain of 1000. If we assume that the input resistance of the circuit has to be 10k, then this makes R1 = 10k. Let us then choose R3 = 1k, which will result in a signicant voltage division eect through the feedback network without having the other resistor values too large. We still have two other resistor values to choose R2 and R4 . Let us arbitrary choose R2 = 100k. The denominator of (4.9) now has a value of 10M, which means that the numerator must have a value of 1010 to achieve the required 1000 gain. The only unknown now is R4 . Substituting the known values into the numerator expression of (4.9), and equating to 1010 , one can calculate that R4 = 98k. Therefore, to summarise, the resistor values are: R1 = 10k, R2 = 100k, R3 = 1k, and R4 = 98k. We have achieved the required gain from the circuit without having to resort to any resistor values greater than 100k. This would reduce the noise pick of this amplier circuit considerably. Remark 4.18 A similar feedback resistor arrangement can be used for inverting ampliers. However, in this case one is not constrained by the input impedance
2 If one did not have the input impedance constraint then a smaller value for the input resistor could be chosen so that the feedback resistor would be less than or equal to 1M.

4.2 Component Selection requirement, and therefore one has more freedom to choose the resistors in the conventional non-inverting feedback amplier.

4-19

4.2.6.3

Gain-Bandwidth Product
Gain (dB)

Aol
Gain bandwidth product

Acl

log f

fol-3db

fcl-3db

funity

Figure 4.8: Gain-bandwidth product of an Op Amp. Consider Figure 4.8 which shows a typical frequency response of an amplier. The open loop gain, Aol , of the amplier is very high a gain greater than 106 is normal. However, the open loop frequency response rolls o at a very low frequency, usually 1 to 2 Hz. Since Op Amps are not designed to be used in open loop this is not a concern. Eventually the open loop gain of the amplier goes to one. The frequency at which this occurs is the gain-bandwidth product of the amplier. This gure is a constant for the amplier. Therefore, if one applies feedback around the amplier, this will lower the gain to say Acl . Therefore the roll-o frequency of the amplier will be increased. The frequency of the -3db roll-o multiplied by the gain at this point is equal to the gain-bandwidth product. Therefore Aol fol3db = Acl fcl3db = funity . The importance of the gain-bandwidth product is that it indicates whether one can simultaneously achieve the gain and bandwidth specications from an Op Amp circuit design. There are many dierent Op Amps available, with widely varying gain-bandwidth products. In SMPS applications one can nd that high gains are required to moderate bandwidths for example a gain of 300 and an bandwidth of 20kHz. In this case one would need an amplier with a gain-bandwidth product of 300 20 103 = 6MHz. Whilst this is a very modest gain-bandwidth product for a discrete Op Amp, it may actually be larger than that of an integrated Op Amp that is inside a PWM IC. The eect of exceeding the gain-bandwidth product of the amplier on the performance of the SMPS system may be poor disturbance rejection, or even worse instability (due to excessive phase shift in the feedback).

4-20

Introduction to Practical Design of Switch Mode Power Supplies 4.2.6.4 Phase Shift

Phase shift is related to the frequency response of the amplier circuit shown in Figure 4.8. It is well known from control theory that at the -3dB point of a single pole frequency response the phase shift from input to output is 45 . At approximately a decade above this the phase shift has converged to approximately 90 . In an Op Amp circuit the situation is often more complicated than this due to the eects of internal compensation within the Op Amp itself. This can result in even more phase shift due to the introduction of more poles in the higher frequency areas of the frequency response. The only way to accurately determine the phase shift characteristics of an Op Amp is to actually measure them over the frequency range of interest. It is not always true that amplier with higher gain-bandwidth product will have less phase shift. Remark 4.19 Excessive phase shift through an error amplier in a feedback loop can result in a degraded phase margin. The result on the performance is ringing when there are step changes in the system, or marginal stability. 4.2.6.5 Slew Rate Limits

Slew rate limits are a non-linear eect related to the current limitations on the output stages of an Op Amp. Any Op Amp has a maximum rate at which the output can change. This is dierent from the gain-bandwidth product where one is assuming that the high frequency signals are very small in amplitude, and therefore do not encounter slew rate limit problems. Consider the situation where an Op Amp circuit is being driven by a sine wave. The maximum rate of change of the sine wave occurs when it goes through zero. The slope of the sine wave at that point is given by its derivative, Vm cos t, evaluated when t = n, n = 0, 1, 2 . One can see that the maximum slope increases with both frequency and amplitude of the sine wave. Therefore, if the amplitude is increased at a given frequency then it may be possible to exceed the slew rate limit of the amplier. If one had an amplier of gain 10, with a 1 V p-p input sine wave input, then the output would be 10 V p-p. If the frequency of the input is 200kHz, then the maximum rate of change of the output would be 10 2 200 103 = 12.6V/sec. Many low power Op Amps cannot slew their output this fast. When the slew rate limit is hit, the output tends to increase as a straight line at the slew rate. The slew rate becomes important in high-bandwidth SMPSs. When there is a rapid transient at the output, the error amplier will see a large input. If the output slew rate of this amplier is hit, then it will eectively introduce a phase lag in the feedback. This can result in poor disturbance rejection. It could also aect phase margins.

4.2.7

Comparators

A comparator is a special type of Op Amp specialised for comparison applications. In relation to voltage and current osets the same principles apply to the comparator.

4.2 Component Selection 4.2.7.1 Hysteresis

4-21

Almost always whenever a comparator is being used it should incorporate hysteresis in the input. This is to prevent false triggering and potential oscillation of the device.

Vref
-

vin R1

vo

R2
Figure 4.9: Comparator with hysteresis. Figure 4.9 shows a comparator circuit with hysteresis established by the judicious application of positive feedback. If one carries out a little analysis on this circuit then one can see: R1 R1 v+ = vin 1 + vo (4.10) R1 + R2 R1 + R2 where v+ the voltage on the + terminal of the comparator. To understand how this works, let us consider a specic example. Assume that R1 = 1kOmega and R2 = 100k, which means that R1 /(R1 + R2 ) 0.01. Under this condition: v+ = 0.99vin + 0.01vo (4.11) If v+ < v , then vo = V , the negative supply voltage. If this is substituted into (4.11) and the expression is rearranged, then for v+ = Vref we have: Vref + 0.01V (4.12) 0.99 Therefore the input voltage, vin , has to be greater than the reference approximately by 0.01V (it is actually a little more than this). At this input the comparator would switch so that the output voltage would become +V . We can then repeat (4.12) for this case and get: vin = Vref 0.01V (4.13) 0.99 As we can see the input voltage has to be less than the reference voltage, again by approximately 0.01V for the comparator to reach the switching state. Therefore we have implemented classic hysteresis by the process, with the hysteresis band being approximately 0.01V around the nominal reference voltage. vin =

4-22

Introduction to Practical Design of Switch Mode Power Supplies 4.2.7.2 Comparator Interfacing

Comparators that have a single supply rail often dont pull the output right down to the ground rail when the output should be zero. This can have a dramatic eect if the device is driving a BJT or a logic gate. For example, some comparators are only guaranteed to have a low output of approximately 0.6-0.7 V when sinking 6mA of current. Practical issue 4.7 If the comparator output does not pull to near zero at the current level the output will be operating at, then the output voltage under the low condition must be accounted for when calculating the resistors for hysteresis.

+V

+V +

10kW

Figure 4.10: Interfacing a comparator to an NPN transistor. Figure 4.10 shows a technique for interfacing a comparator to a NPN transistor. If the comparator only pulls down to say 0.7V, then the 0.7V drop across the diode will ensure that the transistor is still o. The 10k resistor ensures that the base of the transistor is rmly connected to ground when the diode is turned o. For the comparator to turn the transistor on the output needs to be greater than 1.4V.

4.3

Introduction to Magnetics Design

The design of magnetics for a real application is a complex task. there are many application specic decisions that have to be made the core material, core style, type of conductor etc. There is usually no correct answer, since the particular solution that a designer ends up with depends on the criteria used to decide the optimal solution. The following discussion is far from an exhaustive treatise on the design of magnetic for SMPSs. The presentation closely follows that in [5], and will concentrate on some of the main practical issues. A more detailed treatment of the design on magnetics for SMPSs can be found in [4].

4.3 Introduction to Magnetics Design

4-23

4.3.1

Review of the Fundamentals

Before looking a the specics of SMPS magnetics design, it may be opportune to review the fundamental concepts and expressions that are required. 4.3.1.1 Amperes Law

The law that connects the magnetic eld intensity and mmf produced. It also connects the magnetic eld intensity and the ux produced. The normal integral equation for Amperes Law in a physics or electromagnetics text is: F = H dl (4.14)

where boldfacing means that the quantity is a vector, and F the mmf in Ampere-turns, H the magnetic eld intensity vector in Ampere-turns/metre, and dl an incremental path length vector. The direction of the H vector is the same as the direction of the ux vector in a isotropic medium. The direction of the magnetic ux density vector, B, can be determined by other techniques, but is dened for practical purposes by the right hand rule. Let us consider the application of (4.14) to a single strand of wire. We know a-priori that the F value in this case is I, the current being carried in the wire. Since the H and dl vectors are coincident around a circular path of integration (since the H vector is in the same direction as the B vector), and the total path length is 2r, then one can conclude that: H= where r I 2r (4.15)

the radius of the path of integration.

Remark 4.20 Equation (4.15) implies that the magnetic eld intensity can be dened as: mmf F NI H= = = (4.16) l l l The relationship between Amperes Law and the magnetic eld intensity is dened by the following: B = r 0 H = H (4.17) where r the relative permeability, and 0 the permeability of free space. Equation (4.17) allows Amperes Law to be recast into a ux density form: F = 1 B dl (4.18)

In certain circumstances Amperes Law can be used to evaluate the magnetic eld intensity, and under some circumstances the magnetic ux density. Fortunately, the design of transformers is one of the applications where the geometry is constrained in such a way that Amperes Law can be successfully applied in a simple fashion.

4-24

Introduction to Practical Design of Switch Mode Power Supplies 4.3.1.2 Faradays Law

Faradays Law is one of the fundamental laws of electricity. It was originally determined experimentally, and later derived from the more fundamental Maxwells equations, and subsequently from relativity theory. Every electrical engineer should know Faradays Law, but we will restate it here for completeness.

B(t)

v(t)

Area A

Figure 4.11: A loop of wire enclosing an area of time varying ux density. Figure 4.11 shows a typical situation where Faradays Law is active. Here we have a loop of wire, and orthogonal to the surface of the loop there is a time varying ux density, B(t).3 A voltage, v(t) is generated between the ends of the wire under this circumstance. Faradays Law tells us the magnitude of the voltage under this condition: v(t) = where coil. 4.3.1.3 the ux linkage, d d dB =N = NA dt dt dt the ux, and N (4.19)

the number of turns of the

Inductance

We know from Amperes Law that a wire produces magnetic eld intensity, and consequently magnetic ux density. The inductance of a coil is a number that tells us something about how well the physical conguration of the coil produces ux density. For example, if a coil has more turns on it then it would have more inductance, if a coil has a large area then its inductance is larger, and it a coil is wrapped around a high permeable core material then its inductance will be higher. In all these situations, a higher inductance indicates that the coil is better at producing ux.
3 If the magnetic ux density vector is not orthogonal to the surface area, then it is the component that is that contributes to the Faraday voltage eect.

4.3 Introduction to Magnetics Design The fundamental denition of inductance is: L= d di (4.20)

4-25

In the case of linear magnetic materials (i.e. the ux density varies linearly with the current through the coil) this expression can simply be written as: L= I (4.21)

Remark 4.21 A verbal denition of inductance is that it is the ux linkage produced though the coil per unit current owing through the coil. Remark 4.22 Equation (4.20) is evaluated around some point of operation. Strictly speaking this denition is called the incremental inductance, since it is operating point dependent (i.e. dependent on the values of and i). Equation (4.21) can be used to develop the expression for the inductance in terms of the physical parameters of a coil. From (4.21) one can write: N AB N = I I NI Since B = H = l N 2 A L= l L= where l the length of the magnetic path. (4.22)

(4.23)

Remark 4.23 One can see from (4.23) that the inductance is dened entirely in terms of the physical characteristics of the coil. Note that the inductance is related to the square of the coil turns. Remark 4.24 In the case of a high permeability material as the coil the length of the magnetic path is easy to determine in (4.23). One can develop Faradays Law in terms of inductance using the ux form of Faradays Law and (4.22). From (4.22) one can write: N AB = Li (4.24)

where the lower case i indicates that the current is changing. Substituting this into (4.19) one can easily see that: v= dLi di = L for L constant dt dt (4.25)

which is the familiar voltage relationship from circuits. Remark 4.25 Note that the L constant is not correct when the core material in a ferro-magnetic material which saturates.

4-26

Introduction to Practical Design of Switch Mode Power Supplies 4.3.1.4 A Note on Units

Unfortunately the area of magnetics is permeated with inconsistent units. This situation exists for largely historical reasons. Most of the unit confusion occurs between the mks system of units, and the cgs system. Just to make things even more confusing imperial units are also sometimes thrown in as well. Wherever possible I will use mks units in these notes. 4.3.1.5 The Three Rs

In magnetic circuits three terms beginning with the letter R are often used Reactance, Remanence and Reluctance. We shall briey review these (most electrical engineering students should already know what they are). 4.3.1.5.1 Reactance This is a quantity similar to resistance that is used when a circuit contains reactive elements such as inductors and capacitors. The reactance can be used in a generalised form of Ohms Law. For an inductor the magnitude of the reactance is Zl = 2f L where f is the frequency of the voltage across or the current through the inductor. The voltage across the inductor is related to the reactance by Vl = Zl I, where Vl and I are AC phasors. A similar situation occurs with capacitance, where the 1 magnitude of the reactance is Zc = 2f C . If both resistance and reactance are both present, the impedance magnitude is: |Z| = R2 + Z 2 (4.26) where Z is the generic impedance of the reactive element.

Bm

Br

Figure 4.12: A BH loop for a magnetic material. 4.3.1.5.2 Remanence Figure 4.12 shows a BH loop for a ferro-magnetic material. Notice that if the H is applied so that b = Bm and then driven back to zero there is some remnant ux still in the core. The level of this ux is the remanence of the core, and varies depending on the material. If the core is air, then the remanence is zero.

4.3 Introduction to Magnetics Design Remark 4.26 Remanence is important as it relates to core utilisation and losses. For example a core with high remanence used in a uni-uxed SMPS will have a lower core utilisation. If use in a ux reversing type of SMPS the hysteresis losses will be high. 4.3.1.5.3 Reluctance Reluctance is often used in circuit analogies of magnetic systems. Reluctance can be used in a way that is analogous to resistance in conventional circuit theory. Just as with resistance, the reluctance of a magnetic circuit is related to the physical attributes of the circuit. One way of developing the magnetic circuit analogy is to consider the mmf in a similar way to voltage is considered in a conventional circuit. This makes some intuitive sense because one can consider that the mmf is the driving force that produces the ux. We can substitute (4.16) into (4.17) to give: B = H = N I l (4.27)

4-27

Multiplying both sides of (4.27) by the area of the core, A, gives: = BA = AN I l (4.28)

This expression can be rearranged to make the mmf the subject of the expression: l F = NI = (4.29) A From (4.29) we can then identify the reluctance term as: R= Therefore (4.29) can be written as: F = R where the ux, , is analogous to the current in a conventional circuit. Remark 4.27 Magnetic circuit analogies are particularly useful in transformer applications because the magnetic paths are very well dened and their reluctances are known. Remark 4.28 Notice that the reluctance dened in (4.30) obeys the same intuition as resistance of wires. For example, if one doubles the cross-section of the core (i.e. doubling A) then the reluctance drops, just as resistance would if a wire diameter is doubled. Similarly, if the length of the core is increased then the reluctance increases. A similar eect also occurs with resistance. (4.31) l A (4.30)

4.3.2

The Ideal Transformer

It is beyond the scope of these notes to give a full treatise of transformers. Therefore we shall concentrate on the basic properties that are required to understand their design and operation in SMPS applications. We shall begin be considering the ideal transformer, since this is a useful concept to understand

4-28

Introduction to Practical Design of Switch Mode Power Supplies

Primary coil

Secondary coil

N1 turns

N 2 turns

Core
Figure 4.13: Circuit symbol for a transformer. the operation of transformers. In addition, ferro-magnetic cored transformers are a reasonable approximation to the ideal transformer. Figure 4.13 shows the conventional circuit symbol for an iron cored transformer. The primary winding is the winding that is being driven by the source, and the secondary winding is usually connected to a load of some description. The dots on the ends of the coils indicate the way that the wire is wound on the core. If current is injected into the lead at the dotted end of the primary winding, then the ux produced in the core will have the same direction as that produced by the secondary winding if current is injected into its dotted terminal. From a voltage viewpoint, if a positive voltage appears on the dotted terminal of one of the windings, then a positive voltage will appear on the dotted terminal of the other winding. An ideal transformer is a transformer that has a core material of innite permeability. This means that no mmf is required to set up a ux in the core, since the reluctance of the core is zero (regardless of its length or area). The innite permeability has the implications that there will be no leakage ux in the transformer i.e. all the ux produced by the primary winding will link to the secondary winding. We can calculate some of the basic properties of ideal transformers by applying Faradays Law using the properties mentioned in the previous paragraphs. Consider the voltage on the primary side of the transformer: v 1 = N1 A1 Similarly for the secondary we can write: v 2 = N2 A2 dB2 dt (4.33) dB1 dt (4.32)

Since both windings are wound on the same transformer core, then A1 = A2 . Furthermore, since there is no leakage of ux density from the primary to the

4.3 Introduction to Magnetics Design secondary (and vice-versa), then B1 = B2 . Consequently we can write: dB1 dB2 v1 v2 = = = dt dt N1 N2 (4.34)

4-29

Remark 4.29 Notice that the implication of (4.34) is that the volts/turn of the transformer are constant for both the primary and the secondary. Since the ideal transformer requires not mmf to establish ux in the core, we can write: N1 i1 + N2 i2 = 0 (4.35) which implies: i2 i1 = N2 N1 (4.36)

Remark 4.30 Equation (4.36) could also be deduced using conservation of energy together with (4.34): v1 i1 + v2 i2 = 0 (4.37) Using (4.34) one can write: v2 N1 i1 + v2 i2 = 0 N2 N1 i1 = i2 N2 i1 i2 or = N2 N1

(4.38)

Remark 4.31 The negative sign in (4.38) indicates that the secondary current direction is opposite to the primary current direction. Remark 4.32 The implications of (4.34) and (4.38) are that if the voltage is stepped up between the primary and the secondary then the current steps down (and vice-versa).

4.3.3

Real Transformers

Real transformers do not have core materials composed of innite permeability material. The relative permeability of iron based laminations is in the range of 1000-2000. Many of the power based core materials, which are widely used in SMPS applications, have permeabilities in the low hundreds range. The consequence of having nite permeability core materials is that not all the ux that is produced by one winding is linked to the other winding. Another consequence is that it takes mmf to produce ux in the core, since the core has reluctance to be overcome. Models of real transformers are often based on taking the ideal transformer and adding some extra elements around it to account for the non-ideal behaviour. Consider the ux required in the core to induce voltages in the secondary winding. If the secondary winding is open circuit, and if we apply a voltage to the primary, then the voltage across the primary is related to the rate of change of ux in the primary inductance. A small proportion of the primary ux does not link the secondary winding, and this is called the leakage

4-30

Introduction to Practical Design of Switch Mode Power Supplies ux. The inductance associated with this ux is called the leakage inductance. Most of the ux produced by the primary links to the secondary winding, and this is called the magnetising ux, and the inductance associated with it is called the magnetising inductance.

Ideal transformer Magnetising inductance

Lm

Ll

Leakage inductance

Figure 4.14: Simplied model of a real transformer. If the secondary winding has a circuit connected to it, then the voltage induced in the secondary by the magnetising ux will cause a current to ow in this circuit. Consequently there will be ux produced by the secondary winding. This ux will be in such a direction in the core that it will tend to cancel the magnetising ux. However, the ux in the primary is xed by the applied voltage and its frequency (via Faradays Law), therefore this cancellation of ux will result in more current being drawn from the primary circuit to compensate for the cancelled ux. This is eectively the load current on the secondary being reected back into the primary circuit. These arguments lead to the diagram of Figure 4.14. Notice that the magnetising inductance eectively shunts current away from the ideal transformer. Therefore the magnetising current is wasted in the sense that it does not contribute to the output current.4 Similarly, the leakage inductance will support voltage across it, and this voltage does not appear across the primary of the ideal transformer, and will therefore not be transformed to the secondary. 4.3.3.1 Core Materials

As mentioned in the previous section real core materials have nite permeability. In addition they also exhibit properties such as saturation, eddy current and hysteresis losses. These practical issues manifest themselves in dierent ways in dierent applications. Table 4.3 summarises that main types of materials available, and their relative merits and uses.
4 The magnetising current is usually large so that the magnetising current is only a few percent of the load current of the transformer.

4.3 Introduction to Magnetics Design

4-31

Material Air

Consideration Pro Air core magnetics cannot saturate. Con The relative permeability of air is one, so one cannot get large inductances. Furthermore, the leakage of an air core transformer would be very high. Usage Primarily nd application in rf circuits. Not used in SMPS applications. Pro Ferrite magnetic materials are very widely used in both electronic and SMPS applications. They have very high permeability and therefore can be used to produce large values of inductance. These materials are usually relatively low cost. A variety of dierent materials are available for dierent frequency bands (to help control the losses). Con Ferrites usually saturate hard. Poorly controlled initial permeability. Usage Ferrites are often used in power transformers and noise lters. Pro Soft saturation. Wide variety of dierent permeabilities, and there values are well controlled by the manufacturer. Con Higher losses than ferrites at a particular switching frequency.

Ferrite

Molyperm (MPP)

Powdered iron

Usage Used for inductors and noise lters at high DC currents. Pro Lower cost than MPP cores. Con Slightly harder saturation than MPP, and lower permeability generally than MPP. Usage Same applications as MPP where cost is a more important consideration than size. Pro Very high saturation ux density, allowing the production of very high inductances. Con Comparatively expensive, heavy. Saturates hard, and has high losses, especially at high frequencies. New amphorous iron overcomes some of the deciencies in relation to losses. Usage Low frequency transformers, power inductors. Table 4.3: Core materials and their uses.

Steel laminations

4-32

Introduction to Practical Design of Switch Mode Power Supplies 4.3.3.2 Saturation

Saturation is a phenomena in ferro-magnetic cores which causes the permeability of the core to change from the normal high value to a value near the permeability of air as the ux density in the core increases. Another way of stating this is that when the core saturates an increase in the current in the winding around the core results in only a very slight increase in the ux density in the core. Saturation is usually a phenomena that one is wishing to avoid, since the incremental inductance of the core decreases dramatically as the core saturates. If the core inductance is restricting current ow in the circuit, then this decrease in inductance could result in a catastrophic increase in the current. There are two types of saturation associated with cores hard saturation, and soft saturation. Hard saturation refers to a rapid saturation i.e. a small increase in the ux density results in a very rapid change in the permeability. Ferrites and steel laminations fall into this category. Soft saturation is where there is not a clearly dened saturation ux density, but instead the permeability changes gradually with increased ux density. MPP cores display this saturation characteristic. Remark 4.33 A core is said to be saturated if the current ow in the winding of the core has reduced its permeability to 20% of its permeability at very low currents. 4.3.3.3 Other Core Limitations

4.3.3.3.1 Curie Temperature This is the temperature where the core looses all its magnetic properties. When the core reaches that temperature the thermal agitation of the core domains is so severe that the domain alignment is destroyed, and hence the permeability of the material decreases. Once this starts then there is a form of positive feedback occurring, and the collapse of the eld continues. As the eld collapses the domains have less eld to keep them aligned, and therefore the thermal agitation becomes even more dominant. For many of the magnetic core materials the Curie temperature is of the order of 200 C. This temperature is so high that the wire insulation and bobbin materials would be damaged it it were reached. Some inductors may not have a bobbin, and employ special high temperature wire insulation. In this case the Curie temperature could be an important limitation. 4.3.3.3.2 Core Losses Changing ux in any ferro-magnetic material results in losses in the material. These losses are in two dierent forms Eddy current losses, and hysteresis losses. Eddy current losses are due to induced current in the core by the changing ux. These currents result in resistive losses. A general expression for Eddy current losses is [7]: pe = ke 2 B 2 W/m2 (4.39) where ke is a constant related to the particular type of material. The expression for hysteresis loss is [7]: ph = kh B n (4.40)

4.3 Introduction to Magnetics Design where kh and n are empirical constant dependent on the type of material. Typical values of n are 1.5 < n < 2.5 for conventional lamination steel materials. Remark 4.34 Notice from (4.39) that the Eddy current loss is dependent in a squared sense on the applied frequency, whereas hysteresis loss in only linearly dependent on the frequency. Therefore it is very important to have a high resistivity for the core material in high frequency applications. The bonded type core materials such as ferrite, MPP, and iron powder to designed to achieve this. Let us assume that we have a magnetic structure, such as an inductor, that is driven by a sinusoidal voltage source. It is easy to show that the maximum ux density in the magnetic structure is: B= V N A (4.41)

4-33

where V the amplitude of the sinusoidal voltage source, and its frequency. N and A are the turns of the coil and area of the core respectively. Remark 4.35 One can immediately see from (4.41) that if B is to be made smaller, then N or A must be made bigger. Consider the situation where the power loss in the core of our magnetic structure is less than the total copper losses. Based on (4.39) and (4.40) we can see that we must increase the peak ux density experienced by the core, given that the excitation frequency is xed, and the core dimensions are xed. From Remark 4.35 one can deduce that this means that the number of turns wound onto the core must be decreased. This will result in a lower inductance for the core, and hence for a xed supply voltage, a larger peak current. Therefore, even though the wire resistance would have dropped, the higher rms current into the core will result in higher copper losses.

4.3.4

Optimal Design Issues

It can be shown that minimum power loss is obtained in a combined electrical/magnetic structure if: The core losses are equal to the copper losses. The primary copper loss is equal to the secondary copper loss. Remark 4.36 The core losses equal to copper losses equality for minimum overall losses applies equally well to electrical machines as to inductors and transformers. Remark 4.37 Core losses equal to copper losses equality for minimum losses is analogous to the maximum power transfer theorem in circuit theory. You may recall that this theorem says that the load resistance should be equal to the source resistance for the maximum power to be transferred to the load from the source. Therefore, in this case one has the same losses in the source resistance and the load resistance.5
5 In the case of maximum power transfer one is trying to maximise the power. In electrical/magnetic systems the power is minimised.

4-34

Introduction to Practical Design of Switch Mode Power Supplies Assuming that one has a transformer type of structure, consider the following scenario. The power loss in the magnetics is less than that in the copper. Therefore, we wish to increase the power loss in the core and reduce the losses in the copper. The power losses in the core can be increased if the number of turns on the primary winding are decreased. This can be seen if we assume that the structure in being driven at a voltage source: v(t) = V sin t 1 v sin t dt (from Faradays Law) B(t) = NA V cos t = N A V B= N A which is the same as the expression mentioned in (4.41). Remark 4.38 Equation (4.42) shows that the peak ux density in the core is increased if the number of turns in the coil are lowered. If the number of turns in the primary coil are lowered, then the length of the copper wire is lowered, and hence the wire resistance. If the turns in the primary is lowered, then the turns of the secondary are lowered to maintain the same turns ratio. If we maintain the same amount of copper under this condition, then we can increase the diameter of the wire, this again decreasing the resistance of the primary and secondary windings. These two eects mean that the overall losses of the secondary will be reduced, since maintaining the same turns ratio meaning that the secondary current would not change.6 One can mount a similar argument if the losses in the core are larger than the copper losses. In this case the turns on the primary are increased. To help keep the primary and secondary winding losses approximately the same one should allocate similar area to the primary and secondary windings. If the secondary has more turns, it must have proportionately smaller wire. If there are multiple secondaries, allocate their winding area by output power (higher getting more winding area). If one is designing an inductor, then the magnetic losses can be traded o against the copper losses by adjusting the cross-section of the core. For example, if the magnetic losses are low, then they can be increased by decreasing the core cross-section and therefore increasing the ux density. The total losses in the core are related to the losses per unit volume, and of course the volume of the core. If the cross-sectional area is decreased then the core volume drops in proportion to the decrease. The ux density increases in proportion to the decreased area. However, the total losses will increase since the losses per unit volume are related to the peak ux density squared. Example 4.1 Assume that the core cross-section of the typical transformer core has been halved. This will mean that the volume of the core has been halved. The result of the area increase, assuming that the mmf is the same and the core is
6 Note that in this discussion we are assuming that the losses in the primary due to the magnetising current can be neglected. The losses due to this component of the current actually increase with the reduction in the number of turns of the primary.

(4.42)

4.3 Introduction to Magnetics Design not saturated, is that the peak ux density will double. The Eddy current losses per unit volume in the core are proportional to B 2 , therefore the losses per unit volume increase by 4. The total losses would therefore by 1/2 4 = 2 times those before the change in core area.

4-35

4.3.5

Design of an Inductor

In this section we shall proceed through the practical design of an inductor. The reason for this is that this is the simplest magnetic structure that is useful in a SMPS design. For example, inductors are required in the buck converter for the output lter. In the following design we shall be referring to graphs from [8, 9], which is a data manual and selection guide for products by Ferroxcube, formerly Philips. The specications for the inductor are shown in Table 4.4.

Parameter Inductance DC current Max power dissipation Operation frequency Average voltage

Specication 35H 2 Amp 300mW 250kHz 10V

Table 4.4: Inductor specications. From Table 4.4 we need to calculate a few other values that will aid in the selection of a core material. We know from the maximum power dissipation specication that: R< Pmax 300 103 = = 0.075 I2 22 (4.43)

Remark 4.39 Equation (4.43) does not account for losses in the magnetic material. Therefore this value is simply an upper bound on the winding resistance. Let us check to see if we can consider this application to be a DC inductor application. The input voltage to the buck converter is 15V and the output voltage is 5V. Using (2.3) one can deduce that the duty cycle is 33% or 1/3. The switching period, T , is 4sec. Using the circuit expression for the voltage across an inductor we can write: di = 10 4sec VL dt = L 35H
1 3

= 0.381Amp pk-to-pk

(4.44)

Remark 4.40 The di in (4.44) is relatively small compared to the DC current of 2A, therefore the inductor can be considered to be fullling the function of the DC choke. Remark 4.41 The implication of (4.44) is that the permeability of the magnetic material should be fairly low to prevent the magnetic system from saturating. The other alternative is that a high permeability core be used with an air gap.

4-36

Introduction to Practical Design of Switch Mode Power Supplies

Figure 4.15: Ferrite choice (from [9]).

Figure 4.16: Initial permeability with respect to frequency for 2P iron powder Ferroxcube material (from [8]).

Given that the inductor can be considered a DC power inductor (or a DC choke) one can consult [9] to nd out what magnetic types are suggested for this application. The relevant table from [9] is shown in Figure 4.15. This suggests that the 2P range of iron powder cores are suitable for this application, since the operating frequency is less than 500kHz. One could also choose the 3C range of cores these cores have much higher initial i compared to the 2P range. Since the inductance that we desire is not very high then we can

4.3 Introduction to Magnetics Design

4-37

Figure 4.17: Incremental permeability as a function of magnetic eld strength for 2P iron powder Ferroxcube material (from [8]).

aord to use a low permeability material. Another advantage of this is that one would not have to consider introducing a air gap to prevent core saturation. Figure 4.16 shows the initial permeability for a selection of dierent 2P iron powder materials with respect to frequency of operation. Notice that the relative permeability of the 2P90 material is approximately 90 over the frequency range of interest. Another important, and related gure, is Figure 4.17, which shows the incremental permeability of the material versus magnetic eld strength. The incremental permeability is the permeability of the material for small variations of the magnetic eld strength on a DC bias eld. This is precisely the situation that occurs in a lter inductor of the type we are designing. Given that we have decide to use a 2P type material from Ferroxcube, we rstly have to make an estimate of the number of turns required to obtain the desired inductance. An important parameter supplied by the core manufacturers is the AL value. This value is the inductance per turn for a particular core. Therefore, if we assume the initial value of permeability then we can come up with a rst estimate of the number of turns required. Another important value that we have not considered as yet is the size of the core we are to use for any given material there are a number of dierent core sizes. Factors that inuence the core size are the wire diameter and number of turns required,7 and the maximum ux density that is allowed in the core.
7 The combination of the wire size inuence the core size to the extent that the core must be big enough to physically allow the windings to t on the core.

4-38

Introduction to Practical Design of Switch Mode Power Supplies 4.3.5.1 Key Magnetic Parameters

A few notes on key parameters that appear in the data sheets and selection guides for magnetics would be opportune at this juncture. The following discussion is based on the parameters described in [8]. Note that we will not describe all the parameters in these sheets, but will concentrate on those that are most useful for the job at hand. 4.3.5.1.1 Initial Permeability This is the relative permeability at very low magnetic eld intensity. It is formally dened as: i = where H 0. 4.3.5.1.2 Eective Permeability This is the eective permeability of the material when an air gap has been introduced in the magnetic circuit. Its value is dependent on the initial permeability of the material and the eective air gap. The expression for the eective permeability is: e = where: G le the air gap length. the eective magnetic circuit length. i 1 + lieG (4.46) 1 B 0 H (4.45)

This expression is only valid for relatively small air gaps. For larger air gaps fringing eects will raise the value of e above that calculated by the above expression. 4.3.5.1.3 Amplitude Permeability This is relationship between the ux density and eld intensity at high eld strengths with the presence of a bias eld. The expression is: 1 B a = (4.47) 0 H Clearly the value of this parameter depends on the applied eld strength due to the non-linear nature of the materials. 4.3.5.1.4 Incremental Permeability This is the small signal permeability when it is superimposed on a DC biased eld. It is formally dened as: = 1 B 0 H (4.48)
HDC

4.3 Introduction to Magnetics Design 4.3.5.1.5 Eective Core Dimensions Many magnetic cores have irregular shapes. In order to allow design calculations on these structures the manufacturers supply a set of eective dimensions for the core. These eective dimensions are the dimensions of the toroidal core that will produce the same magnetic properties of the original core. The eective dimensions supplied are Ae the eective cross-sectional area, le the eective length of the core material, and Ve the eective volume of the core.8 Given the above values then the eective reluctance of the core can be written as: le (4.49) Re = Ae In many data sheets (e.g. in [8]) (4.49) is usually written as: Re = 1 l A (4.50) core factor

4-39

l where the term A is known as the core factor. Using the core factor one can calculate the inductance of the core using the following expression:9

L=

N N2 = = I Re

0 N 2
1 e l A

(4.51)

If the magnetic structure is being driven by a sinusoidal source then it is simple to show that the peak ux density in the core is: B= V N Ae (4.52)

peak ux with sinusoidal excitation

If the driving waveform is a square wave with a peak of V volts, then the peak ux density is given by: V B= (4.53) 2N Ae Similarly the peak magnetic eld intensity can be worked out using the eective length: NI H= (4.54) le Remark 4.42 The above calculations assume that Ae is uniform throughout the material. However, in many magnetic structures this is not the case. Therefore the peak ux density is calculated using the minimum cross-section area Amin . Most cores are designed so that Ae Amin so that there is no signicant increase of ux density due to the physical core design. 4.3.5.1.6 Inductance Factor The inductance factor for a core is the inductance of a single turn coil for the particular core. This is related to the
8 All 9 Note

peak ux with square wave excitation peak magnetic eld intensity

the measurements are assumed to be in MKS units. that we are using the expression N I = Re from magnetic equivalent circuits [10].

4-40

Introduction to Practical Design of Switch Mode Power Supplies magnetic properties of the core i.e. namely the permeability. The denition of the inductance factor can be simply obtained from (4.51): AL = 4 107 e 1 0 e = Henry = l l Re A A (4.55)

Usually AL is quoted in terms of nH, therefore (4.55) is written as: AL = 1256.7e

l A

nH

(4.56)

The inductance factor is obviously related to the total inductance by the expression: L = N 2 AL (4.57) which means that for a given desired inductance the number of turns can easily determined by rearranging (4.57) to give: N= 4.3.5.2 Details of Inductor Design L AL (4.58)

Figure 4.18: Core type selection table (from [8]). Now that we have reviewed some of the key parameters that are required to understand magnetics data sheets we can now return to the design of the inductor. The material was previously chosen to be Ferroxcube 2P. The next step is to choose a core type and size. We shall use a toroidal or ring core. One can see from the table in Figure 4.18 that this is a favourable choice for this application. Many manufacturers provide tables to aid in the selection of a particular core. These tables not only allow a rst guess at the core selection material,

4.3 Introduction to Magnetics Design but also suggest a specic core. This then gives one an initial core size to base a design on.10 This initial core selection for cores that have a DC current through the windings is often based on a graph that uses the energy stored in the core i.e. 1 LI 2 . The L and I terms in this expression are both related to the size of 2 the core, L via the core length and area, and the current by size of the area to put the windings in. Figure 4.19 shows the core size data and AL parameters for Ferroxcube iron powder 2P cores. Unfortunately the Ferroxcube selection guide does not have such a table for the iron powder cores. We shall select an initial core from the table in Figure 4.19 and then calculate the number of turns required. We shall use this, together with the specication on the power dissipation to work out the amount of area required in the centre of the core for the winding. Depending on the result of this we may have to select another core. One other criteria for the selection of the core that was not previously mentioned was that one would generally want the core to be as small as possible, since this usually correlates to minimum cost. Let us arbitrarily choose core TN17/9.8/4.4 2P90 from Figure 4.19. As can be seen from this gure AL = 42, therefore using (4.58) one can get: N= 35 106 = 28.9 turns 42 109 (4.59)

4-41

This has to be rounded up to an integer number of turns, so lets make it 29 turns. The next thing to consider is the amount of wire required for this. The turns have to be wound around the toroid, so that the copper passes through its centre. The size of the centre of the toroid places a limit on the number of turns for any gauge of wire used. Taking into consideration the diculties of winding the core, as well as the amount of space taken by wire insulation, the typical winding ll factor is 4550% i.e. only 4550% of the available space for the winding can practicably be used. To select the wire we need to consider the amount of current that it has to conduct, and the amount of power that will be dissipated in its resistance. The skin eect should not be that important in this case since the high frequency AC currents are relatively small compared to the DC current ow. A rst selection of the wire can be made from a wire table. We shall use the table printed in [5], which is itself a reprint of a table produced by Magnetics Inc. in their literature.11 One candidate size is AWG18 wire, which nominally has a current capacity of 2.17 Amp. The resistance of the wire per metre is 0.02096/m, and its wire area (including insulation) is 9.83 103 cm2 , or 9.83 107 m2 . Referring to Figure 4.19 we can work out the length that the wire has to go around the core (approximately) as 19.5mm or 0.0195m. However, this value doesnt take into account the ll factor which eectively extends the length of each turn. An approximate expression for the length of a turn for a toroidal core is [5]: lt = D + 2H (4.60)
10 Often this initial selection may prove to be inadequate in some detail. The designer may have to choose a larger or smaller core dependent on the nature of the inadequacy. 11 The Magnetics Inc Web site, http://www.mag-inc.com, has a free program that can be downloaded for the design of lter inductors.

4-42

Introduction to Practical Design of Switch Mode Power Supplies

Figure 4.19: Core data for toroidal cores using powdered iron (from [8]).

4.3 Introduction to Magnetics Design where D and H are as dened in Figure 4.19. Using (4.60) the length of a turn is 0.0181 + 2 0.0053 = 0.0287m. Using the number of turns calculated in (4.59) we can calculate the resistance as 290.02870.02096 = 0.01744. Therefore the power loss in the windings is approximately I 2 R = 4 0.01744 = 70mW. This is well within the specication of less than 300mW total power loss, and leaves 230mW for the core losses. The other issue to examine is whether the wire can be wound on the core i.e. will it t in the hole in the centre. The total wire area, including the insulation, is 29 9.83 107 = 2.85 105 m2 . The total area available in the centre of the core is d2 /4 = 6.65 105 m2 . A ll factor is 0.5, therefore the area available for the wire is 0.5 6.65 105 = 3.325 105 m2 . Therefore it is possible to wind the wire on the core. Remark 4.43 One must also take into account the thickness of the wire. If wire is too thick then there will be trouble bending it around the core. In addition, the act of bending it around the core may also fracture the core, since ferrite and iron powder materials are very brittle. We now need to check the core ux density. This can easily be done using (4.51) and the Ae value from Figure 4.19 to give: B= 35 106 2 LI = = 152mT N Ae 29 15.8 106 (4.61)

4-43

Remark 4.44 The maximum ux density is not related to the losses in this situation, since it is primarily a constant ux density which does not cause losses. However, there is a ripple in the voltage across the inductor, that results in a ripple in the inductor current, and consequently an AC component sitting on top of the DC ux density. It is this component of the ux that is relevant to the loss calculations. Remark 4.45 The DC ux density is important because of the eect that it has on the permeability of the material. If we consider the BH characteristic for the 2P materials (from [8]) shown in Figure 4.20 one can see that the ux density level is far below saturation. Figure 4.21 shows the losses for 2P material at various peak ux densities and frequencies. These plots are very dicult to read with any accuracy. The best approach is to form an equation for the relevant line on the graph. The equation for a line on the graph is of the form: Pv = aB x (4.62)

where a and x are unknowns to be found. Since we have two unknowns then we need two independent equations to nd them.12 Considering Figure 4.21 we can write the following two expressions by examining the 200kHz curve: 28 103 = a (4 103 )x 800 10 = a (20 10
3 3 x

(4.63) (4.64)

12 Even using this technique it is dicult to get accurate results since it is hard to read o the points to develop the simultaneous equations.

4-44

Introduction to Practical Design of Switch Mode Power Supplies

Figure 4.20: Typical BH characteristic for 2P magnetic material (from [8]).

Figure 4.21: Losses in 2P material with respect to ux density and frequency (from [8]).

4.3 Introduction to Magnetics Design Multiplying (4.63) by (800103 )/(28103 ) and equating to (4.64) we can write: 800 a (4 103 )x = a (20 103 )x 28 (4.65)

4-45

Canceling out the common expressions, and taking logarithms of both sides of this expression we can write: log(28.57) + x log(4 103 ) = x log(20 103 ) (4.66)

which can be solved to give x = 2.0829. We can then substitute this into either (4.63) or (4.64) to give a = 2.766 109 . The resultant equation can be multiplied by 250/200 = 1.25 to account for the fact that it has been derived for a frequency of 200kHz (this is a crude extrapolation). Therefore the resultant expression for the losses is: Pv = (3.4575 109 )B 2.089 W/m
3

(4.67)

at a frequency of 250kHz.13 We are now in a position to calculate the losses. However, before doing this we must calculate the AC component of the ux density in the material (as noted earlier). Recall from (4.44) that the current ripple through the inductor is 0.381 Amp. Therefore the AC magnetic eld intensity is: 29 0.381 N IAC = 274.85A/m = HAC = le 0.0402 (4.68)

Assuming that the core relative permeability stays at 90 then we can work out the peak to peak ux density as a result of the ripple current: BAC = 0 e HAC = 4 107 90 274.85 = 0.031Tesla (4.69)

We can now work out the losses by using the B value from (4.69) in (4.67) to give 3 Pv = 2.439e6W/m . For the volume of material in the core (Ve = 635109 m3 ) the loss is Pv Ve = 1.54W. This power dissipation is outside the specication for the inductor by a factor of 5 times. Therefore we must go back to the drawing board with this design.14 In order to lower the losses in the core we need to go to a larger core size. Let us try the TN24/15/7.5 core. We shall quickly go through the same design process as carried out above. In this case the AL = 61nH, and consequently: N= 35 106 = 23.95 turns 61 109 (4.70)

Therefore we will make the turns equal to 24. Given the turns we can now work out the maximum AC ux density variation as: LIAC (35 106 )(0.381) BAC = = = 0.0169 Tesla (4.71) N Ae (24)(32.8 106 )
13 This expression is only going to give a ball park gure for the losses. To get accurate values measurements must be taken. 14 The above design closely follows that in [5] which uses a similar permeability and size core. However, the resultant losses found in [5] are approximately 1/10th those found above. The Lenk analysis uses a complex mix of units, so I am assuming that there has been an error in one of the units conversions. I have been unable to nd an error in the design calculations above.

4-46

Introduction to Practical Design of Switch Mode Power Supplies Substituting this into (4.67) gives Pv = 690, 162 W/m3 . Therefore the total power dissipation is PT = Pv Ve = 690, 162 1895 109 = 1.3 Watts. This is less than in the previous case, but is still approximately 4 times the specication. One might suspect that we will have trouble satisfying the specication from the small change in the losses for the change in the core. Indeed, if one chooses the largest core in Figure 4.19, TN33/20/11, we will still have trouble satisfying the specication. If this is carried out the core losses are of the order of 0.7 Watts, which is still twice the specication. The question is now what can we do. If we are to stick with the frequency of operation we need to nd a core material with lower core losses. However, if the frequency of operation is part of the design mix then we can make this lower. This will also have the eect of increasing the ripple in the current, so the inductance value would have to be varied to allow this specication to be satised. Let us briey consider a drop in the frequency to 100kHz. If we want the same ripple of 0.38 Amp in the 2 Amp DC current then the inductance value can be found to be 87H using (4.44). The turns can now be found to be 32 turns using (4.58) and the value for AL = 87nH (for the TN33/20/11 core). Therefore BAC = 0.012 Tesla using (4.71) with the new values. Reading o the approximate value for the losses per m3 from Figure 4.21 we can see that it is approximately Pv = 70W/m3 . The core volume is 5200 109 m3 , and hence the total core losses are PT = Pv Ve = 0.364 Watts. This is still outside the original specication in relation to the losses, but it is much closer than those calculated previously. A further improvement can be made in relation to the losses by lowering the frequency further, but the number of turns required to achieve the higher inductances mean that check would have to be made to see if there is enough winding area. Remark 4.46 The fundamental problem with the above design is that the material chosen has too high a power dissipation per unit volume. The specication is much easier to satisfy if a lower loss material is chosen. For example, the 2P material we chosen has a lose of approximately 200kW/m3 at 10mT ux density. The 3C material by the same manufacturer has losses so low (of the order of 1 rightarrow 2 kW/m3 ) that the manufacturer has not plotted them below approximately 10mT. Therefore the specication would have been satised if this, or a similar low loss material had been chosen at the outset. For example, in [5] the same design is carried out using MPP material manufactured by Magnetics Inc.. This material has a loss of 18.2kW/m3 at 10mT ux density. In this design the core losses turn out to be 140mW. Remark 4.47 The frequency of operation of this inductor would mean that Litz wire should probably be used. This would change the wire area calculations above. The skin eect at 250kHz needs to be considered. In fact if the frequency is above 50kHz the skin eect must be considered. 4.3.5.3 Issues in Forward Converter Transformer Design

We shall not go through a complete design of a forward converter transformer, but instead we shall highlight a few of the major issues that need to be considered. We shall do this in the context of the paper design. The following is

4.3 Introduction to Magnetics Design based on an example in [5]. The basic design of a forward converter is shown in Figure 3.2. The input voltage to the forward converter is 48VDC, and the output voltage is 5VDC at 100 Watts. This implies that the output current is Io = 100/5 = 20 Amps. This is obviously a very high current, therefore it is important that the resistive losses are kept low for eciency reasons. This means that the number of turns on the secondary should be low, and the wire should be a thick gauge. Let us consider the issues involved in selecting the turns ratio for the transformer. 4.3.5.3.1 Turns Ratio = 1:1 This would imply that when 48VDC is applied across the primary there is 48VDC across the secondary (ignoring the leakage inductance of the transformer). The problem with this voltage is that one cannot obtain Schottky diodes above about 45 volt with a low forward voltage drop. One would require a diode with a voltage rating signicant higher than 48 volt, therefore the forward voltage drop will be high. Remark 4.48 For high current outputs forward voltage drop is important. The loss is Vf Io , and this is being dissipated in the rectier diode, or the free-wheeling diode. One can use synchronous rectiers to overcome this problem, but this requires a signicant increase in the complexity of the circuit due to their drive and control requirements. For the diode loss reason given above the choice of a 1:1 turns ratio is not a good one. 4.3.5.3.2 Turns Ratio = 2:1 The primary has twice the turns of the secondary, meaning that there is 24VDC on the secondary. This means that the duty cycle of the converter is approximately Vout /Vsec = 0.21. The current through the primary of the transformer (assuming that there is a constant 20 Amp current in the load) is 0.5 20 = 10 Amp. This quite a bit of current for a MOSFET switch. The losses in the MOSFET are approximately 102 RDSon 0.2. These losses may result in an expensive MOSFET, or alternatively a large heat sink. 4.3.5.3.3 Turns Ratio = 3:1 In this case the secondary voltage is 16 volt and the primary current is approximately 7 Amp. The duty cycle is 0.31. Therefore the losses are 72 RDSon 0.31, which is substantially lower than in the previous case. 4.3.5.3.4 Turns Ratio = 4:1 The secondary voltage in this case is 48V DC/4 = 12V DC. Therefore the duty cycle is Vout /Vsec = 5/12 = 0.42. This duty cycle is very close to the limit cycle of many of the popular PWM ICs (which are limited to duty cycles of 0.45). If there is any variation in the input voltage, and if the diode drops are accounted for, then it is possible for this limit to be hit. The conclusion of the above turns ratio scenarios is that a turns ratio of 3:1 is probably the best one to choose. The remainder of the design of the forward transformer involves the choice of the core material and the magnetising current. The magnetising current is

4-47

4-48

Introduction to Practical Design of Switch Mode Power Supplies important, since this current does not contribute to the load current, but does contribute to the losses in the converter. The magnetising inductance is also important from the point of view of losses in the core. Fortunately, lowering the magnetising current involves increasing the primary turns (whilst maintaining the 3:1 turns ratio), which in turn also lowers the ux density in the core (for a xed input voltage). There is a limit to how far this can be taken, since the more turns requires more copper in both the primary and secondary. Hence this impacts on the size of the transformer.

4.3.6

Design of Manufacturable Magnetics

Magnetic components are usually custom made in a factory, unlike most other electrical components which are mass produced in an automated fashion. This means that when we design some magnetics for a product that will be mass produced we need to take into consideration how easy it is to manufacture, and also how repeatable the specications will be in a manufacturing environment. 4.3.6.1 Wire Gauge

The general rule in relation to wire gauge is simple dont select wire that is too thick or too thin. Practical issue 4.8 It is best to limit the wire gauges to a maximum of #20 (i.e. 7.91 107 m2 ) and an minimum of approximately #38 (i.e. 0.132 107 m2 ). For wire gauges thicker than #20 some machine cannot wind the cores, and above #18 there is a risk of fracturing the core as the wire is wound around it. Wire gauges thinner that #38 can still be machine wound, but it is dicult to build prototype cores with wire this thin it is as thin as a human hair. Therefore it is best to use #38 wire even if you can get away with thinner wire. Another aspect of wire gauge to consider is that one should try and limit the number of dierent wire gauges being used. This will allow some volume-ofpurchase economies to be obtained. 4.3.6.2 Wire Gauge Ratio

If you are winding dierent wires onto a magnetic structure, and these are layered on top of each other, then try and keep the wire gauges close together. This helps prevent the thinner wire from nding its way into the crevices of the thick wire the dierent windings do not form nice layers. When this happens it can eect the leakage and coupling of the magnetic circuit. Practical issue 4.9 Try to keep the wire gauges in a magnetic structure within 10 of each other. 4.3.6.3 Toroidal Core Winding Limits

If a toroid is going to be machine wound then the only limit on the windings is the size of the winding area and the size of the wire. However, if one is to hand wind these cores there is a practical limit set on a humans ability to concentrate and count.

4.3 Introduction to Magnetics Design Practical issue 4.10 Hand winding a toroidal core is a real pain. If one is going to wind a prototype one by hand it is best the keep the number of turns below approximately 200. It is very easy to forget the number of turns on the core (even for this number). 4.3.6.4 Tape versus Wire Insulation

4-49

For safety reasons tape is often used between the primary and secondary windings of a transformer. When there are high voltage dierences between the primary and secondary a anged bobbin may be used, which divides the winding area into two pieces with a piece of plastic. In many designs there is substantial voltages between the secondaries. Therefore insulation is required between these to prevent arcing. In the case of high voltage secondaries there may need to be insulation between the layers of the same secondary winding. Practical issue 4.11 Adding tape insulation layers should be avoided if possible. The tape takes up a lot of area, and even more importantly it usually must be put on by hand. Remark 4.49 In many cases it may be better to go to thicker and higher class wire insulation instead of using tape. It is less labour intensive and can lead to a more compact design. 4.3.6.5 Layering of Windings

The windings should be wound from the left of the bobbin to the right and then back from the right to the left for each of the layers (except for a toroid). The windings should take into account where the connection pins are, and should be designed so that a winding does not terminate half way up the bobbin. If this does happen then one would have to take the end connection to the top or bottom of the bobbin to connect to the end pins. Any other layer will then have a lump in it where it goes over the top of this end connection. Practical issue 4.12 One should take into account where windings will end when selecting the wire gauge. One should ensure that the winding does not terminate in the middle of layer. The other issue in relation to the windings is the coupling. The windings should be bilar wound in order to maximise the coupling and minimise the leakage inductances if there are no safety considerations. In order to do this the wires should be twisted together. This is often carried out with multiple secondary windings to improve the cross-regulation. The primary and secondary windings should be interleaved if possible. This enhances the inter-winding coupling from primary to secondary, and also helps in relation to cross-regulation with respect to multiple secondary windings. Figure 4.22 shows the basic structure of an interleaved winding transformer that has also been designed to achieve good isolation between the primary and secondary windings.

4-50

Introduction to Practical Design of Switch Mode Power Supplies

High dielectric sleeving

Primary winding Mylar tape Secondary winding Primary winding Bobbin

Figure 4.22: Winding interleaving for high-dielectric isolation and good primary to secondary coupling. 4.3.6.6 Number of Windings

Magnetic coupling issues limit the number of windings that can be practically wound on a core. In addition the layering becomes more dicult. Finally, most winding bobbins only have 8 to 12 pins available for the end connections. Practical issue 4.13 Most magnetic designs should be limited to a maximum of four to six windings. 4.3.6.7 Potting

Potting is the process of lling up a volume surrounding a magnetic structure with a thermally conductive compound for the purpose of improving heat removal by providing a better thermal path. It also strengthens the structure, and prevents the incursion of environment factors that may aect the life of the magnetic structure. The potting can also be utilised to provide mechanical mounting points for the structure. There can be some problems with potting it makes the unit heavier, the shrinkage of the potting mix as it cures can result in changes to air gaps in gapped cores, and some magnetic materials (e.g. MPP) are strain sensitive, and their permeability can change as the potting shrinks. 4.3.6.8 Safety Requirements

If one has high voltage and low voltage windings wound on the same core then it is important from a safety perspective to ensure that the high voltages can never get to the low voltage windings. Figure 4.23 shows a transformer design which satises requirements for isolation. There is a 2mm creep distance from the end of the insulation tape to ensure that the windings can never come into contact. In addition, leads that pass through other windings must have a high voltage insulation rating. The windings are insulated from the core material. All these requirements take up space, therefore a transformer satisfying these requirements will be larger.

4.3 Introduction to Magnetics Design

4-51

Insulation layer Creepage distance (4mm)

Insulating tape

Core

High voltage sleeving

Secondary Primary
Figure 4.23: A transformer design to satisfy safety requirements.

4-52

Introduction to Practical Design of Switch Mode Power Supplies

Part II

Line Commutated Converters and High Power Inverters

Chapter 5

Introduction to High Power Converter Technology

5.1 Introduction

This part of the course is an overview of power electronics that is focused on high power applications. The previous two parts of the course were primarily concentrating on very low power digital switching, and small to medium power switching primarily related to dc-dc power supplies. The term high power is not a precise term, and the distinction between switch mode power supplies and some of the circuits in the following chapters are blurred. It will be assumed that the circuits in the following chapters are used for power levels greater than 1.5 to 2kW, with the top power levels being open ended. For example, the power electronics used in high voltage dc power transmission can be handling many hundreds and possible thousands of megawatts. The other feature that distinguishes many of the circuits in the higher power area are that they rely on natural commutation to turn o the power devices this means that they cannot be explicitly turned o using a gate signal, but rely in certain external circuit conditions to cause them to turn o. The subject material for a course on this topic is huge, and more than enough to ll an entire course in its own right. Therefore we shall be looking briey at a subset of the possible topics, concentrating on the fundamental converter types and operational principles. Specically we shall look at the power devices that are used in the high power area, since they have a large inuence on the circuits, topologies and applications. The next major part is on the line frequency uncontrolled and phase controlled rectiers and inverters. Next we look at hard switched dc-ac inverter technologies. The nal part will consider the application of these devices in electric machine drive systems. There are many references for this work, but the primary ones used for this course are [2, 3, 11, 12].

5.1.1

Applications of Power Converter Technology

Power electronics is becoming increasingly important in the modern world. The ability to control and transform power to forms suitable for particular appli-

5-2

Introduction to High Power Converter Technology cations is fundamental for the operation of any technological society. The increasing emphasis on eciency is spawning even more activity in the Power Electronics area, as new techniques are needed to minimise the production of green house gases. The developments in the power semiconductor area are allowing the application of power electronics in areas that, only a few years ago, were impossible. Examples of modern applications of power electronic converter systems are: Electric vehicle propulsion systems. These systems are one of the very high prole applications of modern power electronics. They incorporate innovative electrical machines coupled with inverter, computer and battery/generator technologies. Electronic washing machines. A current example of is the Fisher-Paykell Smartdrive washing machine, which utilises a direct drive 48 pole permanent magnet motor driven by a computer controlled inverter. The Maytag Neptune washing machine in the US uses an electronically controlled switch reluctance machine. Photovoltaic (PV) grid interfaces. In order to convert the power produced by photovoltaics into a form suitable for domestic use or to export into the grid, power electronic conversion is required. The application of clever control techniques can optimise the amount of power that can be supplied for given illumination levels. High voltage dc transmission (HVDC) systems. These systems allow large amounts of power to be transferred in undersea cables. For example, the power connection between the north and south islands of New Zealand use a HVDC link. Similarly for connections from Norway and mainland Europe. HVDC links are also used to isolated the dynamics of large power supply systems. For example a HVDC link is used for the NSW to Queensland interconnection so that there is not interaction between the two different grid systems. Frequency wild wind and hydro power applications. Conventional wind turbines rotate at a constant speed regardless of the wind speed. In order to extract maximum energy from the wind variable pitch blades are used. However, if the turbine is allowed to vary in speed (without the complex variable pitch bladed) then it is possible to extract even more energy from the wind. By interposing an inverter system between the generator and the grid supply, it is possible to do this, since the inverter converts the frequency wild input into the grid frequency output. The same issues apply to hydro turbines. Power system static VAR compensators. These are power electronic devices that are able to supply the VARs required for inductive loads on power systems. They are commonly used to improve power factor and to aid in the stability of the power system. Active lters. Modern power electronic devices on the power supply grid can generate harmonics into the grid supply. These can cause problems with other devices connected onto the grid. An active lter is another

5.2 Review of Power Semiconductor Devices power electronic device that is capable of canceling out the harmonics produced by these other devices. Flywheel and superconductor energy storage. These two storage techniques will possibly be important in future energy systems. Power Electronics plays a pivotal role in the operation of these systems, as it is required in order to get energy into and out of the energy storage system. Aerospace power systems. Power electronics, because of the weight savings, play an important role in the power systems for both aircraft (civilian and military) and space systems. These applications of power electronics tend to be the leading edge of the technology. Uninterruptible power supplies (UPS). These are power electronic systems that allow battery systems to be used as power backup for mains operated systems in critical applications. Load proportional modulated air conditioning systems. Instead of turning air conditioning compressors on and o to maintain a desired average temperature, and inverter driven compressor motor provides variable continuous output. The saving are due to the fact that the compressor output does not match the energy input for a considerable time after the compressor is rst started. Energy savings up to 30% are achievable using this technique. Electronic uorescent lamp ballast. These ballasts are based purely on a high frequency inverter of some type (no magnetic components). They oer energy savings over magnetic ballasts. Furthermore, external light compensation can also be incorporated into the design. The above examples are only a selection of the industrial and residential applications of power electronics. This technology is not always obvious to the user, but is being incorporated into a larger variety of products. Therefore an understanding of at least the basics of the technology is essential for the modern electrical engineer.

5-3

5.2

Review of Power Semiconductor Devices

At this point it is benecial to review the current state of semiconductor devices used for high power applications. This is required because the operation of many power electronic circuits is intimately tied to the behaviour of various devices.

5.2.1

Diodes

Figure 5.2 shows the basic conceptual diagram for a diode. This diagram is valid for a general purpose diode, but power diodes have a dierent structure in order to improve the voltage blocking capability of the device and at the same time keep the on-state resistance as low as possible. The iv characteristics of conventional and power diodes are much the same, and a generic diagram is shown in Figure 5.1. Note the oset voltage of approximately 1 volt. It is this voltage that leads to the majority of the power

5-4

Introduction to High Power Converter Technology dissipation. Also note the slope on the characteristic as the voltage across the device increases above 1 volt this represents the eects of the bulk resistance of the device. Whilst the 1 volt oset is virtually intrinsic in the operation of the diode, the bulk resistance contribution to the power losses can be minimised by changing the doping of the semiconductor materials. The breakdown voltage, vBD , is a very important parameter in power diodes. Much of the design of these diodes is related to improving vBD .

iD

v BD
1 V

vD

Figure 5.1: The current-voltage characteristic of a diode.

Figure 5.3 shows the conceptual structure of a power diode. Note that the main dierence between this structure and that of Figure 5.2 is that there is a n region interleaved between the normal p+ and n+ regions. This region is known as the drift region, and under reverse bias is the region where the depletion region lies. At rst the presence of the n region in the device would seem to be a little silly, since it must add to the bulk resistance of the device. Under certain circumstances this is indeed true, but by careful control of the doping proles this eect can be minimised. This region is in the device to improve the voltage blocking capability. We shall not look at the equations that prove this, but heuristically the reason is that if one supports a voltage over a longer distance, then the volts per metre must be smaller than if the voltage is supported over a shorter distance. Therefore, when the device is in reverse bias, the depletion region almost exists entirely in the n region1 , and consequently the electric eld in the semiconductor material is lowered because of its length. As mentioned previously the problem with having the n region would appear to be that the bulk resistance of the diode would appear to increase. This
1 The

depletion region supports the reverse voltage.

5.2 Review of Power Semiconductor Devices

5-5

Anode

Cathode

Anode
p+
n+

Cathode

Figure 5.2: Conceptual structure of a conventional diode.

Anode

Cathode

Anode

p+

n-

n+

Cathode

Wd Drift Region

vD
iD

Forward bias voltage and current directions

Figure 5.3: Conceptual structure of a power diode.

5-6

Introduction to High Power Converter Technology is true depending on how the diode is designed. There are two forms of structure in Figure 5.3: a. The non-punch through diode. b. The punch through diode.

non-punch through diode

The non-punch through diode refers to a diode where the depletion region lies entirely in the n region under reverse bias. Therefore the depletion region does not punch through the n region. On the other hand the punch through diode has a the n region a little narrower and more lightly doped. This structural change has two eects: a. The same length n region can support a larger reverse voltage. b. The bulk resistance of the device is lower than that of a non-punch through diode because of the shorter length n region. This gives lower on-state losses. We shall not concentrate on the former eect, suce to say that his is achieved by keeping the peak electric eld intensity lower in the device [2]. The lower bulk resistance is achieved because of a conductivity modulation eect, this occurring because there is injection of carriers into the n material not only from the p+ material, but also from the n+ material during forward bias. These extra carriers create in the n region lower the bulk resistance of the region in forward bias. The other important property of diodes, and especially power diodes, is the reverse recovery. This refers to an eect when the diode can conduct a reverse current for a small period of time under reverse bias, after it has been forward biased. This eect is due to stored minority carriers that accumulate in the device under forward bias conditions. These carriers must be removed before the device can block voltage, and it is the removal of these carriers that constitutes the reverse recovery current. Figure 5.4 shows a typical reverse recovery characteristic of a diode. Initially the diode is forward biased and carries a forward current (i.e. anode to cathode). However as the current goes to zero it continues to ow in the reverse direction through the diode as the charge is removed from the device. Eventually all the minority carriers are removed, and the current then starts to decrease as the reverse voltage rises across the device. During this phase the depletion regions are being established. Eventually all the charge has been removed and the diode then stops conducting and it supports the full reverse voltage. The shaded area represents the total stored charge removed from the device. Remark 5.1 Charge storage and the associated reverse recovery has important practical consequences in power electronic circuits. Alterations can be made to the semiconductor additives in power diodes in order to minimise the reverse recovery time. These diodes are known as fast recovery diodes. The recovery time of a normal diode can be 4 to 6secs, whereas a fast recovery power diode can have a recovery time of 1 to 2secs. Unfortunately fast recovery diodes have a relatively large forward voltage drop ( 1.5 volt). The other main type of diode that is used in power electronic applications is the Schottky diode. Because this diode uses a metal-semiconductor junction as

punch diode

through

reverse recovery

fast recovery

5.2 Review of Power Semiconductor Devices

5-7

iD

Reverse recovery time

t rr

Diode begins to support reverse voltage t

Qrr

Charge storage removal

Depletion region formation

Figure 5.4: Typical reverse recovery characteristic for a diode.

5-8

Introduction to High Power Converter Technology

D1

R1

C1

D2

R2

C2

D3

R3

C3

Figure 5.5: Series connection of diodes to support higher voltage. the basis for the diode it does not have a charge storage problem. Furthermore, the forward turn-on voltage of the device is much lower than a conventional diode of the order of 0.2 to 0.3 volt. One is tempted to ask the question why arent Schottky diodes used everywhere in power electronics?. The answer to this is that the Schottky diode cannot support large reverse voltages, and therefore is only suitable for low voltage applications (up to approximately 100 volt). 5.2.1.1 Series Diodes

Diodes can be put in series to achieve higher blocking voltages. However, one must statically balance the reverse voltages, as well as dynamically balance them. Static balancing is required because of diering reverse bias leakage currents. Parallel resistors are used, the values of the resistors are chosen so that their current dominates the leakage currents (similar to capacitor balancing). Dynamic balancing is required in order to account for dierent charge storage in the diodes. This is achieved by parallel capacitors whose value is chosen so that they dominate the stored charge. The arrangement with static and dynamic balancing is shown in Figure 5.5. Remark 5.2 The presence of the parallel capacitors means that the switching transistor may have to handle more reverse recovery current.

5.2.2

Thyristors

The thyristor, or silicon controlled rectier (SCR) is essentially a controlled turn-on diode in terms of its external characteristics. They are the oldest of the semiconductor power electronic switches (invented in 1957 at General Electric research labs), but nevertheless, because of their characteristics, they will have continuing application in power electronics. They also have the highest power rating out of all the power electronic devices. Figure 5.6 is a conceptual diagram of a thyristors structure and its circuit symbol. Notice that the device is a three terminal structure, with the addition

5.2 Review of Power Semiconductor Devices of a gate terminal. This diagram also shows that the device is a three junction structure, consisting of what appears to be two diodes in series. It should be noted that this linear semiconductor diagram is not really representative of how the device is physically laid out in silicon.

5-9

Anode Gate
iA J1

Cathode

J2 (n ) n1
-

J3

iK
+

p1

Anode

p2 (n ) n2
iG

Cathode

Gate

Figure 5.6: Conceptual diagram of a thyristor. To understand how the device works one can develop the approximate model for the device shown in Figure 5.7. This diagram shows that the thyristor consists of a feedback structure consisting of a PNP and an NPN transistor. From ones knowledge of the behaviour of the transistor one can see that if a current is fed into the gate (terminal G) then transistor Q2 will turn on. This will result in the PNP transistor, Q1 turning on. Because the collector of Q1 is connected to the base of Q2, the current from Q1 forms the base current for Q2. If the current gain around the loop of the two transistors is greater than one then the initial turn gate current can be removed and the device will remain on. Under blocking conditions one wants the gain around the loop consisting of the two transistors to be less than one. This corresponds to 1 + 2 being small (which means that the transistor current gain product 1 2 < 1), where 1,2 = iC1,2 /iE1,2 , . This is the normal state of the transistor. The thyristor is turned on by changing the eective s for the two transistors. This is achieved by changing the depletion region across the J2 junction, which eective modulates the width of the bases of the two transistors. Therefore as a larger positive voltage is applied at the anode with respect to the cathode, the depletion region grows. Eventually the s will get to a point where the leakage currents across the junctions are enough to supply a current which will begin the regenerative process. This will cause the thyristor to turn on without any gate current. The voltage that has to be applied across the device to cause this to happen is known as the forward break over voltage. If a gate current is applied it is possible to cause the device to enter the positive feedback region prior to the forward break over voltage. The gate current causes carriers to be injected across J3 and diuse to the depletion region at J2 . Here they are swept by the electric eld of the depletion region

forward break over voltage

5-10

Introduction to High Power Converter Technology

Anode
J1

iA , iE 1

i B1 iC 2 Q2 J3 iK J2

Q1 iC 1 iG

iB 2 iE 2

Gate

Cathode

Figure 5.7: Transistor model of the thyristor. into n1 . The result is that the depletion region at J2 widens to account for the minority carriers injected. This is due to the fact that more donor atoms have to be uncovered to account for the electrons injected from p2 . The net result is that the eective bases of the two transistors narrow, and consequently the s increase. Once these reach the critical value then the positive feedback will again occur and the device will latch on. The main point to note is that the gate current has achieved this at a lower voltage than the break over voltage. If the gate current is higher, then the lower the forward voltage can be when the device will latch on. The above discussion is captured in the iv characteristic of a generic thyristor shown in Figure 5.7. There are several points to note about this characteristic. If the gate current is zero, and a forward voltage is applied, then if the voltage reaches the level of vBO the thyristor begins to conduct. This is known as the break-over voltage. Once the device begins to conduct, the voltage across the device falls to a low level dependent on where the load line crosses the forward characteristic. Similarly if the thyristor is reverse to a level of vRW M , the maximum reverse working voltage, then the device will begin to conduct (as will a diode if reverse breakdown occurs). The vRW M voltage usually has about the same magnitude as the vBO voltage (by design). The most interesting aspect of the thyristor characteristic is the fact that the eective vBO voltage can be lowered by the application of a gate current. It is this fact that makes the thyristor behave as a switch. Once the device has broken over the device enters a negative resistance region prior to entering the forward on-state region. For the device to enter the forward on-state condition a minimum current, iH , must be owing through the device. This is known as the holding current. If this current cannot be sustained then the device will re-enter the forward blocking state. Remark 5.3 Thyristors are still the device of choice for very high power applications. They are capable of withstanding very high voltages (of the order of 6-7kV) and can conduct currents in the range of 2-3kA.

holding current

5.2 Review of Power Semiconductor Devices

5-11

iA

Forward on-state

Increasing iG iG = 0 iH

v RWM

i BO

vH

v BO

v AK

Forward blocking state

Figure 5.8: Typical characteristic of a thyristor. Remark 5.4 Another important characteristic of the thyristor is that the gate current does not have to be maintained after the current through the device reaches the holding current. However, on the downside, the gate current cannot be used to turn the device o. The device can only be turned o if the external circuit conditions allow the current in the device to fall below the holding current. There are two external aspects of the transient performance of these devices that are practically very important the turn-on and turn-o limitations. 5.2.2.1 Turn-on Transient

Figure 5.9 shows a typical turn-on transient for a thyristor. There are several points that can be made about this diagram. After the gate pulse is applied there is a delay before the thyristor turns on (td ). This is due to the time that it takes the minority carriers to build up in the p2 material shown in Figure 5.6. After td the device starts to enter positive feedback and begins to turn on. The current in the device builds up with a slope of diA /dt, this being determined by the voltage and the external circuit inductance. Notice that during this period the voltage across the device is starting to fall quite rapidly, but there is still a substantial voltage across the device. Consequently there can be substantial power dissipation in the device during this phase. After the rise time period has nished there is a further period of voltage drop across the device known as the spreading time, ts . This is the time required for the current density to become even across the device cross-section. The diA /dt time is important, since if a maximum value is exceeded the device can be damaged. This damage occurs because there is uneven current

5-12

Introduction to High Power Converter Technology

iG

t
iA IA

di A dt

t
v AK

t
td

tr

ts

Figure 5.9: Typical turn-on waveforms for a thyristor.

5.2 Review of Power Semiconductor Devices distribution in the thyristor during turn on, and if the current is increasing too quickly hot spots may develop in the device (because there is not enough time for the current to spread adequately over the cross-section of the device). 5.2.2.2 Turn-o Transient

5-13

To turn-o a thyristor it must be reverse biased by actions of the external circuit for a minimum period of time. In general this minimum time is considerably longer than the turn-on time. Figure 5.10 shows a typical turn-o transient. The current decreases at a rate of diR /dt, this rate being determined by the external circuit. As with a diode, the stored minority carriers in the four regions of device result in current owing in a reverse direction through it. The voltage across the device remains positive until either the junction J1 or J3 become reverse biased. Usually J3 becomes reverse biased rst, this occurring at time t2 in Figure 5.10. At this point the voltage across the device starts to have a reverse voltage across it. The J3 junction cannot support a very large reverse voltage (20-30 volt) due to the high doping levels in the n2 and p2 junctions. Therefore this junction goes into avalanche breakdown. However shortly after the t2 the J1 junction starts to become reverse biased, and at this point the current through the device starts to decrease. The large reverse over-voltage is due to the eects of external inductances in the circuit. As the current through the device becomes zero, then the reverse voltage across the device becomes the steady state reverse voltage as imposed by the external circuit. In power diodes when the reverse recovery current reaches some nominal value of irr /4, then the device was said to have turned o. However, in the case of the thyristor there is still a substantial number of minority carriers in the interior n1 and p2 regions. If a forward voltage is then applied to the device at a rate of change of dvF /dt then a forward current can again occur as these carriers recombine and are swept through the device by the growing forward elds in the device. This current can produce an eect similar to the reapplication of a gate pulse, and the device can once again turn on. In order to prevent the device from turning on with the application of a forward voltage the following precautions must be taken: a. If the device has been forward biased then it must be held in reverse bias for a minimum time of tq , a time specied by the manufacturer. This time is at least several minority carrier line times long. b. The rate of change of the reapplied voltage, dvF /dt, must be kept below a certain value specied by the manufacturer. Remark 5.5 The maximum dvF /dt for slow thyristors is of the order of 100V/sec. For devices intended for high frequency operation the dvF /dt is of the order of several thousand volts per sec.

5.2.3

Gate Turn-o Thyristors

The Gate Turn-o Thyristor (GTO) is essentially a thyristor that can be turned o by the application of a negative gate current. This makes the usage of the

5-14
iA

Introduction to High Power Converter Technology

t rr
di R dt
t1 t2 t3

irr 4

irr

v AK
dv F dt

t
v REV

Turn - off time tq

Figure 5.10: Typical thyristor turn-o waveforms. GTO in dc supply situations much simpler, as compared to the thyristor.2 There are signicant internal structure changes made to the thyristor in order to make it behave as a GTO. We shall not consider these in detail in this course. The GTO works essentially the same as the thyristor. Therefore we shall concentrate on the mechanism that eects the turn-o. If one considers Figure 5.7 it can be seen that: iB2 = 1 iA iG (5.1)

where iG is the negative of the normal gate current. From Figure 5.7 it is clear that by increasing iG one can bring Q2 out of saturation. The collector current for the Q2 transistor, iC2 , is given by: iC2 = (1 1 )iA (5.2)

2 If a thyristor is used in a dc supply application it must be turned o using a forced commutation technique. These techniques will be considered in a later section.

5.2 Review of Power Semiconductor Devices using KCL at Q1 . In order for the structure to turn o we need the following so that Q2 can no longer supply the necessary current to keep the total loop gain greater than one: iC2 iB2 < (5.3) 2 where 2 = 2 /(1 2 ). Using (5.1), (5.2) and (5.3) one can develop that following expression: iA (5.4) iG > t_o where the parameter t_o is the turn o gain given by: t_o = 2 1 + 2 1 (5.5)

5-15

Remark 5.6 From (5.4) one can see that the t_o value should be as large as possible to keep the iG value as small as possible. This implies that 2 1 and 1 should be small. Therefore the semiconductor regions in the GTO are designed to achieve this objective. 5.2.3.1 Snubbers and GTO Thyristors

Consider the circuit shown in Figure 5.11. This is a step down converter using a GTO and the switching element. There are several points that should be noted about this diagram: The circuit symbol for the GTO (as compared to that of the thyristor). The Ls_on inductor and associated parallel resistor and diode form a turnon snubber3 circuit. The Cs_o capacitor,associated resistor Rs_o , and diode Ds_o , form a turn-o snubber circuit. The L inductance is an unwanted parasitic inductance. turn-on snubber The turn-on snubber is required to protect the GTO from the large currents that can ow through it because of the reverse recovery of the freewheeling diode Df w , which is usually a slow device at the power levels that GTOs are used at. The presence of the series inductance Ls_on limits that rate of rise of the current through the GTO. The resistor and diode components that are in parallel with Ls_on are to dissipate the energy stored in Ls_on when the GTO is turned o. These should be designed so that the energy in the inductor is dissipated before the next turn on of the GTO. When the GTO is turned o the voltage across the device would go to Vd almost instantaneously without the presence of a turn-o snubber. If the dv/dt across the device is too large then it will turn on, as was the case for the thyristor. The purpose of the snubber is to ensure that this cannot occur, since the voltage across Cs_o cannot change instantaneously.

5-16

Introduction to High Power Converter Technology

Load current

D fw

iL

Turn-on snubber

Rs_on Cd

Vd

Ls_on D s_on

Parasitic inductance
Ls

D s_off

Rs_off

GTO

C s_off

Turn-off snubber
Figure 5.11: An example of a dc chopper circuit using a GTO thyristor

5.2 Review of Power Semiconductor Devices Remark 5.7 The use of a turn-o snubber with the GTO is absolutely essential. If the device is turned on prior to all the internal stored charge being dissipated, then there is a very poor distribution of the turn-on current, resulting in local heating and possible destruction of the device. This occurs because of the particular internal construction of the GTO. The presence of the turn-o snubber prevents the automatic re-turn-on of the device when the voltage rises across it too quickly. 5.2.3.2 GTO Turn-on turn-o snubber

5-17

We shall briey look at what is required to turn on a GTO. Consider Figure 5.12. The turn-on is instigated by a pulse of gate current. The diG /dt and the peak iG should be large so that the device turns on rapidly and the current distributed evenly in the device. The gate pulse should last of the order of 10 seconds or so to ensure that the turn-on process is complete. After this period a small gate current should be maintained to ensure that the device does not turn o again under low anode current conditions.4 This current is often known as the back-porch current. The other point to note in Figure 5.12 is the eect of the series inductance Ls_on on the anode current during turn-on. Notice that diA /dt is limited by this inductance so that the current is distribute evenly across the device, and the voltage across the device is shared with the inductor during turn-on. This inductor also stops the otherwise large reverse recovery currents in the circuit due to the recovery characteristic of the freewheeling diodes. The reverse recovery actually results in the current overshoot represented by the overshoot during turn-on. 5.2.3.3 GTO Turn-o

Next we briey consider the turn-o waveforms for the GTO. It should be noted that the eect of the snubbers cannot be ignored for the GTO, since it is essential that they are used under normal operation (as mentioned in Remark 5.7). In order to turn the GTO o then the gate current must be negative. The magnitude of this current is approximately 1/5 to 1/3 of the anode current being turned o. Therefore in high power applications this current can be substantial in magnitude. Fortunately the duration of the current is short. Figure 5.13 shows the waveforms during turn-o. The negative diG /dt should be kept large, but it should not be made too large or undesirable tail currents occur in the anode current, and there is the possibility of device destruction. Therefore the diG /dt should be kept within the specications supplied by the device manufacturer. The diG /dt value can be controlled by the design of the inductance in the gate drive circuit and the negative voltage applied to turn-o the device. During the time interval t1 , the growing negative gate current is removing charge stored in the two regions of the device. When enough of this is removed
3 A snubber circuit is an auxiliary circuit that is designed to protect the main switching element from excessive current or voltages. 4 This unwanted turn-o condition could also damage the device due to uneven distribution of the current in the device if there is a sudden increase in anode current.

5-18

Introduction to High Power Converter Technology

iG

t w1

Backporch current iGT 0

iA td

0
v AK

0
vGK

Figure 5.12: Turn on waveforms for a GTO thyristor.

5.2 Review of Power Semiconductor Devices

5-19

iG

iGT

iA

t4

t tail

io

0
v AK
t2 t1

dv dv < dt dt

Vd
max

0
vGK

t Inductive spike due to parasitic L in the snubber circuit. t

t3

0
vGG-

Figure 5.13: Turn-o waveforms for a GTO thyristor.

5-20

Introduction to High Power Converter Technology the regenerative action is stopped, and the device starts to turn-o (i.e. the anode current begins to fall). The growing dierence between the anode current and the constant load current io ows into the snubber capacitor. There is a rapid rise of the voltage across the GTO due to the parasitic inductance of the snubber circuitry (this stray inductance has to be kept to the absolute minimum to kept this voltage small). After time t2 enough carriers have been swept out of the device for the gate-cathode junction to regain its reverse blocking capability. As the gate-cathode junction recovers it reverse blocking capability, the voltage across it starts to go negative, and the negative gate current starts to decrease. The inductance in the gate circuit tries to keep the gate current constant, and this results in avalanche breakdown of the gate-cathode junction during the time t3 i.e. the gate-cathode junction is operating as a zener diode. This breakdown serves to remove further minority charge from the device. The t3 interval should be kept below a manufacturer specied value to prevent destruction of the gate-cathode junction. After the t3 period there is a continuation of anode current ow as the nal stored charge is removed from the device. This is known as the anode tail current, and ows for time ttail . During this time the voltage across the device is growing at the rate of: io dvAK (5.6) dt Cs

GTO minimum on and o times

and contributes a lot to the turn-o losses in the device. Remark 5.8 A GTO should not be turned on too soon after it has been turned o because of the potential for poor current sharing in the device due to residual charge storage. The same applies for turn-o after turn-on. Remark 5.9 If the anode current becomes too large there is the possibility that the gate current may not be able to turn the device o (there is a limit to the magnitude of the gate current, determined by the semiconductor properties of the device). This is a particular problem under short circuit conditions, since this is an abnormal condition that would not be designed for. Remark 5.10 Over-current protection can be achieved by using a crowbar to blow the fuse in the circuit if the current becomes too large. This concept is shown in Figure 5.14. The SCR across the dc link is red, resulting in a short circuit on the link, and consequently the fuse will blow and protect the circuit. If the GTOs are used in an inverter structure then all the devices in the inverter can be red simultaneously to carry out the same function. It should be noted that in Figure 5.14 we have not included the turn-on snubber. It is this snubber that gives the SCR the extra time to turn-on prior to the GTO destroying itself. Remark 5.11 One problem with the crowbar protection technique is that the presence of a fuse in the dc link introduces inductance in this part of the circuit. This can result in signicant over-voltages when the main GTO is turned o.

turn-o failure under short circuit conditions

Remark 5.12 There are several variants to the classical GTO that are being championed by dierent manufacturers. For example, Asea-Brown-Boveri

5.2 Review of Power Semiconductor Devices

5-21

Crowbar SCR Fuse

Short circuit

Load

Figure 5.14: GTO thyristor circuit with additional crowbar SCR (ABB) has the IGCT - the Integrated Gate Commutated Thyristor. This is essentially a modied GTO with tightly coupled gate drive circuitry built onto a card with the GTO power device. It is a high power device 4.5kV and 3kA. The onboard GTO has low conduction losses and does not require a turn-o snubber. The better gating allows higher switching frequencies as compared to standard GTOs (of the order of 1000Hz). Rockwell/Allen-Bradley have a similar device called the SGCT the Symmetrical Gate Commutated Thyristor.

5.2.4

Insulated Gate Bipolar Transistors (IGBTs)

One of the more recent devices that has become pervasive in the lower to medium power area is the IGBT the Insulated Gate Bipolar Transistor. This device is essentially a specialise MOSFET in fact the input is a MOSFET input. The main advantage of these devices is that they can be easily turned o by controlling the devices gate, but unlike the GTO this turn-o process does not require large currents. The basic structure of the n-channel IGBT5 is shown in Figure 5.15. One can see that the structure of the device is nearly identical to the MOSFET, the only major dierence being the presence of the p+ injection layer. It is the presence of this layer that results in the injection of minority carriers into the device, and leads to the operation of the device being something like a MOSFET fed bipolar transistor. The advantages of the device are: The result of the injection of minority carriers in the device is that it can carry much larger currents as compared to the MOSFET, since the current is carried in more than the channel of the device. The presence of a lengthy diode junction in the device allows it to have a signicantly larger forward blocking voltage as compared to the MOSFET. The injection of carriers into the device means that the on-state losses for this device are lower than those of a comparable power MOSFET.
5 The

layer types are all reversed for a p-channel device

5-22

Introduction to High Power Converter Technology Remark 5.13 One could consider the IGBT to be a super MOSFET. In many IGBTs the MOSFET part of the device carries the majority (up to 90%) of the current in the device (this is to help prevent a large amount of minority carrier storage from occurring, which slows down the turn-o of the device).

Source

Gate

SiO2
n
+

SiO2
n
+

Body region

J1 J2 J1

Ls
n
-

Drain drift region Buffer layer

n+

p+

Injecting layer Parasitic SCR Drain

Figure 5.15: A schematic diagram of the basic structure of the IGBT. The n+ layer between the p+ drain layer and the n drift region is not essential for the operation of the device. As with the diode considered earlier, one can have punch-through and non-punch-through IGBTs. The n+ layer is required for the punch-through devices to prevent the J2 space charge region from going all the way to the p+ drain region. The presence of the n+ layer can signicantly improve the operation of the IGBT. Remark 5.14 In Figure 5.15 there is a parasitic SCR shown. This is an undesirable feature of the structure, and design eorts must be made to ensure that the loop gain of the SCR is not greater than one so it does not turn on. The circuit symbol for the IGBT appears in Figure 5.16(c) and (d). Note that the symbol in (c) is very nearly the same as that for the n-channel MOSFET, except that there is an arrow on the drain connection indicating the direction of the current due to the injection of carriers here. Figure 5.16(d) shows a symbol that is emphasising the similarity of IGBT with the NPN bipolar transistor.

5.2.4.1

IGBT Operation

We shall briey consider the salient points of IGBT operation. The following discussion is with reference to Figure 5.17.

5.2 Review of Power Semiconductor Devices

5-23

iD

Increasing vGS

v RM
v DS
brk

v DS

(a)
0.7 V

iD

Drain Drain Gate Gate

Source
vGS th

vGS

Source (c) (d)

(b)

Figure 5.16: The IGBT voltage and current transfer characteristics and circuit symbol: (a) output characteristic; (b) transfer characteristic; (c) and (d) nchannel IGBT circuit symbols.

5-24

Introduction to High Power Converter Technology Figure 5.17(a) shows the current ows in the device when it is turned on. When the gate voltage exceeds the threshold voltage an inversion layer forms beneath the gate of the IGBT. This channel shorts the n+ to the n layer, as occurs in the MOSFET. The current ow through this channel also results in holes being injected from the p+ region into the n region. These holes move across the n drift region via drift and diusion via a number of paths. These carriers reach the p body region (not necessarily where the channel is) and then are swept through to the source via recombination at the source metallisation. The junction of the n region and the p region is called the collector region, since is operates the same as the collector region in a thick PNP transistor. The connection between the layers and parasitic transistors is shown in Figure 5.17(b). Notice that the injection layer, denoted as the p+ layer, acts as an emitter in a BJT transistor, emitting or injecting holes into the n base region of the device. As current ow through the IGBT there are voltage drops in the device due to the bulk resistance of the semiconductor materials used. These are shown in Figure 5.17 as dashed resistors. These resistance values are important for two dierent reasons; (i) if the resistances are too high then the device will dissipate more power; and (ii) if the voltage drops are too high in the resistances then parasitic thyristor in the IGBT may turn on. Figure 5.18(a) and (b) shown an equivalent circuit for the IGBT. Figure 5.18(b) is more complete, showing the parasitic thyristor, and the body spreading resistance. If the body spreading resistance is too high then the current gain of the thyristor may become greater than one, and consequently the thyristor will turn on. Once this happens then the device no longer behaves as an IGBT, and power must be remove across the device to turn it o. Needless to say, much design eort has gone into ensuring that the parasitic IGBT does not turn on.

5.2.4.2

IGBT Turn-on

Typical turn-on waveforms for the IGBT are shown in Figure 5.19. These waveforms are very similar to those for a power MOSFET.6 We are assuming that the voltage to the input of the IGBT circuit is the voltage waveform vGG . The voltage across the gate-source of the IGBT is vGS . Note from Figure 5.19 that this voltage is essentially an exponential, due to the input capacitance of the IGBT, coupled with the gate resistor (which is to limit the current owing into the gate of the IGBT to safe levels). The time period td(on) is the time required for vGS to reach a voltage where the device starts to turn on. From this point the current through the device rises as it starts to turn on harder. Eventually vDS is of the order of vGS and the current stabilises at a value determined by the external circuit. As vDS starts to fall a signicant amount of current starts to ow through the Cgd capacitance. This is due to the fact that there is a changing voltage across the capacitor, and that the value of the capacitance increases considerably as the space charge region width decreases (eectively decreasing the plate separation in a parallel plate capacitor) and the stored charge in the device starts
6 Note that the waveforms for turn-on and turn-o are for the IGBT in a step down chopper circuit of the type shown in Figure 5.11, except that the main power device has been replaced by the IGBT and there are no snubbers.

5.2 Review of Power Semiconductor Devices to increase. Consequently the rise of vGS attens out as this capacitance is charged, this being the result of the extra current being drawn through the gate resistor. Eventually vGS restarts its exponential rise again when vDS vGS , stopping when its value reaches vGG . The vDS waveform during the tf v2 time in Figure 5.19 is usually observed in IGBTs. It is due to two eects the above-mentioned increase in Cgd as vDS falls (which also occurs in power MOSFETs), and the slower turn-on of the PNP section the IGBT (as compared to the MOSFET portion), which delays the associated conductivity modulation due to the injected carriers. 5.2.4.3 IGBT Turn-o

5-25

The waveforms for the turn-o of the IGBT are shown in Figure 5.20. The rise in the voltage vDS before iD drops is typical of all step down converter circuits. This occurs because the load is considered to be eectively a current source, and therefore it continues to supply current into the switch device until the voltage on the switch side of the load reaches the supply. At this point the diode across the load will start to turn on and take the load current. The initial part of the vGS turn-o transient, td(o) , occurs because of the time constant associated with the RG (Cgd2 +Cgs ) time constant of the MOSFET part of the IGBT.7 As the drain-source voltage vDS starts to rise, the Miller eect of Cgd2 starts to take eect. This temporary arrests the decrease of vGS during the interval trv . When vDS stabilises then this eect stops. The decrease of vGS now continues, but with a time constant of RG (Cgd1 + Cgs ), which is smaller than previously due to the change on the value of Cgd caused by the widening of the space charge region in the device. During all the phase so-far the IGBT is behaving as a MOSFET. The major dierence between the IGBT turn-o and the power MOSFET turn-o is observed in the drain current waveform which has two distinct time intervals. During the tf i1 time the MOSFET is turning o. The second time interval tf i2 is due to the stored charge in the n region of the device. Since the MOSFET is o there is no way that these carriers can be swept out of the device by a negative drain current. Consequently these carriers diminish by recombination. The punch-through IGBT attempts to minimise this eect by having a small carrier lifetime in the n+ region. This results in an electron concentration gradient from the n region to the n+ region, thereby sweeping the electrons from the device.8 The non-punch-through IGBT attempts to minimise the tail o current by redesigning the IGBT so that the majority of the current is carried by the MOSFET. This minimises the stored charge. At the time of writing these notes IGBTs are in a rapid state of development. Currently the most advanced devices are capable of withstanding approximately 6kV, and can conduct several thousand amperes. The turn-o times for these devices are of the order of 1sec of less. For medium power systems IGBTs are currently the device of choice.
7 R is the gate resistor that is included in the circuit to limit the gate currents to reasonable G levels. 8 It is desirable to have long carrier life times in the n region so that the bulk resistance is kept low in this region when the device is on.

5-26

Introduction to High Power Converter Technology

5.2.5

Other Devices and Developments

Thus far we have concentrated on the devices that are the most important ones in terms of current practice. However there is also signicant work going on into new devices that still have not reached the commercial stage. We shall briey mention some of these. 5.2.5.1 Power Junction Field Eect Transistors

This device is also sometimes known as the static induction transistor (SIT). It is eectively a JFET transistor with geometry changes to allow the device to withstand high voltages and conduct high currents. The current capability is achieved by paralleling up thousands of basic JFET cells. The main problem with the power JFET is that it is a normally on device. This is not good from a start-up viewpoint, since the device can conduct until the control circuitry begins to operate. Some devices are commercially available, but they have not found widespread usage. 5.2.5.2 Field Controlled Thyristor

This device is essentially a modication of the SIT. The drain of the SIT is modied by changing it into an injecting contact. This is achieved by making it a pn junction. The drain of the device now becomes the anode, and the source of the SIT becomes the cathode. In operation the device is very similar to the JFET, the main dierence being quantitative the FCT can carry much larger currents for the same on-state voltage. The injection of the minority carriers in the device means that there is conductivity modulation and lower on-state resistance. The device also blocks for reverse voltages due to the presence of the pn junction. 5.2.5.3 MOS-Controlled Thyristors

The MOS-controlled thyristor (MCT) is a relatively new device which is available commercially. Unfortunately, despite a lot of hype at the time of its introduction, it has not achieved its potential. This has been largely due to fabrication problems with the device, which has resulted on low yields. Figure 5.21 is an equivalent circuit of the device, and its circuit symbol. From Figure 5.21 one can see that the device is turned on by the ON-FET, and turned o by the OFF-FET. The main current carrying element of the device is the thyristor. To turn the device on a negative voltage relative to the cathode of the device is applied to the gate of the ON-FET. As a result this FET turns on, supplying current to the base of the bottom transistor of the SCR. Consequently the SCR turns on. To turn o the device, a positive voltage is applied to the gate. This causes the ON-FET to turn o, and the OFF-FET to turn on. The result is that the base-emitter junction of the top transistor of the SCR is shorted, and because vBE drops to zero. volt it turns o. Consequently the regeneration process that causes the SCR latching is interrupted and the device turns o.

5.2 Review of Power Semiconductor Devices The P-MCT is given this name because the cathode is connected to P type material. One can also construct an N-MCT, where the cathode is connected to N type material. 5.2.5.4 New Semiconductor Materials

5-27

Silicon is presently the only material that is widely used for the fabrication of the power semiconductors (and integrated circuits for that matter). The reason for this is the ease with which large and very pure crystals can be grown with Silicon. However, there are other materials that have superior properties as compared to Silicon, especially in high power/high voltage applications. Gallium Arsenide (GaAs) is a well used material, especially in high frequency applications, where its very high carrier mobility allows higher frequency devices to be constructed. In addition it has a higher band-gap than Silicon, which means that it can support higher voltages than Silicon, and can be operated at higher temperatures (460C and compared to 300C for Si). Silicon Carbide is a material which is currently attracting a lot of research. It has a signicantly larger band-gap than Si (2.9eV as compared to 1.12ev for Si), has excellent thermal conductivity (approximately 3 times that of Si), and can operate at temperatures of 600C, with a maximum operating temperature of 1240C. The breakdown electric eld strength is approximately 10 times that of Si, meaning that it can withstand signicantly higher voltages. SiC devices are probably on 3 to 5 years from commercialisation. Diamond is the ideal material for power semiconductors. It can operate at very high temperatures (similar to SiC), it can withstand elds approximately 100 times larger than Si, it has thermal conductivity 5 times larger than SiC (and therefore 15 times larger than Si), and it has electron mobility approximately twice that of Si. Unfortunately there is much research to be done before we see commercial diamond based power electronic devices (15-30 years). One can see that there are many exciting developments occurring in the area of power electronic devices. These new devices then open up new applications, that previously were not feasible.

5-28

Introduction to High Power Converter Technology

Source

Gate Channel

SiO2

SiO2

Drift region resistance

nn+

+ + + +

+ + + +

Minority carrier injection

Drain (a) Source

Lateral body spreading resistance

Gate

SiO2
n
+

SiO2
n
+

Collector region

nn+

Minority carrier injection

Drain (b)

Figure 5.17: Current ows in the IGBT.

5.2 Review of Power Semiconductor Devices

5-29

Drift region resistance

Drain

Drift region resistance

Drain

Gate

Gate

Source Source Body region spreading resistance

(a)

(b)

Figure 5.18: Equivalent circuits for the IGBT: (a) approximate equivalent circuit for normal operating conditions; (b) more complete equivalent circuit showing the parasitic thyristor.

5-30

Introduction to High Power Converter Technology

vGS / vGG

vGG

vGS

0
iD

t
td(on)

Io

t
t ri

v DS
Vd

v DS (on)
t fv1 t fv 2

C gd

Rg

v DS vGG vGS

Definitions

C gs

Figure 5.19: Typical turn-on waveforms for an IGBT.

5.2 Review of Power Semiconductor Devices

5-31

vGS / vGG

vGG vGS

vGG
vGS ,I
o

vGS(th)

0
iD

Io

td(off)

t fi 2

}
}

MOSFET current BJT current

0
t rv
t fi1

v DS
Vd

Figure 5.20: Turn-o waveforms for an IGBT.

Anode A Gate G

OFF-FET K ON-FET Cathode

Figure 5.21: Schematic and circuit symbol for the P-MCT.

5-32

Introduction to High Power Converter Technology

Chapter 6

Line Frequency Uncontrolled Rectiers

6.1 Introduction

The power input into most power electronic devices is derived from 50/60Hz ac sine wave supplies provided by the electricity authorities. This supply generally is converted into a dc supply before being used or converted into another form. The traditional and simplest way of achieving the acdc conversion is via an uncontrolled rectier based on diodes. Such rectiers only allow power to ow from the ac to the dc side. The vast majority of power electronic applications currently use such rectiers to do the acdc conversion, although this situation may change in the future due to mains harmonic requirements (which are dicult to meet using conventional rectiers). This chapter shall look at the basic operation single phase and three phase uncontrolled rectiers. Some analysis will be carried out (based on the assumption of ideal diodes) to ascertain the harmonic performance of the various rectiers. Before doing this there is some concepts that we will need to introduce.

6.2

Some Mathematical Preliminaries

One of the characteristics of diode rectier circuits is that the produce nonsinusoidal currents in the ac mains. Therefore consideration of non-sinusoidal waveforms is relevant to carrying out analysis of these types of circuits. Much of the analysis is carried out assuming that the circuits are in steady state, and then calculating the Fourier components in the current (and in some cases the voltage) waveforms. We shall therefore quickly review Fourier analysis as applicable to power electronic waveforms.

6-2

Line Frequency Uncontrolled Rectiers

6.2.1

Fourier Analysis of Repetitive Waveforms

In general, a non-sinusoidal waveform, f (t), which repeats with an angular frequency of , can be expressed as [13]:

f (t) = F0 +
n=1

fn (t) =

1 a0 + {an cos(nt) + bn sin(nt)} 2 n=1

(6.1)

1 where F0 = 2 a0 corresponds to the average value of the waveform (or the dc component), and the coecients in (6.1) are:

an = bn =

1 1

f (t) cos(nt) d(t)

0 2

(6.2) (6.3)

f (t) sin(nt) d(t)

0

Note that the F0 term is calculated if the harmonic number starts from 0 instead of 1 i.e.: 2 1 1 1 T F0 = a0 = f (t)d(t) = f (t)dt (6.4) 2 2 0 T 0 which is the average value of f (t) as noted previously. Each component of the waveform can therefore be written as: fn (t) = an cos(nt) + bn sin(nt) which can be simplied using the following trigonometric identity: A cos + B sin =
B A.

(6.5)

A2 + B 2 cos( )

(6.6)

where tan = Since via (6.6) equation (6.5) can be written as a cos function, then we can eliminate the frequency component of the waveform and write the expression as a phasor: F n = Fn ejn (6.7) where: a2 + b2 n n 2 (bn ) tan n = an Fn = (6.8) (6.9)

In many situations in power electronics the waveforms do not have a dc component. This coupled with the symmetry that is present can considerably simplify the generation of the Fourier coecients. These are shown in Table 6.1 for several of the common symmetries. If the denition of the rms value1 of a waveform f (t) is applied to the function when expressed in terms of its Fourier components, it can be easily shown that the rms amplitude is:

F =
1 Denition

2 F0 + n=1

2 Fn

(6.10)
1 T T 0

of the rms value of a quantity is xrms =

x(t)2 dt.

6.2 Some Mathematical Preliminaries Symmetry Even Odd Half-wave Condition Required f (t) = f (t) f (t) = f (t) 1 f (t) = f (t + 2 T ) Fourier Coecients 2 an = 0 f (t) cos(nt) d(t) bn = 0 2 an = 0 bn = 0 f (t) sin(nt) d(t) an = bn = 0 for even n 2 an = 0 f (t) cos(nt) d(t) for odd n 2 bn = 0 f (t) sin(nt) d(t) for odd n 4 /2 f (t) cos(nt) d(t) for odd n 0 an = 0 for even n bn = 0 for all n an = 0 for all n 4 /2 f (t) sin(nt) d(t) for odd n 0 bn = 0 for even n

6-3

Even quarter-wave Odd quarter-wave

Even and half-wave Odd and half-wave

Table 6.1: Fourier coecient formulae with symmetry.

6.2.1.1

Measures of Waveform Distortion

Consider Figure 6.1 which shows the voltage and current waveforms in a situation where a power electronic device is connected to the grid supply [2]. The current waveform shows signicant distortion.2 The voltage on the other hand is shown without distortion, since it usually does not display the same amount of distortion as the current. This is the case because the voltage distortion arises from the current causing a voltage drop across the line impedances.3

vs

v, i

is
is1 i dis

wt

f1

Figure 6.1: Line current waveform distortion. Let us assume that the supply voltage can be represented as: vs (t) = 2Vs sin 1 t (6.11)

2 The distortion in this current waveform is typical of that one would expect from a diode rectier connected to the grid. 3 The undistorted voltage assumption makes the analysis simpler in this section.

6-4

Line Frequency Uncontrolled Rectiers The input current is represented by its Fourier components:

is (t) = is1 (t) +

n=1

isn (t)

(6.12)

where: is1 isn the fundamental line current the harmonic components of the line current

We can write (6.12) in an expanded form as follows: is (t) = where: 1 the phase angle of the fundamental (6.14) (6.15) (6.16) (6.17) (6.18)

2Is1 sin(1 t 1 ) +
n=1

2Isn sin(n t n )

(6.13)

n = n1 n t = n1 t = n1 n = n1 Is , Isn rms value of the relevant harmonic

The rms value of the current can be calculated using the general expression noted in footnote 1. If expression (6.12) is substituted into this, the crossproduct terms all integrate to zero due to the orthogonality property of cos and sin functions. The rms current therefore becomes:

Is =

2 Is1 + n=1

2 Isn

(6.19)

total harmonic distortion

The total distortion of waveforms in general is usually measured by a parameter called the total harmonic distortion, which is abbreviated as the THD. The distorted component of the current is essentially all the components of the current except the fundamental component. Therefore using the time domain expressions for the currents we can write the distortion component as:

idis (t) = is (t) is1 (t) =

n=1

isn (t)

(6.20)

This current is shown schematically in Figure 6.1. Therefore, using (6.19), the rms value of the distortion section of the current can be written as:

Idis =

2 2 Is Is1 = n=1

2 Isn

(6.21)

6.2 Some Mathematical Preliminaries The THD of the current dened as: %THD = 100 Idis Is1 2 2 Is Is1 = 100 Is1

6-5

(6.22) (6.23)
2

= 100
n=1

Isn Is1

(6.24)

6.2.1.2

Power and Power Factor

Clearly the purpose of a power electronic system is to convert electrical energy in dierent ways to allow energy (or power) to be eectively and eciently used. Therefore it is relevant to briey review the concept of power, and then to look at a generalisation of the concept of power factor to systems with non-sinusoidal waveforms. Let us begin with single phase power expressions. Consider the following time domain expressions for current and voltage owing into some arbitrary network: v = V cos t i = I cos(t + ) Using the denition of instantaneous power we can write: P = vi = [V cos t][I cos(t + )] = V I cos t[cos t cos sin t sin ] = V I cos t cos V I cos t sin t sin 1 Using cos2 t = [1 + cos 2t] one can write 2 V I cos P = [1 + cos 2t] V I sin cos t sin t 2 Using the trig relation: cos t sin t = 1 sin 2t 2
2

(6.25) (6.26)

(6.27) (6.28) (6.29) (6.30) (6.31) (6.32)

we can modify the last term of (6.32) as follows: P = V I cos VI [1 + cos 2t] sin 2t sin 2 2 VI VI VI = cos + cos cos 2t sin sin 2t 2 2 2 (6.33) (6.34)

Using cos(x + y) = cos x cos y sin x sin y, this can be written as P = V I cos 2
Average Real power

VI cos(2t + ) 2
Oscillatory component

(6.35)

6-6

Line Frequency Uncontrolled Rectiers The oscillatory power component represents the power owing into and out of the storage element of the particular circuit.4 The average real power component essentially causes an oset in this oscillation component so that there is an average value of power over a complete cycle. The other way of representing the power expression for sinusoidal steady state systems is in the form of the complex power: S =V I (6.36)

complex power

where represents the complex conjugate, and the means that x is a phasor. x Let us assume that: V = Vrms ej I = Irms ej where Irms and Vrms represent the current and voltage RMS values. Substituting (6.38) and (6.37) into (6.36) we can write: S = Vrms Irms cos + jVrms Irms sin where = .5 Equation (6.39) is broken up into two components: P = Vrms Irms cos Q = Vrms Irms sin (6.40) (6.41) (6.39) (6.37) (6.38)

One can see the vector relationship of these components in Figure 6.2. Notice that the use of the complex conjugate in the complex power expression means that the angle used is eectively the angle of the voltage phasor with respect to the current, despite the fact that the convention is that the currents phase is measured relative to the voltage.6
Imag
Q = VI sin
r I
P = VI cos

r V

I sin

I cos

Real

Figure 6.2: Phasor relationship for complex power.

4 As we shall see later this component consists of two dierent parts, one belonging to the real power and the other to the imaginary power. 5 The angle is the angle from the current vector to the voltage vector. 6 It is possible to dene complex power as = . In this case the angle is the current S I V with respect to the voltage in the power expression. The meaning of the sign of the complex power changes with this denition.

6.2 Some Mathematical Preliminaries The correspondence between (D.8) and the average real power component of (6.35) is easy to see. However, the correspondence between (D.9) and the oscillatory power part of (6.35) is not immediately obvious. Clearly Q is related the component of the voltage that is orthogonal (in a temporal sense) to the current, multiplied by that current. This correspondence is more easily seen from (6.34): P = V I cos V I cos + cos 2t 2 2
Real power component

6-7

V I sin sin 2t 2
Reactive power component

(6.42)

where V and I are the peak values of the voltage and current. We can see from this expression that the real power actually oscillates (with the oscillation being unipolar), and has an average value of (V I/2) cos . The reactive power component on the other hand does not have an oset term and its average value is zero. The amplitude of this term is equal to the Q term in the complex power expression. Therefore the reactive power component corresponds to power that is owing into the circuit and out again per half cycle of the fundamental voltage (or current). These components are shown in Figure 6.3 for a phase angle of 30 . This plot is of the normalised power, the normalisation factor being Vrms Irms . Notice the reactive power component has no average dc component.
2
Real power

1.5

Total power Average power

Normalised power

0.5

Reactive power

-0.5 0

3
q [rad]

Figure 6.3: Diagram of the normalised single phase power components with a 30 phase angle the power is normalised by dividing by Vrms Irms . Remark 6.1 The presence of reactive power is generally undesirable because it contributes to the current in the circuit (and therefore the size of the conductors required) without carrying any average power to the load.

6-8

Line Frequency Uncontrolled Rectiers Remark 6.2 With an inductive load the current lags the voltage (or the voltage leads the current). Therefore in the complex power expression the angle is positive, and consequently Q is positive. Therefore an inductive load absorbs reactive power, which is given the units of VARs (Volt Ampere Reactive). This is called absorbing lagging VARs. Conversely, a capacitive load results in the current leading the voltage (or the voltage lags the current). Therefore in this case the angle is negative, and therefore a capacitive load draws negative VARs from the supply (called leading VARs). It can also be said that the capacitor supplies positive VARs to the supply.

three phase real and reactive power

Let us now briey consider the concept of three phase real and reactive power. We shall assume that the phase currents and voltages in a star connected system are:7 va = V cos t vb = V cos(t + 2 ) 3 2 vc = V cos(t 3 ) (6.43) ia = I cos(t + ) ib = I cos(t + 2 + ) 3 ic = I cos(t 2 + ) 3 These voltages and currents can be multiplied together to give the three phase power expression: P = va ia + vb ib + vc ic 2 2 3V I cos V I cos + (cos 2t + cos(2t ) + cos(2t + )) = 2 2 3 3 V I sin 2 2 (sin 2t + sin(2t ) + sin(2t + )) (6.44) 2 3 3 Terms two and three in (D.12) are zero because the cosine and sine terms each add to be zero. Therefore the power expression becomes: P = 3V I cos 2 (6.45)

which is simply three times the average power in (D.10) (as one would expect). Remark 6.3 The interesting aspect about the three phase real power is that it is constant i.e. the total real power owing into a three phase system is constant despite the fact that the individual powers in the phase are oscillating. Let us consider the last part of (D.12). Rewriting this term one can see that: V I sin V I sin 2 2 sin 2t = sin(2t ) + sin(2t + ) 2 2 3 3 (6.46)

which means that the reactive power in one phase is being absorbed by two other phases. Therefore the reactive power is cycling around between the three phases, and hence is not seen on the external three phase power (although there is obviously still the single phase reactive power there in each of the individual
7 The

star connection means that there are no zero sequence currents owing.

6.2 Some Mathematical Preliminaries phases). The reactive power of three phase systems is considered to be the reactive power of an individual phase, whereas the real power of a three phase system is three times the real power of an individual phase. Now that we have consider the concepts of real and reactive power for single and three phase systems, let use now revise the concept of power factor for sinusoidal systems. We know from (D.8) that the real power is: P = Vrms Irms cos (6.47)

6-9

power factor

where is the angle from the current to the voltage phasor. If the current and the voltage were in phase then the power is obviously Vrms Irms . This is the maximum possible power. It is also known as the apparent power in a system where there is a phase dierence between the voltage and the current. The power factor is a measure of how close the actual real power is to the apparent power i.e.: P (6.48) PF = cos = Vrms Irms The next step is to generalise the power factor expression to the case where the current is not sinusoidal. We begin with the basic denition of average power: P = 1 T1
T1

p(t) dt =
0

1 T1

T1

generalised factor

power

vs (t)is (t) dt
0

(6.49)

where T1 is the period of the fundamental waveform. Remark 6.4 Mathematical preliminary: Using cos cos n = 1 2 cos( n), where n = 2,3,. . ., one can write:
2 2 1 2

cos( + n) +

cos() cos(n) d =
0 0

1 [cos((n + 1)) + cos((1 n))] d 2

2 2

(6.50) (6.51) (6.52)

= = =

1 2 1 2 1 2

cos(n + 1) d +
o 0 2

cos(1 n) d
2 0

sin(n + 1) n+1

+
0

sin(1 n) 1n

sin(n + 1)2 sin0 sin(1 n)2 sin 0 + n+1 n+1 1n 1n (6.53) (6.54)

=0 Note that if n = 1, then (6.50) becomes:

2 2

cos() cos() d =
0 0 2

cos2 1 [cos 2 + cos 0] d 2 sin 2 2

2

(6.55) (6.56) (6.57) (6.58)

=
0

1 2

+ []0
0

= 2

6-10

Line Frequency Uncontrolled Rectiers Remark 6.5 Remark 6.4 above shows that the product terms involving dierent frequencies integrate over the fundamental frequency to zero, whereas terms at the same frequency integrate to give a non-zero term. Substituting in (6.11) for vs and (6.13) for is , and noting from Remark 6.4 that the the integral of the cross-product terms are zero, we can write: P = 1 T1
T1 0

2Vs sin 1 t

2Is1 sin(1 t 1 )dt = Vs Is1 cos 1

(6.59)

Remark 6.6 Equation (6.59) shows that the harmonic currents DO NOT contribute to the average (real) power drawn from the source. Therefore, one can consider that the harmonics contribute to the reactive power drawn from the source. This is the basis for the generalisation of the concept of power factor. Note 6.1 The remark immediately above is true if the voltage on the supply remains purely sinusoidal. However, the presence of the harmonics can also cause the introduction of harmonic voltages because of the voltage drop across the transmission line impedances. Usually these impedances are reactive (inductive), and consequently the induced voltage across then is 90 out of phase with the current. Therefore the harmonic voltage appearing across the load is zero. Therefore, even under this condition the harmonic power is zero. However, if there is substantial resistance in the line, then there can be a harmonic voltage across the load that is approximately in-phase with the harmonic current. Under this condition the harmonic real power to the load is no longer zero. We can generalise the power factor expression by realising that the apparent power is simply: S = Vs Is (6.60) where Vs and Is are the true rms values of the voltage and the current (i.e. the rms value of a non-sinusoidal current). Therefore, using the same approach as that for sinusoidal quantities we can write: PF = P S (6.61)

Therefore, substituting in the denitions into this expression we can write: PF = Vs Is1 cos 1 Is1 = cos 1 Vs Is Is (6.62)

Remark 6.7 From (6.62) one can see that with a non-sinusoidal current source that the sinusoidal power factor is modied by the term Is1 /Is i.e. the fundamental current rms value divided by the total current rms value. Therefore, as the harmonics increase, the rms value of the current will increase, but the fundamental will not. Therefore the power factor will decrease. The normal power factor expression is given a new name in this context it is called the displacement power factor (DPF): DPF = cos 1 (6.63)

6.3 The Half Wave Rectier Circuit Therefore the power factor with the non-sinusoidal current is: PF = Is1 DPF Is (6.64)

6-11

Using (6.24) it is possible to write the power in terms of the total harmonic distortion: 1 DPF (6.65) PF = 1 + THD2 i

6.3

The Half Wave Rectier Circuit

We shall start our study of uncontrolled rectiers by looking at the simplest possible rectier circuit a single diode rectier.

6.3.1

Pure Resistive Load

The simplest possible load for the simplest possible rectier is a pure resistive load. The circuit and input and output current and voltages and shown in Figure 6.4. The operation of this circuit is very straight forward and does not warrant much further discussion. In addition, this circuit is not generally used because of the very high ripple in the output voltage and current. Because the output load is a pure resistance there is not output lter, and consequently the output voltage is not a very good dc voltage at all.
v diode + -

+
vs

vd

v s , vd

v diode
i, vd

v s , v diode

Figure 6.4: Half wave rectier with a resistive load.

6.3.2

Inductive Load

The case of a half wave rectier with a inductive-resistive load is more interesting than the previous case. With inductance in the load the current is more ltered

6-12

Line Frequency Uncontrolled Rectiers than the previous case. The following discussion is with reference to the circuit shown in Figure 6.5. The output plots have been generated by putting the circuit of Figure 6.6, with L = 200mH and R = 50, into the Saber , and running the simulation.

+ +
vs

v diode

vL

iL

L R

+
v out

Figure 6.5: Half wave rectier with an LR load.

The rst point that one notices in Figure 6.6 is that the current continues to ow even when the source voltage has gone negative. When the energy stored in the inductor reaches zero then the current stops owing. If the resistor value is made smaller then the current will ow further into the negative half cycle. If the resistance was zero then the current would continue to ow for the whole of the negative half cycle. Let us analyse the situation in Figure 6.6. At t = 0 then the diode becomes forward biased and current begins to ow. Assuming an ideal diode then the circuit whilst the current is owing is: di (6.66) dt At time t1 the current through the inductor reaches its peak value, since from t = 0 to t1 , vL = vs vout is positive. Notice that after t1 vL becomes negative as the source voltage decreases, and hence the current through the inductor starts to decrease. At time t2 vs becomes negative. However, the current through the inductor continues in the same direction due to the stored energy in the inductor. Eventually at t3 the energy in the inductor is exhausted and the current drops to zero. Because the current is zero at t = 0 and t3 , we can use the inductor current equation to write: vs = Ri + L i = i(t3 ) i(0) = 1 L
t3

vL dt = 0
0

(6.67)

since i(0) = i(t3 ). This means that the total area under the voltage curve across the inductor is zero (which it must be for the circuit to be in steady state). The integral in (6.67) can be written as follows:
t1 t3

vL dt +
0 t1

vL dt = 0

(6.68)

6.3 The Half Wave Rectier Circuit

6-13

t1
0.8 0.6

t2

t3

iL
(A)
0.4 0.2 0.0 -0.2 60.0 40.0 20.0

Due to simulation numerics

vs

v out

vL

(V)

Area A
0.0 -20.0 -40.0 -60.0 0.0 0.005 0.01 0.015 0.02 t(s) 0.025 0.03 0.035 0.04

Area B

v diode

Figure 6.6: Plots for a half wave rectier with an LR load L = 200mH and R = 50. which means that: Area A Area B = 0 (6.69)

Remark 6.8 To get the exact times for t1 , t2 and t3 one needs to solve (6.66).

6.3.3

Inductive Load with Back EMF

Another case of interest is the inductor feeding a back emf scenario. This is shown schematically in Figure 6.7. The voltage source Ed could represent a large capacitor, for example. The result of the presence of this voltage source is that the turn-on time for the diode is change as compared to the previous case. One can see the dierence in the performance of the circuit from the Saber simulation plots shown in Figure 6.8. One can see from Figure 6.8 that the inductor current iL has much the same shape as that shown in the Figure 6.6, but the magnitude of the current in smaller. This is an obvious result, since the voltage that can increase the current through the inductor is much smaller in this case because of the Ed voltage. In addition the time for the current to build up is also smaller. The other notable dierence between this case in that of Figure 6.6 is that the diode reverse voltage is substantially larger in this case.

6-14

Line Frequency Uncontrolled Rectiers

+ +

v diode

vL

iL

L +
vs

Ed

Figure 6.7: Half wave rectier circuit with an inductor and back emf.

t1

t2

t3

20.0 0.0 -20.0 -40.0 -60.0 -80.0 -100.0 0.2

v diode

(V)

iL

(A) (V)

0.0

-0.2 60.0 40.0 20.0 0.0 -20.0 -40.0 Area A Area B -60.0 0.0 0.005 0.01

Ed

vL

vs

0.015

0.02 t(s)

0.025

0.03

0.035

0.04

Figure 6.8: Plots for a half wave rectier with an inductor and back emf as a load.

6.4 The Concept of Current Commutation

6-15

6.4

The Concept of Current Commutation

Before looking at a practical single phase rectier circuit we shall briey look at the concept of current commutation in power electronic circuits. Although we shall be looking at this in terms of naturally (or self) commutated circuits, the same principles also apply to force commutated circuits. Up until this point we have not had to consider commutation issues because we have been dealing with a single diode circuit. Current commutation refers to the transfer of the current in a circuit from one power electronic device to another, as one device starts to turn o and the other turn on. In the case of a diode circuit the turn on occurs because the device becomes forward biased, and the turn o because a device becomes reverse biased. If one is dealing with an ideal circuit, then the current would transfer instantaneously from one device to another, but if there is inductance in the circuit then this does not occur instantaneously. In order to study current commutation consider the test circuit in Figure 6.9.
vL
Ls is

D1

+
vs

vD

D2

vd

Id

v s , vd
is

vd

Waveforms with Ls = 0

Figure 6.9: Test circuit used for current commutation discussion. The following discussion is with respect to Figure 6.10. Prior to t = 0 the input voltage vs < 0, and therefore the diode D2 is conducting the output current Id . At t = 0 vs becomes positive and the diode D1 becomes forward biased and turns on. However, due to the inductance Ls the current iD1 does

6-16

Line Frequency Uncontrolled Rectiers not instantly go to Id . The rise in the current in Ls is limited by the value of Ls and the voltage across it. Eventually the current in Ls will rise to the value if Id . During this rise the current iD2 will be falling at the same rate as the increase in iD1 , so that the current to the current source is maintained at Id . When iD1 = Id then the commutation process is complete, and the current iD2 = 0, turning o D2 .
i D1

vL
Ls

D1

+
vs

is

D2 i D2

Id

Id

vd = 0

(a) During commutation

is = I d

+ vL = 0
Ls

D1

+
vs

is

D2

Id

vd = v s

(b) After commutation

Figure 6.10: Circuit congurations during current commutation of the circuit in Figure 6.9. Let us analyse this situation as little more closely. Consider the situation when the input voltage vs initially becomes greater than zero. The voltage on the load side of the inductor is zero because D2 is on. Therefore the current across the inductor is: vL = 2Vs sin t = Ls dis dt 0 < t < tc (6.70)

where tc the time when commutation is complete. We can rearrange (6.70) and integrate both sides to give:
tc Id

2Vs
0

sin t dt = Ls
0

dis

(6.71)

6.4 The Concept of Current Commutation which becomes: Ac =

6-17

2Vs (1 cos tc ) = Ls Id

(6.72)

where Ac the volt-second area under the inductor voltage. Rearranging this expression we can write: Ls Id cos c = 1 2Vs where c tc , the commutation angle. (6.73)

Remark 6.9 Equation (6.73) conrms our previous assertion that if Ls = 0 then the commutation occurs immediately the diode D1 turns on i.e. cos c = 1 c = 0. Also note that as Ls increases the commutation angle increases (as one would intuitively expect), and as Id increases the angle increases due to the fact that it will take longer before iD1 = Id . Remark 6.10 Another interesting eect of the commutation is that the average voltage produced at the output of the circuit is lower due to commutation notches. These notches result in sections of vs not appearing at the output. Waveforms for the commutation of the current are shown in Figure 6.11. These waveforms are the outputs of a Saber simulation. These plots clearly show the commutation notches in the output voltage, vd . The commutation notches appear as the voltage across the Ls inductor. The area of these commutation notches, where the horizontal axis is = t, was evaluated in the expression (6.72). The plots of Figure 6.11, however, are on the time axis. Therefore, under this condition it can be shown that the expression for the area under the inductor notch is Ls Id (the term is omitted). Examination of the notch integral plot of Figure 6.11 shows that the area is 0.0050081 in other words Ls , which it should be since Id = 1. It is clear from Figure 6.11 that the commutation notches lower the output voltage. We can calculate voltage loss analytically. Firstly we can calculate the average output voltage as follows: 1 2 2 Vd0 = 2Vs sin t d(t) = Vs = 0.45Vs (6.74) 2 0 2 In the case where one has commutation notches then the average voltage can be calculated as: 1 Vd = 2Vs sin t d(t) (6.75) 2 c This expression can be rewritten as the average voltage with Ls = 0 minus the average voltage of the commutation notches: Vd = 1 2
0

commutation notches

2Vs sin t d(t)

1 2

c 0

2Vs sin t d(t)

(6.76) (6.77) (6.78)

area Ac 2 Ls = 0.45Vs Id 2 = 0.45Vs

6-18

Line Frequency Uncontrolled Rectiers

(V*sec) : t(s) 0.006 Notch Area

(V*sec)

0.004 (0.020805, 0.0050081) 0.002 0.0 20.0 10.0 (0.020007, 0.10216)

(V) : t(s)

Comm notches vL

(V)

0.0 -10.0 -20.0 1.0 (0.020807, -0.022068) (A) : t(s)

Inductor current i L , is

(A)

0.5

0.0 (V) : t(s) 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0 0.0 0.005 0.01

Output vd

vs

(V)

vD

Output vd
0.015 0.02 t(s) 0.025 0.03 0.035 0.04

Figure 6.11: Plots of the currents in the test circuit of Figure 6.9 vs = 50 sin t, Ls = 5mH, Id = 1 Amp.

6.5 Practical Uncontrolled Single Phase Rectiers Remark 6.11 From equation (6.78) one can see that the loss of output voltage is: area Ac Ls Vd = = Id (6.79) 2 2

6-19

6.5

Practical Uncontrolled Single Phase Rectiers

We have now carried out some preliminary analysis on half wave rectiers to develop some techniques to analyse rectier circuits. We shall now apply these techniques to a practical single phase rectier. These circuits are very important, as they form the front end of almost all switch mode power supplies used in domestic and computing applications. Remark 6.12 The prevalence of the single phase rectier in computer based equipment is becoming a problem in power systems due to the harmonics that they inject into the power supply. This results in poor power factor, and can lead to heating problems in other pieces of equipment, and occasionally causing false triggering of frequency controlled equipment on the network. The circuit which is the subject of this section is shown in Figure 6.12. This is typical of a rectier used in a linear or switch mode power supply.
id

Ls

Rs

+
vs

is
Cd

vd

Rload

Figure 6.12: A practical single phase rectier. If we assume that the current id is discontinuous due to the capacitor voltage resulting in the current going to zero before the end of the half cycle of the input voltage (similarly to the waveforms for the circuit in Section 6.3.3), then we dont have to worry about the current commutation from one diode to another. We shall generate the analytical equations for the circuit under these conditions. We shall not solve the equations, as this is a little complicated, but the solutions are obtainable. If there is current commutation in the circuit then the solutions get a little more complicated.

6-20

Line Frequency Uncontrolled Rectiers Whilst the diodes are conducting the equivalent circuit is as shown in Figure 6.13. Applying KVL to this circuit we can write the following dierential equation: did vs = Rs id + Ls + vd (6.80) dt Similarly one can also apply KCL to the circuit to give: id = Cd dvd vd + dt Rload (6.81)

Rearranging we can write the following matrix expressions when the diode is conducting:
did dt dvd dt

s Rs L

1 Cd

1 Cd Rload

1 Ls

id vd

1 Ls

vs

(6.82)

Ls

Rs

id

+
vs

Cd

vd

Rload

Figure 6.13: Equivalent circuit of the single phase rectier when the diodes are conducting. During the time when the diodes are o (i.e. when the energy in Ls has been expended and vs < vd ), the capacitor is discharging into the load resistor. Therefore there is an exponential decay of the output voltage. The expression for this time is (using KCL): Cd dvd vd + =0 dt Rload dvd vd = dt Cd Rload (6.83) (6.84)

Remark 6.13 Using equations (6.82) and (6.84) one can solve for the complete analytical solution for the currents and the voltages in this circuit. We shall not attempt to solve (6.82) and (6.84), but instead we shall simulate the circuit of Figure 6.12 using Saber . The plots in Figure 6.14 are the output waveforms of this circuit. In particular notice the very spikey current owing into the rectier, and the ripples on the output voltage due to this, and the discharge time when all the diodes are o and the output is disconnected from the input.

6.5 Practical Uncontrolled Single Phase Rectiers

6-21

40.0

80.0

(V) : t(s)

vd
(A) : t(s)

60.0 20.0

is
(V)
40.0

(A)
0.0

20.0

-20.0

0.0 60.0 40.0 20.0 (V) : t(s)

vs

(V)

0.0 -20.0 -40.0 -60.0 0.0 0.025 0.05 0.075 0.1 t(s) 0.125 0.15 0.175 0.2

Figure 6.14: Waveforms for the practical single phase rectier circuit of Figure 6.12.

6-22

Line Frequency Uncontrolled Rectiers If one evaluates that harmonics on the current waveform the plot shown in Figure 6.15 is obtained. One can see that the output voltage has a dominant dc component (as it should) which has an amplitude of approximately 47 volts. There is also a harmonic at 100Hz corresponding to the fundamental of the ripple on the dc output voltage. The main harmonic in the current is at 50Hz, but there are also signicant harmonics at 150, 250 and 350Hz as well (i.e. the 3rd, 5th and 7th harmonics). One can treat each of the harmonics in the current as a phasor (as in (6.7)). The amplitudes of the real and imaginary components of these phasors can be found using the waveform analysis tools in Saber , and these are plotted in Figure 6.16.

Mag(A) : f(Hz) 6.0

is

4.0

Mag(A)
2.0 0.0 60.0

Mag(V) : f(Hz)

vd

40.0

Mag(V)
20.0 0.0 0.0 50.0 100.0 0.15k 0.2k 0.25k 0.3k 0.35k f(Hz) 0.4k 0.45k 0.5k 0.55k 0.6k 0.65k 0.7k

Figure 6.15: Input current and output voltage harmonics in a single phase rectier.

In Figure 6.16 one can see the amplitude of the fundamental real and imaginary harmonics a1 = 0.40077 and b1 = 4.6573.8 Therefore using the
8 In Saber the b coecient is called the imaginary coecient. It is the negative of the actual b coecient as appears in a normal Fourier series. Hence we have written the coecient as b1 .

6.5 Practical Uncontrolled Single Phase Rectiers

6-23

Fourier components generated before 140msec and 180msec

1.0

Re(A) : f(Hz)

is

0.0

Re(A)

(50.0, -0.40077) -1.0

-2.0 4.0

Im(A) : f(Hz)

is

2.0

0.0

Im(A)
-2.0 -4.0 (50.0, -4.6573) -6.0 0.0 50.0 100.0 0.15k 0.2k 0.25k 0.3k 0.35k f(Hz) 0.4k 0.45k 0.5k 0.55k 0.6k 0.65k 0.7k

Figure 6.16: Real and imaginary components of the harmonic phasors for the harmonics single phase rectier harmonics plotted in Figure 6.14.

6-24

Line Frequency Uncontrolled Rectiers denitions associated with (6.7) one can see that: F (1) = a2 + b2 = 4.4745 Amp 1 1 b1 = 265.08 = 94.92 a1 (6.85) (6.86)

1 = tan1

Comparison of (6.85) with the fundamental shown in Figure 6.15 indicates that the value appears to be correct. The phase in (6.86) is the phase of a cos waveform (which is the time domain representation of a phasor). The harmonics in Figure 6.15 and Figure 6.16 were taken by looking at the input current over two fundamental periods of the input voltage starting at 120msec and ending at 180msec. This was done so that the rectier was operating in steady state, and the transients that can be seen in Figure 6.14 would not aect the harmonic analysis. This also means that the phase in (6.86) is with respect to the voltage input waveform. Consequently we can use the value in (6.86) to get the phase (and hence power factor) of the current fundamental. Realising that the time domain form of the phasor is: fn (t) = Fn cos(n1 t + n ) (6.87)

one can write the time domain expression for the fundamental current as: i1 (t) = I cos(1 t + 1 ) = 4.47 cos(100t 94.92 )

(6.88) (6.89)

Using the trigonometric identity cos(x) = sin(x + 90 ) then we can write: i1 (t) = 4.47 sin(100t 4.92 ) (6.90)

Hence there is a phase shift of the fundamental from the input voltage of 4.92 . Consequently, from (6.63) we can see that the DPF is: DPF = cos 1 = cos(4.92 ) = 0.996 (6.91)

Remark 6.14 From a fundamental current view point the power factor of the system is very good. The presence of harmonics is the main contributor to poor power factor. The non-sinusoidal power factor is dened by (6.64). Therefore if we can calculate the rms value of the non-sinusoidal current then we can calculate the non-sinusoidal power factor. From Figure 6.15 one can see that the harmonics amplitudes and rms values are as shown in Table 6.2. Using (6.24) we can now calculated the THD for the input current waveform. Calculating the distorted current using (6.21) we get:
13

Idis =
n=1

2 Isn = 3.1076

(6.92)

6.5 Practical Uncontrolled Single Phase Rectiers Harmonic 1 3 5 7 9 11 13 Amplitude 4.6775 3.6788 2.1911 0.87625 0.30301 0.29773 0.18 RMS value 3.3054 2.6013 1.5493 0.6196 0.2143 0.2105 0.1273

6-25

Table 6.2: Current harmonic amplitudes. Therefore the input current THD is: THD = 100 Idis Is1 3.1076 = 100 3.3054 = 94%

(6.93)

Remark 6.15 The value in (6.93) shows that the harmonic distortion of the input current is quite high. We can now also calculate the non-sinusoidal power factor using (6.62): PF = Is1 cos 1 Is 3.3054 0.996 = 3.10762 + 3.30542 = 0.73

(6.94)

using (6.19). Remark 6.16 From (6.94) one can see that the power factor has been lowered by the presence of the harmonics. Compare this to the DPF which is 0.996. Therefore the presence of the harmonics in the input current waveform is a major contributor to the poor power factor of this circuit. Remark 6.17 Single phase full wave rectiers such as depicted in Figure 6.12 are present in large numbers on the power supply grid (e.g. in computer power supplies). Therefore the cumulative aect of this could result in a very poor overall power factor. Techniques for improving the power factor of this rectiers are now being used.

6.5.1

Unity Power Factor Single Phase Rectier

The requirement for unity power factor (which implies low harmonic content) for single phase rectiers connected to the grid has spurred research into techniques to modify the standard single phase full wave rectier. One of the standard techniques to lter supply current waveforms is to use passive lters at the input of rectier. These passive lters usually consisted of combinations of L or LC components. An example of a circuit with this type

6-26

Line Frequency Uncontrolled Rectiers of ltering is shown in Figure 6.17 [2]. This particular circuit has lters at the ac input and the dc output. The input lter is a classic T low pass lter. This lter basically lters out the higher order harmonics in the input current. The lter in the dc link needs a little explanation. Clearly it is also a low pass lter, and appears to have the classic structure. The choice of the size of the components is important from another point of view. The capacitor Cd1 is chosen to be small so that there is considerable ripple in the vd1 voltage. This causes the current to ow in smoother fashion from the supply via the diodes. The extra ripple in vd1 is then ltered via the low pass lter formed by Ld and Cd . The Cd capacitor is much larger than Cd1 .
Ld

id

Lf 1

Lf 2

+
vs

is
Cf

C d1

vd1

Cd

Rload

vd

Figure 6.17: Single phase rectier with input and dc link lters.

Remark 6.18 The passive circuits have a limited capacity to smooth the input current. The ltering achieved is capable of improving the power factor the acceptable levels. However there are some shortcomings: a. The output voltage is lowered due to the presence of the inductors. b. There is an obvious disadvantage in the cost of the lters, size, losses and dependence of the output voltage on the load current drawn. The limitations cited in Remark 6.18 have led to the investigation of active current shaping techniques to improve the power factor of the rectiers. These techniques also have the advantage that they extend the range of operation of the rectier i.e. the input voltage can vary but the output voltage will stay constant. For any current shaping circuit to be of practical use it has to have the following attributes: The current shaping circuit should be of low cost and small size. It should enable the input power factor to be near unity. The circuit should be simple to control. It should allow the rectier to provide the correct voltages under overvoltage as well as under-voltage conditions.

6.5 Practical Uncontrolled Single Phase Rectiers Given these specications the obvious circuit to provide this functionality is the boost converter. This circuit is the most suitable for the following reasons: a. The circuit is capable of producing an higher voltage at the output than at the input. Therefore as the input voltage falls the output voltage can be kept constant. b. If the converter is set-up to provide an output voltage, that is say 10% higher than the nominal peak input voltage, then the circuit can cope with over-voltages of up to 10% without altering the output voltage. c. The boost converter conguration maintains a continuous current through the input inductor (if operating is continuous conduction mode). Therefore the current can be kept continuous through the diodes on the circuit. This intrinsically allows better input power factor to be achieved. Remark 6.19 Note that the buck converter is in general not suitable for this application because the input current is highly discontinuous. This is due to the fact that the switch in the circuit disconnects the output of the diodes in the rectier from the input to the converter during normal operation. Figure 6.18 shows the basic structure of a single phase rectier with a boost converter for current shaping.
Boost converter

6-27

Ld iL

id

i load

Ls

Rs

ic

+
vs

is

vs

Cd

Rload

vd (> v s )

Figure 6.18: Circuit for the a single phase rectier with current wave shaping boost converter. As can be seen from Figure 6.18 the circuit is simply a conventional rectier followed by a conventional non-isolated boost converter. The boost converter is usually controlled so that the output voltage is approximately 10% higher than the nominal rated voltage of the rectier. This allows the circuit to work correctly if the supply is up to 10% higher than the nominal voltage. One implicitly gets a circuit that can operate with low voltages because of the boost converter. How low the voltage can go depends on the design of the boost converter and the load current and voltage required.

6-28

Line Frequency Uncontrolled Rectiers The key to the operation of the unity power factor rectier is the control of the boost converter. Before considering the general principles of the control we rstly need to clarify the requirements for the control. If we want unity power factor, than we need a sinusoidal input current which is in phase with the input voltage and does not have any signicant harmonics. The desired waveforms are shown in Figure 6.19(a) and (b). One can see that the waveforms in the boost converter section of the circuit are sinusoidal in nature.
vs

is

wt

(a)
vs
iL

wt

(b)

Figure 6.19: Waveforms for a single phase rectier with active current waveshaping (a) the input current and voltage; (b) the boost converter input voltage and inductor current. Remark 6.20 Examination of the waveforms in Figure 6.19 indicate that there will be a ripple voltage on the output lter capacitor (as there is in the conventional rectier). The capacitor has to be designed to be large enough to keep this ripple below acceptable limits. Ignoring power losses in the boost converter we can apply some basic analysis to the circuit of Figure 6.18 with the waveforms of Figure 6.19. Dene Vs = 2Vs , and Is = 2Is i.e. Vs and Is are the rms values of the voltage and the current. Clearly the instantaneous power owing into the circuit is (using sin2 x = 1 (1 cos 2x)): 2 pin (t) = Vs sin tIs sin t = Vs Is Vs Is cos 2t (6.95)

6.5 Practical Uncontrolled Single Phase Rectiers which is similar to (6.35), except that this was calculated for cos waveforms with a phase dierence between them. If we assume that the output capacitor is large then the voltage ripple across it will be minimal, and consequently the output power can be written as: pd (t) = Vd id (6.96)

6-29

where Vd the average output voltage = vd . The current owing into the load and the capacitor is: id (t) = Iload + ic (t) (6.97) Assuming that the switching frequency is very high then the inductor can be negligibly small. This allows one to use the simplifying assumption that on an instantaneous basis that: pin (t) = pd (t) (6.98) and therefore we can write: Vs Is Vs Is cos 2t = Vd id (t) id (t) = Iload + ic (t) = One can see from this expression that: Id = Iload = ic (t) = Vs Is Vd (6.101) (6.102) Vs Is Vs Is cos 2t Vd Vd (6.99) (6.100)

Vs Is cos 2t = Id cos 2t Vd

Even though the assumption was made that the voltage across the capacitor was constant, we can use (6.102) to get an approximate value of the voltage ripple across the capacitor: vd,ripple (t) 1 Cd ic (t) dt = Id sin 2t 2Cd (6.103)

Remark 6.21 From (6.103) it can be seen that if Cd is made large then vd,ripple can be arbitrarily small. The key to the correct functioning of this circuit is the control. Two control loops are required in order to achieve the required control a voltage control loop so that the output voltage stays are the correct value despite load variations, and a current control loop to provide the input current wave-shaping. These two loops have to work cooperatively. We have previously encountered both voltage and current control loops, arranged in a hierarchical or nested structure, in relation to switched mode power supply control. A similar arrangement is used here, the main dierence being the desired reference value for the current. Figure 6.20 shows a block diagram of the basic structure of the control for the unity power factor single phase rectier. This block diagram is almost the same as that shown in Figure 3.25. The major dierence is the inclusion of the multiplier of the error by the absolute value of the supply voltage, which results in a sinusoidal rectied inductor current reference waveform. This is

6-30

Line Frequency Uncontrolled Rectiers then fed to the current control algorithm. The current control algorithm can be implemented in a variety of ways (see Section 3.3.3.3), but the most common technique is the constant frequency with turn-on at clock time controller.

vs
e = Vd* -Vd ,measured

Vd*

PI Regulator

* iL

Current mode control

Switch control signal

Vd,measured

i L,measued

Figure 6.20: Block diagram of the control system for a single phase rectier with active current wave-shaping. With this control strategy the net result is that the sinusoidal reference current amplitude is modulated by the output voltage error the larger the voltage error the larger the amplitude of the sinusoidal current pulse. Some other points to note about this circuit: a. A resistor in series with the Ld inductor is often used to limit the inrush current at start-up. This resistor is usually shorted out by a SCR (large voltage drop with this though), a relay or a MOSFET once the circuit starts to operate normally. b. A small lter capacitor is usually placed across the output of the diode bridge to prevent the switching noise from entering the grid supply. c. The output lter capacitor only has to be about half the size of that in an uncontrolled rectier, for the same ripple. Therefore the active rectier circuit saves on weight and space. d. The energy eciency of a typical active current controlled signal phase rectier is 96%. An uncontrolled conventional rectier has an eciency of approximately 99%.

6.5.2

Eect of Current Harmonics on Line Voltages

We have seen in Section 6.5 that the single phase rectier can produce many harmonics in the current. In the subsequent analysis of the power factor of the circuit it was assumed (for simplicity reasons) that the voltage was unaected by the presence of these harmonics. However, in a real network this is not the case. Consider the circuit shown in Figure 6.21. Here we can see a conventional single phase rectier connected to the grid supply via a source resistance and inductance. Note that the inductance is divided into two sections, the section between them being the so called point of common coupling (PCC). The PCC is the nearest point to the rectier where other equipment can be connected

6.5 Practical Uncontrolled Single Phase Rectiers to the grid supply. Note that there is an additional inductance, representing the inductance of the grid supply, between the PCC and the grid supply voltage source. It is the inductance of this impedance that causes the current harmonics to aect the supply voltage seen by other devices connected to the grid supply.
Point of common coupling (PCC)
id

6-31

Ls2

Ls1

Rs

+
vs

is

v PCC

Cd

vd

Rload

Other equipment connected to the supply

Figure 6.21: Single phase rectier showing the point of common coupling. The voltage across other equipment at the PCC is: dis1 (6.104) dt where vs is assumed to be an ideal sinusoidal voltage source. The current is1 contains the harmonic currents of the single phase rectier (as well as the harmonics drawn by the other equipment). These harmonics will cause a voltage drop across the Ls1 inductance. This drop can be considerable, since the impedance of an inductor increases with increased frequency. One can break the current into a sinusoidal component and the distorted components as follows: vP CC = vs Ls1 vP CC = vs Ls1 dis1 dt Ls1
h=1

dish dt

(6.105)

Clearly the fundamental component is: vP CC1 = vs Ls1 and the distortion component is: vP CCdis = Ls1
h=1

dis1 dt dish dt

(6.106)

(6.107)

6.5.3

Voltage Doubler Single Phase Rectiers

The circuit shown in Figure 6.22 is sometimes used in cost conscious commercial products to produce voltage doubling without the use of a transformer. Depending on the position of the switch the rectied dc voltage is either approximately

6-32

Line Frequency Uncontrolled Rectiers the peak of the sinusoidal input voltage, or alternatively it is twice this peak voltage.

D1

C1

vac

D2

Double pos

vd
C2

Figure 6.22: Single phase rectier voltage doubler. If the switch is closed then on a positive half cycle of the input voltage current ows via D1 , capacitor C1 , and the switch back to the supply. On the negative half cycle the current ow via the switch, capacitor C2 and diode D2 back to the supply. The result is that the two capacitors have the peak supply voltage across them, and their voltages sum. If the switch is open, then the circuit behaves as conventional bridge rectier.

6.5.4

The Eect of Single Phase Rectiers on Three Phase, Four Wire Systems

In large commercial buildings the primary loads are of a single phase nature, even though the building as a whole is supplied with a three phase power system. These single phase loads are usually distributed as evenly as possible between each of the three phases and the neutral of the system, as shown in Figure 6.23. If the loads on the system are linear loads then such a strategy will lead to a neutral current that is approximately zero. However, if the loads are largely single phase rectiers, the non-linear nature of these loads can lead to substantial neutral currents. Assume that the diode rectiers in each of the phases are identical. We can therefore write the currents in the phases as a combination of the fundamental and harmonics currents (which are the odd harmonics, since, as shown previously, the even harmonics are zero):

ia = ia1 +
h=2k+1

iah

(6.108) 2Ish sin(h t h )

2Is1 sin(1 t 1 ) +
h=2k+1

(6.109)

6.5 Practical Uncontrolled Single Phase Rectiers

6-33

ia

ib

a b n

ic

in

Single phase rectifier loads

Figure 6.23: Single phase rectiers loads in a three phase, four wire distribution system.

6-34

Line Frequency Uncontrolled Rectiers In a similar manner to (6.109) one can write the other currents in the phases (assuming they are of similar form): ib =

2Is1 sin(1 t 1 120 ) +

h=2k+1

2Ish sin(h t h 120 h) (6.110)

ic =

2Is1 sin(1 t 1 240 ) +

h=2k+1

2Ish sin(h t h 240 h) (6.111)

Applying Kirchhos current law to Figure 6.23 we can write: in = ia + ib + ic (6.112)

If one substitutes (6.109), (6.110) and (6.111) into (6.112) then all the nontriplen and fundamental harmonics add to be zero. The triplen harmonics on the other hand add to give:

in = 3
h=3(2k1)

2Ish sin(h h )

(6.113)

which can be written in rms terms as: In = 3

1/2
2 Ish

(6.114)

h=3(2k1)

Therefore the third harmonics add together in the neutral, and the neutral current therefore becomes: In = 3Is3 (6.115) The third harmonic current in the lines can be quite signicant with single phase rectier loads, and consequently the neutral current can be large. In fact under conditions of highly non-linear loads, the neutral current can be as much as 3Iline . Therefore, the neutral should be a conductor that can at least carry as much as the lines.

6.6

Three Phase, Full Bridge Rectiers

Whilst single phase rectiers predominate in domestic and computer rectication applications, industrial rectication is carried mainly with three phase rectiers. This is due to their lower voltage and current ripple, and their higher power carrying capabilities. These devices naturally balance the loading on each of the phases, and therefore do not require any planning action in this respect. Furthermore, no triplen harmonics can ow in these circuits since there is no neutral connection. The fundamental circuit for the conventional six pulse three phase rectier is shown in Figure 6.24. In order to understand the operation of this device we shall rstly look at a simplied model of its operation. Assume that the load is not modeled as an

6.6 Three Phase, Full Bridge Rectiers

id D1 D3 D5

6-35

a + b n c + +

Ls

Ls

ia
Cd

Rload

vd

Ls

ib

ic
D4 D6 D2

Figure 6.24: Basic three phase, six pulse, full wave rectier circuit. RC as in Figure 6.24, but as a constant current sink. This is an approximation to a highly inductive load. The plots of the phase currents and output voltages of this converter are shown in Figure 6.25. As can be seen from this diagram, the output voltage consists of 6 segments per input voltage period. Therefore this rectier is often known as a six pulse rectier.

6-36

Line Frequency Uncontrolled Rectiers

Graph0 (A) : t(s) 5.0 (A) i(v_sin.phase_c)

0.0

-5.0 (A) : t(s) 5.0 (A) i(v_sin.phase_b)

0.0

-5.0 (A) : t(s) 5.0 (A) i(v_sin.phase_a)

0.0

-5.0 (V) : t(s) 400.0 200.0 (V) 0.0 -200.0 -400.0 600.0 400.0 200.0 0.0 0.0 0.01 0.02 0.03 0.04 0.05 t(s) 0.06 0.07 0.08 0.09 v(v_sin.phase_c) (V) : t(s) output_voltage v(v_sin.phase_b) v(v_sin.phase_a)

Figure 6.25: Waveforms of a three phase rectier with a constant current source load.

(V)

Chapter 7

Introduction to Other Power Electronic Devices and Applications

7.1 Introduction

This chapter briey introduces several other high power, power electronic switching devices and applications that are industrially important. The presentation here is brief and introductory in nature, and by no means comprehensive. It is intended to introduce the student to other power electronic circuits, hitherto not considered, and some of their applications. The applications chosen are, hopefully, those that are interesting to the readers. Those who wish to research into any of the circuits and applications presented are encouraged to follow up the topics in the references. The remainder of this chapter will consider the following: Inverters and applications Multilevel converters and applications Matrix converters

7.2

Inverters and Applications

In the previous chapter we briey considered rectiers. A rectier is the name given to a power electronic device which accepts AC voltage at its input, and recties this to DC voltage at the output. The power ow is considered to be from the AC to the DC side. The term rectier refers to the operational function of the power electronic hardware, but not the conguration of the hardware. This distinction is demonstrated by the cycloconverter. The cycloconverter uses power electronic hardware that is virtually the same as that of a phase controlled rectier and generates AC output voltages from AC input voltages. Power can ow bidirectionally in these devices.

7-2

Introduction to Other Power Electronic Devices and Applications

Rectifier mode P

AC

CONVERTER

DC

P Inverter mode
Figure 7.1: Denition of rectier and inverter modes of operation [2]. An inverter, is the dual of the rectier, in that it accepts DC input and generates an AC output i.e. power ow is from the DC to the AC side of the power electronic device. As with the rectier, this denition does not dene the hardware conguration, since it is possible to have the same hardware acting as an inverter and rectier. The above is summarised in Figure 7.1. Consider, for example, the rectier considered at the end of Chapter 6, i.e. Figure 6.24. In this circuit that main electronic components are diodes. Diodes can only conduct current in one direction. Therefore, if the output voltage is only allowed to be one polarity, then power cannot be transferred from the DC side to the AC side of the converter, as current cannot ow in the reverse direction through the diodes. It is this fact that denes this circuit to be a rectier.

Input

Converter 1 Energy Storage Element

Converter 2

Output

Figure 7.2: Generic power processing block [2]. Many power electronic systems have the conguration shown in Figure 7.2. Converter 1 transforms the input to DC. There is a storage element that is able to accept the energy. Converter 2 then converters to DC to the desired output. The energy storage element is typically a capacitor or inductor. Its presence means that the instantaneous input power does not have to equal to instantaneous output power, thereby providing a degree of decoupling of the input from the output, and allowing a degree of independence in the control

7.2 Inverters and Applications and operation of the two converters.

DC link

7-3

AC Utility

Converter 1

Converter 2

AC

AC Motor

Figure 7.3: Block diagram of a generic AC drive system. Figure 7.3 shows a less abstract version of Figure 7.2 for one form of an AC drive system. Notice that in this particular case to energy storage element is a capacitor. Both the input and the output is AC. Therefore, in this application there is inherently an inversion process, since one way or another power must go from the DC to AC side. In many actual implementations of Figure 7.3 Converter 1 is a rectier, and Converter 2 is an inverter. This means that power can only ow from the utility to the motor, and not in the reverse direction since the rectier cannot transfer power back to the utility. Depending on the details of the implementation of Converter 2, it is possible that it can act as a rectier, and power can from the motor (which is now acting as a generator, the mode being called regeneration) back to the DC link. In this case the capacitor can accept the energy, but one must be careful to ensure that not too much energy is transferred, else the capacitor will experience over-voltage and be destroyed. If a motor is going to be regenerating for a signicant percentage of time during operation, then both Converter 1 and Converter 2 need to be able to act as both a rectier and an inverter. If this is the situation then regenerated energy can be transferred back to the utility supply, and the capacitor voltage can be controlled to remain within bounds. Remark 7.1 It is possible to further classify inverters based on the type of technology used to implement the inverter forced commutated converters, resonant link converters. We shall not look a these dierences in detail here.

Figure 7.4 shows a specic implementation of an inverter. The main dierence between this and Figure 6.24 is that the diodes in the circuit are in parallel with a switch. Most modern small to medium power inverters these days use IGBTs as the switch. The arrows on the switches in Figure 7.4 indicate that this is the direction that current can ow through the switch. The presence of the parallel switches across the diodes makes a major difference to the operation of this circuit. By appropriate switching of the six switches an AC voltage (in an average sense) can be synthesized on the three phase outputs of the inverter. The presence of the diodes, of course, means that the circuit can always operate as a rectier. In fact, this very circuit is now coming into use as the rectier front end to large drive systems. Its ability to allow bidirectional power ow means that this rectier allows a fully regenerative system.

7-4

Introduction to Other Power Electronic Devices and Applications

DC link Artificial ground

3 phase AC load
vag

a DC + g c b Z
vbg

Z
vcg

Figure 7.4: Specic implementation of an inverter.

7.2.1

Pulse Width Modulation

Thus far we have only considered one form of the hardware for an inverter. In order for an inverter to work, there has to be a strategy for controlling the switches. In section 1.3.2.2 on page 1-10 the essential ideas behind a triangular wave PWM modulator was briey discussed. Furthermore, in section 2.4.2 on page 2-11 we considered how to generate a Pulse Width Modulator based on sawtooth modulation waveforms to produce a desired average output voltage for a switched mode power supply. Therefore this section, is to some degree, a brief rehash of this material. The reader is referred to the sections 1.3.2.2 and 2.4.2. The essentials of this technique are shown in Figure 2.11 on page 2-13. The same technique can be used for three phase systems. If we consider just one leg of the three phase converter of Figure 7.4, then the technique outlined in sections 2.4.2 on page 2-11 and 1.3.2.2 on page 1-10 can be applied directly. When the reference waveform exceeds the triangular waveform then the top switch in the leg is turned on, and the bottom leg o. When the reference waveform is less that the triangular waveform, then the bottom transistor is turned on and the bottom transistor is turned o. The waveforms produced when the centre of the DC link is used as the reference point for the voltage are shown in Figure 7.5. Remark 7.2 Note that the fact that the load is referenced to the centre of the DC link allows true AC voltage and AC current to be applied to the load. This is similar to the situation in the three phase inverter. In the case of a three phase inverter to see how the waveforms appear is a little more complex, and not quite as obvious. As in the single leg case one needs to establish a reference point to dene the voltages, and similarly the mid point of the DC link is often chosen. Therefore, if the top switch of a leg is closed (meaning that the bottom switch is open) then the voltage on the 1 phase output terminal is 2 VDC where VDC is the total voltage across the DC

7.2 Inverters and Applications

7-5

DC link

Modulator

Reference waveform Carrier waveform

Approximate fundamental

Figure 7.5: Single leg of inverter and the PWM waveforms.

7-6

Introduction to Other Power Electronic Devices and Applications link. Similarly if the bottom switch is closed (meaning that the top switch is 1 open), then the voltage on the phase output terminal is 2 VDC . Therefore, the output of a single leg has two values. Therefore with three legs we have 23 = 8 possible unique output voltage combinations, corresponding the 8 dierent possible switching combinations. A notation that we shall use is that the leg switching states are represented by a binary value a 1 denotes that the top switch of a leg is closed, and the bottom switch is open, and a 0 denotes that the top switch is open and the bottom switch is closed. Therefore, the possible switching combinations, with the phase leg voltages with respect to the mid link ground point (denoted as g), and the line-to-line voltages across a three phase load (such as that in Figure 7.4) are shown in Table 7.1. Switch pattern abc 000 001 010 011 100 101 110 111 vag 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC vbg 1 VDC 2 1 VDC 2 1 2 VDC 1 2 VDC 1 VDC 2 1 VDC 2 1 2 VDC 1 2 VDC vcg 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 VDC 2 1 2 VDC 1 2 VDC 1 2 VDC vab 0 0 VDC VDC VDC VDC 0 0 vbc 0 VDC VDC 0 0 VDC VDC 0 vca 0 VDC 0 VDC VDC 0 VDC 0

Table 7.1: Switching combinations and associated phase and line-to-line voltages. Remark 7.3 Note from Table 7.1 that the line-to-line voltages always add together to be zero (similar to line-to-line voltages in a sinusoidal three phase system). Remark 7.4 Note also from Table 7.1 that two of the switching states lead to zero line-to-line voltages. These two states correspond to all the top switches on, or all the bottom switches on. These switching combinations lead to a short circuit across the three phases. The phase voltages i.e. van , vbn , vcn are also of interest. Let us consider switching state 001 as an example. In this case we have: vab = van vbn = 0 vbc = vbn vcn = VDC vca = vcn van = VDC (7.1) (7.2) (7.3)

One can immediately see from (7.1) that van = vbn . However, these equations are not independent, and therefore one cannot solve for the phase voltages. If one considers the three phase load to be a passive one of the form shown in Figure 7.4, then one can write, using Kirchos voltage law, the following expressions: vag = ia Z + vn vbg = ib Z + vn vcg = ic Z + vn (7.4) (7.5) (7.6)

7.2 Inverters and Applications Adding these equations together we can write: vag + vbg + vcg = (ia + ib + ic )Z + 3vn Because the load is star connected then we know that: ia + ib + ic = 0 and hence (7.7) becomes: vag + vbg + vcg = 3vn 1 vn = (vag + vbg + vcg ) 3 (7.9) (7.10) (7.8) (7.7)

7-7

Using (7.10) one can therefore write the following expressions for the phaseto-neutral voltages: van = vag vn = vbn vcn 1 1 2 vag vbg vcg 3 3 3 2 1 1 = vbg vn = vbg vag vcg 3 3 3 1 1 2 = vcg vn = vcg vag vbg 3 3 3 (7.11) (7.12) (7.13)

Using equations (7.11), (7.12) and (7.13) together with the values for the voltages vag , vbg and vcg in Table 7.1 one can write all the values for the phase voltages that can be produced by the inverter. These appear in Table 7.2. Switch pattern abc 000 001 010 011 100 101 110 111 vag 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC vbg 1 VDC 2 1 VDC 2 1 2 VDC 1 2 VDC 1 VDC 2 1 VDC 2 1 2 VDC 1 2 VDC vcg 1 2 VDC 1 2 VDC 1 VDC 2 1 2 VDC 1 VDC 2 1 2 VDC 1 VDC 2 1 2 VDC van 0 1 VDC 3 1 VDC 3 2 VDC 3 2 3 VDC 1 3 VDC 1 3 VDC 0 vbn 0 1 3 VDC 2 3 VDC 1 3 VDC 1 VDC 3 2 VDC 3 1 3 VDC 0 vcn 0 2 VDC 3 1 VDC 3 1 3 VDC 1 VDC 3 1 3 VDC 2 VDC 3 0

Table 7.2: Switching combinations and associated phase and phase-to-neutral voltages. Remark 7.5 Adding together equations (7.11),(7.12) and (7.13) one gets: van + vbn + vcn = 2 1 1 (vag + vbg + vcg ) (vag + vbg + vcg ) (vag + vbg + vcg ) 3 3 3 (7.14) (7.15)

van + vbn + vcn = 0

Therefore the phase voltages always add to be zero, regardless of the applied voltages, when the three phase load is passive. It can be shown that this also applies if there are three phase sinusoidal voltage sources in the load as well.

7-8

Introduction to Other Power Electronic Devices and Applications Remark 7.6 The neutral voltage of the three phase load moves around relative to the ground at the mid point of the DC link. Consider the extreme cases of switching patterns 000 and 111. For 000, using (7.10) and substituting for the voltages from Table 7.2 one can see that vn = 1 VDC . Similarly for the case 2 of 111 we get vn = 1 VDC . Therefore the neutral voltage has moved around by 2 VDC . These large voltage excursions in the neutral can cause bearing currents to ow when electrical machines are the load on the inverter. 7.2.1.1 Space Vectors and PWM

If an electrical machine is used as the load on an inverter, then space vectors can be used to represent the phase voltages. These phase voltages are appearing across the phases of the machine. Almost all AC machines are wound so that their windings are sinusoidally distributed in space. This fact allows a space vector concept to be used to represent currents, uxes, mmfs, and voltages in the machine. Refer to [14, 2] for more detail. In this concept, currents, voltages, uxes and mmfs are considered to be sinusoidally distributed in space. As an example, if one has a sinusoidally distributed winding in an AC machine, and this winding is fed with a DC current, then the mmf is sinusoidally distributed around the periphery of the AC machine. Remark 7.7 It can be shown that if we have three phase sinusoidally spatially distributed windings, fed with three phase temporal sinusoidal currents, then one ends up with a spatially sinusoidally distributed resultant mmf that moves around the machine at the electrical supply frequency. This can be represented as a single vector that is rotating with an angular velocity of (the electrical supply frequency). The reason for introducing the space vector concept here is because it is convenient to use this concept to represent the output voltages for an inverter. Figure 7.6 shows the space vector diagram for the various switch positions for the inverter. The length of the space vector corresponds to the maximum phase2 to-neutral voltage for each phase i.e. 3 VDC . Notice that there are six active vectors that can be spaced around a machine every 60 electrical. Remark 7.8 Although the space vector concept comes about because of the spatial properties of machine windings, it is often used in situations where this does not exist. For example, in Figure 7.3 we have a passive load consisting of impedances, and we can use the space vector concept to represent the voltages on this circuit. I will not, in this brief introduction, go into detail as to why this can be done, suce to say that it is due to the very close relationship between space vectors and temporal phasors in circuits. Space vectors can be used as a basis for a dierent type of PWM, called Space Vector PWM (SVPWM). The basis of this PWM strategy is the realisation that three phase temporal sinusoidal voltages lead to a spatially rotating voltage vector in a three phase sinusoidally wound machine (as noted previously). However, with an inverter we do not have innitely variable voltages that we can apply to each phase, and therefore we can switch the inverter so that at any instant of time we can, in an average sense, produce a desired voltage vector.

7.2 Inverters and Applications

7-9

A
va vb vc

V dc

V 3 (010)

(110) V 2 2 V7 (111) (000) V8 5 A 1 (100) V 1 6 B C

3
V 4 (011)

V 5 (001)

(101) V 6

Figure 7.6: Switch positions and the resultant voltage space vectors.

T T/2 10 0 1 1 1 1 T/2 1 1 0 A

10 0

0 B

10 0

0
t2

1
t0

1
t0

0
t2

t 0 t1

t1 t 0

Figure 7.7: Switching waveforms for double edge pulse width modulation.

7-10

Introduction to Other Power Electronic Devices and Applications

In order to develop a PWM strategy using space vectors let us dene as the duty cycle for a vector. Consider Figure 7.7 which shows the switching waveforms to generate a particular voltage vector. One can see from this diagram that the same switching pattern is generated symmetrically around the centre of the PWM period. By reading vertically one can determine the switching states for this switching sequence they are 000, 100, 110, 111, 111, 110, 100, 000 i.e. we are switching between vectors V8 , V1 , V2 , V7 , and then the reverse. The vector nomenclature appears in Figure 7.6. As one can imagine this would lead to an average vector somewhere in between V1 and V2 , the length of the vector being controlled by the duration of the zero vectors V7 and V8 . The duty cycle for each of the vectors is simply the total time of the vector divided by the control period time T . For example, the duty cycle for the V1 vector is: 2t1 (7.16) T Similarly one can dened the duty cycle for V2 . Using this notation, if only this vector and the zero vector was switched during an interval of T then the average voltage vector magnitude produced over the interval is 1 VDC volts. 1 = Note 7.1 Space vectors are dened (for reasons that I shall not elaborate on here) as 2 the amplitude of the resultant vector in the machine. For a three 3 phase machine this means that the maximum voltage vector magnitude is the same as the peak voltage that occurs across the phases. It is this correspondence of the voltage vectors with the phase voltages that is one of the main reasons for using this convention. Remark 7.9 A further comment on note 7.1 one can resolve the space vector onto three axes 120 apart and get the instantaneous value of the voltage on the respective three phase axes. The same logic applies to the current vector.

One of the very convenient features of vectors is that one can take orthogonal components of them i.e. one can not only resolve the vectors onto the 120 axes but one can also resolve them onto 90 axes. Consider the situation depicted in Figure 7.8. This shows a desired voltage vector. Note that we have not considered what limits there are on the length of the voltage vector that can be produced by this system. We do know that the limit if the voltage vector lies on one of the natural vectors that can be produced 2 by the inverter is 3 VDC . One can consider the vector in Figure 7.8 is a normalised vector (i.e. divided 2 by 3 VDC ), and hence d and q are the normalised orthogonal projections onto a set of orthogonal dq axes. If we apply vector V1 for 2t1 seconds, and V2 for 2t2 seconds then the desired normalised vector, in an average sense, is obtained. Let us now calculate the actual switching times. In order to do this let us dene the normalised voltage vector lengths: 1 2 = = 2t1 T 2t2 T (7.17) (7.18)

7.2 Inverters and Applications

7-11

q
V2

Desired voltage vector 1

aq
2t 2
60 o

d
ad
V1

2t 1
Figure 7.8: Switching time determination. where T the switching period, and 1 and 2 are eectively the normalised voltage vectors in Figure 7.8. Using trigonometry on this Figure one can clearly write: d = 1 + 2 cos 60 1 = 1 + 2 2 3 = 2 sin 60 = 2 2 2t1 1 2t1 2t1 t2 + = + T 2 T T T 3 2t2 3t2 = 2 T T q T 3 (7.19) (7.20) (7.21)

Using the denitions for 1 and 2 we can write: d q t2 = = = (7.22) (7.23) (7.24)

Substituting into the expression for d and making t1 the subject of the expression we can write: t1 t1 = = 1 1 q T (d T t2 ) = (d T ) 2 2 3 T q (d ) 2 3 (7.25) (7.26)

Thus t1 and t2 calculate the active vector times. One can now calculate the zero time by realising the there are four t0 periods in one switching period due

7-12

Introduction to Other Power Electronic Devices and Applications

Condition for sector Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6 d > 0; q 0; q < 3d q > 0; q 3 d d < 0; q 0; q < 3 d Firing order V8 V1 V2 V7 V7 V2 V1 V8 V8 V3 V2 V7 V7 V2 V3 V8 V8 V3 V4 V7 V7 V4 V3 V8 V8 V5 V4 V7 V7 V4 V5 V8 V8 V5 V6 V7 V7 V6 V5 V8 V8 V1 V6 V7 V7 V6 V1 V8 t0 T (1 q ) d 4 3 2q T (1 ) 4 3 T (1 + q ) d 4 3 T (1 + + q ) d 4 3 T (1 + 2d ) 4 3 T (1 + q ) d 4 3 t1 T ( q ) d 2 3 q T ( ) d 2 3 q T 3 q T 3 q T (d + ) 2 3 q T ( + ) d 2 3 t2 q T 3 T ( + q ) d 2 3 q T (d + ) 2 3 T ( + q ) d 2 3 T ( q ) d 2 3 q T 3

d < 0; q < 0; q > 3d q < 0; q 3 d d > 0; q < 0; q < 3d

Table 7.3: PWM ring times for various sectors to the centred PWM algorithm. Therefore: 4t0 = = t0 = T (2t1 + 2t2 ) T q 2q T T T d + 3 3 q T (1 d ) 4 3 (7.27) (7.28) (7.29)

It is possible to show, from the geometry of this situation, that for a given set of normalised orthogonal vectors d and q the switching times for the vectors in sector 1 of the PWM star are: t1 t2 t0 = = = q T (d ) 2 3 q T 3 T q (1 d ) 4 3 (7.30) (7.31) (7.32)

where the various t values are dened in Figure 7.7. If a similar analysis is carried out for all the sectors then one can get a complete set of switching times as shown in Table 7.3. Another important aspect that was eluded to earlier was that there is limiting of the resultant space vectors. For example, one cannot ask for d = 1 and q = 1, since this would be asking for a resultant space vector that is larger than that which can be obtained given the vectors that the inverter can produce. If one applies the expressions from Table 7.3 to such a situation then this problem manifests itself by the condition [15]: 2t1 2t2 + >1 (7.33) T T or: q d + > 1 (7.34) 3 in the case of sector 1 limiting. Clearly (7.33) means that the total switching time of the active vectors exceeds the total control period. It can be shown that the limitations imposed by the available ring times result in a hexagon limit. This is shown in Figure 7.9. If a desired vector exceeds the limit hexagon, then it has to be limited to the hexagon [15].

7.2 Inverters and Applications

7-13

Limit hexagon Limit circle V3 (010) 2 V7 (111) (000) V8 5

V (110)2

3
V4 (011)

1 (100)V 1 6

(001) V5

(101) V6

Figure 7.9: Voltage limit hexagon. If the times are to be scaled so that they add to give one, then we require: or: = 2t1 2t2 + T T 1 d + =1 (7.35)

q 3

(7.36)

Remark 7.10 Note that the use of the on both the total times means that the angle of the resultant vector is preserved. The new limited ring times for sector 1 are now: 2t1lim 2t2lim = = 2t1 2t2 (7.37) (7.38)

The 1/ values for all the sectors are summarised in Table 7.4.

Remark 7.11 Space vector based PWM is particular amenable to implementation in digital form. This can be contrasted with carrier wave based PWM, which was originally devised for analogue implementation. Of particular importance is that this technique does not involve the solution of any transcendental equations, and it does not involve the use of any trigonometric functions.

7-14

Introduction to Other Power Electronic Devices and Applications Sector 1 2 3 4 5 6 1/ d + q 3 d (d + q ) 3

q 3 d q 3

q 3

2q 3

Table 7.4: Voltage limit s Remark 7.12 Another interesting feature of space vector PWM is that the maximum amplitude of the fundamental that can be produced by the technique is larger, by approximately 15%, than that produced by carrier based sinusoidal PWM. A similar eect can be obtained in sinusoidally PWM by putting a third harmonic in the reference waveform.

7.2.2

Dead-time Issues

An important practical issue that arises with totem pole inverter legs is the problem of shoot through. This term refers to the phenomena of both the top and bottom device being momentarily on when there is a switching transition from the top to the bottom device, or vice-versa. Remark 7.13 The shoot through problem also exists in low power digital circuits. One may recall from your studies of logic families that CMOS and TTL both suer from shoot through. In the case of digital systems the shoot through is a very short period of time, and the power levels involved are low. Consequently the problem can be tolerated. However, in high power inverter systems the devices will fail if shoot through occurs. Shoot through is overcome by making sure that the outgoing device is turned o before the incoming device turns on. This is achieved in practice by manipulating the device signals that turn the devices on and o.

The turn o of a power device is not instantaneous due to the phenomena of charge storage in the devices. In order to give the device time to turn o before turning on the other device in the a small delay (typically of the order of 3 to 4secs for todays IGBT devices) is allowed between the turning o of one device and the turning on of the other. This delay results in a dierent voltage being applied to the machine compared to that being demanded by the control. This is due to the fact that the dead-time delay results in a shift of the switching edges. The dead-time error problem is a little more complicated than I have outlined above. The presence of the dead-time switching delay is actually variable depending on the direction of the current through the inverter leg. The following discussion is with reference to Figures 7.10 and 7.11. Figure 7.10 shows two legs of an IGBT based inverter, with the current owing out of leg A and into leg B. Figure 7.11 shows the eects of the current direction on the actual time of

7.2 Inverters and Applications

Phase A Leg + Phase B Leg Phase C Leg

7-15

Initial current Final current

ia i

ib

DC Bus Input/Output

ia f
ib
f

Three Phase Input/Output

Figure 7.10: Inverter showing the initial and nal current ow after a leg is red. switching. As can be seen when current ows out of a leg (i.e. leg A) the actual time of switching is the desired time of switching. Therefore the dead-time of the inverter does not cause a problem. However, when current is owing into a leg (i.e. leg B) then the switching time is delayed by the dead-time. Therefore, if one wishes to compensate for the dead-time so that correct switching always occurs, one should sense the current direction and compensate the switching time as appropriate. However, because the compensation of the switching time has to occur in the control interval before the interval it is going to be applied, then there is the possibility that the current direction may be incorrect. This situation only occurs around the times that the fundamental current is about to change direction. The result of incorrect compensation is that the cross-over of the current through zero may be considerably distorted even more than if compensation is not being applied. This issue has not been resolved.

7.2.3

Some Inverter Applications

In this subsection we shall consider some of the applications for inverters. The presentation is by no means exhaustive, and the more common applications will be highlighted. 7.2.3.1 Variable Speed Drives

One of the most common applications of inverters are in AC variable speed drives. These drives are most commonly based on the use of induction machines. Figure 7.3 shows the generic layout of an AC drive. As mentioned in section 7.1 Converter 1 in this gure is often a uncontrolled three phase rectier (although if the supply is single phase then one could have a single phase rectier). Converter 2 is a conventional inverter, much as shown in Figure 7.4. At low powers and voltages the power devices in the inverter can be MOSFETs. At small to medium powers, the IGBT has become the device of choice. The range of operation of the IGBT is extending all the time in terms of the currents and voltages that can be handled. At the time of writing these notes IGBTs

7-16

Introduction to Other Power Electronic Devices and Applications

Leg A switching

Top

On Off On Off

Bot

Dead - time Td

Leg A currents

Top

ia i

Desired switching point and actual switching point

Bot

ia f = ia i

Leg B switching

Top

On Off On Off

Bot

Dead - time Td

Actual switching point

Leg B currents

Top

0
ib
i

0
f i

Bot i = i b b

Desired switching point

Figure 7.11: Example of dead-time induced switching error in an inverter.

7.2 Inverters and Applications are available with maximum voltages of 6kV, and current capabilities in the thousand of amps range. Variable speed AC drives are becoming ubiquitous devices these days. They can be found in anything from domestic air conditioners, washing machines and microwave ovens, right through to large drives in power station bag houses and rolling mills. If better power sources are found, then AC drives will become very prevalent in vehicular transportation. They are currently widespread in train transportation. The main driving factors towards the increasing use of inverters are: a. The simultaneous arrival of low cost high performance microprocessors, as well as reliable, robust and reasonable cost power electronic devices in the since the mid 1990s. b. The renement of the control algorithms for AC machines allowing high performance from AC drives. c. A community demand for more ecient use of energy. Let us briey consider a few of the applications mentioned above. It is not uncommon to hear in advertisements for air conditioners that they are inverter air conditioners. The inverter in these air conditioners are being used to drive the compressor in a variable speed mode. Normally an air conditioner is driven in an on-o mode, controlled by a thermostat. The reason for going to a variable speed mode is that the compressor is much more ecient in this mode. When a compressor starts for the next 30 to 60 seconds it is not really pumping any heat, but simply compressing the refrigerant. If the compressor is being started and stopped on a regular basis this non-productive time will be a signicant part of the total operating time of the compressor. Under variable speed operation the thermostat simply controls the speed of the compressor, but it does not stop. Therefore the refrigerant does not have to be re-compressed, since it does not decompress whilst the compressor is running, albeit more slowly. Inverter air conditioners can be up to 30% more ecient as compared to the traditional ono air conditioner (depending on operating cycle of the on-o air conditioner). Another domestic appliance that now has an inverter in it is the microwave oven. The inverter is used to supply variable voltage to the magnetron, and therefore get true variable power instead of pulsed on-o 100% power as in a conventional oven. This is main motivated by better cooking performance at low power levels. In actual fact the so-called inverter circuit in a microwave oven is more like a yback switch mode power supply circuit. The switch mode supply can be operated at high frequency, and therefore allow a smaller high frequency transformer to be used. In addition, the output voltage and/or current can be controlled allowing completely variable, constant power from the magnetron. 7.2.3.2 Grid Connected Applications

7-17

As the power electronic devices improve in voltage rating, grid connected applications of inverters are becoming more common. The classic example of the use of an inverter in a grid connected application is interfacing photo-voltaics to the grid.

7-18

Introduction to Other Power Electronic Devices and Applications

Controller

DC Photo-voltaic solar cells Inverter

AC Utility supply

Domestic load

Figure 7.12: Generic non-battery based photo-voltaic supply system.

In a photo-voltaic interface, the solar cells are producing DC voltage which either has to be converted into AC to feed the utility grid, or converted to AC to supply domestic AC appliances. Both of these are classic inverter applications. In some situations the output of the solar cells will rstly be fed to a bank of batteries for storage. It is then the DC in the batteries that is converted to AC. In other situations, the DC from the solar cells may be fed directly into the grid without the intermediate batteries (see Figure 7.12). This is the situation that is common for non-remote properties that are connected to the main utility grid supply. The inverter is its associate controller can either deliver power to the grid, or take power from the grid, depending on the insolation falling on the solar cells. In the case of remote properties, there in many cases will not be a utility supply, and the inverter would be powering the household appliances. A more industrial application of inverters is the static var compensator (SVC). A compensator is a device that can be connected to the power system to provide voltage support for the supply, especially at the end of long transmission lines. This is achieved by the compensator being a variable capacitor. Traditionally this was achieved by using a synchronous machine, and varying the excitation to vary the apparent capacitive load represented by the machine. Later banks of switchable capacitors were used, the switching being achieved by thyristors. More recently a traditional inverter has been used. This circuit has the signicant advantages over the previous techniques injects less harmonics into the supply, very rapid bumpless changes can be achieved, can compensator for general power factor (i.e. can perform an active lter function). Figure 7.13 shows some variants of the static compensator (STATCOM) oered by the Siemens company. Some of these devices do more than simple static var compensation, and are capable of real power ow control as well as reactive power ow control. AC transmission systems that include these power electronic devices are known as Flexible AC Transmission Systems (FACTS). See the next chapter for much more details on grid connected applications related to renewable energy.

7.2 Inverters and Applications

7-19

Statcom

Static Synchronous Series Compensator (SSSC)

Unified Power Flow Controller (UPFC)

Back-to-Back Statcom

Figure 7.13: Some grid connected FACTS units oered by Siemens.

7-20

Introduction to Other Power Electronic Devices and Applications

Figure 7.14: Conceptual diagram of a matrix converter.

7.3

Multilevel Converters and Applications

This section still has to be written

7.4
7.4.1

Basic Introduction to Matrix Converters

Introduction

Matrix converters are a converter type that does not have an intermediate energy storage element. It is a converter that allows direct conversion of an AC waveform of one frequency and magnitude, to a waveform of another frequency and magnitude using only semiconductor switching elements. The essential idea behind the matrix converter is that one has an array of switches that allow any input phase to be connected to any output phase. Figure 7.14 shows a conceptual diagram of a matrix converter. Note that the switches in this gure have to conduct current bidirectionally and have to be able to block current in both directions. Currently most semiconductor switches conduct current in both directions, but can only block current in one direction. Fortunately it is possible to combine these switches so that the composite switch behaves as a bidirectional bi-blocking switch. Remark 7.14 The fact that the matrix converter allows any input phase to be connected to any output phase means that there is a lot of freedom with respect to the connections that can be made with this converter. However, this also means that there are many ways that a short circuit can be created.

7.4 Basic Introduction to Matrix Converters

7-21

Figure 7.15: Recongured conceptual diagram of the matrix converter. It is possible to recongure the switch arrangement shown in Figure 7.14 on page 7-20 to that shown in Figure 7.15. This particular gure more graphically shows the matrix property of this converter. Remark 7.15 Note that the gaps in the wires in Figure 7.15 are actually continuous lines that run over the crossing line.

7.4.2

Switching Rules

There are 29 = 512 dierent combinations of the 9 possible switches. However one has to restrict the combinations for electrical reasons. Typically the input to a matrix converter is a voltage source, and the output load of the converter is an inductive load. Therefore the switching if the converter cannot short circuit the input, and at the same time cannot attempt the open circuit the output. The rules that guide these restrictions can be summed up as: DO NOT connect two dierent input lines to the same output line. This is to prevent a short circuit between two or more phases. DO NOT disconnect the output lines inductive currents will result in very high voltages across the switches. Remark 7.16 The latter of these two rules means that output lines must be connected to an input line at all times. Remark 7.17 The fact that the output lines have to be connected to an input line under all circumstances means that the state of the matrix converter can be symbolised with only three input values. For example, ACC means that phase A is connected to a, phase C is connected to b and phase C is connected to c. Therefore the symbols used in this notation have positional relevance. If the switching rules above are applied then the 512 possible switch states are decreased to 27 permitted switch states, which have the following properties:

7-22

Introduction to Other Power Electronic Devices and Applications a. 3 states produce forward rotating space vector voltages. These states correspond to each output phase being connected to a dierent input phase. Therefore a space vector is produced that rotates at the mains frequency. b. 3 states produce reverse rotating space vector voltages. This is the reverse phase sequence of the previous set of states. c. 18 states produce stationary space vector voltages of various amplitudes. This group occurs if two output phases are connected to a common input phase, and the third output phase is connected to a dierent input. d. 3 states produce zero space vector voltages. This corresponds to all three outputs being connected to the same input line. Remark 7.18 Most modulation techniques for matrix converters have used the states associated with points c and d above because of the diculty of dealing with the rotating vectors with the control techniques traditionally employed.

7.4.3
7.4.3.1

Switching Some More Detail

Alesina/Venturini Modulation Algorithm

The information in this section mostly comes from a review paper on matrix converters[16], and is reproduced here much as it is written, but with some additional explanation where appropriate. One can dene the switching function for a single switch as: SKj = 1, switch Skj closed 0, switch SKj open (7.39)

where K = {A, B, C} and j = {a, b, c}. The constraint above can be expressed mathematically as: SAj + SBj + SCj = 1 (7.40)

which means that there always has to be a switched closed onto output phase j (i.e. no open circuits) and there can only be one switch closed onto output j (i.e. no short circuits). This restriction leads to the 27 valid switching states mentioned previously. Remark 7.19 Equation (7.40) has to be true if the switches are truly bidirectional in current ow when they are closed. However, as we share see it is possible to violate this condition if the switches have controlled bidirectional current ow i.e. the switches are bidirectional, but via control the current ow direction can be selected. If the load and source voltages are referenced to the incoming supply neutral point (assuming that the supply is star connected), then the input and output vectors can be expressed as:

7.4 Basic Introduction to Matrix Converters

7-23

vi =

vo

vA (t) vB (t) vC (t) va (t) vb (t) vc (t)

(7.41)

(7.42)

The relationship between the load and the input voltages using these denitions can be expressed as follows: va (t) SAa (t) SBa (t) SCa (t) vA (t) vb (t) = SAb (t) SBb (t) SCb (t) vB (t) (7.43) vc (t) SAc (t) SBc (t) SCc (t) vC (t) vo = Tvi (7.44)

where T is the instantaneous transfer matrix. Similarly the relationships between the input and output currents can be dened as: ia (t) (7.45) io = ib (t) ic (t) iA (t) ii = iB (t) (7.46) iC (t) and: ii = T1 io where T1 is the inverse transfer matrix. Remark 7.20 Equation (7.43) essentially says that the output voltages of the matrix converter are simply related to the value of one of the input voltages. Note that (7.40) indicates that at any point of time only one of the input voltages, vA, vB or vC can be connected to the output lines. Remark 7.21 The obvious question to ask with respect to (7.43) is what is the ref switching function to make the vo vector equation to the desired vo . Therefore a modulation strategy has to be dened. Figure 7.16 shows the typical form of the switching for the matrix converter switches [16]. Notice that each output phase is connected in order to one of the input phases in a repeating sequence. This means, for example, that input phase A is connected to output phase a then input phase B is connected and nally input phase C is connected, each one for a specic period of time dened by the modulation strategy. (7.47)

7-24

Introduction to Other Power Electronic Devices and Applications

SAa = 1
tAa

SBa = 1
tBa
SBb = 1

SCa = 1
tCa
SCb = 1

Output Phase a

SAb = 1
tAb
SAc = 1

tBb
SBc = 1

tCb
SCc = 1

Output Phase b

tAc

tBc

tCc

Output Phase c

Tseq (time sequence)

Repeats

Figure 7.16: General form of switching pattern [16]. Let us dene the duty cycle modulation function of one of the switches as: mKj (t) = where can take on the following values: 0 mKj 1 K = {A, B, C}, j = {a, b, c} (7.49) tKj Tseq (7.48)

One can now dene a low frequency transfer matrix as: mAa (t) mBa (t) mCa (t) M(t) = mAb (t) mBb (t) mCb (t) mAc (t) mBc (t) mCc (t) this matrix being a matrix of duty cycles. Remark 7.22 Equation (7.50) is called a low frequency matrix because if we use it to calculate the output then we are implicitly assuming that the output voltage is related to the duty cycle multiplied by the input voltage i.e. we are considering the average output voltage over the control cycle of the converter (over Tseq ). Using (7.50) we can dene the average output voltage vector as: vo = M(t)vi (t) and the low frequency component of the input current is: ii = M(t)T io (7.52) (7.51)

(7.50)

7.4 Basic Introduction to Matrix Converters Remark 7.23 One can see from Figure 7.16 on page 7-24 and the denition of the switch duty cycle in (7.48) that this means that the sum of the duty cycles can only be one for any particular output line, i.e. mAa (t) + mBa (t) + mCa (t) = tAa tBa tCa + + =1 Tseq Tseq Tseq (7.53)

7-25

If this is expressed in matrix form it becomes: M(t)1 = 1 (7.54)

where 1 is a column vector of 1s. Note that this condition, together with the valid switch condition (7.40) means that there is always a connection a particular input line to an output line. Summary 7.1 Summarising so far, the key expressions which the modulation matrix must satisfy are: v0 = M(t)vi ii = M(t) io M(t)1 = 1
T

(7.55) (7.56) (7.57)

If vi is not proportional to the vector 1 then (7.55) and (7.57) provide two independent conditions on every row of the matrix M(t) while (7.56) provides one condition on every column of M(t) [17]. Two more equations can be provided from Kircho s current law and assuming that the converter is lossless: ii T vi
T

io T vo ii T 1

(7.58) (7.59)

io 1 =

We have 9 unknowns in the form of the modulation functions. The input voltages and output currents are known measured variables, and the output voltage vo is a desired output voltage (if the objective is to obtain this desired output voltage). Between all of the equations above it is possible to get 9 independent equations, and therefore the system is solvable. Let us consider a three phase system. Let the sinusoidal voltages at the input be: vA vB vC = = = Vi cos(i t) 2 ) 3 4 Vi cos(i t + ) 3 Vi cos(i t + (7.60) (7.61) (7.62)

and the assumed output sinusoidal currents: ia ib ic = Io cos(o t + o ) 2 = Io cos(o t + + o ) 3 4 = Io cos(o t + + o ) 3 (7.63) (7.64) (7.65)

7-26

Introduction to Other Power Electronic Devices and Applications Remark 7.24 Note that both the input voltages and the output current are measured and assumed respectively. The output current is assumed, because if the converter is driving a passive circuit then the output current is a function of the output voltages, which are what we are trying to calculate. The desired input currents are dened as follows: iA iB iC = = = Ii cos(i t + i ) 2 Ii cos(i t + + i ) 3 4 + i ) Ii cos(i t + 3 (7.66) (7.67) (7.68)

and the desired output voltages: va vb vc = Vo cos(o t) 2 = Vo cos(o t + ) 3 4 = Vo cos(o t + ) 3 (7.69) (7.70) (7.71)

There is an existence theorem in [17] that denes the relationship between the input voltage amplitude and the amplitude of the output voltage, and the amplitude of the output current and the input current. it states (fairly obviously) that:: Vo Ii Vi 2 Io 2 (7.72) (7.73)

These relationships are related to the fact that the input voltages and output currents are three phase 120 separated sine waves, and the cross-over point of the sine waves is one half the amplitude of the sine waves. Since the waves can be selected by the modulator at any time, this limits the output voltage to one half the amplitude of these waveforms. The condition in (7.58) can be written as: Vo Io cos o Vo Vi = Vi Ii cos i Ii cos i = Io cos o (7.74) (7.75)

Taking into consideration all these conditions the (7.55), (7.56)and (7.57) can be solved to give the modulation functions for this converter[17]: 1 + 2qCS(0) 1 + 2qCS( 2 ) 1 + 2qCS( 4 ) 3 3 1 1 + 2qCS( 4 ) 1 + 2qCS(0) 1 + 2qCS( 2 ) M(t) = 1 + 3 3 3 2 4 1 + 2qCS( 3 ) 1 + 2qCS( 3 ) 1 + 2qCS(0) 1 + 2qCA(0) 1 + 2qCA( 2 ) 1 + 2qCA( 4 ) 3 3 1 1 + 2qCA(0) 2 1 + 2qCA( 2 ) 1 + 2qCA( 4 ) (7.76) 3 3 3 1 + 2qCA( 4 ) 1 + 2qCA(0) 1 + 2qCA( 2 ) 3 3

7.4 Basic Introduction to Matrix Converters where: CS(x) CA(x) m 1 2 q = = cos(m t + x) cos[(m + 2i )t + x]

7-27

= o i 1 = [1 + tan(i ) cot(o )] 2 1 = 1 1 = [1 tan(i ) cot(o )] 2 Vo = Vi

with the added conditions: 1 2 0 0 1 2

0 q

The question that arises from the above analysis is: How does one use the expressions in (7.76) to come up with a switching strategy. It should be remembered that the modulating functions have been derived in the sense that the converter switching is at such a high rate that the duty cycles of the switches (i.e. the m values in the matrix M) are a continuously changing set of values. In reality this is not the case, and there is a nite switching frequency. However, as discussed in Chapter 1 on page 1-1 converters only work because of the averaging action of the loads that the converter is connected under the assumption that the switching frequency is high enough that the switching harmonics produced are ltered by the load. Based on these assumptions, the switching time for each of the switches can be written as: tKj = T mKj (kT ) (7.77) k where tKj denotes the switching on time for switch Kj for the interval k. Note k that:
n j Tk

matrix converter switching time

=
K=1

tKj k

(7.78)

which is simply a restatement of the condition in (7.57) saying that all the switch times for a particular output phase can only add up to be the switching period. Remark 7.25 As mentioned in the previous discussion (7.77) only gives the correct output if the switching frequency satises: fT = 1 T i o , 2 2

Remark 7.26 The equations presented immediately above are those originally developed by Alesina and Venturini [17] and are for a system limited to an output voltage magnitude that is half the input voltage magnitude i.e. Vo 0.5Vi .

7-28

Introduction to Other Power Electronic Devices and Applications This is quite a restriction on these systems. Fortunately it was subsequently shown that the output voltage could be improved by adding third harmonics of the form 1 1 vo3rd = cos(3o t) + cos(3i t) (7.79) 6 2 3 to the reference voltages. If this is done then it was shown in [18] that: Vo 0.87Vi (7.80)

improved voltage

output

and this is the theoretical maximum output voltage that can be obtained from a direct AC-AC converter system regardless of the converter architecture. Remark 7.27 The solution of (7.76) is reasonably complicated, and is one reason why this technique is regarded by many as too complex. Nevertheless the technique presented in [17] is the foundation of all the subsequent work in this area. 7.4.3.2 Space Vector Modulation Techniques

Space vector modulation (SVM) is a well known modulation technique in conventional PWM inverters. It has the nice attribute that it is very amenable to digital implementation. As mentioned previously in point c and point d on page 7-22 there are a total of 18 active stationary vectors that can be produced by the converter, and 3 zero vectors, giving a total of 21 useful vectors for the SVM application. The output voltage space vector and the input current space vector are dened as[14]: vo ii
2

= =
2

2 (va + avb + a2 vc ) 3 2 (iA + aiB + a2 iC ) 3

(7.81) (7.82)

where a = ej 3 and a2 = ej 3 . The nomenclature is as follows: ABC means that input phase A is connected to output phase a, input phase B is connected to output phase b and nally input phase C is connected to output phase c. As can be seen there is an implied positional dependency of the nomenclature, with the rst position being the connection to output phase a, the second to output phase b, and the third position to output phase c. This compact notation can be used because the input and the output have to be connected at all times due to the requirement that the current ow through the converter cannot be interrupted. In order to calculate the output voltage and the input currents for a particular switch situation one has to apply the above denitions for the voltage and current space vectors to the various 21 stationary vector switch congurations. As an example of this consider the situation of the switches being ABB i.e. input phase A is connected to output phase a, input phase B is connected to output phase b and input phase B is connected to output phase c. This means that input phase C is not connect to anything, and therefore there is no current ow in this input phase. The output voltage phasor is dened by (7.81), and with the ABB switch conguration then we can say that va = vA , vb = vB , and

7.4 Basic Introduction to Matrix Converters vc = vB , therefore (7.81) can be written as: vo = = = vo = 2 (vA + avB + a2 vB ) 3 2 3 3 [vA + (0.5 + j )vB + (0.5 j )vB ] 3 2 2 2 (vA vB ) 3 2 vAB 3

7-29

(7.83)

Similarly one can calculate the input current for this switch conguration by applying the denition of the input current space vector dened in (7.82) and realising that for the ABB switch setting that iA = ia , iB = ib + ic , and iC = 0, and that ia + ib + ic = 0: ii = = = = = = ii = 2 (iA + aiB ) 3 2 [ia + a(ib + ic )] 3 2 3 [ia + (0.5 + j )(ia )] 3 2 2 3 3 ( j )ia 3 2 2 2 1 3 3 ( j )ia 2 2 3 3 1 2 3 ( j )ia 2 3 2 2 ia ej 6 3

(7.84)

Similar results can be obtained for all the other switch congurations. Table 7.5 on page 7-30 shows these vectors and the output voltage and input current vector angles for them.

These space vectors can be placed on a traditional space vector hexagon. These appear in Figure 7.17. Remark 7.28 As can be seen from Figure 7.17 the hexagons are similar to those for a conventional PWM inverter. However, one point that is not clear from these diagrams is that the length of the vectors are dynamic and dependent on the various instantaneous line-to-line voltages. Similarly the current vectors are variable length and dependent on the instantaneous line currents.

Let us consider a situation where the desired voltage vector v o is in sector 1 and the angle of the current vector ii is i as shown in Figure 7.17. As we shall see, in order to generate the average v o vector the switching vectors 7, 8, 9

7-30

Introduction to Other Power Electronic Devices and Applications

Switching conguration list 01 02 03 +1 -1 +2 -2 +3 -3 +4 -4 +5 -5 +6 -6 +7 -7 +8 -8 +9 -9

Switch connections

vo

ii

AAA BBB CCC ABB BAA BCC CBB CAA ACC BAB ABA CBC BCB ACA CAC BBA AAB CCB BBC AAC CCA

0 0 0 2 vAB 3 2 3 vAB 2 3 vBC 2 vBC 3 2 3 vCA 2 3 vCA 2 3 vAB 2 3 vAB 2 3 vBC 2 vBC 3 2 3 vCA 2 3 vCA 2 3 vAB 2 3 vAB 2 3 vBC 2 vBC 3 2 3 vCA 2 3 vCA

0 0 0 0 0 0
2 3 2 3 2 3 2 3 2 3 2 3 4 3 4 3 4 3 4 3 4 3 4 3

0 0 0 2 ia 3 2 3 ia 2 ia 3 2 3 ia 2 ia 3 2 3 ia 2 ib 3 2 3 i b 2 ib 3 2 3 i b 2 ib 3 2 3 i b 2 ic 3 2 3 ic 2 ic 3 2 3 ic 2 ic 3 2 3 ic

2 2 7 6 7 6 6 6 2 2 7 6 7 6 6 6 2 2 7 6 7 6

6 6

Table 7.5: Switching values used in SVM.

7.4 Basic Introduction to Matrix Converters

7-31

4; 5; 6

2 1 vo
o

1; 2; 3

4
7; 8; 9

6 5 (a)

2; 5; 8

ii

3; 6; 9

5 (b)

1; 4; 7

Figure 7.17: (a) Direction of the output line-to-neutral voltage vectors for the active switch congurations. (b) Directions of the input line current vectors generated by the active switch congurations.

7-32

Introduction to Other Power Electronic Devices and Applications Output voltage sector 2 or 5 +6 +4 +9 +7 +5 +6 +8 +9 +4 +5 +7 +8 I II III IV

Input current sector

1 or 4 2 or 5 3 or 6

+9 +8 +7 I

1 or 4 +7 +3 +9 +2 +8 +1 II III

+1 +3 +2 IV

+3 +2 +1 I

3 or 6 +1 +6 +3 +5 +2 +4 II III

+4 +6 +5 IV

Table 7.6: Selection of switching congurations for combinations of output voltage and input current vectors. and 1, 2, 3 must be used. However, for the current vector to be a angle i then vectors 3, 6, 9 and 1, 4, 7 must be used. In order to achieve this simultaneously then only the vectors that are common to the two objectives can be used, which is in this case 7, 9, 3, 1. The 8, 2, 6, 4 vectors are not common between the two control objectives, and therefore cannot be used. If a similar process is carried out for all desired voltage vectors and current vector angles then the active vectors in each sector can be compiled into a table so that the vectors that can be used to control the current and the voltage can immediately be seen. This appears in Table 7.6. Remark 7.29 Note that only the positive vectors are listed in Table 7.6. This has implications on the calculated duty cycle times for the switches which allows the correct switches to be chosen under conditions where the negative vectors have to be used. Let us consider the use of this table by an example of the generation of a particular output voltage vector and a particular input current angle. Remark 7.30 The magnitude of the current is determined by the output voltage and the load that this voltage is applied across. The input current angle can be controlled by the length of time that we switch onto each of the current vectors. We are able to satisfy both of these requirements because we have four available vectors and four unknown lengths of time that these vectors are going to be switched. Note that in the case of the voltage vectors, there is also the zero vector which is used to control the magnitude of the output voltage (and by implication the input current). The following discussion is with reference to Figure 7.18, which is a detailed picture of sector 1 of Figure 7.171 . This diagram shows the desired voltage vector v o being resolved onto the vectors that are obtainable from the switching of the converter. As with all PWM type systems the v o is obtained in an average sense by switching the converter to produce a vector of average length of |v o | and |v o |. These two vectors in turn, as can be seen from Figure 7.18 result in an average vector v o as required. The v I , v II , v III , and v IV vectors correspond o o o o to the vector numbers dened in Table 7.6, and are valid for the voltage and current vectors both in sector 1. In order to calculate the switching times we must rstly calculate |v o | and |v o |. This is carried out using relatively simple trigonometry, which is reproduced here so that the reader can see the process in detail. Let us rstly calculate
1 We

are also assuming that the current vector ii lies in sector 1 for this example.

7.4 Basic Introduction to Matrix Converters

7-33

v I ; v II o o

Sector 1
vo
v0 o
y

=3

v 00 o

v III ; v IV o o
x

Figure 7.18: Derivation of the voltage components for a desired voltage space vector.

7-34

Introduction to Other Power Electronic Devices and Applications |v o | . We can write: = |v o | sin o |v | x = o sin o 3 x 2 |v 0 | = = 2x = |v o | sin o cos 3 3 y (7.85) (7.86) (7.87)

Using the notation of [19] this is expressed in terms of o which is the angle of the vector relative to a reference axis that bisects the sector that the vector lies in. Therefore, we can write: o = + o (7.88) 6 and substituting this into (7.87) and manipulating gives: 2 |v o | = |v o | cos(o ) 3 3 Similarly, for |v o |we can write: |v o | = |v o | cos o x |v | = |v o | cos o o sin o 3 1 = |v o | (cos o sin o ) 3 2 3 1 = |v o | ( cos o sin o ) 2 2 3 2 = |v o | (cos cos o sin sin o ) 6 6 3 2 |v o | = |v o | cos(o + ) 6 3 Using (7.88) we can write (7.90) as: 2 |v o | = |v o | cos(o + ) 3 3 (7.91) (7.89)

(7.90)

Equations (7.89) and (7.91) allow us to write the space vectors for these vectors, not only for sector 1, but also for the other sectors as: vo vo = = 2 |v o | cos(o 3 2 |v o | cos(o + 3 j[(Kv 1) + ] 3 3 )e 3 j[(Kv 1) ] 3 )e 3

(7.92) (7.93)

where Kv = 1, 2, 3, , 6 and < o < , and the ej[(Kv 1) 3 + 3 ] and 6 6 j[(Kv 1) ] 3 e and unit vectors in the direction of the respective space vectors. Let us dene the duty cycle of a particular applied voltage space vector: m = t T (7.94)

7.4 Basic Introduction to Matrix Converters where I, II, III, IV . Therefore m is the duty cycle of one of the particular switching vectors for the matrix converter. As can be seen from Figure 7.18, v o and v o are composed by switching on the output vectors v I and v II (for v o ) and v III and v IV (for v o ) 2 for certain o o o o periods of time over the switching period. Realising this we can write the alternate expression for these vectors as: vo vo = v I mI + v II mII o o = v III mIII + v IV mIV o o (7.95) (7.96)

7-35

Remark 7.31 Clearly substituting (7.92) and (7.93) into (7.95) and (7.96) one has two equations with four unknowns (the m duty cycles). The other two equations come from considering the angle of the current. Note that the magnitude of the current is controlled by the output voltage and the load. Now let us consider the control of the input current angle. Since we are only controlling the angle of the current, and not its magnitude, then we have to formulate an expression in terms of the desired current angle. Remark 7.32 The principle used to get the equations for the current angle is that the duty cycle equations for each for the switched current vectors has to lead to a zero orthogonal component of current to the desired angle of the current. If this is the case then the only components of current must be in the desired direction of current. The magnitude of the current (as mentioned previously) is not, and cannot be controlled. Firstly let us write the duty cycle expressions for the switching components of the current vector ii : ii ii = iI mI + iII mII i i = iIII mIII i + iIV i m
IV

(7.97) (7.98)

where iI,II,III,IV are the current vectors for the particular sector as dened in i Table 7.6. The direction of the desired current vector is dened by the unit vector ej i . Therefore the vector that is orthogonal to the desired vector is i jej . Therefore we have to ensure that both ii jej i and ii jej i are zero, or in other words: iI mI + iII mII jej i ej(Ki 1) 3 i i iIII mIII i + iIV i m
IV

= =

0 0

(7.99) (7.100)

je

j i j(Ki 1) 3

where i is measured from the reference axis that bisects the sector that the current vector lies in, and Ki = 1, 2, , 6. We now have with equations (7.95), (7.96), (7.99) and (7.100) four independent equations with four unknowns the mI,II,III,IV duty cycles. The manipulations to solve these equations are tedious and messy, and the end result
2 These

are the vectors as dened in Table 7.6.

7-36

Introduction to Other Power Electronic Devices and Applications is[20]: mI mII mIII mIV = 2 cos(o ) cos(i ) 3 3 (1)(Kv +Ki +1) q cos i 3 2 cos(o ) cos(i + ) 3 3 = (1)(Kv +Ki ) q cos i 3 2 cos(o + ) cos(i ) 3 3 = (1)(Kv +Ki ) q cos i 3 2 cos(o + ) cos(i + ) 3 3 = (1)(Kv +Ki +1) q cos i 3 (7.101) (7.102) (7.103) (7.104)

where i is the desired phase angle between the current vector and the input voltage vector (which is measured), and q the instantaneous voltage transfer |v | ratio, which is q = vo . Therefore i = i i where i is the angle of the | i| input voltage relative to the bisecting reference on the current vector hexagon. Remark 7.33 One can see from the (1)(Kv +Ki +1) and (1)(Kv +Ki ) that one of the duty cycles can be positive and the other negative. A negative duty cycle means that the negative vector is chosen (e.g. -9 instead of +9 if in sector 1 for the voltage). Remark 7.34 Another constraint on the feasibility of the strategy is that the sum of the absolute values for the four duty cycles must be lower than unity in other words the one times for the various vectors have to be less than the control period. This can be written mathematically as: mI + mII + mIII + mIV 1 (7.105)

If this condition is less than one, then the remainder of the time is lled by applying a zero voltage vectors. If (7.101)(7.104) are substituted into (7.105) and some manipulations are carried out one can get the following expression: 3 |cos i | q (7.106) 2 cos i cos o which is the theoretical maximum instantaneous voltage transfer ratio. Therefore at any point of calculating the duty cycles one cannot be demanding a voltage transfer ratio larger than this value. In the case of balance supply voltages and output voltages, the maximum transfer ratio occurs when (7.106) is a minimum (which implies cos i and cos o are equal to 1, which in turn implies that the power factor of the load is unity) which gives: 3 q |cos i | (7.107) 2 which has the theoretical maximum value for matrix converter of 0.866 under the condition of unity power factor.

7.4 Basic Introduction to Matrix Converters Remark 7.35 Having the ability to control the input power factor to be other than the output power factor comes at the price of decreased output voltage. One can see from the denominator of (7.106) that if cos i = cos o = 1 this means the o i = /6 then the output power factor is unity (i.e. cos o = 3/2 = 0.866). If the input power factor is also unity then cos i = 1 and therefore q 23 . This demonstrates that it is the change of the input power factor that results in the loss of the voltage transfer ratio. If other input power factors are required then the voltage transfer ratio will decrease from this value. Once the duty cycles have been calculated then the ring sequence of the devices has to be determined. Consider the situation that we have investigated as an example above i.e. the desired output voltage vector and in the input current vector lie in sector 1. We shall assume that the active switching sequence is to achieve the desired output voltage and input current power factor is +1, -3, -7, +9. The other vectors that come into play here, depending on the output voltage magnitude, are the zero vectors. It can be veried that there in only one switching sequence characterised by one one switch commutation for each switch change, and that is 03 , 3, +9, 01 , 7, +1, 02 . If one uses this switching sequence in a double sided symmetrical switching pattern (as is done for traditional PWM inverters), then the switching pattern is simply this switching pattern reversed for the second half of the cycle. Figure 7.19 shows the switching pattern and the associated duty cycles and switches used. Note that in this diagram the switching times for the particular vectors are denoted as t where is the vector number i.e. 3, 9, 7 etc. As can be seen from the gure there are 12 switching over one control cycle. This switching technique is called a symmetrical SVM, and utilises all of the zero switching sequences. An alternative is to use an asymmetrical switching sequence which only uses one of the switching sequences. In this sequence the switches of one of the columns in Figure 7.15 on page 721 do not change state, and the number of switch commutations in each cycle period is reduced to 8 (SAa , SBa , SCa are always on).

7-37

7.4.4

Implementation Issues

Thus-far we have considered issues related to the modulation strategies for the matrix converter. Throughout this discussion the interested reader has probably been asked themselves the questions: but how does one implement all of this? There are a number of dierent aspects that must be addressed to answer this question. We shall probably present the most important of these. 7.4.4.1 Bidirectional Switches

The switches used in matrix converters are bidirectional as discussed in the initial introduction. Most of the common semiconductor switches available on the market are only capable of blocking current in one direction. In order to implement a matrix converter one must have a bidirectional switch. There are several ways to design bidirectional switches using technologies that can only block in one direction. Figure 7.20 shows a technique that involves the use of only one switch, but required four diodes. The function of the diodes is to direct the current only into the collector of the IGBT so that it is always presented with a positive voltage at this terminal.

7-38

Introduction to Other Power Electronic Devices and Applications

Output phase
a

mCa 2

mAa 2

mBa 2

mBa 2

mAa 2

mCa 2

C
mCb 2

A
mAb 2

B
mBb 2

B
mBb 2

A
mAb 2

C
mCb 2

C
mAa 2

A
mAc 2

B
mBc 2

B
mBc 2

A
mAc 2

C
mAa 2

A
01
t01 2T

B
02
t02 2T

B
02
t02 2T

A
01
t01 2T

C
03
t03 2T

03
t03 2T

3 +9
t2 2T t9 2T

7 +1
t7 2T t1 2T

+1 7
t1 2T t7 2T

+9 3
t9 2T t2 2T

T 2

T 2

Figure 7.19: Double sided switching sequences for a matrix converter over one control cycle.

Figure 7.20: Diode bridge bidirectional switch cell.

7.4 Basic Introduction to Matrix Converters

7-39

Body diode

Common emitter

Common collector

Figure 7.21: Common emitter and common collector back-to-back bidirectional switches.

Remark 7.36 The diode switch cell has the advantage that only one switching device is required. This minimises the number of gate drivers required for the system. However there are two signicant disadvantages of this arrangement: a. When the device is on there are three series devices i.e. two diodes and the IGBT switch itself. Therefore the losses in the switch are higher than other strategies. b. When the switch is turned on there is no way of controlling the direction of the current through the cell i.e. the cell operates as a normal switch. The inability to control the current direction has implications with respect to commutation strategies. The above two disadvantages are important enough that this cell is not commonly used. The common emitter and common collector switch cells are shown in Figure 7.21. This cell arrangement consists of two diodes and two switches connected in anti-parallel. The diodes are required to provide the reverse blocking capability. common ter and collector cells emitcommon switch

Remark 7.37 There are several advantages of the common emitter /collector switching cells compared to the diode based cell: a. There are only two devices in the conduction path, therefore the switches are more ecient. b. The current direction through the device can be controlled. This occurs because the appropriate switch has to be turned on for current to conduct in the forward direction for this switch. This ability is used in the commutation algorithms as we shall see later.

7-40

Introduction to Other Power Electronic Devices and Applications The most obvious disadvantage of these cells relative to the diode cell is that they have two active devices. The choice of the use of the common emitter version of the switch cell versus the common collector version is no immediately obvious. In the case of the common collector version, the emitters of the switching devices are connected to the incoming and outgoing lines of the converter. Therefore one needs three isolated power supplies with the common for each of the supplies connected to one of the three incoming lines, and three isolated power supplies with the common of each of them connected to the one of the three outgoing lines. Practical issue 7.1 In practice the use of only six isolated supplies for the common collector bidirectional switch is not viable because of the need to minimise stray inductance. The common emitter version of the switching cell requires on isolated power supply for each switching cell (i.e. a total of nine). The common emitters form the ground point for the supply. The common emitter cell is the one most commonly used. The above discussion has been with respect to implementing the bidirectional cells using discrete components. It is also possible to build an integrated matrix converter module, similar to the intelligent power modules used for three leg inverter systems. This has been done by EUPEC using devices connected in the common collector conguration, and is now commercially available. this type of packages has distinct advantages relative to discrete layouts in the lower stray inductances. The switching devices (IGBTs) discussed thus-far, due to the presence of parasitic internal diodes, do not have reverse blocking capability. However, devices such as the MOS turn-o thyristor (MTOs) do have reverse blocking capability, and therefore the bidirectional switch can be built using two devices in anti-parallel. 7.4.4.2 Current Commutation

Basic switching rules were outlined in Section 7.4.2 on page 7-21 which reduced the possible 512 switching combinations down to 27. These switching rules arose from electrical considerations of various switch combinations. However these same electrical considerations also have an inuence on the commutation from one switch combination to another. Remark 7.38 Reliable current commutation between switches in matrix converters in more dicult to achieve than in conventional VSIs since there are no natural freewheeling paths[16]. To understand the issues consider Figure 7.22 which shows two dierent situations of two input phases and one output phase and commutation is occurring from one input phase to another. In Figure 7.22(a) both the switches have been closed onto the same output leg. Clearly this will result in a short circuit between the two input phases and consequent destruction of the switches. Figure 7.22(b) shows the alternative situation where both the switches have been opened. If the switches were carrying current at the time that were opened the input and output inductances would result in a very large voltage spike and destruction of the switch.

commutation

7.4 Basic Introduction to Matrix Converters

7-41

SW1

SW1

SW2

SW2

Load (a) (b)

Load

Figure 7.22: Short and open circuit situations that can occur during commutation.

Practical issue 7.2 Any practical commutation strategy has to avoid both the situations shown in Figure 7.22. In order to avoid the situations that are shown in Figure 7.22 a number of dierent commutation strategies have been devised. Two obvious ones are: break before make approach the outgoing switch is opened before the incoming switch is closed. This prevents the short circuit situation, but because there is an overlap period when both switches are open (to account for the charge storage turn-o delays of the semiconductor switches) then high voltages can occur due to inductive eects. Extra clamping circuitry is required to prevent these voltages from getting too high. make before break approach this is the dual of the previous case and results in a momentary short circuit between the phases. One needs interphase reactors to prevent the short circuit during the switching transient. These inter-phase reactors can be quite large. These two strategies, whilst they work, are not all that satisfactory for the reasons cited above. This lead to the development of the 4 stage commutation process, with the step being: a. Turn o the o-going non-conducting switch. This prevents current reversal, which could otherwise occur during the rest of the commutation process. b. Turn on the on-going conducting switch. At this point one has the ogoing conducting switch on, and the on-going conducting switch on. A short circuit is not generated because the process is utilising the fact that one can control by the choice of device in the switch cell to activate the direction of the current that can ow through the switch cell. c. Turn o the o-going conducting switch. The on-going conducting switch,

7-42

Introduction to Other Power Electronic Devices and Applications

SAa2

VA

SAa1

iL
a

VB
B

SBa2

Load
SBa1

Va

Figure 7.23: Two phase switching matrix example. if it wasnt already conducting the current3 , will now be forced to conduct the load current. d. Turn on the on-going non-conducting switch. This then allows natural current reversal to occur through the switch if required. In order to understand this process in more detail consider Figure 7.23 of two switching cells connected to two phases and a single output line. The state and timing diagram for the commutation process is taken directly from [16], and appears in Figure 7.24. The nomenclature iL > 0 means that the current is in the direction shown in Figure 7.23. Once can see from Figure 7.24 that the switching sequence proceeds through the four steps outlined above. Notice that there is a point where SAa1 ad SBa1 are both closed. However, a short circuit cannot develop because the SXa1 switches can only carry the iL current in the direction shown in Figure 7.23. Therefore if VA > VB then the diode in series with SBa1 will ensure that the device is turned o and no short can develop. SBa2 is already o as we have not turned it on. Similarly if VB > VA then SAa1 will be o, and SAa2 has not been turned on. Remark 7.39 One can see that the four stage commutation process exploits the fact that the switches have the extra degree of freedom at that direction of current ow through the switch is under direct control.

Remark 7.40 One variant of this technique is to only gate the conducting device. By doing this the sequence can be shortened since the initial (1100) state is not there, but instead it is (1000). Similarly the nal state in the example of Figure 7.24 becomes (0010). Therefore only the top path of two transitions occurs.
3 The on-going conducting switch may not have been conducting current because the voltage across the on-going switch device may be been such that the device is eectively reverse biased.

7.4 Basic Introduction to Matrix Converters

7-43

SAa

1 0 1 1 0 0

0 1 1 1 0 0 0 0 0 1 1 0 0 0
td Timing diagram iL > 0

SBa
SAa1

0 0 1 1

SAa2
SBa1

SBa2

X X ) X X

SAa1 SAa2 SBa1 SBa2

iL > 0

1 1 0 0

1 0 0 0

1 0 1 0

0 0 1 0

iL < 0

0 1 0 0

0 1 0 1

0 0 0 1

0 0 1 1

Steady state

Transitional states

Steady state

State transition diagram

Figure 7.24: Four step commutation process between bidirectional switch cells in Figure 7.23.

7-44

Introduction to Other Power Electronic Devices and Applications Practical issue 7.3 One practical issue with the four stage and two stage commutation sequences is that they rely on accurate knowledge of the current direction in order to determine which devices to turn on. This is particular the case with the two stage process, as there is no natural current reversal in this sequence (i.e. the two anti-parallel devices in the switch are no both actively gated at the same time). One simple technique used to prevent problems is to no carry out any commutation when the absolute value of the current is below a certain value. This prevents ambiguity of current direction form upsetting the commutation. However this technique results in distortion at low currents. There are other techniques using voltage measurements across the devices that solve this problem 7.4.4.3 Input Filters

Filters are required at the input of a matrix converter in order to reduce the switching harmonics present in the input current. This lter must have the following characteristics[16]: a. have a cuto frequency lower than the switching frequency of the converter; b. minimise it reactive power at the grid frequency; c. minimise the volume and weight for capacitors and chokes; d. minimise the lter inductance drop at rated current in order to avoid a reduction in the voltage transfer ratio. The matrix converter was originally envisaged as a pure silicon converter solution, however in reality the passive ltering components become a signicant part of the design. It has turned out in some converter designs that the LC components of the lter have been comparable in size to those required for a conventional DC link based inverter. An addition issue related to the input lters is that they can cause transient over-voltages on start-up due to ringing of the lter. In order to prevent this series resistors are used during the start-up phase, and these are shorted once the converter is running. Figure 7.25 shows a matrix converter with the LC input lters. Notice the damping resistors at the input. 7.4.4.4 Over-voltage Protection

Over-voltages can occur in matrix converters for the following reasons: input voltage transients interacting with the input lters; interruption of over-current faults when the load has inductance. The usual solution to this problem is to connect a diode based clamping circuit to the input and output of the converter. Figure 7.26 shows this general conguration. As can be seen it is simply a rectier circuit. Because a conventional converter already has such a circuit as an implicit part of its design, there is no need for an explicit protection circuit. There are some other more clever strategies that are employed that try to achieve the same result with less components.

7.4 Basic Introduction to Matrix Converters

7-45

A
SAa
SAb

SAc

B
SBa
SBb

SBc

C
SCa
a

SCb
b

SCc
c

Figure 7.25: Matrix converter input lters and damping resistors.

LC filter

50Hz supply

Matrix Converter

Motor +

Diode clamp circuit

Figure 7.26: Matrix converter with over-voltage diode clamp protection.

7-46

Introduction to Other Power Electronic Devices and Applications

7.4.5

Comments

After almost three decades of research the modulation and commutation strategies and control methods for the matrix converter are reasonably mature. Two early drawbacks of the converter were the lack of a suitably packaged bidirectional switches and the large number of semiconductor switches required. Over recent years these limitations has largely been overcome with the introduction of power modules which include the complete power circuit. A remaining issue is the size of the passive ltering components in the converter the dream of a pure silicon converter has not been realised. Research is continuing on reducing the size of the ltering components. When introduced approximately 30 years ago the matrix converter has the potential to be a superior converter, in that one had a bidirectional converter which could control harmonics at the input and output, as well as the input power factor. However, in the intervening years other converters did not stand still, and the active front end (AFE) on the conventional inverter also oers the same capabilities. This is a variant of a very mature technology. In addition the AFE inverter also has implicit ride through capability when there are supply dips due to the presence of a DC link capacitor. As it stands at the moment the matrix converter is used for niche applications. The US military are investigating its use in the electric tank, where its compact size and robust because of the absence of a DC link capacitor may be an advantage. A motor and drive manufacturer has also integrated a matrix converter into a motor frame, where again the lack of a large DC link capacitor is an advantage.

Chapter 8

Grid Connected Converters and Renewable Energy Systems

8.1 Introduction

An excellent resource for this chapter is the new book [21]. This book concentrates specically on issues related to the use of converters to interface photovoltaics and wind turbines to the electricity grid. Although it has been written from a European perspective, nevertheless most of the material is relevant to Australia. Much of the material in this Chapter is based on content from this book. The clean production of energy is becoming increasingly important. In fact the production of low cost, environmentally friendly energy is probably the greatest challenge of our time. The consensus amongst creditable climate scientists is that man made greenhouse gases are a signicant contributor to the currently measured rise in global temperature. Therefore low or zero emission production of energy is going to become increasingly important as we move into the future. Even if one is skeptical about the climate science, the sustainable use of the earths resources is a worthy goal in its own right. The availability of low cost energy and a system to distribute this energy is a key contributor to the lifestyle that we enjoy. It will also be a key factor in changing the lifestyles of those in the 2nd and 3rd world as they move towards the lifestyle which we enjoy. Therefore the current issues surrounding clean low cost energy are not going to go away to the contrary they will be exacerbated. We can all see this happening with the rapid development of China and India. These factors mean that the issues that will be discussed in this Chapter are of increasing importance. This Chapter will not be attempting to consider the complex economic factors that surround the transformation of the worlds energy production systems away from fossil fuels, and towards sustainable sources. Instead it will concentrate at a much lower level on the technical issues of how to interface renewable sources to the electricity grid. Issues associated with the control of an electricity

8-2

Grid Connected Converters and Renewable Energy Systems grid with high renewable penetration will only be considered in the form of grid codes that are still under development. The remainder of this section will consider the current statistics related to the use of wind power and photovoltaics.

8.1.1

Wind Power

Wind power is a fairly mature technology for renewable generation. The nice feature about this technology is that energy can be available at all times of the day (although wind resources tend to be more available during the day time). This technology developed rst because, in principle, the technology required has been known for a long time blade design, induction generators, towers. The use of power electronics in wind power has been a more recent development as power electronics became cheaper, and the demands on the wind turbines motivated the exploration of the use of this technology. Even though wind power is a mature technology, the cost of the energy has limited its penetration in many countries. Without subsidies it was simply too expensive compared to the fossil fuel technology. This is particularly the situation in Australia. The situation is Europe has been somewhat dierent, where subsidies have been available for many years in countries such as Denmark. Government support for wind power technology lead to the development of a wind turbine industry in Denmark that is now selling turbines on the international market.

8.1.2

Photovoltaics

Photovoltaics is also a fairly mature technology for renewable energy. Having said that, its degree of penetration is nowhere near that of wind, although it is growing. Surprisingly, Europe has a fairly high penetration of photovoltaics even though in many parts of Europe there resource is not that good. Of the European countries, Germany has the most PV systems installed. Australia has excellent solar radiation resources, but as yet has not exploited this to the extent that the resource availability would indicate. However, this is changing as more domestic photovoltaic systems are being installed (supported by generous government subsidy schemes), and some large scale solar array projects are in the ong.

8.1.3

Outline and Scope of this Chapter

This chapter, by virtue of the fact that it is only a small part of a general course on power electronics, is limited in scope and depth. Having said that, it will attempt to at least cover, to some degree, the key issues in the use of converters to interface photovoltaics and wind turbines to the grid. It should be noted that this Chapter concentrates on the technical aspects of grid interfacing, and the politics and economic aspects of renewables is not the main focus. Note 8.1 The presentation in this chapter is limited to grid interfaced systems. The other class of systems that use renewables are microgrid systems. These are distinguished by the fact that they operate separate from a large innite bus that

8.2 Photovoltaic Inverters is the grid system. This fact leads to a lot of interesting control issues, some of which are: getting converters to share load on the grid; issues related to handling the variable input energy available in wind and solar systems when there is not the large reverse of the gird there to buer out these variations; reliability and security of supply; power quality issues. There are also broader issues involved in these systems as well. Because one is not constrained by the grid then, for example, consideration can be given to whether the underlying system of the microgrid is DC voltage based. I With both photovoltaic and wind turbine interfacing the same topics will be covered. Grid requirements, as legislated, will be briey introduced and their signicance highlighted. Then the specic issue of synchronizing the control strategies to the grid system will be introduced. This is very much a specic detail, but of great practical importance for the development of high performance control strategies. Basic control strategies for grid connected power electronic systems will be introduced, and some of the higher level control strategies that sit on top of the basic algorithms will be introduced (such as Maximum Power Point Tracking for Photovoltaic systems). This Chapter will hopefully give you a feeling for how power electronics is an enabling technology for the introduction of renewable energy systems.

8-3

8.2
8.2.1

Photovoltaic Inverters
Review of Power Electronic Congurations for Grid Connected Converters

There are a number of possible topologies that can be used for photovoltaic converters. These topologies can be divided into two broad categories based on whether they are: Three phase converters generally used in high power photovoltaic applications Single phase converters generally used in domestic and lower power applications These two categories can then be further divided into two main types of converter topologies: Galvanically isolated converters Non-galvanically isolated converters Galvanic isolation is typically achieved by either using a mains frequency transformer on the mains frequency side of the converter, or alternatively using a high frequency transformer as part of a DC-DC converter in the midst of the overall

8-4

Grid Connected Converters and Renewable Energy Systems converter structure. Sometimes a boost converter is required in a photovoltaic converter system (if the voltages from the panel are no sucient to connect to the mains), and consequently galvanic isolation is achieved as a byproduct of this. In Australia up until relatively recently most domestic scale photovoltaic converters were galvanically isolated usually with a mains frequency transformer placed on the grid side of the output lter. This was the general practice because of the obvious safety benets associated with isolation of the PV array from the mains supply that occurs with such an arrangement. In Europe the situation is dierent, with non-isolated domestic PV converters being commonplace for some 15 or more years. One obvious question to ask at this juncture is: What are the pros and cons of galvanic versus non-galvanic isolated converters? The obvious pro of the transformer based systems is the safety that ensues from its inclusion. However there is (literally) a price to pay for this, namely: Higher cost for the converter. The unit is bulky and heavy. The converter loses about 1% to 2% in eciency due to transformer losses. The safety issue is still there, but set against this is the fact that transformerless converters have been used safely in Europe for over 15 years, and their voltages are in many case similar to ours. So the balance of safety versus economic and eciency gains has seen the increased use of transformerless systems in Australia [22]. In addition to the particular hardware architecture of the inverter there is a hierarchical control structure to control. A generic hardware and control structure block diagram is shown in Figure 8.1. Not all PV systems will have all of the hardware components. For example, if the PV string can produce high enough voltages then the boost converter stage may not be required, and as we have noted some converters are directly connected to the grid, and therefore there is no transformer present. The main hardware components of the PV system are fairly obvious. Of course there are the PV panels themselves. They are usually connected together in a string so that an appropriate voltage is generated from the array. What is an appropriate voltage? In many cases this will be a voltage that will give sucient headroom in voltage to allow a DC-AC conversion to the grid without having to have a boost converter. The presence of the boost converter obviously leads to extra complexity and lowers the eciency of the system. The boost converter, as eluded to in the previous paragraph, is required if the PV string voltage is below the voltage required for the DC-AC conversion. There may be a variety of reasons for this being the case, and depends on the application. The next component in the hardware structure is the DC-AC converter. There is a variety of structures that can be used for this component of the system, the details of which are the main subject of most of this Chapter. Whatever the DC-AC converter is, the next component is a lter. In the case of the diagram it is shown as an LCL lter as it is the most common lter used for this application. The lter is the purpose of removing the switching harmonics

8.2 Photovoltaic Inverters from the output waveforms so that grid harmonic standards are satised. Notice that the AC feedback measurements occur after the lter so that there are no switching harmonics to corrupt them. Remark 8.1 It should be noted that the LCL lter is a more elaborate lter. In some cases a simple inductor suces in order to achieve the ltering required. The use of this has the added advantage that the dynamics introduced by the lter are less complex, which simplies the control. I The control structure in Figure 8.1 is quite complex, and is one of the features of PV power electronic systems that set then apart from variable speed drives. The control in the PV case in some senses is more complex than variable speed drive control the PV systems have a deeper hierarchical structure. The PV control is divided into a number of sub-blocks: Basic grid control This block as the name implies, provides the basic control functions to interface the inverter onto the grid. It allows synchronization of the converter output voltages to the grid voltage, controls the DC link voltages so that enough voltage is available for the current control to work. These functions have a lot of similarity to variable speed drive converter control functions. PV specic functions This block contains a number of control functions that are unique to the PV application MPPT (Maximum Power Point Tracking) is the name given to a class of algorithms that control the current from converter so that the maximum power is obtained from the PV array under all irradiation conditions; anti-islanding protection is required to detect if the a circuit breaker has been opened on the grid isolating the section of the grid where the PV array is. The PV array should disconnect under this condition; and nally some monitoring functions of the PV array itself to check on cell performance. Ancillary functions These are high level functions that may or may not be performed depending on the sophistication of the PV system. For example active ltering of harmonics can be performed; micro-grid control functions such as control of Vars or power factor at the connection point to the grid. Note 8.2 In this chapter we shall only be considering in detail the basic converter functions in this control hierarchy. I 8.2.1.1 How do photovoltaic devices work?

8-5

In this section we will briey consider the basic mechanism that allows a semiconductor diode to generate a voltage, conduct current, and ultimately generate power. This is provided simply as background material, and is not really essential to know with respect to the power electronics side of the system. However, as a philosophical point, engineerings should not be considering systems to be black boxes, and hopefully your natural curiosity will have you asking the question as to how this all works. You should have enough background from your basic semiconductor Physics courses to understand the basic principles of operation.

8-6

Grid Connected Converters and Renewable Energy Systems

PV Panels string

DC-DC Boost converter

DC-AC PWM-VSI

LCL Low Pass filter

Xformer and Grid

IP V

VP V

PWM

VDC

PWM
Ig Vg

Grid Current VDC synchronization control control Basic grid connected converter functions MPPT Anti-islanding Grid/PV plant protection monitoring PV specific functions Micro-grid control Ancillary functions Grid support (V/F/Q)

Active filter functions

Figure 8.1: Block diagram of a generic PV system [21] Remark 8.2 Even though I have just stated that knowing the fundamental operational principles of photovoltaics is not really necessary for this course, these principles have a profound inuence on the control strategies used for photovoltaic systems. The VI relationship of a solar cell, which is irradiation dependent, is non-linear. It means that there is a optimal point of operation to get the maximum power out of a cell for a particular irradiation level. The algorithms to nd this point at called Maximum Power Point Tracking (MPPT) algorithms, and they are used to determine the current set points for the power electronic controllers that interface to PV array to the grid or load. I Remark 8.3 Another inuence that the basic operation of a solar cell has on the design of a power electronic system is related to the number of converters in a large system. The irradiation on large arrays of solar cells in many cases will not be uniform due to partial shading from clouds for example. Partially shaded cells become a loading on the other cells in a series string, and reduce the eciency of the system. This can be partially catered for if the cells are connected together into smaller arrays where maximum power point tracking can be applied to each subsystem separately. I Figure 8.2 shows the band gap diagram of a pn junction (i.e. a diode band gap). As can be seen from the diagram the doping to produce the p and n materials eectively moves the Fermi level of the semiconductors. Since the p and n materials are connected together then the only stable situation is that the Fermi level is constant on both sides of the junction. This is forced by diusion which is a consequence of the dierent concentrations of holes and electrons in the materials due to the doping. As a result of this diusion process and electric eld is developed in the material which drives the carriers in the opposite direction to the diusion process. The equilibrium is reached when the

8.2 Photovoltaic Inverters

Centre of junction

8-7

Space charge region Photon Conduction band Electron Metal ohmic contacts Fermi level Hole Forbidden Energy gap Metal ohmic contacts

n semiconductor

p semiconductor Valence band

Figure 8.2: Band gap diagram of a solar cell (pn junction).

drift due to the space charge equals the diusion current. The voltage produced by the electric eld is the contact potential of the diode, and is typically 0.6 to 0.7 volts for Silicon. Remark 8.4 Normally the contact potential cannot be seen from the outside of the diode. If one places, for example, a voltmeter on the diodes terminals one will not see any voltage and no current will ow. The metal-semiconductor contacts of the probes on the semiconductor essentially cancel the internal electric eld. This should not be a surprise, because if there was an external voltage then a current could ow and energy could be extracted. This would violate the conservation of energy, as there is no source of energy in the diode. I If photons from a radiation source can incident on the pn junction around the space charge region as shown in Figure 8.2, and if the energy of the photon is larger than the band gap (forbidden gap) energy for the particular semiconductor material (the energy of a photon is E = hf where h is Plancks constant, and f is the frequency of the radiation), then an electron can be excited from the valence ban into the conduction band of the material. This process forms a hole in the p type material, and an free electron is generated in the p material. If this occurs in the space charge region, or near it, then the electron will be sweep by the space charge electric eld towards the n material. It eective rolls down the potential gradient as shown in the gure. In this situation current can ow in an external circuit, and energy can be provided as the energy is coming from the photons striking the junction area and generating the carriers.

8-8 8.2.1.2

Grid Connected Converters and Renewable Energy Systems Equivalent Circuit of a Solar Cell

As can be seen from the previous explanation the mechanisms within a solar cell are quite complex, and when it comes to the ne detail, it involves quantum mechanics. In order for electrical engineerings to have a simpler way of explaining the properties of a solar cell or array of solar cells, and equivalent circuit model is needed. This model can be developed from the normal equation for the current through a diode. The normal diode equation is [23]: ID = I0 (e nkTK 1) where: ID I0 q k TK n V
qV

(8.1)

the diode current -positive when forward biased diode the reverse saturation current the charge of and electron = 1.6 1019 C Boltzmanns constant = 1.38 1023 J/K the temperature in Kelvin the diode ideality factor 1 2 the voltage across the diode - positive for forward bias

Under normal non-illuminated circumstances when the diode is reverse biased then the reverse saturation current is the only current that ows. This can be seen from (8.1) when V is negative and the expression becomes: ID = I0 e nkTK
qV

I0 I0

(8.2)

Remark 8.5 The I0 current is essentially the current due to the generation of hole-electron pairs within the Lp and Ln distances of the space charge region. The Lp and Ln are the average distance a hole and electron respectively can diuse as minority carriers before recombining. Therefore if minority carriers are generated within Lp,n distances of the space charge region then they can make it to the space charge region and be swept across the junction by the space charge electric eld there. I We shall briey go through the development of the basic equations for a solar cell, and this will lead onto the equivalent circuit for the device. This presentation is not comprehensive and the interested reader is encouraged to look at the reference (or other texts on semiconductor physics) to nd out more details. The following discussion is with respect to Figure 8.3. This diagram shows a junction that is optically irradiated. The junction in Figure 8.3(a) is reverse biased and is being irradiated with energy that is greater than the band-gap of the material. Therefore electron-hole-pairs (EHP) will be generated. Figure 8.3(b) shows a section of the n material on the right side of the junction. As mentioned previously Lp is the mean diusion distance of holes in the material before recombination. Therefore if the irradiation is generating gop holes/cm3 /sec then these carriers will be able to diuse to the space charge

8.2 Photovoltaic Inverters

8-9

E W

n p n A V

(a)

(b)

(c)

Figure 8.3: Optical generation of carriers in a pn junction. region and then be swept to the p side of the junction by the electric eld in the space charge region. The number of carriers involved in this current is ALp gop . Similarly in the p material we have ALn gop electrons generated per second within Ln of the space charge region. Therefore the total current owing due to this optically generated current is: Iop = qAgop (Lp + Ln ) (8.3)

Remark 8.6 If there are gop excess EHP (Electron-hole-pairs) are being generated within say n material, then these excess carriers will diuse in both directions i.e. 50% will go in one direction, and 50% in the other if one assumes, for simplicity, a two dimensional diusion process. However, if the n material is being uniformly illuminated then this will clearly balance out as this diusion in each direction is occurring at all points in the material, and therefore there is no net diusion. However, due to the boundary at the space charge region this countering of the diusion in one direction with diusion in the other no longer occurs. In the case of Figure 8.3(a) all of the hole carriers within Lp of the space charge region can diuse to the space charge region without a counter group of holes from Lp to the left of the beginning of the space charge region countering the hole ow. The problem with this last statement is all of the hole carriers. We have just said that 50% go in one direction and 50% in the other. This would mean that only 50% of the holes generated within Lp of the space charge region would be contributing to the current. This is true if both diusion directions are feasible. In the case of the holes at the extreme right edge of the n material the holes cannot diuse to the right as there is no material to diuse into. Therefore all of the hole have to be diusing to the left. At the space charge region boundary holes are being swept across the region. We do not have the same end eect here that is occurring at the right ohmic contact there is somewhere for the left diusing holes to go. The push-back hole current ow from the right edge of the material aects the overall net hole ow from left to right in the material. If the material is in steady state then the hole ow to the space charge region if the normal 50% probability base ow plus the 50% push-back eectively from the other end of the material. Therefore all

8-10

Grid Connected Converters and Renewable Energy Systems of the carriers in the ALp volume are being swept across the space charge region boundary for the material concentrations to be in a steady state under optical excitation. I Using this expression we can augment (8.1) as follows: ID = I0 (e nkTK 1) qAgop (Lp + Ln )
qV

(8.4)

Remark 8.7 The gop rate is directly related to the number of photons of the correct energy hitting the Lp,n are from the junction. As can be seen from (8.4) the qAgop (Lp + Ln ) is eectively a current source whose value is related to illumination. I If the diode is short circuited then V = 0 in (8.4), and therefore there is a reverse current owing of Iop . If the diode is open circuited then ID = 0 and therefore (8.4) can be rearranged as: Voc = nkTK ln q qAgop (Lp + Ln ) +1 I0 (8.5)

Remark 8.8 If would appear from (8.5) that Voc can increase without limit as gop is increased. However this is not the case. The reverse saturation current is due to the thermal creation of minority carriers within the Lp,n distances of the space charge region. Therefore: I0 = qA Lp Lp pn + np p n (8.6)

where pn is the steady state minority concentration of holes in the n material, and np is the steady state minority concentration of electrons in the p material, and p and n are the respective minority carrier lifetimes. Now pn and np are determined by the doping and the temperature. However the p and n terms become smaller as the EHPs due to optical generation increase, and therefore the np terms pn and n become larger. This clearly means that I0 becomes larger and p
op p n in (8.5) will stabilise at some value it does not therefore the term I0 continue to increase. It turns out that this maximum value of Voc , regardless of the gop value, is V0 , the contact potential of a diode (typically about 0.6 V). This makes sense as V0 is the maximum voltage that can appear across a diode in forward bias. I

qAg

(L +L )

The above discussions can lead to the following equivalent circuit for an ideal solar cell. Note that this equivalent circuit comes directly from the expressions developed above. As noted previously, the gop optical EHP generation operates virtually like a current source, and its value is basically the short circuit current of the cell. Secondly the open circuit voltage of the device is limited to the contact potential, regardless of the gop value. This leads to the following ideal equivalent circuit shown in Figure 8.4. As can be seen the short circuit current is IL and the open circuit voltage is V0 . Clearly if a load is place across the cell then as it is increased more of the irradiation current will be diverted into the diode. The current through the diode is related to the output voltage by (8.1). In a real solar cell there are other eects. For example the solar cell has a series resistance (RS ) which is related to the resistance of the semiconductor

8.2 Photovoltaic Inverters

8-11

Figure 8.4: Equivalent circuit of an ideal solar cell.

Figure 8.5: Equivalent circuit of a non-ideal solar cell. materials as the current ows from the cell out of it terminals and into the load. There is also a shunt resistance (RSH ) which is related to leakage currents around the cell. We want RS to be as small as possible, and RSH to be as large as possible. Figure 8.5 shows the non-ideal model of the solar cell that includes these components. From Figure 8.5 one can write the following expressions for the current and voltage: I = IL ID ISH (8.7) and the current through the diode and the shunt resistor is governed by the voltage that appears across them, namely: VD = V + IRS (8.8)

We can determine the current through the diode from (8.1), and the current through RSH is: VD ISH = (8.9) RSH Therefore the solar cell output current is: I = IL I0 e
q(V +IRS ) nkTK

V + IRS RSH

(8.10)

8-12

Grid Connected Converters and Renewable Energy Systems

+ Solar cell Solar cell series array

Figure 8.6: Circuit symbols for a solar cell and a series array of solar cells. Remark 8.9 Equation (8.10) cannot be solved in closed form, and has to be solved numerically for I. In addition the parameters in the equation cannot be directly measured, and usually have to be estimated from terminal measurements of the device under various test conditions. I Remark 8.10 The temperature of the cell also has important eects on its operation. If the temperature increases then the Voc of the cell will decrease. This in turn decreases the maximum possible output power. Therefore one wants the cell to operate at lower temperatures rather than high temperatures. I Practical issue 8.1 One thing that can be surmised from the model is that if solar cells are connected in series (as they usually are to increase the output voltage), and if one or more cells are not illuminated as much as others, then current will be forced up through RSH and RS resulting in a loss of power for the series array, and heating of the poorly illuminated solar cell. The reverse voltage from this current can result in the breakdown of the pn junction. The voltage for this is from 10 to 30 volts. Therefore one shaded cell can absorb the voltage produced by 20 or more unshaded cells. Reverse voltage diode clamps are usually place around practical solar cell arrays to prevent this from occurring.I The circuit symbols for an individual solar cell and a series array of cells are shown in Figure 8.6. The other important aspect of the operation of solar cells and arrays is how to extract the maximum power from the devices. The IV characteristics of a solar cell can be gleaned from Figure 8.3(c) by inverting the curves in the bottom right hand quadrant (this is the quadrant that the system operates in when the cell is generating power). Redrawing this section of Figure 8.3(c) we get Figure 8.7, which also shows the power diagram and the gure-of-merit power rectangle (shown in grey). The larger this rectangle the more power the cell can produce (as the area is ID V ). The theoretical ideal power would be Isc Voc . Also drawn on this diagram is the power that the cell develops at various currents and voltages for the IV characteristic drawn. One can see that the power reaches a maximum value as the voltage from the cell increases, and then it begins to fall to zero as the current from the cell decreases. For your information a data sheet for a typical PV panel appears in Appendix F.2.

8.2 Photovoltaic Inverters

8-13

Figure 8.7: Maximum power diagram for a solar cell. Remark 8.11 The IV characteristic shown in Figure 8.7 varies depending on the temperature and illumination of the cell and the series and shunt resistances 1 of the cell. The load line shown on the diagram (the RL lines) assumes a value of the eective load resistance on the cell of RL . The R1 line crosses through Lo the ID V curve at its maximum power value, and therefore the load would be receiving the maximum power that the cell can produce. The RLo value is the optimal load resistance for the condition drawn. The two other load lines on the diagram are for values of load resistance that are smaller than the optimal value ( R1 ) and larger than the optimal value ( R1 ). As can be seen from the L1 L2 diagram in both cases (P1 and P2 ) the power produced by the solar cell will be less than the maximum value (Po ). I Remark 8.12 As mentioned in the previous remark, the ID V characteristics of the solar cell change with illumination and temperature. In order for the correct eective resistance to be place on the solar cell under varying conditions the maximum power point has to be found. This is achieve in practice by Maximum Power Point Tracking (MPPT) algorithms. Most of these algorithms work by carrying out a small perturbations in the current supplied to the load and then measuring the change in the power. If the power gradient is positive then another perturbation occurs in the same direction. If not then a perturbation in the opposite direction occurs. This approach assumes that the power electronics is operating as a programmable current source. I Summary 8.1 The main issues that arise from this section that are related to interfacing PV systems to a load or the grid are: A solar cell can be modeled as a current source in parallel with a forward biased diode.

8-14

Grid Connected Converters and Renewable Energy Systems The current source current value is related to the irradiation of the solar cell. Solar cells are usually connected in series to get higher voltages (the voltage of a single cell is about 0.5 V). If some cells in a series connected array are shaded their current source is not as large as the others. This can result in excessive power dissipation in the shaded cells, and lowers the eciency of the array. Shading eects mentioned in Practical Issue 8.1 can be handled by changing the power electronic architecture so that small groups of cells have their own power converter. This will allow power optimisation for the shaded cells, and prevents the eects mentioned in the previous point. Clearly there are cost implications involved in this solution. In order to extract the maximum power from the solar array the power electronic controller has to emulate the optimal load resistance. This value changes dynamically as irradiation and temperature changes. A MPPT algorithm is required to achieve this. I 8.2.1.3 Traditional PV Inverter Topologies

In this section we shall consider in a little more detail the common topologies for PV inverters. These were briey introduced in Section 8.2.1 when the inverter systems were broadly categorised into three phase, single phase, and galvanically isolated and non-isolated topologies. As also mentioned previously, galvanically isolated power electronic topologies have, until the last few years, been the main category of PV inverters that have been installed in Australia. This was probably due to the inherent safety of these systems, and the conservative approach Australian regulation authorities tend to take when systems are to be installed into a domestic premise. However, the non-galvanically isolated topologies have been popular in Europe for a number of years now, and over the last few years they have started to become popular in Australia. The reason for this increase in popularity can readily be seen in Figure 8.8 (which is taken from [24]). This gure compares the dierent inverter topologies that would be used in domestic applications on the basis of eciency, weight, and volume. As can be seen, it is fairly clear that the non-isolated inverters win in all these categories this is the driving motivation for their introduction in Australia. It is also clear that within the isolated category the high frequency transformer oers smaller weight and size, but it does not necessarily have better eciency than the low frequency transformer design. The fact that there have not been major safety issues with transformerless systems in Europe appears to have allayed the fears of the regulation authorities in Australia1 . Other issues such as DC injection to the grid, that can occur with directly connected systems, can also be handled with appropriate control. Three phase systems are usually involved in PV systems with large powers, and can be used to interface a DC bus being fed from a number of PV arrays to the AC grid supply. These three phase inverter systems are fairly standard
1 It

should be noted that isolation is a requirement in the United States.

8.2 Photovoltaic Inverters

8-15

Figure 8.8: Relative merits of dierent inverter topologies for PV systems [24].

8-16

Grid Connected Converters and Renewable Energy Systems and are in wide use in the AC variable speed drive industry. They are treated elsewhere in these notes, and this will not be repeated here. Two structures that are used in larger power systems are the one phase multi-string converter. This type of system breaks the PV array into sections, each with a DC-DC converter that implements the MPPT algorithm. These DC-DC converters feed onto a common DC bus which in turn feeds into a single phase DC-AC converter. Usually these are arranged as three systems, with each of the DC-AC converters feeding into separate phases. Figure 8.9 shows the general conguration of this arrangement. Figure 8.10 shows a detailed view of one of the three modules. As can be seen the DC-DC converters are non-isolated, therefore they have low losses (as compared to an isolated high frequency converter based system). The grid interfacing is taken care of by the totem pole output converter. Remark 8.13 One of the best features of the topology shown in Figure 8.9 is that the MPPT and voltage control can be taken care of by the DC-DC converter controllers, and the grid interfacing control by the control unit (CU) shown. The DC bus essentially isolates these two control algorithms. This allows the controllers for these dierent output objectives to be designed independently. I Remark 8.14 Another advantage of the multi-DC-DC converter based topology is that each DC-DC converter can implement its own MPPT algorithm, thereby taking into consideration the particular circumstances of the solar panel array connected to the converter. This allows the possibility of dierent panels being in dierent orientations, and also accounts for dierential shading across the array. I An alternative arrangement of this is to use a single three phase converter instead of the three single phase ones. This conguration is shown in Figure 8.11, and the number of switches involved is the same. The only dierence between these two approaches is the control with respect to the grid interfacing one uses three single phase controllers, and the other a three phase control algorithm. In the three phase inverter case special control strategies would have to be undertaken to account for unbalance in the grid voltages (if they exist), whereas in the single phase case there is no concept of unbalance as the control is implemented on a phase-by-phase basis. Remark 8.15 Three phase transformerless topologies tend not be be used very much. The main reason is the the DC voltage needs to be relatively high at least 600-VDC for a 415 VAC line-to-line mains. The DC voltage is limited (in Europe) to 1000-VDC for safety reasons. It is considered that this voltage range is too narrow given that there are DC voltage changes due to temperature, and also the grid voltage can change. Single phase systems on the other hand only have to handle the line-to-neutral voltages. In addition to this reason, many manufacturers want to make up their three phase systems by using three of their single phase systems. This makes sense from the manufacturing, production and maintenance point of view. I The single phase inverters that are commonly used at the domestic level, and with smaller scale PV systems will be the focus of our attention in this section. A survey of power electronic systems for grid integration can be found

8.2 Photovoltaic Inverters

8-17

= = = = = =

CU

Converter 1

= = = = = =

CU

Converter 2

= = = = = =

CU

Converter 3

Figure 8.9: Single-phase multi-string converter [25].

8-18

Grid Connected Converters and Renewable Energy Systems

DC Bus + L DC-DC Conv 1

DC-DC Conv 2

Utility Grid L DC-DC Conv 3

Figure 8.10: Detailed view of a single single phase output module [25]. in [25]. Some of the following discussion will be based on the contents of this paper together with [21]. Figure 8.12 shows the basic conguration of a modern transformerless PV bridge converter. This circuit forms the basis for most modern converters that are used in domestic situations. As can be seen from the gure the circuit is simply a basic single phase bridge converter as discussed in other parts of these notes. As we shall see, this basic circuit has some problems, that are not all that obvious, when used in the transformerless PV application. Remark 8.16 A few things to note from Figure 8.12: The PV array is not electrically isolated from the mains supply. Therefore the PV array is oating at some voltage with respect to the ground (as noted previously). The converter uses a very simple inductor lter. The PV array has to have a voltage high enough so that the converter can operate directly connected to the mains without a boost converter. In Europe, where the voltages are much the same as Australia, the minimum PV array voltage is 350-VDC. There is a capacitance between the isolated PV array and the ground with a voltage Vcg across it. If there is an AC component to this voltage a current will ow through this capacitance. If there is substantial current ow through the Cg parasitic capacitance there is the possibility of electrical shock to a person touching the array. In addition high frequency currents through this capacitance would contribute substantially to EMI pollution, especially if arrays with this issue were widely deployed.

8.2 Photovoltaic Inverters

8-19

= = = = = = = = = = = = = = = = = = = = = = = =

CU

Figure 8.11: Multi-string converter with a three phase output stage [25].

8-20

Grid Connected Converters and Renewable Energy Systems

L L L N

Figure 8.12: A transformerless bridge converter interface for a PV system. For safety reasons the PV array and the associated power electronics has to be double insulated. I The basics of PWM for a full bridge converter (aka a H-bridge converter) were developed in Sections 1.3.2.2 and 2.4.7 and will not be repeated here, however as eluded to previously the modulation strategy adopted with this converter has profound aects on its safety and therefore usability in domestic environments. Let us initially consider bipolar switching. In this mode of switching we have the following characteristics: The two legs are switched so that S1 = S4 = closed or S2 = S3 = closed at a high frequency and the switching is so arranged so that the output fundamental is some desired fundamental frequency. No zero voltage state of the inverter itself is possible (although a zero average output voltage is possible). The other very interesting aspect of this modulation strategy is that the Vcg (the PV array to ground voltage) only has a small amplitude grid frequency component to it (this will be shown shortly). Therefore the current owing through the parasitic capacitance between the array and the ground is very small due to the high impedance of this capacitance at these frequencies. The following discussion is with reference to Figures 8.13 and 8.14 which show the equivalent circuits for the PV H-bridge converter when switches S1 and S4 are turned on, and S2 and S3 are turned on. These are the two state associated with bipolar modulation switching. We are interested in what happens to the voltage across the parasitic capacitance between the PV panel and ground. Carrying out KVL around the loop shown in Figure 8.13 we can write: VP V + 2L di vac dt di L dt = = 0 vac VP V 2 (8.11) (8.12)

8.2 Photovoltaic Inverters

8-21

+ i L

Figure 8.13: Equivalent circuit for the H-bridge PV converter with S1 and S4 turned on.

i L

Figure 8.14: Equivalent circuit for the H-bridge PV converter with S2 and S3 turned on.

8-22 Clearly:

Grid Connected Converters and Renewable Energy Systems

di vac VP V = (8.13) dt 2 Similarly one can do the same with Figure 8.14 allowing us to write: Vcg1 = L VP V + 2L di + vac dt di L dt = = 0 (VP V + vac ) 2 (8.14) (8.15)

Therefore, we have the following expression for the common mode voltage under these switching conditions: Vcg2 = = Vcg2 = di + vac dt VP V vac + vac 2 2 vac VP V 2 L (8.16) (8.17) (8.18)

We can now work out the change in the voltage across the parasitic capacitor between then two switching positions: Vcg = = Vcg = Vcg1 Vcg2 vac Vpv vac VP V 2 2 0 (8.19) (8.20) (8.21)

Remark 8.17 This analysis shows that there is no change in the voltage across the parasitic capacitor when switching occurs, and therefore there will be no high frequency currents owing through the capacitor. I If should be noted that the Vcg voltage is the dierence in voltage between the two switching congurations. The question then remains as to what the actual voltage is appearing across Cg ? Since the dierence in the voltages between the two switching instances is zero, then the voltage to ground is simply either Vcg1 or Vcg2 depending on the time instant. Since, for a grid connected system vac = V sin t then the voltage that appears across the capacitor is Vcg = . Remark 8.18 The overall conclusion is that the voltage appearing across the Cg capacitor is the grid voltage. Since the supply frequency is low, and the capacitor Cg has a relatively small value, then the leakage current through this capacitor is very small. Therefore the potential for enough current to ow through a person touching the outside (insulated) surface of the PV array and receiving an electric shock is virtually zero. I Summary 8.2 The PV connected H-bridge has the following properties with bipolar modulation: V VP V sin t 2 2 (8.22)

8.2 Photovoltaic Inverters Uses the simple bipolar switching algorithm. There are no high frequency switching components in the Vcg voltage. This means that the common mode currents through Cg are very small. The common mode voltage is at the grid frequency. The bipolar switching means that there is higher ripple relative to unipolar switching strategies, and this in turn means that the ltering requirements are increased. The lter inductors are subjected to bidirectional ux transitions. This increases the losses in the inductors, and decreases eciency. The ripple in the current results in reactive power exchanges with the capacitor across the PV array. The current ows associated with this result in extra losses and lower eciency for this converter. The overall eciency of these converters is of the order of 96.5%. The lower eciency of the converter because of the issues raised above means that bipolar modulated converters are not used in commercial PV inverters. I Now let us consider the PV H-bridge converter, but this time with unipolar modulation. Again we are interested in issues related to the current through the parasitic capacitance, as well as the eciency and ltering requirements of the converter. At the outset, we already know that the ltering requirements for a unipolar modulated system, assuming the same switching frequency, will be less than that of the bipolar system (this has come from previous work in the notes on these modulation strategies). In addition to this it is easy to see that the ltering inductors in the converter will be subject to unipolar ux excursions over a switching cycle since the voltage is being switched from VP V to zero volts or from VP V to zero volts, depending on the polarity of the output waveform. Therefore, these two properties mean that the losses in the inductors will be less for unipolar operation as compared to bipolar operation. Let us consider the Vcg voltage with this type of converter. Obviously the situation with S1 = S4 = closed is the same as in Figure 8.13. In unipolar operation the zero voltage is produced by shorting the grid supply, and this is achieved by S1 = S3 = closed. This situation in shown in Figure 8.15. Let us analysis this situation. Similar to the previous analysis we can write: L di di vac + L dt dt di L dt = = 0 vac 2 (8.23) (8.24)

8-23

We can then write the expression for the voltage across the parasitic ground capacitor: Vcg2 Vcg2 = = VP V + L vac VP V 2 di dt (8.25) (8.26)

8-24

Grid Connected Converters and Renewable Energy Systems

L i L +

Figure 8.15: Equivalent circuit for the H-bridge PV converter with S1 and S3 turned on. We are now in a position to calculate the change in the voltage across Cg due to the change in the switch conguration. Using (8.13) we can write: Vcg = Vcg1 Vcg2 vac vac VP V + VP V = 2 2 VP V = 2 (8.27) (8.28) (8.29)

Vcg

Remark 8.19 One can see from (8.29) relative to (8.29) that with unipolar modulation there is a switching component across the Cg capacitor. This switching component, with an amplitude of VP V /2 will have very fast edges, and therefore the spectral components in the waveform will have a very high frequency content. Consequently, even though Cg is a parasitic capacitor (and would have a relatively small value), a high current can ow through it. In practice currents as high as 3 to 4 Amps can ow. The exact current depends on the physical location of the panel with respect to ground. I Summary 8.3 The following can be deduced from this analysis of unipolar modulation: The high Cg current under unipolar modulation means that there is a potential for electric shock if a person touches the outside of the array. This situation is likely to increase Cg and therefore the current. The fact that the grid supply is disconnected from the PV array and its capacitor during the zero voltage period means that there is no reactive power exchange between the supply and the capacitor. This will improve eciency. The lter inductors are only subjected to unipolar ux transitions, and this will lower the losses in the inductors, thereby improving eciency.

8.2 Photovoltaic Inverters Unipolar modulation generates the same harmonic content as bipolar modulation, but can do so at half the switching frequency. Therefore, the ltering requirements of this modulation strategy are less than with bipolar modulation. The eciency of this type of converter can be up to 98%, which is the maximum eciency that has been measured for PV inverters. Despite the extremely good eciency of the unipolar modulated H-bridge it is not used because of the high ground currents and consequent safety issues. I An variation to the unipolar modulation strategy is the hybrid modulation strategy [26]. In this modulation strategy one of the inverter legs is PWMed in the traditional sense, whilst the other leg is switched at the grid frequency (i.e. at 50Hz in Australia). Let us briey consider this scheme. Figure 8.16 shows the H-bridge converter for a hybrid switching algorithm. The only dierence between this and the previous H-bridge converter of Figure 8.12 is that there is only one inductor in the lter. From a modulation perspective Leg B (i.e. switches S3 and S4 ) are switched at the grid frequency. The switching occurs in synchronism with the voltage supply i.e. when Vg > 0 then S4 is closed, and when Vg < 0 then S3 is closed. The equivalent circuits for these two situations are shown in Figure 8.17. Remark 8.20 One can see from Figure 8.17 that for both the cases that the equivalent circuit of the H-bridge is that of the traditional DC-DC buck converter. If Vg > 0 then S4 is closed and the PWM is carried out by S1 and S2 . If Vg < 0 then S3 is closed and again the high frequency PWM is carried out by S1 and S2 . I Remark 8.21 Since the equivalent circuits are buck converters each equivalent circuit can only operate in one quadrant. There are two equivalent circuits for the two dierent switch positions meaning that this circuit can only operate in two quadrants. I Remark 8.22 It is clear from the diagrams that the common mode voltage is a square wave that has moves between 0 volts (S4 closed) and -VP V volts (S3 closed). Since these switching are synchronized with the grid frequency then this square wave has the same frequency. I Remark 8.23 The rst major spectral component is the switching frequency of S1,2 . Therefore this inverter does not get the 2 frequency benet that the normal H-bridge does in unipolar modulation. Consequently it will have more stringent ltering requirements. I Remark 8.24 The inductors in the circuit are subjected to unipolar ux transitions. This makes the losses in the inductors low, and increases the eciency of the system. I Remark 8.25 During the zero voltage intervals there is no reactive power exchange between the inductor and the PV capacitor. This increases the eciency of the system. I

8-25

8-26

Grid Connected Converters and Renewable Energy Systems

L A B

Figure 8.16: Hybrid Switching H-bridge converter. Remark 8.26 The lower switching frequency in one of the legs also increases the eciency of the converter by lowering the switching losses. I Summary 8.4 Summing up, one can see that there are a lot of nice properties with this converter. Of particular note is its eciency, which is of the order of 98%. However, in the form of Figure 8.16 the converter is not used. The problem is the step changes in the common mode voltage. These steps are very fast, and this can lead to spurts of current through the parasitic capacitance at 100 times a second. I

8.2.2

New PV Inverter Topologies

The deciencies of the transformerless H-bridge converter when used with bipolar, unipolar and hybrid modulation mode were investigated in the previous section. This section will consider some newer inverter topologies, which are based on the H-bridge, but attempt to address the eciency issues of bipolar modulation, and the safety issues that arise with unipolar and hybrid modulation. The inverter topologies are currently being used by several manufacturers of commercial inverter systems. 8.2.2.1 H5 Inverter (SMA)

This is an inverter topology patented in 2005 by SMA Solar Technology of Germany. It consists of a classic H-bridge inverter with an extra switch in the DC link [21]. The basic circuit is shown in Figure 8.18. The name of the converter clearly comes from the fact that it is a H-bridge implemented with 5 switches. Similarly to the Hybrid converter, this converter uses a combination of switching speeds. Some of the switches are switched at mains frequency, and some are switched at high PWM frequencies. As with the hybrid H-bridge converter this has some eciency benets. Let us consider how this converter works. Essentially the extra switch gives an extra degree of freedom to allow a freewheeling path when zero volts is being

8.2 Photovoltaic Inverters

8-27

L i +

L i

Figure 8.17: Hybrid Switching H-bridge converter equivalent circuit for the two positions of the low frequency switches.

8-28

Grid Connected Converters and Renewable Energy Systems

L A B L

Figure 8.18: H5 H-bridge converter. applied whilst at the same time isolating the grid supply from the PV array it is this connection of the PV array to the grid supply during the zero voltage times that allows the high frequency switching to appear across the Cg parasitic capacitance. Similarly to the hybrid H-bridge, there are two cases that one needs to consider: a. Vg > 0; i > 0 b. Vg < 0; i < 0 The reason that the Vg > 0 and i > 0 are coupled together is that the PV array is delivering real power, and this is the only condition (and the vice-versa) when this will occur. The other major dierence between this converter and the hybrid H-bridge we previously considered is the switching sequence. Because we want to isolate the bridge from the grid during the zero vector times we need to ensure that during these times the bottom two switches are o (i.e. S2 and S4 ) and the freewheeling path is supplied by the top switches. The isolation of the top switches from the gird is implemented by the new switch S5 . This means that S5 has to be switched every time that the zero vector is produced i.e. it is switching at high frequency. The remainder of the switching can be worked out by realising that we need to again implement a DC-DC buck converter for both the positive Vg and negative Vg grid voltages. The following discussion can be visualised with the assistance of Figure 8.19 for the Vg > 0 case, and 8.20 for the Vg < 0. The two gures in each of these diagrams show the same respective situation for the Vg polarity. The top gure is the situation where the inverter is delivering power in the PWM cycle, and the bottom gure is the case during the PWM cycle when the inverter is in the zero voltage state. If Vg > 0 then we can form the rst buck converter by closing S1 for the whole half cycle, and then PWMing S5 and S4 . When S5 and S4 are closed

8.2 Photovoltaic Inverters

8-29

L A B i

L A B i

These switches open

Figure 8.19: H5 H-bridge equivalent circuit for Vg > 0. power is being supplied to Vg , and when they open then the current can freewheel via S1 and S3 (and their associated diodes if required). This is the zero voltage output state of the inverter, and obviously no power is being delivered to the load. Since S2 and S4 are open then the bottom rail of the converter is not connected to the grid side. The top rail is also not connected since, as we have already said, S5 is also open during this time. Therefore whatever voltage was on Cg prior to this operation mode will remain there over this zero output voltage period (if it is small). Upon the next active switch state any sag in the Vcg voltage would be restored. A similar situation also occurs in the Vg < 0 situation (depicted in Figure 8.20). Switch S3 is closed for the whole negative half cycle, and therefore connects point B to the positive PV array rail. This allow S5 and S2 to be PWMed into the DC-DC equivalent buck converter. As in the previous case when S5 is o so is S2 and the freewheeling occurs around the S1 ; S3 loop ap-

8-30

Grid Connected Converters and Renewable Energy Systems plying zero volts to the grid. Because S5 is o, as well as S2 and S4 then the grid voltage is completely isolated from the PV array. Remark 8.27 One can see that in the H5 converter that the top switches, S1 and S3 are the switches that are switched at the grid frequency. Their purpose is to connect the positive terminal of the PV array to the positive terminal of the grid supply. The bottom switches and the extra S5 switch are switched at the high frequency to produce the PWM. I The other question that has not been answered at this stage about this circuit is what is the Vcg voltage? This can be calculated by considering the equivalent circuits for the various modes of operation. Let us consider the top diagram in Figure 8.19. Carrying out KVL around the loop shown by the dashed line we can write: VP V + L di di + Vg + L dt dt di L dt = = 0 VP V Vg 2 (8.30) (8.31)

Clearly: Vcg Vcg = L = di dt Vg VP V 2 (8.32) (8.33)

Conclusion 8.1 The conclusion that can be drawn from this analysis is that under the active power output condition the voltage appearing across the Cg capacitor is the value in (8.33). Examination of this expression indicates that the voltage is the grid voltage with an oset. I Conclusion 8.2 The second conclusion that can be drawn from this gure is that when the zero voltage is being produced, the isolation of the PV array from the grid means that the voltage of equation (8.33) is retained (except for whatever leakage that would occur). I The second situation is shown in the top diagram of Figure 8.20. Again using KVL around the loop shown by the dashed current direction line we can write: VP V + L di di Vg + L dt dt di L dt = = 0 VP V + Vg 2 (8.34) (8.35)

As previously the Cg capacitor voltage is: Vcg = Vg L = Vg Vcg = di dt (8.36) (8.37) (8.38)

VP V + Vg 2 Vg VP V 2

8.2 Photovoltaic Inverters

8-31

L A B i

L A B i

These switches open

Figure 8.20: H5 H-bridge equivalent circuit for Vg < 0.

8-32

Grid Connected Converters and Renewable Energy Systems Remark 8.28 Equation (8.38) is the same as (8.33). Note that in this case the Vg value would be negative since this was derived for this situation. The situation for the bottom diagram is similar to that of the Vg > 0 case. The PV array is again isolated from the mains supply. I Conclusion 8.3 The overall conclusion from (8.33) and (8.38) is that Vcg = Vg VP V 2 (8.39)

for all switching positions. This means that there is no high frequency component, and the voltage across the parasitic capacitance is an oset version of the grid voltage. This fact means that there is little Cg leakage current and low EMI from this inverter. I Summary 8.5 The H5 inverter has all the advantages of the hybrid inverter, and at the same time eliminates the high frequency components in the Vcg voltage. It has been shown to have a European Eciency of 97.7% and a maximum eciency of 98%. This eciency is the same as the maximum eciency of all the very ecient inverter structures. This inverter is used commercially in the SunnyBoy 4000/5000 TL PV inverter. A data sheet for this inverter can be found in Appendix F section F.1. I 8.2.2.2 HEIRC Inverter (Sunways)

This is another inverter topology that is similar to the previous one. Even though it is similar, it is worth having a brief look at this topology as another variant. This is also a topology that is patented and commercialised by Sunways (in 2006). This topology diers from the previous one in that is is formed again from a H-bridge but has a bypass leg in the AC side of the bridge. Figure 8.21 shows the basic circuit. Under active power output the operation of this circuit is much the same as the operation of the H5 converter. However under zero voltage output the switches S1 , S2 ,S3 and S4 are all turned o and the current is allowed to ow around a short-circuit path produced by S+, D+ or S, and D. Note that these switches use unidirectional switches to eectively form a bidirectional switch. Which ever switch is chosen remains switched on for the whole half cycle of the current ow. Remark 8.29 The main points to make about this conguration [21]: The voltage across of the lter components is unipolar (as it was with the H5 topology), and therefore the core losses in the inductors will be lower. It has reasonable eciency (European Eciency of 95%) relative to other topologies that prevent reactive power exchange between CP V and the lter inductors. The Vcg voltage only has grid frequency components in it, and therefore there is only a small ground current and the EMI is not large. The topology has one extra switch compared to the H5 topology.

8.2 Photovoltaic Inverters

L

8-33

Figure 8.21: The HERIC PV inverter topology (Sunways) The HERIC has two switches conducting at the same time, whereas the H5 has three switches conducting. I

8.2.2.3

Full Bridge with DC Bypass (Ingeteam)

This is yet another modied full bridge topology. It has a patent pending by Ingeteam in 2010. Figure 8.22 shows the circuit for this inverter. This is an interesting design in that the switches S1 and S4 are switched on for the positive half cycle of Vg , and S3 and S2 for the negative half cycle of Vg . The PWM is carried out using the S5 and S6 switches. The clamp diodes D+ and D are there to prevent the DC link bypass switches from being subjected to more than half the DC link voltage. Due to the similarity in the operation of these converters the operation will only be briey described. To deliver an active positive voltage switches S5 , S1 , S4 and S6 are closed this essentially again forms the buck converter circuit. To get the zero vector then S5 and S6 are opened and S2 , S3 are turned on, and the current circulates via two paths D3 and S1 as well as S4 and D2 . Again this is analogous to the freewheeling diode of the traditional buck converter. Remark 8.30 One nice feature of the inverter is that the switching of S3 , S2 during the zero vector production can be undertaken with no current owing through them. Therefore there is no switching losses. I Remark 8.31 Some remarks about this topology: As with the similar topologies the voltage across the lter is unipolar. This means that the magnetic losses will be low. The DC bypass switches are rated at half the DC link voltage. The D+, D diode clamps ensure that this is the case since if the voltage on the H-bridge side of the bypass switch falls below VP V /2 then the diode will turn on.

8-34

Grid Connected Converters and Renewable Energy Systems

Figure 8.22: The full bridge DC bypass PV inverter (Ingeteam). As with all the other modied H-bridge converters there is no reactive power exchange between the lter inductors and the CP V capacitors during the zero voltage period. The Vcg voltage only has a grid frequency component which means that the leakage current and EMI are low. The inverter has two extra switches and two extra diodes compared to the standard H-bridge. During the active vector there are four switches conducting. This will aect the overall eciency. European Eciency is 95.1% and maximum eciency is 96.5%. Note that this gure is a little down compared to the H5 topology for example. Commercialised by Ingeteam in the Ingecon kW). Sun TL series (2.5/3.3/6

Conjecture 8.1 It would seem to me that the proliferation of dierent topologies for these H-bridge based converters is more about circumventing the patents of other companies rather than a distinct advantage of any particular topology. It would seem that it is better to accept a slightly less ecient inverter which may be more expensive to make rather than pay a royalty to a competitor. I Up until this point the inverters that we have been looking at have been derivatives of the H-bridge. There are a lot of dierent versions of these, and I only covered a few of them. If one considers the PV panel integrated inverters (the inverter and panel come as an integrated set) then the inverter topologies proliferate even more. In order to ensure that these notes are not repetitive I shall not consider anymore of this genre of inverters. Instead in the next section we shall briey consider inverters for PV applications that are derived from multi-level converter topologies. These are still single phase systems.

8.2 Photovoltaic Inverters 8.2.2.4 Neutral Point Clamped (NPC) Half-Bridge Inverter

8-35

The neutral point clamped converter is a well known converter in the multilevel converter community. The three level NPC converter (commonly used in medium voltage three phase variable speed drives) can also be used in single phase systems as well. Similarly to the H-bridge systems it enables one to produce two active voltages and a zero voltage. The basic circuit for a classic single phase NPC inverter is shown in Figure 8.23. In order to understand this circuit refer to Figures 8.24 and 8.25. Figure 8.24 is for the case where Vg > 0 and i > 0. The top drawing in this gure is for the case when there is an active voltage delivering power from the PV array to the grid. As with all the previous cases the switches are turn on so that a DC-DC buck converter circuit is formed and energy is being delivered to the load (the grid voltage in this case) as well as the lter inductor (L). The current ow is, as in previous cases, shown as the dashed line. Note that there are two switches on, S1 and S2 , and the complementary switches S3 and S4 are o (as is the normal case in a totem pole leg). The voltage being produced across the load is VAB = VP V the voltage appears across one of the two series capacitors in 2 the DC link of the inverter. Remark 8.32 One can see from the gure that the current that is being delivered to the load is eectively owing from one of the capacitors. The other capacitor is has no current owing through it. I Remark 8.33 The other obvious dierence between this inverter and the previous ones is that the output voltage is half the PV array voltage. This has the implication that the PV array voltage would have to be twice as big as in the previous converters if a boost converter is not used as part of the overall converter. However, a positive feature is that the devices themselves are subject to the only VP V . I 2 Remark 8.34 Under this switching state it is important point to note is that the voltage supported across S3 and S4 is VP V . A question that arises is whether this voltage is equally supported by these two devices? If the voltage at the top of S4 goes above zero volts (relative to ground) then the diode D will become forward biased clamping this voltage. This means that the voltage across S4 has been clamped at VP V . Therefore the voltage across S3 is also eectively clamped 2 at the same voltage. I Remark 8.35 The voltage sharing described in the previous remark works very well despite the variations in components for several reasons: When the switches are o the reverse currents are essentially thermal current sources (essentially reverse leakage currents through diodes). Therefore if one of the series elements tends to have an eective impedance that is lower than the other, then it will be supporting less voltage and therefore will dissipate less power. The other device on the other hand will tend to dissipate more power, and therefore the reverse current will tend to increase. This will make it eective impedance lower, and therefore an equilibrium will be achieved. Therefore there is a tendency for nature voltage sharing.

8-36

Grid Connected Converters and Renewable Energy Systems The diode D will contribute to the leakage current of S4 in addition to the leakage current from S3 . This will tend to make the voltage across S4 rise, and the diode D will start to turn on. This will then clamp the voltage across both devices. These same ideas are the basis for voltage sharing of series devices in this type of clamped converters. I The bottom drawing in Figure 8.24 is when the zero voltage is being produced. One can see from this gure that this is achieved by simply turning S1 o. The lter inductor forces D+ to turn on, and the voltage VAB becomes 0 as a short circuit is developed across the output terminals of the converter. Therefore when Vg > 0 and i > 0 the S1 switch is PWMed to produce the desired output voltage and S2 remains on for the whole of the grid voltage half cycle. Note 8.3 It should be noted implicit in this explanation (and the previous ones for the H-bridges for that matter) is that the output current and voltage are inphase i.e. the converter is only producing real output power and no reactive power. This is the usual case, but there could be circumstances where the PV inverters may form part of a more integrated grid control system and they could produce or absorb reactive power as well as real power. This converter can operate at non-unity power factors. For example, if Vg > 0 and i < 0 then for positive output voltage the same switches are closed (S1 and S2 the current is actually owing through the parallel diodes) but when zero volts is produced then S1 opens and S3 closes. The current will then ow via S3 and D forming the short circuit across the load terminals. Similarly if Vg < 0 and i > 0 the positive voltage situation is the same, again with the parallel diodes around the switches S3 and S4 conducting. To get the zero voltage then S4 is opened and S2 is closed forming a current via S2 D+.I Figure 8.25 shows the other situation for the inverter switching. A quick perusal of the gure shows that the situation is a virtually identical to the previous case in terms of the general principle of the operation. Therefore the detailed description will not be repeated. Summary 8.6 Summing up we can say the following about this topology: The PWM frequency is applied to switches S1 and S4 and the switches S2 and S3 are switched at the grid frequency. The converter is able to handle non-unity output power factors. The voltage across the lter is unipolar giving low core losses. Able to achieve high eciency (98%) since there is no reactive power exchange during the zero voltage state. The voltage rating of the switches is VP V /2, which is half the voltage rating of the H-bridge topologies for the same VP V . Due to the fact that the peak output voltage VAB = VP V then the VP V 2 voltage will have to be twice that of the H-bridge for the same grid voltage. This means that there is no saving in switch voltage rating with NPC.

8.2 Photovoltaic Inverters

8-37

Figure 8.23: Basic NPC single phase leg. Because the centre point of the capacitors is held at zero volts then Vcg = VP V (the voltage across the bottom capacitor). Therefore there is theo2 retically no ground current or ground current induced EMI. The switching losses between the switches are uneven due to the fact that S1 and S4 are PWMed and S2 and S3 are switched at grid frequency. The ground wire from the load to the capacitor centre point has to be very low inductance to prevent transient common mode voltages from being generated. The NPC topology has been commercialised in the transformerless TripleLynx PV inverter sold by Danfoss Solar. These are rated at 10, 12.5 and 15 kW. They are reported to have a European Eciency of 97% and a maximum eciency of 98%. 8.2.2.5 Some Other Topologies and Issues

Thus far several topologies have been introduced and considered in various amounts of detail. In this section several other issues will be covered, some of which are relevant to all the topologies presented, as well as a brief discussion of three phase topologies. Up until now we have considered H-bridge converters without a boost circuit. Depending on the circumstances and application a boost converter may be required. There are two main ways of achieving the boost:

8-38

Grid Connected Converters and Renewable Energy Systems

L B A

L B A

Figure 8.24: NPC with Vg > 0 and i > 0.

8.2 Photovoltaic Inverters

8-39

L B A

L B A

Figure 8.25: NPC with Vg < 0 and i < 0.

8-40
PV array

Grid Connected Converters and Renewable Energy Systems

Boost converter HF Transformer Rectifier DC link filter Grid interface converter Switching harmonic filter

Figure 8.26: Basic structure of a single phase PV interface with a high frequency isolated boost converter. a high frequency transformer. a traditional boost converter with a low frequency transformer. Considering the rst case, a traditional high frequency converter solution appears in Figure 8.26. As can be seen if is formed by placing a conventional H-bridge on the primary side of the a high frequency transformer, followed by a rectier, lter and another H-bridge on the secondary side. Of course the traditional H-bridges we have in this diagram can be replaced for the H5, HERIC etc to get a more ecient circuit. Remark 8.36 The PV array can be grounded in this circuit since the PV array side is completely electrically isolated from the grid supply. There could be still some high frequency feed-through from the output side via the capacitance of the transformer. However if this is carefully designed this can be minimised. I An alternative to the isolated HF transformer is to use a low frequency transformer on the output of the PV grid interface inverter and the boost function is implemented using a conventional non-isolated boost converter. Figure 8.27 shows the basic layout of this type of converter. As can be seen from this gure the transformer is now on the low frequency side of the converter after the lter. Therefore this transformer is a mains frequency transformer, and would be much larger and heavier than an equivalent high frequency transformer capable of the same power throughput. However there are three fewer switches in this design as compared to the high frequency converter design. Remark 8.37 In both these boost converter systems the presence of the two converters means that the control for the system can be distributed. The MPPT for example can be handled by the boost converter, and the grid interface control issues by the output H-bridge. I Finally a note on three phase converters. These were very briey introduced via Figure 8.11. However most three phase systems are built using single phase modules i.e. they are three phase, four wire systems. This has been mainly done so that existing single phase modules can be used. The are essentially controlled as three single phase systems. An example of a commercial system that is built like this is the SMA Sunny Mini Central 8000TL. Other companies like Conergy, Refusol and Danfoss Solar are building true three phase inverters in the large power range of 10-15kW. In terms of eciency, low leakage and performance they are on par with the H-bridge systems we have

8.2 Photovoltaic Inverters

PV array Filter Non-isolated boost converter Filter H-bridge

8-41

Filter

Low frequency transformer

Figure 8.27: Basic structure of a single phase PV interface with a low frequency transformer and non-isolated boost converter. studied. The main problem with three phase systems is the relatively high DC link voltage (minimum of 600VDC for a 400 Volt grid). Taking into account variations that must be catered for, this does not leave much headroom to 1000VDC, which is the maximum voltage for safety reasons in Europe [21].

8.2.3

Grid Requirements for PV Systems

Because PV inverters are generally (but not always) interfaced to the gird, then they have to satisfy certain requirements, known as the grid requirements in order to comply with the rules of connection. The main issues related to the grid interfacing are: Anti-islanding protection An island is formed if the grid is disconnected or fails and one or more PV inverters maintain the supply to the isolated section of the grid. The issues that arise with islanding are safety issues and quality of supply. Voltage and frequency limits If the grid voltage and/or frequency move outside certain limits then the PV inverter should disconnect. Indeed the movement of grid voltage and frequency is one of the passive methods to determine when islanding is occurring. DC current injection There is a possibility of injecting signicant DC currents into the grid if the control of the inverter is not very good. Therefore the control has to be such that the DC injected current remains below a certain value. If a low frequency output transformer is used then DC injection (except transiently) will not occur. Power factor The current standard only allows small PV inverters to operate at near unity power factor. There are provisions in most standard to allow for inverters to operate at power factors other than unity, but this will also involve some supervisory control of these systems. Harmonics The inverter output ltering must be such that certain harmonic standards are satised.

8-42

Grid Connected Converters and Renewable Energy Systems We shall now consider these issues in a little more detail. Reference will be made to European Standards (these comments mainly sourced from [21]) and also from the relevant sections of the Australian Standards on grid connected converters. These are in Appendix F.3 for convenience and if the interested reader wishes to study them in more detail. As you can well imagine there is a high degree of commonality between standards from dierent countries. Obviously the standards committees would look at overseas standards when beginning to formulate their own. Inevitably there are dierences as well they reect dierent perspectives of the committees, different electrical conditions, dierent degrees of safety, and (somewhat cynically) the desire of most committees to justify their existence by doing something different. Even with these dierences there is a fair degree of collaboration between countries in order to get the base of the grid standards the same. This helps facilitate equipment manufacturers that sell systems internationally. From an international perspective the most relevant bodies in relation to standards are the IEEE in the US, IEC (International Electrotechnical Commission) in Switzerland, and the DKE (German Commission for Electrical, Electronic and Information Technologies of DIN and VDE). The later is important, as Germany is a dominant player in the PV market at the moment. Standards Australia, who set the Australian Standards, are of course aware of all the overseas standards, and as shall be seen there is a large degree of similarity between them all. In the remainder of this section we shall look in a little more detail at the standards, and compare and contrast those of the US, IEC, VDE and the Australian Standards. This presentation is by no means exhaustive and complete, but nevertheless it will serve to high the main issues. The international context of these standards is very important for Australian manufacturers in this area who intend to export they clearly have to satisfy the standards of the countries where they intend to export to. Most of the material used to write this chapter appears in a grid standards summary in [21] as well as in the AS4777.2-2005 which is titled Grid connection of energy systems via inverters Part 2: Inverter requirements and AS4777.3-2005 titled Grid connection of energy systems via inverters Part 2: Grid protection requirements. Relevant excerpts from these documents appear in Appendices F.3.1 and F.3.2. These are provided so that you can see how these standards are worded and their general structure. For your information the other part of this standard that are not directly relevant to this discussion is AS4777.1-2005 Grid connection of energy systems via inverters Part 1: Installation requirements. 8.2.3.1 Discussion of the International Standards

As mentioned in the previous section the IEEE, IEC and VDE have developed standards in relation to grid connection of converters. In this section we shall consider some aspects of these standards. IEEE Standard 1547, which is titled Standard for Interconnecting Distributed Resources with Electric Power Systems is probably the most inuential standard in the US these days. This standard is noteworthy in that it is attempting to develop a single standard that applies to all technologies up to power levels of 10MW. It covers issues of the interconnection standards themselves, as well as how to test that these standards to adhered to.

8.2 Photovoltaic Inverters Underwriters Laboratories Inc. are an important body in the US with respect to standardisation. They have developed standards derived from the earlier IEEE 929 standard, which is designated as UL 1741 Standard for Inverter, Converters, and Controllers for Use in Independent Power Systems. The latest version of this standard also acknowledges the development of the IEEE 1547 standard and says that UL 1741 should be used in conjunction with this standard. The IEC has been working towards bringing together the variety of international standards. For example they have developed IEC 61727 (Dec 2004) Photovoltaic (PV) Systems Characteristics of the Utility Interface, and the related standard IEC 62116 Ed 1 (2005) Testing Procedure for Islanding Prevention Measures for Utility Interactive Photovoltaic Inverters. These standards have reasonable conformity with IEEE 1547. Germany in one of the largest PV markets in the world at the moment. Because of this fact any standards developed in Germany take on an importance that transcends the German domestic context. Amongst the plethora of standards developed was some about devices for automatic disconnection between generators and the public low-voltage grid. This standard was essentially about the prevention of islanding (an issue that we shall return to in some detail later). In its original form this standard stated that the auto disconnection device (which incidentally could be a software device) had to be able to detect a jump of 0.5 in the grid impedance in power balanced situation. After some experience with this requirement it was concluded that this standard was too tight it resulted in too much false tripping of PV systems, especially when a number of PV inverters were connected in close proximity. In addition active detection techniques had to be used to try and satisfy it (i.e. injection of test signals in order to determine the grid impedance), and this result in a degradation of the power quality. The upshot of these problems was that a new revised standard VDE 01261-12006 was formulated, and this relaxed the impedance change detection from 0.5 to 1. It is hoped that this will result in less problems with PV units on the grid, and at the same time not compromise the safety aspects. Another aspect to these VDE standards is the passive detection limits i.e. the detection of under-voltage and over-voltage and the frequency deviation limits. These limits form a passive detection method for islanding, as well as making sure that the inverter is not operating on a dysfunctional grid. The VDE standard also describes test procedures to determine if a PV inverter will disconnect from the grid if there is too much DC current injection, or fault currents are exceeded, or there is not sucient isolation from earth. I will not go into anymore detail on these issues here the interested reader should look at the appropriate source for these standards to nd the details. One issue that has not been touched on in the discussion thus-far is harmonics. PV inverters can of course introduce high frequency harmonics into the grid, and if there are large numbers of them the cumulative eect could be signicant. The most signicant standard with respect to harmonics that can be produced by equipment is the IEC61000 Electromagnetic Compatibility Standard. One specic part of this standard (IEC61000-3-2) is related to current harmonics for equipment with currents up to 16 Amp per phase. For equipment with currents greater than this but less than 75 Amp there is another standard IEC61000-2-12.

8-43

8-44

Grid Connected Converters and Renewable Energy Systems There are also corresponding standards for voltage related conditions such as icker and uctuations (IEC61000-3-3 and IEC61000-3-11) for the 16 Amp and 16 to 75 Amp conditions respectively. They specify limits and test conditions that are used to measure the performance of the equipment. These standards are for the low voltage public network i.e. 220 to 250 V line to neutral at 50 Hz. Remark 8.38 The IEC61000 standards are related to the EMC of the equipment, and specify values of injected EMC from a piece of equipment into the grid and the means of testing the equipment for compliance. I The EN50160 are European Standards the related to the voltage quality of the public network from the customers perspective.2 For example permissible voltage ranges are given for the low voltage and medium voltage public network under normal operating conditions. These conditions must be met for 95% of the mandated test period. Voltage specications that are of interest to manufacturers of PV inverter systems are [21]: Voltage harmonic maximum THD is 8%. See Table 8.1 for the distribution of these limits amongst the various harmonics. Voltage unbalance for three phase is less than 3% (this would be using the European denition of unbalance
Vneg . Vpos

Maximum voltage amplitude variation is 10%. Maximum frequency variation is 1%. Voltage dips should be less than 1 second duration and the maximum depth of the dip is 60% of the nominal voltage. As will be seen the PV standards exceed most of the above supply requirements. In respect of the voltage dips, there are currently no requirements in Europe for ride-through. However as the penetration of PV systems increases undoubtedly this will come in. Wind turbine systems for example already have to satisfy very stringent ride-through requirements. The EN50160 standards are related to normal operation of the public distribution grid. With respect to PV inverters, there are also standards as to how they should operate under the circumstance of abnormal distribution grid conditions. These standards are in many senses a type of passive anti-islanding standard. A comparison of the main international standards in respect of PV inverter disconnection when there is a voltage variation is shown in Table 8.2. Remark 8.39 The Discon time in Table 8.2 refers to the maximum length of time allowed from the onset of the abnormal voltage condition to the inverter disconnecting itself from the distribution grid. I
2 These standards are about dening what are the normal limits for the operating conditions for the gird itself. They do not dene the performance of the equipment. However, if equipment was put onto the grid that resulted in these conditions not being met then clearly there is a problem.

8.2 Photovoltaic Inverters

8-45

Odd harmonics Not multiple of 3 Multiple of 3 Order h Relative Order h Relative voltage % voltage % 5 6 3 5 7 5 9 1.5 15 0.5 11 3.5 13 3 21 0.5 17 2 19 1.5 23 1.5 25 1.5

Even harmonics Order h 2 4 6 to 24 Relative voltage % 2 1 0.5

Table 8.1: EN50160 European standards for public distribution grid voltage harmonics limits.

IEEE 1547 Voltage range Discon (%) time (sec) V < 50 0.16 50 V < 88 2.00 110 < V < 120 1.00 120 V 0.16

IEC 61727 Voltage range Discon (%) time (sec) V < 50 0.10 50 V < 85 2.00 110 < V < 135 2.00 135 V 0.05

VDE 0126-1-1 Voltage range Discon (%) time (sec) 110 V < 85 0.2

Table 8.2: Comparison of US and European Standards on disconnection times for PV inverters under abnormal voltage variations.

8-46

Grid Connected Converters and Renewable Energy Systems IEEE 1547 Freq range Discon (Hz) time (sec) 59.3 60.5a 0.16
a For

IEC 61727 Freq range Discon (Hz) time (sec) fn 1 < f < 0.2 fn + 1 b

VDE 0126-1-1 Freq range Discon (Hz) time (sec) 47.5 50.2c 0.2

systems with power < 30kW the lower limit can be adjusted to allow participation in frequency control. b The f is the nominal frequency of the supply. n c The lower frequency limit in this standard means that adaptive frequency synchronization is required.

Table 8.3: Comparison of European and US standard for disconnection with respect to frequency deviations. Remark 8.40 One can see from the above table that the VDE standard for is very stringent. There are very tight bounds on the voltage, and the time of disconnection is reasonably fast. This means that good quality instrumentation has be to used to satisfy this standard. I Remark 8.41 Even though the inverter power circuit should disconnect due to the conditions of Table 8.2 the instrumentation for the converter should remain connected. This is the allow conditions of the supply coming back into specication to be detected, and resychronisation of the inverter to this supply to allow automatic reconnection. I Similarly to the voltage variation disconnection standards there are also standards for disconnection if the distribution grid frequency moves outside certain limits. These limits, and the time delays associated with them are to help prevent nuisance tripping in weak grids, but at the same time satisfy the passive anti-islanding that is required for safety reasons. A comparison of the main US and European standards are shown in Table 8.3 Tables 8.2 and 8.3 provide the framework for passive anti-islanding of PV systems. This therefore denes when the PV system should disconnect from the grid using available measurements n the inverter. The next question that arises is when should an inverter that has been disconnected under these circumstances be reconnected to the grid. Table 8.4 shows a comparison of standards for the conditions required for reconnection after an out-of-limits trip. One can see that both the voltage and the frequency have to be within certain limits before the reconnection can occur. Also note that under the IEC standard that there is a 3 minute minimum delay before reconnection which is designed to make sure that the inverter is going to be properly synchronized before reconnection is attempted. Another aspect of the grid requirements, also from the inverter viewpoint, is the power quality requirements. These requirements fall into two main categories: DC current injection limitations. Injected current harmonics.

8.2 Photovoltaic Inverters IEEE 1547 88 < V < 100 (%) and 59.3 < f < 60.5 (Hz) IEC 61727 85 < V < 110 (%) and fn 1 < f < fn + 1 (Hz) and Minimum delay of 3 mins. VDE 0126-1-1

8-47

Table 8.4: European and US reconnection conditions for PV inverter systems after a trip [21]. IEEE 1574 IDC < 0.5 (%) of the rated RMS current IEC 61727 IDC < 1 (%) of the rated RMS current VDE 0126-1-1 IDC < 1 A Maximum trip time of 0.2 sec

Table 8.5: European and US DC current injection limitations Power factor. We shall have a look at the international standards on these two issues. Table 8.5 shows various limits for DC injection into the grid from PV inverters. DC injection is a particular problem for transformerless PV inverters. If a PV inverter has a transformer (as is specied in much of the US) then DC injection into the grid cannot occur (since a transformer cannot pass DC in steady state). Remark 8.42 It should be noted however that one may wish to minimise the DC output to the isolation transformer in transformer based PV inverters because one can also get DC saturation of this isolation transformer. However, the problem is not as severe as in the grid case because the DC injection is limited to only the one inverter. I Remark 8.43 You will notice from Table 8.5 that the IEEE and IEC standards do not have any time specied for the trip time if DC trip limit is exceeded, whereas the VDE standard does specify a maximum time that the limit can be exceeded before the inverter should disconnect from the grid. I We have previously discussed harmonics from the point of view of the grid i.e. the maximum harmonic levels that are allowed on the grid. The requirements for the injection of harmonics from the PV inverters is related to but at the same time separate from this. Clearly the standard for the inverters has to be set up on the assumption that there will be multiple inverters connected onto the grid, and therefore there is the potential that the harmonics may be cumulative. Remark 8.44 It should be emphasised that the harmonics for the grid in Table 8.1 are the voltage harmonics. The standards with respect to the inverters is with reference to the current harmonics. Clearly the interaction of the current harmonics with the grid system impedance will lead to voltage harmonics. I Table 8.6 show current harmonic limits from the IEEE 1547 and IEC 61727 standards. These harmonics are usually measured with an ideal grid voltage

8-48

Grid Connected Converters and Renewable Energy Systems IEEE 1547 and IEC 61727a Individual odd harmonic order (h)b (%)c
a The b The

h < 11

11 h < 17

17 h < 23

23 h < 35

35 h

4.0

2.0

1.5

0.6

0.3

THD has to be less than 5.0% even harmonics are limited to 25% of the odd harmonic limits. c This is the percentage of the fundamental amplitude.

Table 8.6: IEC and IEEE standards for injected current harmonics Odd harmonics Order h I (A) 3 2.3 5 1.14 7 0.77 9 0.4 11 0.33 13 0.21 13 h 39 0.15 15 h Even harmonics Order h I (A) 2 1.08 4 0.43 6 0.3 8 8 h 40 0.23 h

Table 8.7: IEC61000-3-2 current harmonic limits.

(i.e. from an ideal voltage source with no voltage harmonics). The IEC 61727 standard has not yet been approved in Europe. The standard currently being used is IEC 61000-3-2 (for equipment up to 16 A). These limits are shown in Table 8.7 The nal aspect of power quality that shall be commented on is power factor. For the most part PV inverters are designed to operate with a power factor of unity or very close to it. The reason for this as that this power factor will minimise the rating of the power electronics for the real power that is going to be delivered to the grid. The IEC 61727 standard is the only one that mentions that a PV inverter should have an average lagging power factor greater than 0.9 when operating at 50% or greater output power. The IEEE 1574 and VDE 0126-1-1 standards do not include any specications about PV inverter power factor. Remark 8.45 As the number of PV inverters on the grid increases, and also as the size of some of the installations gets bigger, then the possibility of PV inverters exchanging reactive power with the grid will become more of a prospect. Regulations will have to be developed. Furthermore, communications standards may also have to be developed that will allow some decentralised/centralised control of these reactive power sources. The presence of these devices will add a lot more actuators to the grid for control of voltage, but it will also make the grid control far more complicated. I

8.2 Photovoltaic Inverters 8.2.3.2 Anti-islanding Standards

8-49

The concept of islanding of PV inverters has been mentioned several times. Just as a reminder, islanding refers to the idea that a PV inverter will continue to operate and feed local loads even though the area of the grid where the inverter is located has been isolated from the main part of the grid, and the conventional grid generation sources. Islanding is an important issue for two reasons: If islanding occurs when the inverter section of the grid is isolated due to a fault or intentional isolation for maintenance, then there is the potential that maintenance personnel or a member of the public can be electrocuted. If the PV inverter continues to supply energy to the isolated section of the grid then there is the possibility of damage to equipment if a re-closure occurs. As far as the PV inverter is concerned if there is the potential to form an island then the inverter has to detect this and isolate itself from the grid. It is required that this task is performed without any supervisory control i.e. the inverter has to be able to autonomously determine that islanding has occurred. In order to do this an anti-islanding algorithm has to be implemented in the inverter. The development of such algorithms is a very active research area in PV inverters, as all algorithms developed thus-far have some limitations in terms of the time to detect islanding, and the conditions under which islanding can be detected. Let us look at some of the standards to test whether a PV inverter satises the anti-islanding regulations. IEEE 1547/UL 1741 requires the distributed resource (in our case the PV inverter) to detect the islanding and cease to energise the area within 2 seconds of the island forming. In order to test whether a PV inverter is compliant with this, a standard test circuit has been established. This test circuit is shown in Figure 8.28. As can be seen a test RLC load is situated between the PV inverter and the grid. This is meant to simulate the local load when the grid has been disconnected. The load is set up so that the Q of the circuit is 1 and the natural frequency of the circuit is the nominal grid frequency fn . If Pn is the nominal output power (i.e. it is very close to the rated output power) of the PV inverter, then the values of the RLC load are established as follows: R = V2 Pn V2 2fn Pn Q Pn Q 2fn V 2 (8.40) (8.41) (8.42)

L = C =

Remark 8.46 It is clear from (8.40) that the resistor has been chosen so that the load pulls the nominal output power of the inverter. I With the circuit conguration of Figure 8.28 established, then the power level to the grid is established at 2% of the nominal output power by ne tuning the parameters of the simulated local load. The switch S3 is then opened and

8-50

Grid Connected Converters and Renewable Energy Systems

RLC load Simulated Electrical Power System Equipment under test

Figure 8.28: Test set up for testing the compliance of a distributed resource with the IEEE 1547 standard in anti-islanding.

the inverter should disconnect in less than 2 seconds to comply. For threephase four wire PV systems then each phase is tested with the circuit connected between the phase and neutral. For a three-phase three wire system the local RLC load is connected between the phases i.e. it is a balanced three phase local load. The IEC 62116 standard and test for anti-islanding has many similarities to IEEE 1547. The test circuit, for example, is the same, and similar power balance conditions are established. One dierence is that the tests are carried out at three dierent power levels 100 105%, 50 66% and 25 33%. The voltage also is closely specied. The test is applied for the condition of no change in the real and reactive power, as well as a set of tests where these are stepped in increments of 5% in a range of 10% around the nominal value for real and reactive power. Similar tests are applied at the other two power conditions where the increment in the powers is 1% around a range of 5% of the particular power value. As with the IEEE 1547 standard, the maximum trip time after islanding occurs is 2 seconds. It should be noted that the IEC standard is still in development and is subject to review [21]. The nal international anti-islanding standard is the VDE 0126-1-1 German standard. One test in this standard uses a dierent test circuit to determine when the PV system under test can detect a change in the grid impedance and disconnect itself. This test circuit is shown in Figure 8.29. As can be seen the circuit employs a local load simulated by a parallel RLC circuit, however is this case the Q = 2. The local active and reactive power is balanced using the variable RLC circuit, and then the switch S is opened in order to increase the grid impedance by 1.0. The inverter should detect this change in the grid impedance and disconnect within 5 seconds. The test is repeated with dierent values of the simulated grid impedance (R2 , L2 ) in the magnitude range of 1 with a maximum inductive reactance of 0.5. The second part of the VDE anti-islanding standard uses the same test circuit as IEEE 1547 i.e. the circuit of Figure 8.28. The dierence is that the Q = 2 as mentioned above and the rest of the parameters are set using (8.40), (8.41) and (8.42). With balanced power the PV inverter should disconnect when S3 is opened within 5 seconds. This test is carried out for power levels of 25%,

8.2 Photovoltaic Inverters

8-51

DC-AC inverter

Semiconductor switch

Grid

Figure 8.29: VDE 0126-1-1 anti-islanding standard test circuit. 50% and 100% of the nominal inverter output power. 8.2.3.3 Australian Standards

The discussion of the PV grid connection standards thus-far have been with respect to the international standards in the US and Europe. As can be seen from this discussion, there is a commonality between these standards, but also some signicant deviations in some aspects. The Australian standards with respect to this are no exception. The relevant standards are included in Appendix F.3. The Australian Standard appears as three related documents Part 1 is related to the installation requirements of PV systems, Part 2 is titled Inverter Requirements and Part 3 Grid protection requirements. Only the last two are included in the Appendix. The inverter requirements relate to limits on certain parameters that the inverter can impose on the grid. For example, there are limits on the odd and even current harmonics that the inverter can inject, the nominal voltage that it operates at, the frequency, the power factor range that the inverter should operate at, limits on the transient voltages when the inverter is disconnected from the grid, and so on. These will not be reproduced here as the interested reader can look at the standards themselves that appear in the Appendix. A few comments on some of the standards. With respect to the current harmonics, one can see from comparing Table 8.6 with the equivalent one in Appendix F.3.1 that the Australian Standard is based on the IEEE/IEC standard in this area. The Australian Standard on DC current injection is very similar to those of the IEEE, IEC and VDE. As can be seen from Appendix F.3.1 the DC current is limited to 0.5% of the rated output current, or 5mA, which ever is the greater. These limits are to be tested under all the operating power levels. There is no requirement for tripping if this is exceeded in operation, as is the case with the VDE 0126-1-1 German standard. One other standard that was not mentioned in the discussion of international standards was the impulse protection standard. This is an important standard test that an inverter must pass to ensure that it can withstand a voltage impulse on the grid without being destroyed. Such impulses can occur due to circuit breaker intervention during faults, but also as a result of lightning strikes on the grid lines. Clearly if an inverter cannot withstand such events then it will have a very poor reliability. In the case of the Australian standard it resorts to a compliance test based on the IEC 60255-5 impulse testing procedure. Under the Australian Standard the PV inverter must be able to stand an impulse with 0.5 Joules of energy at a voltage of 5kV and and what is known as a 1.2/50

8-52

Grid Connected Converters and Renewable Energy Systems Voltage Vmin Vmax 1: 200 230V 1: 230 270V 3: 350 400V 3: 400 470V Frequency fmin fmax 45 50Hz 50 55Hz

Table 8.8: Australian Standard voltage and frequency limits.

waveform. This type of waveform is shown in Figure 8.30 with the various time denitions on it. The name of the waveform arises from the fact that the nominal rise time tr is 1.2sec, and the tail time tt is 50sec. Remark 8.47 The impulse voltage waveform specication should not be confused with transient voltage specication. The later is all about transients that are produced by the disconnection of the inverter itself, whereas the later is externally imposed transient voltage waveforms. I The grid protection section of the standards has to do how the inverter responds to externally generated conditions such as over-voltage, under-voltage, frequency variations and islanding. So the specication says what the anti-islanding behaviour will be and the basic algorithms that should be used to achieve this, as well as physically how disconnection occurs (i.e. does an electromechanical switch need to be used). In the event of anti-islanding disconnection occurring the standard then species the reconnection procedure. As an example, islanding detection can be passive, which means that the inverters sensors are looking for voltages or frequencies that go outside the grid specications. The other type of islanding that has to be present is active islanding detection. These techniques involve injection of some type of a test signal and then measuring the results and deducing whether the grid is still connected to the inverter. There are a number of dierent techniques for doing this, and it is still a very active area of research. For example, one technique is to look for grid impedance changes by the inverter injecting a current pulse into the grid and local load. The reconnection procedure under the Australian Standard is not dissimilar to the international standards. To under standard the reconnection conditions one needs to know the limitations on the voltage and frequency for the Australian system. These are summarised in Table 8.8. Given these denitions we can now summarise the reconnection procedure as follows: a. the voltage on the grid has to be maintained within the range Vmin Vmax for at least 1 minute; and b. the frequency of the grid has to be maintained with the range fmin fmax for at least 1 minute; and c. the inverter is phase synchronized with the grid at the time of reconnection. For more information about the Australian Standards on PV inverters the interested reader should read the detailed Standards in Appendix F.3.

8.2 Photovoltaic Inverters

Voltage

8-53

Time

Figure 8.30: Lightning impulse test waveform.

8.2.4

Grid Synchronization and Related Control for PV Systems

One of the key aspects of making a PV inverter system (or any other renewable source) operate with the grid is being able to synchronize the output of the inverter with the grid system. This synchronization needs to be very accurate, as small angle dierences can result in large transfers of power from the inverter to the gird (or vice-versa). In addition to accurate phase knowledge, the grid voltage and inverter currents also have to be accurately known. These quantities are usually far from idea in nature, and can have considerable harmonic pollution and noise in them as raw measurements. Therefore any ltering or estimation technique has to be capable of rejecting the noise and harmonic pollution, and at the same time achieve reasonable bandwidth so that the PV inverter can see grid condition changes as quickly as possible. Grid synchronization is not only required for normal operation of the inverter, but it is also used as part of passive anti-islanding algorithms. Being synchronized to the grid allows accurate determination of the frequency of the supply, for example, which is one of the key values used for passive island detection. Furthermore, many grid synchronization techniques also allow accurate voltage magnitude to be determined, which again is required for passive islanding detection. Most of the techniques for grid synchronization are based on the use of a Phase Locked Loop (PLL), or a closely associated algorithm. The PLL was

8-54

Grid Connected Converters and Renewable Energy Systems

Reference

Phase detector

Loop filter

Voltage controlled oscillator Signal phase-locked to the reference

Figure 8.31: Classic PLL block diagram. originally a concept from communications one of the main ways of demodulating FM for example is based on the use of hardware PLLs. We shall briey review the concept of the PLL as applied in communication systems, and then consider some specic implementations used in PV inverters and other grid connected distributed generation systems. In addition to PLL methods for detecting synchronization, techniques using adaptive ltering will also be very briey reviewed. 8.2.4.1 Brief review of PLLs

As mentioned in the previous section PLLs were originally introduced as a component in communications systems, and had particular application in the demodulation of Frequency Modulated (FM) signals. The earliest us of the concept was with the birth of coherent communication in 1932. One of the earliest uses of PLLs was in the horizontal and vertical sweeps used in television where a continuous clocking signal had to be synchronized with a periodic sync pulse. PLLs were also crucial to the development of colour television in the 1950s. In approximately 1965 the rst analogue PLL integrated circuit was developed. This made the implementation of PLLs much simpler, and there was an explosion in their use. The rst digital PLL appeared in 1970. Today PLLs can and are implemented entirely in software using sampled data. Every mobile phone, television, radio, pager, computer as well as many other things include PLLs as part of their circuitry or software. Subsequently they were used in other applications in communications. The PLL is essentially a control system, and therefore has been morphed into a variety of dierent forms to suit dierent applications. The use of these devices in PV inverters, and inverters in general, is but one of these additional uses. Figure 8.31 shows the general structure of a classic analogue communications PLL. As can be seen from this diagram there are three main components to a PLL the phase detector, a loop lter (usually a rst order low pass lter), and a voltage controlled oscillator. These components are arranged in a feedback control loop. Strictly speaking this feedback loop is a non-linear feedback system, however, when the loop is locked it can be analyzed using linear control theory since the behaviour is then small signal and the operation is essentially linear. The phase detector in Figure 8.31 is usually implemented in hardware with a Gilbert Cell, which is essentially an analogue hardware multiplier. The low pass

8.2 Photovoltaic Inverters lter is usually (but does not have to be) a 1st order low pass lter. The voltage controlled oscillator (VCO) accepts an input signal and produces a sine wave at a frequency that is proportional to the input voltage. We shall now consider the operation of the PLL when it is essentially in lock under the condition that the PLL has been implemented with analogue components. We shall assume that the input signal is a sine waveform and the VCO produces a cosinusoidal waveform under steady state locked conditions. Assume that the input waveform is: uin (t) = U sin(i t + i ) and the waveform from the VCO is: y(t) = Y cos(o t + o ) (8.44) (8.43)

8-55

Therefore the output of the phase detector is (since it is implemented as an analogue multiplier): x(t) = = x(t) uin (t)y(t) (8.45) (8.46)

(U sin(i t + i ))(Y cos(o t + o )) UY = [sin((i + o )t + i + o )) + 2 sin((i o )t + (i o ))]

(8.47)

Remark 8.48 As can be seen from (8.47) there are two terms in this expression. One has a frequency of i + o and the other has a frequency of i o . Clearly the second one will have a lower frequency than the rst. I The waveform x(t) is subsequently ltered by a low pass lter that is designed to lter out the higher of the two frequencies present in the waveform. This would Y leave the term U2 sin((i o )t + (i o )). The (i o )t can be considered to be a low frequency changing phase denoted by (t). There if there is a nonzero (i o ) term then as t becomes larger then (t) will become larger. This means that it is eectively integrating the frequency to get the phase. Of course if one continues to integrate frequency that the integrated value will continue to increase. Forgetting for a moment the i o term, then this will mean that the VCO input would increase (albeit in a nonlinear way because of the sine function), and hence the output frequency of the VCO will change in such a way that the output frequency o will move towards i so the the (t) term will go to zero and therefore the integration will stop. Using this approximation we can write: UY UY UY sin((i o )t + (i o )) sin(i (t) o (t)) = sin(e (t)) (8.48) 2 2 2 where the (t) term representing the (i o )t term has been folded into the e (t) term. Remark 8.49 The implication of the previous paragraph is that the VCO is eectively acting as an integrator in the feedback loop. Unless the phase of the output of the VCO matches at all points in time the phase of the input signal then there will be a residual phase error that is integrated by the VCO to drive the phase error to zero. I

8-56

Grid Connected Converters and Renewable Energy Systems

Phase detector Phase detector gain + VCO VCO gain LPF Amplifier

Figure 8.32: Block diagram of a PLL control system when in lock. Remark 8.50 The i o term in (8.47) does not necessarily go to zero as there is no time term in this expression. Therefore this component of the phase error is not integrated and is only decreased by the loop proportional gain. Therefore when i o = 0 then there can still be a static phase error. This means that the frequency of the VCO will match the input frequency, and the two waveforms are phase locked, albeit with a static phase error. I Remark 8.51 One will also note from (8.44) that the output of the VCO is a cosine waveform, whereas the input waveform is a sine waveform. Therefore there is a constant phase dierence due to this alone of radians. I 2 Remark 8.52 Since the output frequency of the VCO is locked to the input frequency by the feedback process of the PLL then if the input frequency is modulated by audio for example, then in order for the PLL to remain locked the frequency of the VCO must track the modulated frequency changes. Therefore the input to the VCO will not be zero or a constant value but will track the frequency changes of the input. Therefore in an FM system this input if the demodulated signal. I When locked and the frequency related phase error is zero or very close to it the model of an electronic PLL becomes that shown in Figure 8.32. As can be seen in this gure there are gains associated with the phase detector and the VCO. Strictly speaking the loop is still non-linear since the term from the phase detector is still that in (8.48). However if the e (t) term is small then we know that sin if is small, therefore we can represent the output of the phase detector as e . Remark 8.53 It should be recognised that the above description of how the PLL works is only valid if i o . If this is the case then the assumption that t e = 0 (i o )dt + (i o ) is valid. This integration is where the integrator comes from in the block diagram of Figure 8.32. Since the e is driving the VCO until the frequency error becomes zero, and the e value is eectively t (and t is increasing as time does), then the VCO implicitly has an integrator in it (as mentioned previously). Incidentally this is not obvious. I

8.2 Photovoltaic Inverters Remark 8.54 One aspect of VCO operation that we have not touched on is the fact the the VCO is set initially to output a non-zero frequency. This frequency is called the centre frequency, and it is usually set to be close to the expected input frequency. Classic PLLs have a capture range around this frequency, where the capture range is the maximum input frequency deviation from the centre frequency where the PLL will pull into lock. The process of capture is highly non-linear. We shall not discuss this here any further, but the interested read is encouraged to look further in the wealth of literature available on PLLs. I The following linear analysis of the PLL is essentially taken from [27]. We shall dene the centre frequency of the VCO to be o . Therefore the output frequency of the VCO would be: osc = o + Ko Vo (8.49) Clearly the block diagram in Figure 8.32 is a classic feedback control system, and the transfer function is of the form: G(s) Y (s) = U (s) 1 + G(s)H(s) where the G(s) = KD AF (s) and H(s) = can be written as: Vo (s) i (s) Vo (s) i (s) = =
Ko s .

8-57

(8.50)

Therefore the transfer function

Ko AF (s) 1 + KD AF (s) Ko s Ko AF (s)s s + KD AF (s)Ko

(8.51) (8.52)

In communications applications one is usually interested in the response of the PLL to frequency inputs i.e. how fast can the loop track loop variations. The above transfer function can be modied by realising that: i = di dt si (s) 1 Vo (s) Ko AF (s) = s i (s) s + KD AF (s)Ko (8.53) (8.54) (8.55)

i (s) = Vo (s) = i (s)

Remark 8.55 If F (s) = 1 the (8.55) is clearly a rst order low pass lter. Loops with F (s) = 1 are therefore called rst order PLLs. If should be noted that these loops cannot be used in practice as the double frequency component will not be ltered out and will disrupt the locking of the loop. I If (8.55) is made a 1st order loop, then the transfer function for the loop becomes: Vo (s) Kv 1 = (8.56) i (s) s + Kv Ko where Kv = Ko KD A Remark 8.56 Equation (8.56) has a single -3db point of Kv rad/sec (in other 1 1 words a time constant of secs), and a DC gain of Ko . Therefore the output voltage will response as a 1st order function with respect to a step change in the input frequency. I

8-58

Grid Connected Converters and Renewable Energy Systems

Closed loop pole

Open loop pole

(log scale) Root Locus Closed-loop response

Figure 8.33: Root locus and Bode plot for a 1st order classic PLL. Figure 8.33 shows the Root Locus and Bode plot for the 1st order PLL. As can be seen the bandwidth of the loop is set by the open loop gain Kv and the DC gain by the inverse of the VCO gain. Due to the presence of the implicit integrator the PLL is a natural low pass lter. As mentioned previously the 1st order loop is never used because of the propagation of the high frequency terms around the loop. Most practical PLLs are 2nd order loops that employ a 1st order lter in the feedback path i.e. F (s) is a 1st order lter using implemented with a resistor and capacitor on the case of integrated circuit PLLs. Therefore we can write the lter as: F (s) = 1 s 1 + 1 (8.57)

which allows the overall transfer function of the PLL to be now written as follow when we substitute into (8.55): 1 Vo (s) = i (s) Ko 1 + (8.58)

1+

s Kv

s2 1 Kv

The Root Locus and Bode plot for this transfer function appears in Figure 8.34. Clearly the roots of the transfer function are: s= 1 2 1 1 4Kv 1 (8.59)

Equation (8.58) can also be written in the classic 2nd order form as follows. This allows the easy identication of resonant frequency, resonant natural frequency and damping coecient parameters. A brief review of 2nd order equations in Appendix A is recommended for the reader who has forgotten the details of this. Equation (8.58) can now be written as: 1 Vo (s) = i (s) Ko 1
s2 2 n

2 n s

+1

(8.60)

8.2 Photovoltaic Inverters

8-59

(log scale)

Root Locus

Bode Plot

Figure 8.34: Root locus and Bode plot for the 2nd order PLL. where: n = = Kv 1 1 1 2 Kv (8.61) (8.62)

Figure 8.34 shows the root locus and Bode plot for the 2nd order PLL. As can be seen as Kv increases the poles of the system become resonant in nature. This can be seen in the Bode plot, with the resonant peak in the frequency response at around Kv rad/sec. The loop bandwidth is primarily determined by Kv . To tune the loop Kv is chosen for the bandwidth required, and then 1 is chosen as low as possible without causing unacceptable resonant behaviour in the loop. One good compromise is to chose the pole positions to be at the Butterworth lter positions which is a maximally at response. This means that the poles at at an angle of 45 with respect to the real axis in the Root Locus. Mathematically this means that: 1 = (8.63) 2 and we can therefore write: 1 1 1 = (8.64) 2 Kv 2 which means that: 1 = 2Kv (8.65) Remark 8.57 This last expression means that the lter pole and the overall loop gain (and therefore loop bandwidth) are not independent. Furthermore (although we have not shown it) the lock range is also dependent on Kv . Therefore one cannot can have a wide lock range, for example, and at the same time have good noise rejection. I This situation can be improved by the introduction of a zero into lter F (s). The if the zero is positioned correctly with respect to the pole of the lter, then

8-60

Grid Connected Converters and Renewable Energy Systems

Loop gain with loop filter and zero (log scale)

Crossover frequency

Phase

Improved phase margin

Figure 8.35: Open loop Bode plots for a 2nd order PLL with zero added. sucient phase margin can be achieved in the closed loop Bode plot to allow the lter bandwidth to be reduced (i.e. a low cut-o frequency for the feedback) independently of the lock range. The eect of adding a zero to the lter can be seen in the open loop frequency response of the PLL in Figure 8.35. As can be seen, at the unity gain point the phase of open loop phase is approximately < 180 as compared to 180 in the case of the simple 1st order lter. This means that the phase margin has been improved considerably, and the resonant peaking that could occur in the 2nd order PLL case can be more easily handled. Figure 8.36 shows the closed loop magnitude frequency response of the PLL with the zero added into the lter. Notice that there is another degree of freedom with the loop since the frequency response of the loop is determined by the interaction of three parameters Kv , 1 and 2 . Therefore the lock range, which is directly related to the loop gain, can be determined independently of the closed loop bandwidth. 8.2.4.2 Brief Review of Synchronisation Techniques for Power Systems

The previous section presented an overview of the operation of the traditional PLL and various issues associated with the analysis and design of the loop for particular performance. In this section we shall build on this by giving an overview of how techniques related to the PLL are used for grid synchronisation in general.

8.2 Photovoltaic Inverters

8-61

40db/decade

Figure 8.36: Closed loop magnitude response of a 2nd order PLL with zero added. Remark 8.58 Grid synchronisation is required not only in photovoltaic systems that are interfacing to the grid, but to any system that needs to synchronise. These techniques there have widespread use in power system control in general. I The use of the PLL in power system applications leads to some issues that do not arise in communications applications. Consider (8.47) for the traditional PLL, which I have rewritten here for convenience: UY [sin((i + o )t + i + o )) + sin((i o )t + (i o ))] 2

x(t) =

(8.66)

In communications applications the i frequency is usually very large, and o is small by comparison. Therefore the i + o frequency (the high frequency term) is large compared to i o (the low frequency term). Therefore it is easy to set the bandwidth of the loop lter to get rid of the i + o term almost totally without aecting the desired i o term. This in turn means that the bandwidth of the loop i.e. its ability to track transient changes in the input phase, can be increased without causing any issues with the loop performance. In power systems applications the situation is slightly dierent. The phase/frequency we are attempting to lock onto is the grid frequency in Australia 50Hz or 314 rad/sec. Therefore the terms that we have coming out of the phase detector section of the loop is, assuming that the loop is in lock for the moment, 100Hz (i.e. i + o ) and DC (since in lock and steady state i = o ). However during the lock phase the i 0 term will not be zero, and is required to provide the movement towards lock. In order not to attenuate this signal too much the bandwidth of the lter cannot be set too low. Consequently some of the undesired 100Hz signal will creep through to the VCO and propagate around the loop. Remark 8.59 The propagation of the 100Hz signal around the loop in power systems applications leads to the loop being disrupted. Consequently the analysis

8-62

Grid Connected Converters and Renewable Energy Systems

Quadrature phase detector cosine PI controller Quadrature signal generator + + + + VCO

sine

Figure 8.37: Basic in-quadrature PLL. of loop performance that appears in most books on PLLs is not applicable to power systems, since in the applications that these books consider the double frequency component is a much higher frequency than the loop bandwidth. In the power systems situation the eect of the 100Hz ripple getting through the lter is that the PLL takes a lot longer to lock compared to the time predicted by the theory. I In order to get better performance from PLLs when used in power systems applications, almost always some sort of in-quadrature based PLL is used. This approach allows the analysis that is applied to PLLs in communications to be applied to power systems PLLs. Remark 8.60 It is ironic that in the case of PLLs the use of three phase PLLs is simpler than the single phase counterparts. This is mainly due to the fact that an in-quadrature signal has to be generated somehow from the one input signal. I The essential idea behind in-quadrature PLLs is that from a single input waveform an orthogonal waveform is produced (i.e. 90 out of phase with the input). Clearly, if the input waveform in not a pure sinusoidal waveform then this process has to be applied to the various harmonic components as well. Remark 8.61 The production of the in-quadrature component produces a two phase system, and consequently its properties are the same as a three phase system, since any three phase system can be converted into an equivalent two phase system. I Now for a little more detail of what is behind in-quadrature processing for PLLs. The input signal, which we shall assume for the moment that the input signal is xin (t) = Xin sin(t + ). This signal is input to the quadrature generator that produces an output signal xq (t) = Xin cos(t + ). These two signals are in turn multiplied by the feedback signals, which due to the operation of the PLL are 90 out of phase with the two input signals. Finally the two resultant signals from this multiplication are added together and eectively form the output of the phase detector. Figure 8.37 shows the basic structure of this type of PLL. In order to understand the advantage of this approach to the PLL a little mathematics is required. If we consider what is happening at the phase detector

8.2 Photovoltaic Inverters multiplier we can write the following expressions: pd = X[sin(t + ) cos( t + ) cos(t + ) sin( t + )] (8.67) = X[sin(t + ( t + )] = X[sin(( )t + ( ))] (8.68) (8.69)

8-63

Clearly if the loop is close to lock then is small and therefore the terms and the terms can be rolled into one to give the following expression: pd pd = X sin(t + ( t + )) = X sin( ) (8.70) (8.71)

where = t + and = t + . Remark 8.62 One can see that the main advantage of the in-quadrature approach is that there is no longer an + term appearing out of the phase detector. Therefore the signal emanating from the phase detector does not required the same degree of ltering. In the case of a power system synchronisation PLL where this double frequency component was disrupting the loop performance from the ideal behaviour, the use of the quadrature PLL means that the transient performance of the loop will now conform to the theory. I One can see from Figure 8.37 that the output of the phase detector is now fed into an PI controller. The use of the PI controller here will ensure that the phase detector error term pd will be forced to zero when in lock, which in turn means that the = 0 in (8.71). Therefore the PLL has locked onto the phase of the signal with zero phase error, and the PLL is also giving the frequency of the input signal, and the two quadrature components. Remark 8.63 The main issue with the in-quadrature approach when there is a single phase input signal is the production of the quadrature component of the signal. This is especially a problem when there are harmonics present in the input waveform. We will briey consider in the following paragraphs some techniques to do this. I We can test the above algorithm by setting up a simple simulation. In this case the simulation has been carried out using the public domain dynamic system simulation and matrix computation system called Scilab/Xcos (available for Windows, Linux and Mac OSX from http://www.scilab.org). You can download this system and load up the le for this simulation if you want to experiment. It will be made available on the Blackboard system. Figure 8.38 shows the Xcos model for the in-quadrature PLL used for the simulation. The performance of this PLL is shown in Figures 8.39, 8.40 and 8.41. In this simulation the input frequency and the centre frequency are equal to 2 50 radians/sec at t = 0. At t = 1 sec the frequency becomes 251 radians/sec. Figure 8.39 shows the input waveform and the fed back sine waveform (both normalised to unity amplitude). The part of the response shown is around the area where the input frequency undergoes the step change. One can see that there is virtually no dierence between the two waveforms they are sitting on top of each other. This can be seen from Figure 8.40 which is the error between the two normalised waveforms (i.e. both the input waveform and the output waveform have an amplitude of

8-64

Grid Connected Converters and Renewable Energy Systems

Figure 8.38: Xcos simulation model of the basic in-quadrature PLL. 1). Therefore the maximum error due to phase error is 5% in instantaneous amplitude. One can also see that the within about 200 msec this has converged back close to zero. The nal gure, Figure 8.41 shows the output of the PI controller used in the PLL. The integrator in this controller essentially stores the frequency dierence between the input and the output frequency. As can be seen from the Figure then dierence becomes 2 at t = 1.0 secs. This dierence is then added to the centre frequency to give the estimated input frequency. Once can see that the transient performance of this is quite good, with the correct input frequency being identied in approximately 20 to 30 msec. Remark 8.64 The transient response of the PLL can be improved by raising the feedback gain, but this also lets more noise into the loop. It is the inevitable trade-o between bandwidth and noise rejection. I The quadrature signal generator (Figure 8.38) is developed as follows. The step change generator in the diagram is the desired frequency (it is a step change generator to allow transient changes in frequency to be input for testing purposes). The frequency is passed into an integrator:
t

=
0

dt

(8.72)

This term is in turn passed to a A sin function and the output is A sin t as required. In order to generate the quadrature waveform this wave form is passed through an integrator. The output is:
t 0

A A A A sin t dt = (cos t 1) = cos t +

(8.73)

Therefore in order to get A cos t we need to multiply the above expression by and subtract o A. Remark 8.65 In practice one cannot use this technique to generate the quadrature waveform why is this the case? Answer: one would have to know the amplitude and radian frequency of the waveform. Since we do not control the input waveform we have no idea what these quantities are. I

8.2 Photovoltaic Inverters

8-65

Figure 8.39: Xcos simulation result input waveform and feedback sine waveform.

Figure 8.40: Xcos simulation result the error between the input waveform and the sine feedback waveform.

8-66

Grid Connected Converters and Renewable Energy Systems

Figure 8.41: Xcos simulation result the output of the PI controller which indicates the dierence between the input frequency and the loop centre frequency. The quadrature signal generator is simple to do in the case of the simulation since one can articially create the waveforms. However, in the case of true input waveforms, which may contain harmonics, this task is not quite as simple. For example if the waveform was of the form: x(t) = A1 sin 1 t + A2 sin 2 t (8.74)

then it is not known what the amplitudes are (i.e. we do not know A1 and A2 ) and we have an estimate of, say, 1 only. The particular harmonic frequency may not be known. Therefore if the integration approach is taken to generate the quadrature component we have:
t

x(t) dt =
0

A1 A2 A1 A2 cos 1 t cos 2 t + + 1 2 1 2

(8.75)

Remark 8.66 One can see from this expression that one would have to be able to pull the harmonic components apart to apply the correct to the amplitudes and to subtract o the osets (if they are known). I Remark 8.67 One can also see from (8.75) that the correct phase relationship is maintained between the harmonics for example, the A2 sin 2 t term and the 2 A2 cos 2 t have the correct in-quadrature relationship. Therefore the integra tion does preserve this if one is attempting to get the PLL to synchronise to the 2 frequency. I One can make a clear connection between the single phase in-quadrature signal processing an dq or space vector processing that we are familiar with in variable speed drives and other three-phase power systems applications. If one considers

8.2 Photovoltaic Inverters

Phase detector (PD) PI controller Quadrature signal generator + + Frequency to phase angle generator (FPG)

8-67

Figure 8.42: In-quadrature PLL implemented with a Park transformation. (8.67) one can see that the quadrature outputs of the quadrature generator can be written as: v = v v =X sin(t + ) cos(t + ) (8.76)

Using some denitions from above we can write generate the pd term out of the phase detector as: vd = v cos + v sin (8.77) We know from the two phase stationary frame to two phase rotating frame transformations present in (B.79) in Section B.3.2 on page B-14 (repeated here for convenience in slightly dierent notation): vd vq = cos sin sin cos v v (8.78)

that the above quadrature signal generation is basically the same as a two stationary frame to rotating frame transformation i.e. a Park transformation. In Figure 8.37 we are only utilising the vd component in the PLL. This realisation allows use to draw the PLL of Figure 8.37 in a slightly dierent form as shown in Figure 8.42. This PLL can also be used for three phase systems. The block diagram for this situation is shown in Figure 8.43. As can be seen the three phase values are fed into a Clark Transformation which essentially outputs the two phase stationary frame values which are equivalent to the quadrature values. Notice in this gure that we have drawn the PLL as a control system, explicitly showing the feedback processes that form the loop. Remark 8.68 If the control loop in Figure 8.42 is doing its job correctly then the xd signal will be driven to zero (by the action of the PI controller). If one considers the system to be a two phase system with x and x inputs, then this means that the angle will be 90 out of phase with the angle of the x space vector representation of the in-quadrature stationary frame inputs. I Remark 8.69 If one looks carefully at Figure 8.42 one can see that it is exactly the same as the model in Figure 8.38 I Figure 8.44 shows the space vector representation of the space vector of the quadrature signals relative to the stationary frame axes, and the projection

8-68

Grid Connected Converters and Renewable Energy Systems

!
+

vd

+ -

! +

vd

vq

Park Transformation

v
Clark Transformation

va vb vc

Figure 8.43: The three phase quadrature PLL using a Park Transformation. of this vector onto the rotating dq axes. In this particular case the x vector is not aligned with the q axis, so there is a projection onto the positive d axis. It is this value that is multiplied by 1 and then pass it into the PI controller whose output becomes the value that is added to the centre frequency of the PLL. The value of in this particular case will be a negative value (since the vd value is negated before the PI controller), and this therefore means that the rotation speed of the dq frame will be slowed down as it will be eectively subtracted from centre frequency. This resultant frequency is then integrated and becomes the value that is used to generate the position of the dq axes. Since the frequency of the dq frame is being lowered this means that the angle increasing at a slower rate, which in turn means that the angle is increasing and the x is moving more in-line with the q axis. Eventually the x vector will be in-line with the q axis, and then there will be no projection of the vector onto the d axis. At this point the PLL has locked, and the value is at x 2 radians and = . Note that the q axis value is clearly |x| at this convergence point as well. This situation is shown in Figure 8.45. The in-quadrature PLL was programmed up in the Python language.3 This version shows how the algorithm may be programmed up, and also has the addition of generating a fth harmonic in the input waveforms to see how the PLL copes with this. A listing of the software appears in Appendix G. This listing contains more than the code of the two phase PLL. It also contains code for other variants of PLLs (which are not the current subject of discussion as
3 Python is a very powerful freeware object oriented language that is exible enough to be used to implement websites and coordinate nuclear explosion simulations at Los Almos. It has a very powerful numeric library that oers matrix manipulation facilities similar Matlab at compiled speeds. In addition there is a library that mimics the graphics plotting facilities of Matlab. For Windows the best version of Python(x,y) available at http://www.pythonxy.com. For the MAC the best version if Enthought Python available at http://www.enthought.com.

8.2 Photovoltaic Inverters

8-69

Figure 8.44: Space vector representation of the convergence process of a Park Transformation based quadrature PLL.

8-70

Grid Connected Converters and Renewable Energy Systems

Figure 8.45: Space vector representation when the Park Transformation quadrature based PLL is locked.

8.2 Photovoltaic Inverters

8-71

axis values

50

50

100

4900

5000

5100

5200

5300

5400

Figure 8.46: Two phase PLL implemented in Python showing the estimated waveform versus the actual waveform. well). The test conditions for the following plots are: Amplitude of the input signal is 100; initial frequency of the input is 50Hz; the sampling frequency is 5kHz; there is a step change in the input frequency from 50Hz to 60 Hz at 5000 samples (i.e. 1 sec) into the simulation4 . The in-quadrature waveforms are simply dened as in-quadrature i..e the simulation does not develop the inquadrature waveforms from a single phase waveform. Figure 8.46 shows the identied axis waveform from the PLL (there is also an amplitude estimator so that the original waveform can be constructed from an estimated phase and amplitude). The true waveform is shown as a solid line, and the estimated waveform as a dashed line. One can see at the point of the step change that the true waveform line becomes visible. If one move to the right further in the waveform, then these two waveforms again merge over the top of one another. Figure 8.47 shows estimated centre frequency error that is added to the centre frequency to generate the actual frequency. One can see that there is very rapid identication of the new frequency. The correct value is 62.8 radians (i.e. 10Hz), and this is the value shown in this plot if a cursor is place on the line to the right of the 5000 sample point. The power supply is rarely an ideal sinusoid. One interesting question is how does this PLL operate under this condition. Figures 8.48 show the same plots as above, but for the situation where there is a signicant 5th harmonic in the input
4 This step change in frequency is quite large, and far larger than would be experience in power systems applications. This change was chosen to demonstrate the tracking capability of this PLL.

8-72

Grid Connected Converters and Renewable Energy Systems

Estimated Frequency Error

60 50 40 30 20 10 0 4500 5000 5500

Figure 8.47: Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL. the amplitude of the 5th harmonic is 30% of the fundamental. As can be seen there is signicant distortion in the estimated waveform, and Figure 8.49 shows that there are very large oscillations in the estimated frequency error . The ltering action of the frequency integrator smooths this to some degree, but still allows signicant phase distortion through which would render the PLL unusable in these applications. A low pass lter can be placed in the part of the loop, and the resulting plot is shown in Figure ??. The gains in the PI feedback also have to be lowered to ensure that the loop is stable, but even with this there are substantial oscillations in . The lower gains also mean that the phase convergence is very slow. Remark 8.70 The upshot of the simulations with the 5th harmonic input injection is that the two phase in-quadrature PLL does not work very well. I The issue of generation of the quadrature signal when the input is a single phase signal is not simple, especially when harmonics are present. One popular technique used when the frequency of the input is well known (such as in power system applications) is the T transport delay. Clearly this technique is based on 4 the idea that a delay of T where T is the period of the fundamental waveform 4 is eectively a 90 phase shift. The practical implementation of the T delay 4 can be achieved by a digital shift register where the sampled digital values are shifted on each clocked sample. The length of the shift register is T secs. 4 Remark 8.71 The
T 4

phase shift technique will have diculties when there are

8.3 Wind Turbine Converter Systems

8-73

axis values
100 50 0 50 100 4800 4900 5000 5100 5200

Figure 8.48: Two phase PLL implemented in Python showing the estimated waveform versus the actual waveform when there is a 30% 5th input harmonic.

harmonics in the supply and it the frequency of the supply varies over a wider range of frequencies. I STILL HAVE TO ADD MORE HERE ON OTHER TYPES OF SYNCHRONISING STRATEGIES.

8.2.5

Islanding Detection Techniques

Yet to be written.

8.3

Wind Turbine Converter Systems

Yet to be written.

8.3.1

Grid Requirements for Wind Turbine Systems

Yet to be written.

8.3.2

Grid Synchronization for Three Phase Systems

Yet to be written

8-74

Grid Connected Converters and Renewable Energy Systems

Estimated Frequency Error

300 200 100 0 100 200 4600 4700 4800 4900 5000 5100 5200

Figure 8.49: Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL when there is a 30% 5th input harmonic.

8.3 Wind Turbine Converter Systems

8-75

120 100 80 60 40 20 0 200 2000

Estimated Frequency Error

4000

6000

8000

10000

Figure 8.50: Two phase PLL implemented in Python showing the estimate frequency error from the centre frequency of the PLL when there is a 30% 5th input harmonic and lter.

8-76

Grid Connected Converters and Renewable Energy Systems

8.3.3

Brief Overview of Wind Turbine Converter Control

Yet to be written.

Part III

Appendices

Appendix A

Review of Second Order Circuits

This appendix will give a brief review of second order circuits. This is included as second order series and parallel circuit inevitably come into high speed digital systems due to the presence of inductance and capacitance in the various circuits.

A.1

Series RLC Circuits

Consider a circuit of the form shown in Figure A.1. Carrying out standard loop analysis we can write the following dierential equation for this circuit: R di d2 i i dvin +L 2 + = dt dt C dt (A.1)

Taking the Laplace Transform of (A.1) we can write the following transfer function for the current: i(s) sC = 2 + RCs + 1 vin (s) LCs and therefore the transfer function for the voltage across the capacitor is: vo (s) 1 = 2 + RCs + 1 vin (s) LCs One can see that the poles of (A.3) are: R 2L R2 1 4L2 LC
2 2 o

transfer function

(A.2)

(A.3) poles

s= which can be written as:

(A.4)

s =

(A.5)

A-2

Review of Second Order Circuits

+
vin
i

vout

L
Figure A.1: Series RLC circuit where: R 2L 1 o = LC = (A.6) (A.7)

natural resonant frequency resonant frequency damping factor

One can get a better impression of the position of the poles if they are plotted on the complex plane. This is shown in Figure A.2. Note that this diagram is only showing one of the two conjugate poles. We can dene several other terms from this diagram. The natural resonant frequency, d , is the frequency of oscillation of the natural response (i.e. source free response) of the circuit when there is resistance present. This is dierent from the resonant frequency, o , which is the resonant frequency of a lossless series RLC circuit.1 Another variable of interest is the damping factor . The formal denitions are: d =
2 o 2 (natural resonant frequency) = cos = (damping factor) o

(A.8) (A.9)

critical damping

From Figure A.2 one can see that if the poles are o the real axis of the complex plane then there is a projection of the complex vector onto the imaginary axis. This means that there is an oscillatory mode in the response of the circuit. If the angle is zero, then the two poles are coincident. This condition corresponds to critical damping.2 Because there is not projection onto the imaginary
1 The resonant frequency is the frequency at which a driven series RLC circuit will exhibit is minimum impedance.

A.1 Series RLC Circuits

Im
wo

A-3

wd

wo

Re

Figure A.2: Series RLC circuit pole positions. axis there is no oscillatory or over shoot behaviour in the response. From the viewpoint of the equations critical damping corresponds to the condition: d =
2 o 2 = 0

(A.10)

Therefore critical damping means that: = o 1 R = 2L LC R=2 For the case where: > o (A.12) we have two real poles generated. One the these poles will move towards the left on the real axis and the other to the right. The system response is now very slow, and it is said to be over-damped . There are no oscillations. Another important property of a series RLC circuit is its impedance. Rearranging (A.2) we can write the impedance transfer function: Z(s) = vo (s) LCs2 + RCs + 1 = i(s) Cs (A.13) L C (A.11)

over damped

If we let s = j (i.e. the resonant frequency), and substitute this into (A.13) we get: Z(s) = R + 1 L jC j 2 LC 1 =R+j C

(A.14)

2 Critical

damping gives the fastest response without overshoot.

A-4

Review of Second Order Circuits Clearly the magnitude of this expression has a minimum value when the imaginary term is zero. Therefore: 2 LC 1 = 0 = 1 = o LC (A.15)

The minimum impedance is R under this condition. As noted earlier, this occurs at the resonant frequency (o ), and not the natural resonant frequency (d ).

A.1.1

Quality Factor

Another important measure of resonant second order circuits is the quality factor Q. When a circuit is being driven in resonance this is dened as: Q 2 Total energy stored in the circuit Energy dissipated per period (A.16)

In the case of the series RLC circuit consider it to be driven with i(t) = Im cos o t. The expression for the instantaneous energy stored in the inductor is: 1 1 2 eL (t) = Li2 = LIm cos2 o t (A.17) 2 2 Similarly the energy stored in the capacitor can be calculated as follows. We know from the relationship between the current and voltage for a capacitor that: v v We can therefore write: v2 = Consequently we have: eC (t) =
2 1 2 1 Im I2 L Cv = sin2 o t = m sin2 o t 2C 2 2 o 2

= =

1 t Im cos o t dt C 0 Im sin o t o C
2 Im sin2 o t 2C 2 o

(A.18) (A.19)

(A.20)

(A.21)

using (A.15). Therefore the total energy is: eL (t) + eC (t) = 1 2 1 2 LI (cos2 o t + sin2 o t) = LIm 2 m 2 (A.22)

which is obviously a constant. The average power dissipation in a resistor with a sinusoidal input is: PR = 1 2 I R 2 m (A.23)

and hence the energy dissipated over a period To is: PR T = 1 2 1 2 I RTo = I R 2 m 2fo m (A.24)

A.1 Series RLC Circuits Using (A.22) and (A.24) in (A.16) one can write: Q = 2 = o Q= If Q = 0.5 then: R= 1 Q L =2 C L C (A.26) 1 R
1 2 2 LIm 1 2 2fo Im R

A-5

= 2fo

L R

L R L C using o = 1 LC (A.25)

which is the same expression for the resistance when the circuit is critically damped. If Q = 1 then we have: R= L C (A.27)

which is the same expression for the characteristic impedance in transmission lines. It also means that the energy stored in the circuit is the same as the energy dissipated per cycle. Therefore the energy that has to be replace per cycle is the same as that energy dissipated in the resistor which is the same as the stored energy.

A.1.2

Time Domain Response

Let us now consider the time domain solution of (A.3). In this we shall be assuming that for t < 0 then vin (t) = V0 , and at t 0 vin (t) = 0 i.e. the voltage drops to zero. Therefore the circuit becomes a source free circuit with an initial voltage on the capacitor of V0 volts. Therefore we only need to consider the natural response of the circuit. This situation will also give us a lot of information about the case when there is a positive step in the voltage. Examination of (A.1) suggests that a possible candidate solution is: v0 (t) = A1 es1 t + A2 es2 t where: s1,2 = jd Expanding the exponential terms in this equation we can write: v0 (t) = et [B1 cos d t + B2 sin d t] where: B 1 = A1 + A2 B2 = j(A1 A2 ) (A.31) (A.32) (A.30) (A.29) (A.28)

Remark A.1 Equation (A.30) is the solution for the underdamped situation in 2 an RLC circuit. Underdamping is characterised by 2 < 0 , which means that s1 and s2 in (A.28) are complex terms.

A-6

Review of Second Order Circuits In order that we can determine the B1 and B2 coecients we apply some boundary conditions: v0 (0) = V0 dv0 (0) =0 dt Applying the rst of these conditions to (A.30) we can write: B1 = V0 Taking the derivative of (A.30) we get: dv0 = et [(B2 d B1 ) cos d t (B1 d + B2 ) sin d t] dt Applying (A.34) to this expression gives: B1 = B2 d B2 = and hence the voltage equation becomes: v0 (t) = V0 et cos d t + and the derivative of this is: dv0 (t) = V0 dt d + 2 d sin d t (A.39) sin d t d (A.38) V0 d (A.37) (A.36) (A.35) (A.33) (A.34)

From (A.8), (A.7), (A.6) and (A.25) we can derive the following expressions: d = 1 R2 LC 4L2 1 1 = LC 4LCQ2 1 1 = 1 4Q2 LC

(A.40)

We shall assume that Q > 0.5, which means that the circuit is underdamped and d > 0. If we want to nd the point of the rst maximum swing in the time response (i.e. the rst maximum in the oscillatory response), then we know this must occur when d t = . Therefore: tf m = tf m = d LC 1
1 4Q2

(A.41)

A.1 Series RLC Circuits We also also write: v0 (tf m ) = V0 etf m

R 2L

A-7

since d tf m =
LC 1 1 2 4Q

v0 (tf m ) = V0 e = V0 e

4Q2 1

(A.42)

Figure A.3 shows that time plot for a series RLC circuit. In this particular case the circuit Q is 6.3. From (A.42) we can drawn the conclusion that: Vovershoot /Vstep = e

4Q2 1

(A.43)

1 0.8 0.6 0.4

-M t P e N 2L Q

LR O

Voltage v volts

0.2 0 -0.2 -0.4 - 0.6 -0.8 0

0.5

1.5

2 2.5 Time t (secs)

3.5

t fm =
-p

v 0 (t fm ) = - 0e V

4Q 2 -1

p LC 1 14Q 2

Figure A.3: Time response of a series RLC circuit with Q = 6.3.

A.1.2.1

Forced Response of Series RLC Circuit with Initial Inductor Current

In this section we shall consider the forced response of the series RLC circuit where we have an initial inductor current. The forced response will assumed to be a constant input voltage. More general forcing functions will not be considered as they are not required for the material in these notes. Consider (A.1) which is the general dierential equation for the series RLC circuit. For a constant input voltage the equation becomes: R d2 i i di +L 2 + =0 dt dt C (A.44)

A-8

Review of Second Order Circuits The natural response for this circuit is of a similar form as that in (A.28) except that the left side of the equation is i(t). As per general theory for the solution of dierential equations, the total solution is the sum of the natural response and the forced response. Therefore the solution is: i(t) = A1 es1 t + A2 es2 t + if (A.45)

where if is the forced response. The forced response in the case of a constant input voltage is zero as the capacitor is an open circuit as time goes to innity. Therefore the situation degrades to the simple natural response. Therefore, assuming the underdamped situation, the solution to the current equation is of the same form as (A.30) except that it is in terms of current and not voltage. It can be written as: i(t) = et (B1 cos d t + B2 sin d t) (A.46)

However the initial conditions are now dierent. We know the following at t = 0: i(0) = B1 = i0 where i0 is the initial inductor current. Taking the derivative of (A.46) we can write (similarly to (A.36)): di(t) = et [(d B2 B2 ) cos d t (d B1 + B2 ) sin d ] dt (A.48) (A.47)

The second initial condition is with respect to the derivative of the current. We know that: di vL = L (A.49) dt therefore at t = 0 we have that: vL (0) Vin i0 R di(0) = = dt L L (A.50)

since the capacitor is assumed to be uncharged. Clearly at t = 0 the second term of (A.48) is zero, therefore we can write: d B2 i0 = Vin i0 R L Vin i0 R + i0 L B2 = d L (A.51) (A.52)

Substituting for B1 and B2 into (A.46) we can write: i(t) = et i0 cos d t + Vin i0 R + i0 L d L sin d t (A.53)

A.2

Parallel RLC Circuits

This section carries out a similar analysis for a parallel circuit RLC as was carried out above for the series RLC circuit. To a large extent the results for

A.2 Parallel RLC Circuits this circuit conguration are a dual of those above, therefore some of the analysis here will be brief. The following discussion will be with reference to Figure A.4. If one applies nodal analysis to this gure one can write the following dierential equation for the circuit: 1 dvin vin 1 diin d2 vin + + = (A.54) 2 dt RC dt LC C dt If we take the Laplace transform of this and rearrange we can get the following transfer function: 1 1 C(s2 + RC s + LC ) iin (s) = (A.55) vin (s) s

A-9

transfer function

iin

vin

Figure A.4: Parallel RLC circuit. The impedance transfer function can be simply written from a rearrangement of A.55 as: vin (s) s Z(s) = = (A.56) 1 1 iin (s) C(s2 + RC s + LC ) As in the series RLC circuit case we can now nd the poles of this transfer function, which have a similar form to those for the series RLC circuit: s = where: 1 2RC 1 o = LC = As with the series RLC circuit we can dene: d =
2 o 2 2 2 o

impedance transfer function

poles

(A.57)

(A.58) (A.59)

(A.60) Critical damping

Critical damping is dened similarly to that for series RLC circuits in that

A-10 d = 0. This leads to:

Review of Second Order Circuits

= o 1 1 = 2RC LC R= 1 2 1 LC (A.61)

The impedance of the circuit at resonance, as with the series RLC circuit, is of interest. Substituting s = j into (A.56) and simplifying and taking the magnitude we can write: |Z(s)| = If = o = 1/ LC then: |Z(s)| = R which can be shown to be the maximum impedance of the circuit. (A.63)
2 R2

(A.62) C 2

1 L

A.2.1

Quality Factor

This will not be evaluated in the same detail as was carried out in the series RLC circuit section since the development is so close. However, the key expressions will be presented. It is assumed that the input voltage has the form: vin = Vm cos o t Therefore the current into the inductor is: 1 t vin d L 0 1 t = Vm cos o td L 0 Vm i= sin o t Lo i= The energy stored in the inductor is therefore: eL (t) = 1 2 Li 2 1 2 = Vm C sin2 o t 2 (A.64)

(A.65)

(A.66)

Similarly the energy stored in the capacitor is: eC (t) = 1 2 Cv 2 in 1 2 = CVm cos2 o t 2

(A.67)

A.2 Parallel RLC Circuits The total stored energy is: eT (t) = eL (t) + eC (t) 1 2 = Vm C(sin2 o t + cos2 o t) 2 1 2 = Vm C 2 The energy dissipated in the resistor is: eR (t) = PR To = =
2 Vm 2fo R 2 Vm To 2R

A-11

(A.68)

(A.69)

Applying the denition of quality factor (A.16) we can write:

1 2 V C Q = 2 2 Vm 2
m

2fo R

= 2fo RC = o RC =R C L (A.70)

A-12

Review of Second Order Circuits

Appendix B

Introduction to Space Vectors

B.1 Introduction

This appendix introduces the concept of space vectors. This introduction is carried out in a three stage process. Firstly consideration is given to machine windings to demonstrate that electrical machines can be accurately modeled using sinusoidal functions, even under conditions where there are non-sinusoidal waveforms present. The sinusoidal assumption is very important in machine modeling, and is developed because space vectors are developed based on sinusoidal function variations in machines. The second part of the appendix uses the sinusoidal assumption to develop dq models for electrical machines. Even though dq models were originally developed for electrical machines they nd much more general use in power systems and power electronics where one has three phase supplies. Finally space vector models are developed as an extension of dq modeling, and the connections between them are shown.

B.2

The Sinusoidal Assumption

One of the main assumptions that is used in the modeling of many types of AC machines is the sinusoidal assumption. Essentially the assumption is that the windings in the machine are arranged so that the resultant mmf has a spatially sinusoidal distribution. A normal AC machine usually has three windings spaced at 120 electrical, each producing a spatially sinusoidal mmf when fed with a current. An amazing property of this arrangement is that if it is fed with three temporal sinusoidal currents, separated temporally by 120 , then the resultant mmf is a spatially moving sine wave around the machine (this will be shown mathematically in later sections in this Chapter). Why is this assumption so important? From a modeling point of view the sinusoidal functions have a rich set of mathematical properties which make the modeling of machines analytically tractable. One of the key properties of sinusoidal functions is their connection with vectors, and the consequent ability to take orthogonal components of them. In reality the mmf produced by real windings are not pure sinusoids. Most windings for real machines are conned to slots in the stator. This leads to an

B-2

Introduction to Space Vectors mmf that has step changes in it, and consequent higher order spatial harmonics. However, the winding conguration is designed to minimize these harmonics. As we shall see below, the signicance of these winding harmonics on the performance of the machine also depends on the harmonics in the ux waveforms that interact with the windings. The sinusoidal assumption is not only applied to the mmf produced by the windings, but it is also applied to the resultant uxes produced by the action of the mmf on the iron circuit of the machine. In the case of the SYNCREL the iron circuit reluctance varies in a complex fashion due to the rotor saliency. This means that the ux density produced by the mmf is in general not spatially sinusoidal. However, the harmonics in these waveforms are usually neglected, and only the fundamental component is considered from an analysis point of view. This may seem to be a gross approximation, but models developed using this approach have been shown to give reasonable representations of the behaviour of real machines. In the remainder of this section we shall look at some of the properties of a sinusoidally distributed winding. Specically, the characteristics of a nonsinusoidal ux density interacting with a sinusoidal winding shall be considered. This is of particular relevance to the SYNCREL and other salient pole machines as their ux density distributions in general are not sinusoidal. The remainder of this section discusses the foundations of the sinusoidal assumption, and why it can be used successfully to simplify the modeling of machines, with special emphasis on the SYNCREL. Specic issues addressed are: Consideration of some of the general properties of sinusoidally distributed windings (e.g. only link with elds of the same pole number). Detailed analysis of the variation of inductance with rotor position for a two pole axially laminated rotor would be benecial.

B.2.1

Winding Interaction with Spatial Flux Density Distribution

In this sub-section we shall consider the interaction of a spatially non-sinusoidal ux density distribution with an ideal sinusoidal winding. Such an ideal winding will produce a temporal sinusoidally varying current density around the machine. The following equation can be written for the conductor density as a function of the angle p around the periphery of the machine: n(p ) = na sin p (B.1)

This waveform has an amplitude of na conductors, and goes positive and negative. How can one have positive and negative numbers of conductors? The sign convention is based on the direction of the current in the conductor. The positive part of this conductor distribution carry currents in one direction, and the negative part carry the return currents [7]. Given this winding distribution, the mmf spatial distribution readily follows. If the a-phase is carrying ia amps, then the mmf can be calculated by implementing Amperes Law. This is achieved by carrying out a closed path integral

B.2 The Sinusoidal Assumption

B-3

Figure B.1: MMF calculation integration path. over the full coil span (see Figure B.1 for the path of integration):
p +

FaT (p ) =
p

na ia sin p dp

= 2na ia cos p = 2Fa cos p Fa (p ) = Fa cos p where Fa = na ia (B.2)

The 2 factor in the front of the right hand side of the above expression is there because the total mmf is expended across two air gaps, and the Fa (p ) expression represents the mmf expended per air gap. The total number of coils in the winding is simply the sum of the number of coils at each p position. Due to the continuous nature of the proposed distribution this sum becomes an integral:

Na =
0

na sin p dp (B.3)

= 2na Therefore the peak mmf for the winding may be written as: Na i a Fa = 2

Now let us consider some general ux density waveform that varies in the following way spatially with respect to p around the machine, and also has a

B-4 time varying spatial phase angle (t):

Introduction to Space Vectors

B(p ) = Bn sin n(p (t))

(B.4)

This ux waveform is a non-sinusoidal waveform as it contains a number of harmonics denoted by the integer value of n. Furthermore assume that the winding is on a machine with the following physical dimensions: l vB r the length of the machine. the linear velocity of the B eld. the radius of the stator of the machine.

Therefore the B(p ) eld phase is changing in the following fashion: (t) = vB t r (B.5)

This expression implies that the B(p ) eld is spatially moving with respect to time. From basic physics we can say the following the voltage induced in a length of conductor l, moving with a velocity of vB perpendicular to a magnetic ux density of B is: e = BlvB (B.6) In the case of a sinusoidally distributed coil the length of conductor for one side of the coil at some position p is: lT = na l sin p (B.7)

therefore the induced voltage in the conductors at this angular position is: e(p ) = BvB na l sin p (B.8)

The ux density at this position at a particular instant of time can be determined from (B.4), and consequently (B.8) becomes: e(p ) = vB na lBn sin p sin n(p (t)) (B.9)

To simplify the following manipulations let Kn vB na lBn . In order to calculate the total voltage produced by these conductors we have to add up the contributions of all the conductors in the coil. This involves integrating the voltage at each position p for the circumference of the machine. Therefore assuming a single pole pair machine we have:
2

eT =
0

Kn sin p sin n(p

vB t )dp r

(B.10)

Using the trigonometric relation sin x sin y = 1/2[sin(x + y) + sin(x y)] one can write:
2

eT =
0

Kn nvB t sin (n + 1)p 2 r

+ sin (n 1)p

nvB t r

dp (B.11)

B.2 The Sinusoidal Assumption For the specic case of n = 1 (i.e. only the fundamental harmonic present) then (B.11) can be integrated and becomes: eT = K1 sin vB t r (B.12)

B-5

= K1 sin(B t)

i.e. the voltage induced by the winding is a temporal sinusoidal voltage (as expected). Now consider what happens to the higher order harmonics in the ux density waveform. If we carry out the integration of (B.11) for the case of n > 1 we have: eT = + Kn 2 cos n+1 2(n + 1) cos nvB t r nvB t r cos n1 2(n 1) nvB t r (B.13)

1 1 + n+1 n1

If we consider the various terms in (B.13) using the trigonometric relation: cos(x y) = cos x cos y + sin x sin y we get the following: cos n+1 2(n + 1) nvB t r 1 nvB t cos 2(n + 1) cos n+1 r nvB t + sin 2(n + 1) sin r nvB t 1 cos (B.15) = n+1 r = (B.14)

and similarly: cos n1 2(n 1) nvB t r = nvB t 1 cos n1 r (B.16)

Therefore (B.13) can be written as: eT = Kn 2 1 1 + n+1 n1 cos nvB t + r 1 1 + n+1 n1 cos nvB t r (B.17)

= 0; n > 1

Remark B.1 The implications of the above expression are that the higher order harmonics in the ux density spatial waveform do not link to the sinusoidally distributed winding. In other words the pole number of the ux density waveform has to be the same as that of the winding. This is a very important property of sinusoidal windings. One can then consider the ux density harmonics to be contributing to the leakage ux. Remark B.2 Real machine windings are not exactly sinusoidally distributed as in the ideal case above. Therefore there are spatial harmonics in the winding distribution itself. Consequently it is possible for higher order harmonics in the

B-6

Introduction to Space Vectors

Figure B.2: Dimensions of a single coil.

ux density waveform to link with same pole number harmonic in the winding distribution, resulting in a harmonic voltage. For example, most winding congurations contain a signicant third harmonic spatial component, therefore the third harmonic in the ux density waveform (introduced by saturation eects) can link with the individual windings. Consequently third harmonic voltages can be seen in the phase voltages.

B.2.2

Winding Interaction with Temporal Flux Density Variation

In this section we consider a non-sinusoidal, spatially stationary ux density distribution which has a sinusoidal temporal variation, interacting with a sinusoidal winding distribution. For the sake of the following argument consider the ux density to have the following form: B(p ) = Bn cos np (B.18)

Let us rstly consider the n = 1 case. Consider a single coil which has the dimensions shown in Figure B.2. One can calculate the ux linking a coil at any position using the general expression: = B.dS (B.19)

Consider the situation where there is only the fundamental ux density distribution. The above surface integral can be written as follows (using Figure B.2)

B.2 The Sinusoidal Assumption for the ux at angle coil position p 1 : (p ) = B1 r = B1 r

p + p p + 0 l

B-7

cos dl d l cos d
p

= 2B1 rl sin p

(B.20)

The dot product is eliminated in this situation as the ux density is perpendicular to the integration surface. In order to get the voltage induced in the coils at a particular position around the machine the following calculation has to be carried out: e(p ) = n(p ) d(p ) dt d 2B1 rl sin p = na sin p dt 2na rlB1 sin2 p = cos t (B.21)

(B.22)

Remark B.3 Equation (B.22) is obtained by realising that we are dealing with a sinusoidal temporal variation of a sinusoidal spatial distribution. Therefore the amplitude of the ux density is varying with respect to time in a sinusoidal manner. Therefore: B1 = B1 sin t (B.23) where is the frequency of the temporal variation. It is important to realise that the p angle in (B.22) is constant with respect to time in this case. To nd the total voltage for the whole winding the individual contributions for the number of turns at each position p have to be added:

eT =
0

e(p ) dp
0

2na rlB1 cos t na rlB1 = cos t =

sin2 p dp (B.24)

i.e. a temporal sinusoidal voltage is produced from the winding as one would expect. The more interesting case is when the ux density spatial distribution is non-sinusoidal as in (B.18). In this case the ux for a single coil is:
p + l

(p )n = Bn r
p 0

cos n dl d (B.25)

=
1 Note

Bn rl [sin n(p + ) sin np ] n

that the p in the following expression is the angle of the most clockwise side of the

coil.

B-8

Introduction to Space Vectors Clearly (p )n = 0 for n even. Therefore the even harmonics do not link to a single coil. For the n odd case it can be seen that the expression for the ux becomes: (p )n = 2Bn rl sin np n (B.26)

To calculate the voltage in a single coil at some position p we again apply (B.21). Carrying out the dierentiation on (B.26) we get: e(p )n = 2na Bn rl sin p sin np cos t n :n is odd (B.27)

To get the total voltage due to the winding the individual contributions are integrated as in the previous case: eT = 2na Bn rl cos t n

sin p sin np dp
0

(B.28)

It can be shown that 0 sin p sin np dp = 0, therefore the total voltage due to the odd harmonics is zero. Therefore, as with the spatially moving ux density case, only the component of the ux density that has the same pole number as the winding links with the winding, even if the harmonics are space stationary and have a time varying amplitude. Remark B.4 The main implications of the above analysis is that the ux density component with the same pole number as the winding links with the winding. Therefore, for a pure sinusoidally distributed winding, the harmonics in the ux density only contribute to the leakage ux, and do not have a role in determining the performance of the machine. However, in reality a pure sinusoidal winding cannot be produced, and there are spatial harmonics in the winding distribution. Therefore, harmonics in the ux density waveform can link with similar pole number harmonics in the winding distribution resulting in higher order voltage harmonics being produced in the winding. These harmonics will also have an inuence on machine performance.

B.3

dq Models

Most electrical machines with sinusoidally distributed windings are modeled mathematically using a technique called dq modeling. We actually used a restricted form of dq modeling in Section C.1, where the dq axes were strongly associated with the dierent permeance axes of the rotor. It is not the purpose of this chapter to give an exhaustive derivation of dq modeling of machines, as this has been done in many machines text books. However, an overview of the principles of dq modeling will be presented, and then the dq model for the SYNCREL will be derived. The fundamental assumption used as the basis of dq modeling is that the winding distribution in a machine is sinusoidal. In addition a number of other secondary assumptions are made, which are similar to the assumptions used in Section C.1, namely: a. The machine does not exhibit stator or rotor slotting eects.

B.3 dq Models

B-9

120

Figure B.3: Three phase to two phase transformation.

b. The machine iron is linear material, i.e. there is no saturation eects. The combined eect of these assumptions is that traditional linear circuit analysis techniques can be used to analyse the electrical circuit of a machine. The sinusoidal assumption means that various spatial quantities in the machine can be broken into orthogonal components. It is this that is used to carry out coordinate transformations from the three phase axes of a machine to the two phase dq axes.

B.3.1

Stationary Frame Transformations

The general idea of a dq type of transformation can be obtained by considering the transformation of the three phase currents to their two phase equivalents. Consider Figure B.3. This shows a conceptual diagram of a three phase machine. The windings represented by the concentrated coils are actually spatially sinusoidal distributed windings similar to that shown in Figure B.1. The lines through the centre of the coils are the axes of the associated winding mmfs, and therefore can be thought of as a vector that represents the sinusoidal quantities.

B.3.1.1

MMF transformations

Given that the space distribution of the mmfs for windings a, b and c can be modeled similarly to (B.2) then the following expressions can be written for the mmfs: Fa = Fa cos p 2 3 2 Fc = Fc cos p + 3 Fb = Fb cos p (B.29) (B.30) (B.31)

B-10

Introduction to Space Vectors where p is dened in Figure B.3. The resultant mmf distribution for the three phase machine is: 2 FT = Fa cos p + Fb cos p 3 2 + Fc cos p + 3 (B.32)

Assuming that the three phase windings have identical turns, and they are being driven by three phase currents of the form: ia = Ipk cos t 2 3 2 ic = Ipk cos t + 3 ib = Ipk cos t then (B.32) can be written as: FT = N Ipk cos t cos p + cos t + cos t + = 2 3 cos p + 2 3 2 3 cos p 2 3 (B.33) (B.34) (B.35)

3 N Ipk cos(t p ) (B.36) 2 i.e. the resultant mmf has a spatial sinusoidal distribution which is rotating around the machine at t electrical radians per second. Remark B.5 Note that this total mmf is expended across two air gaps. Therefore the mmf per air gap is half the value in FT . If the vectors associated with (B.29), (B.30) and (B.31) are resolved along two orthogonal axes called the dq axes then the following expressions can be written for the resultant dq axes mmfs: Fs = TFabc dq i.e.
s Fd s Fq

(B.37)
3 2

1 0

1 2

1 2 23

Fa Fb Fc

(B.38)

s s It can be shown that Fd + Fq gives the same resultant mmf distribution around the machine as the original three phase machine. In other words that transformation has converted the three phase into an equivalent two phase machine with the same mmf distribution.

Addition Add the proof that the DQ axes calculations give the same resultant mmf. In order to make this transformation invertible the T matrix and Fs vector are dq augmented as follows: 1 1 s 1 2 2 Fd Fa 3 s Fq = 0 23 Fb (B.39) 2 1 1 1 s Fc F 2 2 2 i.e. Fs = SFabc dq and Fabc = S
1

(B.40) (B.41)

Fs dq

B.3 dq Models where: S1 =

2 3 1 3 1 3

B-11

0
1 3 1 3

2 3 2 3 2 3

(B.42)

2 1 2 3 1 2 2 T S 3

3 2 23

1 2 1 2 1 2

i.e. S1 =

The choice of the 1/ 2 augmentation of T was made so that the property in (B.42) was obtained. Note that the F term is zero if the three phase mmfs contain no zero sequence components, else this term is not zero. Therefore, for a star connected machine with an isolated neutral F always equals zero, since one cannot have zero sequence currents with this conguration. B.3.1.2 Current Transformations

Given the mmf transformation in the previous section, it is a simple matter to construct the transformation for the three phase currents to their equivalent two phase currents. This transformation can be handled in two sensible ways. The transformation could be carried out in such a way that the transformed machine produces the same total power as the original three phase machine. Such transformations are called power invariant transformations. Another transformation can be implemented such that the transformed machine produces 2/3rds the power of the three phase machine. This is one particular example of a power variant transformation. Usually the power variant transformation is used, since it turns out that in steady state the two phase currents and voltages have exactly the same amplitude as the phase voltages and currents of the three phase machine. If the magnitude of the two phase quantity is taken, and then projected onto the relevant three phase axis, then the instantaneous phase value can be found. This transformation is commonly used in the machine modeling literature because of this property. Consider the situation where the two phase machine has 2/3rds the resultant mmf compared to the three phase machine. It can be shown that this means that the right hand side of (B.40) has to be multiplied by 2/3. Therefore (B.40) and (B.41) can be written as: Fs = dqy Fabc 2 SFabc 3 3 = S1 Fs = ST Fs dq dq 2 (B.43) (B.44)

Now consider the mmf expressions expressed in terms of currents and winding turns: Fs = N2 is dq dq Fabc = N3 iabc (B.45) (B.46)

B-12 Using (B.43) one can write: N2 is = dq where: N2 N3

Introduction to Space Vectors

2 SN3 iabc 3

(B.47)

the number of turns for a winding of the two phase dq machine. the number of turns for each winding of the three phase machine.

Since the two phase dq machine is an articial machine of our creation, we are free to choose the number of turns for each of the windings. Clearly if N2 = N3 , i.e. the two phase machine has the same number of turns on its windings as the three phase machine, and the is relationship has the same form as the mmf relationship. Consequently the is vector has 2/3rds the magnitude dq of the iabc resultant current vector. Therefore the current relationships between the two machines is: 2 (B.48) is = Siabc dq 3 T s iabc = S idq (B.49) B.3.1.3 Voltage Transformations

Similarly, one can derive the relationship between the three phase and two phase voltages. Consider the power relationships for the two machines:
T P3 = vabc iabc

(B.50) (B.51)

P2 =

sT vdq idq

We want P2 = 2/3P3 . Therefore substituting (B.50) and (B.51) into this expression and using (B.48) one can obtain:
s vdq =

vabc

2 Svabc 3 s = ST vdq

(B.52) (B.53)

Notice that this expression is in the same form as that for the current. Therefore it has the same property that the magnitude of the voltage vector is 2/3rds that of the voltage vector for the three phase machine. If one considers the case where the windings are excited by three phase currents of the form in (B.33), (B.34) and (B.35), then it is easy to show that: is dq = Ipk (B.54)

i.e. the magnitude of the resultant dq vector is equal to the peak current in a phase in steady state. Similarly we can write:
s vdq = Vpk

(B.55)

where Vpk the peak of three phase sinusoidal voltages supplying the abc windings. Therefore the use of the 2/3rds power relationship has allowed one to easily correlate the dq voltages and currents to their abc counterparts.

B.3 dq Models B.3.1.4 Impedance Transformations

B-13

Next we need to consider the transformation of the machine parameters between the three phase and two phase machines. Consider the following general expressions for the two machines: vabc = Zabc iabc
s vdq

(B.56) (B.57)

Zs is dq dq

Using (B.56) together with (B.49) and (B.53) one can write:
s vdq =

2 SZabc ST is dq 3

(B.58)

Comparing this expression with (B.57) one can see that: Zs = dq and Zabc 2 SZabc ST 3 2 = ST Zs S dq 3 (B.59) (B.60)

These general impedance transformations can be used to generate specic transformations for the inductances and resistances for a three phase winding. For a three phase winding the impedance matrix can be written as: Ra + Laa p Lba p = Lca p Lab p Rb + Lbb p Lcb p Lac p Lbc p Rc + Lcc p

Zabc

(B.61)

where p d/dt. By inspection it can be seen that the resistive and inductive transformations become: Rs = dq Rabc Ls dq Labc where: Ra 0 0 = 0 Rb 0 0 0 Rc Laa Lab Lac = Lba Lbb Lbc Lca Lcb Lcc 2 SRabc ST 3 2 = ST Rs S dq 3 2 = SLabc ST 3 2 = ST Ls S dq 3 (B.62) (B.63) (B.64) (B.65)

Rabc

Labc

B-14 To dq s 2 Fs = 3 SFabc dq 2 s idq = 3 Siabc 2 s vdq = 3 Svabc 2 s = 3 Sabc dq Ls = 2 SLabc ST dq 3 Rs = 2 SRabc ST dq 3 Zs = 2 SZabc ST dq 3

Introduction to Space Vectors To abc Fabc = ST Fs dq iabc = ST is dq s vabc = ST vdq T abc = S s dq Labc = 2 ST Ls S dq 3 Rabc = 2 ST Rs S dq 3 Zabc = 2 ST Zs S dq 3

Table B.1: Summary of Stationary Frame Transformations B.3.1.5 Flux Linkage Transformations

Now that we have the inductance and current transformations it is possible to develop the transformations for the ux linkages. The ux linkage expressions for the three and two phase machines are: abc = Labc iabc s dq = Ls is dq dq If (B.64) and (B.48) are substituted into (B.67) then one gets: s = dq 2 2 SLabc ST Siabc 3 3 2 = SLabc iabc 3 2 = Sabc 3 = ST s dq (B.66) (B.67)

s dq and abc

(B.68) (B.69)

The stationary frame transformations are summarized in Table B.1.

B.3.2

Rotating Frame Transformations

The transformation in (B.40) allows the three phase windings to be represented by an equivalent set of two phase windings. These winding are stationary with respect to the original three phase winding. It is then possible to project the stationary two phase windings onto two phase windings that are at some angle to the stationary winding axes and moving with respect to these axes. The following discussion is with respect to Figure B.4. This diagram shows a rotating dq axes with respect to the stationary dq axes derived in the previous section. The angle sr is dened with reference to the rotating axis as this makes it easier to see the projections of the stationary quantities onto this axis. Using the normal convention for angle sign (anti-clockwise is positive angle), one can write the following expressions:
r s Fd1 = Fd cos sr r Fd2 r Fq1 r Fq2

(B.70) (B.71) (B.72) (B.73)

s s = Fq cos(sr + ) = Fq sin sr 2 s = Fq cos sr =

s Fd

sin sr

B.3 dq Models Clearly the total mmf on each of the rotating axes is:
r r r Fd = Fd1 + Fd2 s s = Fd cos sr Fq sin sr r Fq

B-15

(B.74) (B.75)

= =

r r Fq1 + Fq2 s Fq cos sr

s + Fd sin sr

This expression can be written more succinctly in matrix form:

r Fd r Fq

cos sr sin sr

sin sr cos sr

s Fd s Fq

(B.76)

The zero sequence component can be included by ensuring that it makes no contribution to the projected vectors as follows: r Fd r Fq = r F s Fd s and Fq = s F cos sr sin sr 0 cos sr sin sr 0 sin sr cos sr 0 sin sr cos sr 0 0 0 1 0 0 1 s Fd s Fq s F r Fd r Fq r F

(B.77)

(B.78)

To make the denition consistent with the angle denition used to dene the inductance expressions, use sr = rs . Therefore the above can be written as: r Fd r Fq = r F s Fd s and Fq = s F cos rs sin rs 0 cos rs sin rs 0 sin rs cos rs 0 sin rs cos rs 0 0 0 1 0 0 1 s Fd s Fq s F r Fd r Fq r F

(B.79)

(B.80)

These relationships can be written in short form as: Fr = BFs dq dq Fs = BT Fr dq dq (B.81) (B.82)

The stationary to rotating frame transformation can be combined with the three phase to stationary two phase transformation to give the transformation from a three phase stationary frame to an arbitrary rotating frame. Clearly the transformations for the mmf are (using (B.43) and (B.44)): Fr = dq Fabc 2 CFabc 3 = CT Fr dq (B.83) (B.84)

B-16

Introduction to Space Vectors

Figure B.4: Two phase stationary to two phase rotating transformations. where: cos rs C = BS = sin rs
1 2

cos(rs + 2 ) cos(rs 2 ) 3 3 sin(rs 2 ) sin(rs + 2 ) 3 3

1 2 1 2 1 2 1 2 1 2

(B.85)

cos rs sin rs cos( 2 ) sin( 2 ) T T T C =S B = rs rs 3 3 cos(rs + 2 ) sin(rs + 2 ) 3 3

(B.86)

It can be shown that all the transformations from the abc frame to the dq r frame have the same form as the stationary frame transformations of Table B.1, except that C and CT are substituted for S and ST respectively, and the superscript on the variables becomes r . From Faradays law it is possible to express the voltages in terms of rate of change of ux linkage. In the case of the rotating transformations, this rate of change can be from two causes; (a) the time rate of change of ux linkage caused by the time rate of change of currents, and (b) the rate of change due to the relative movement of the frames. The general Faraday relationship is: vabc = pabc and abc = therefore vabc = C r dq pCT r dq
T

(B.87) (B.88) (B.89)

As can be seen from (B.85), the C matrix is a time dependent matrix, since rs is changing with respect to time. Therefore expanding (B.89) using the

B.3 dq Models To dq r Fr = 2 CFabc dq 3 ir = 2 Ciabc dq 3 r vdq = 2 Cvabc 3 r = 2 Cabc dq 3 Lr = 2 CLabc CT dq 3 Rr = 2 CRabc CT dq 3 Zr = 2 CZabc CT dq 3 To abc Fabc = CT Fr dq iabc = CT ir dq r vabc = CT vdq T abc = C r dq 2 Labc = 3 CT Lr C dq 2 Rabc = 3 CT Rr C dq Zabc = 2 CT Zr C dq 3

B-17

Table B.2: Summary of Rotating Frame Transformations chain rule one gets: vabc = {pCT }r + CT {pr } dq dq (B.90)

If one expands (B.90) by taking the appropriate derivatives, and then rearranges the result the following expression can be obtained: r r d q r r r vabc = CT p q + rs d = CT vdq (B.91) r 0 r r d q r r r (B.92) vdq = p q + rs d r 0 As we shall see in the next section, (B.92) is the form of the reluctance machine dq equations. A summary of the transformations from a stationary frame to a rotating frame appear in Table B.2.

B.3.3

Example SYNCREL Linear dq Model

Using the transformations and inductance expressions from the previous sections we are now in the position to form a linear dq model for the three phase SYNCREL. The transformation process will be carried out in a two stage process. The rst step in process is to convert the three phase model of the machine to the two phase stationary frame model of the machine. Then this model is converted to a two phase rotating model. The reason for this doing this two stage process is to expose the nature of the two phase stationary frame machine, whereas if a direct transformation to the rotating frame is carried out then this model is stepped over. The following discussion is with reference to Figure B.5. This diagram shows a three phase, two pole SYNCREL. The stationary dq frame is aligned with the d-axis along the a-phase mmf axis. The rotating d-axis is located along the high permeance axis of the rotor. Because the SYNCREL is a synchronous machine, the rotor has to be synchronized with the rotating eld in steady state. Hence this frame is also synchronized with this eld, and is known as a synchronously rotating reference frame. In this frame it will be seen that the angle dependence of the inductances disappears, and the currents and voltages are D.C. values in steady state.

B-18

Introduction to Space Vectors

Figure B.5: Conceptual diagram of a three phase SYNCREL. The most complicated part of the three phase machine to two phase machine conversion is the inductance transformation, so we shall look at this in detail. The inductances for this model were calculated in Section C.1 and appear in (C.56) and (C.57). These inductance expressions have to be transformed using the transformations in Table B.1. The inductance matrix in the stationary frame becomes: 2 L + L1 + L2 cos 2pd L2 sin 2pd 0 3 3 l 2 0 (B.93) L2 sin 2pd Ls = dq 3 Ll + L1 L2 cos 2pd 2 2 0 0 3 Ll Equation (B.93) can now be converted to the rotating frame by carrying out the BLs BT transformation using the fact that rs = pd (i.e. the reference dq frame d-axis is aligned with the high permeance axis of the rotor). After considerable manipulation one arrives at the following expression for the dq inductance matrix: 3 0 0 Ll + 2 (L1 + L2 ) 0 Ll + 3 (L1 L2 ) 0 (B.94) Lr = dq 2 0 0 Ll If one assumes that the system has not zero sequence currents owing (i.e. the machine has star connected windings with an open circuit neutral) then the last column and row can be deleted from the above matrices. Therefore the relevant matrix for the dq inductances is: Lr = dq 0 Ll + 3 (L1 + L2 ) 2 0 Ll + 3 (L1 L2 ) 2 (B.95)

B.3 dq Models Notice in (B.95) that the pd dependent inductance values of the original three phase model have been converted to time invariant and pd independent inductances in the dq frame. This results from the fact that the dq reference frame is tied to the rotor. If one were measuring the inductance whilst xed to the rotor, the inductance will not change as the rotor is rotated (assuming a non-salient stator). In addition, the transformed windings that are xed to this frame do not see any movement of the rotor from the moving d-axis, and therefore the mutual inductance term to the orthogonal winding is zero. A consequence of this simplication of the inductances is that the dq frame dynamic equations are much simpler than the three phase equations. In (B.92) we calculated the generic form of the dq dynamic equations taking into account only the voltage terms due to the ux linkages. If the three phase conversion process is carried out for the resistance it can be shown that the dq values are identical to the three phase values. Therefore, the generic dq equation can be rewritten in the following form if we include the resistive drop term and use the fact that the dq inductances are time invariant:
r vdq =

B-19

R R

ir + dq

Lr d Lr q

pir + pd dq

Lr q Lr d

ir qd

(B.96)

which can be written in scalar form as:

r vd = Rir + Lr d d r vq = Rir + q dir d dt dir q Lr dt q

pd Lr ir q q + pd Lr ir d d

(B.97)

where: 3 Lr = Ll + (L1 + L2 ) d 2 3 r Lq = Ll + (L1 L2 ) 2 Equation (B.97) is shown in diagram form in Figure B.6. It should be noted that the magnitude of the total ux linkage for the SYNCREL can be written in terms of the d and q-axis inductances as follows: = (Lr ir )2 + (Lr ir )2 q q d d (B.98)

The expression for the torque in a doubly excited system can be shown to be [28]: dLs 1 2 dLs 1 2 dLs q dq d Te = is + is + is is (B.99) d q 2 d dpd 2 q dpd dpd where the inductance terms are dened as in (B.93). Note that Ls is the dq mutual inductance between the d and q windings. Taking the derivatives in this expression, and introducing the 3/2 factor to account for three phases, we get the following expression for the torque in terms of the stationary frame dq currents: 2 3 s2 Te = (i is )L2 sin 2pd + 2L2 is is cos 2pd (B.100) d d q 2 q Using the relationship: is = BT ir (B.101) dq dq

B-20

Introduction to Space Vectors

r r pd Lq iq

R
r id r vd

Lr d

d-axis

R
r iq
r vq

r r pd Ld id

Lr q

q-axis

Figure B.6: Ideal dq equations.

one can substitute for is and is in (B.100) in terms of ir and ir , and obtain: q q d d Te = 3 2L2 ir ir d q 2 r = (Ld Lr )ir ir q d q

(B.102)

All of the analysis thus far has been for a two phase single pole pair machine. A three phase multiple pole machine only requires a slight modication to the torque expression, with the previously derived torque expression being multiplied by the pole pairs of the machine and 3/2: Te = 3 pp (Lr Lr )ir ir d q d q 2 (B.103)

The only other transformation of immediate interest that has not been explicitly carried out is the current transformation. It was eluded to in Section B.3.1.3 that one property of the rotating transformations was that the magnitude of the current and voltage vectors was equal to that of a single phase of the three phase machine in steady state. Another property that occurs is that in steady state ir and ir have D.C. values if the dq-axes are rotating synq d chronously with the rotor. To formally show these properties consider the abc machine to be driven by currents of the form in (B.132B.134). These currents are synchronized to the rotation of the rotor, and consequently so is the resultant current vector. Carrying out the transformation from the abc frame to the

B.4 Space Vector Model dq stationary frame we get: Ipk cos(pd + ) = Ipk sin(pd + ) 0

B-21

is dq

(B.104)

and the further transformation to the dq rotating frame gives: Ipk cos = Ipk sin 0

ir dq

(B.105)

Notice that if the phase angle is zero then the q-axis current is zero, and all the current lies in the d-axisi.e. along the high permeance axis of the rotor. If the peak value of the abc currents is constant, then in the dq-axes we have a constant amplitude D.C. value equal to the abc phase amplitude.

B.4

Space Vector Model

An alternative method for modeling machines that has become popular is the space vector technique. This method of modeling is very similar to the dq modeling technique, and in fact it is very simple to convert between the two dierent types of models. This technique has become popular because of the growth in vector based control techniques and the fact that machine equations take a simpler form due to its notation. For example, the electrical dynamics of an induction machine can represented by two equations (instead of four with a dq model). The form of the equations also evokes a resultant vector way of thinking about the machines operation, as opposed to a component vector approach with the dq modeling technique. A full discussion of space vectors applied to the control of machines can be found in [14]. The application of space vectors to reluctance machines has not been as pervasive as it has with induction machines because the reluctance machine more naturally relates to a component viewpoint due to the presence of two dierent permeance axes. However, in some situations space vectors are a useful tool for viewing the machines operation. It should be emphasized that because the reluctance machine does not have any rotor winding we have no need to develop rotor expressions, as is the case with the induction machine. Space vector modeling is based on the concept that the mmf of a three phase machine can be represented by a resultant vector that has a physical location in space. This stems from the fact that the individual windings of the phases are sinusoidally distributed, and the vector for each of the windings can be considered to lie on the axis of the phases. It should be noted that the dq modeling developed in the previous sections used similar assumptions, but the modeling approach was dierent.

B-22

Introduction to Space Vectors

B.4.1
B.4.1.1

Current Space Vectors

Stationary Frame Current Vectors

In a manner similar to (B.32) we can write the following expression for the resultant mmf in a three phase machine:
s FT = N3 [ia (t)cosp + ib (t)cos(p

4 2 ) + ic (t)cos(p )] 3 3

(B.106)

where p is the angle from the axis of the a-phase winding as dened previously. The notational simplicity of the space vector formulation is obtained by introducing complex notation. In the following equations the _ is used to denote vectors in the complex form. Equation (B.106) can be written as:
s FT = N3 Re[ia (t)ejp + ib (t)ej(2/3p ) + ic (t)ej(4/3p ) ] 2 3 = N3 Re[ia (t) + aib (t) + a2 ic (t)]ejp 2 3

(B.107)

where a = ej2/3 , and is a vector of unit length lying spatially along the axis of the b-phase. Similarly a2 = ej4/3 , and lies along the c-phase axis. Notice that this complex notation implicitly means that we have a set of pseudo dq axes, which now correspond to the real and imaginary axes. If (B.107) is broken apart and the current section extracted, and then the real and complex components are collected together we can write: is = 2 [ia (t) + aib (t) + a2 ic (t)] 3 = |is | ejs

(B.108)

Figure B.7 shows pictorially what this expression means. The |is | vector is the magnitude of the resultant current vector. Notice that the direction of this vector is spatially the same direction as the original mmf vector (since mmf and current are related by a scalar). The s angle is the angle of this vector with respect to the reference a-phase axis. If one were to add together the ia , ib , and ic current vectors graphically on this diagram, the resultant current vector would have the angle s but be 3/2 times the magnitude. The 2/3rd term was introduced into (B.107), and then carried into (B.108), since the resultant current vector has the property that the vector can be directly projected back onto the three phase axes. It should be noted that implicit in this projection is that there are not zero sequence currents owing (i.e. ia + ib + ic = 0). It can also be shown that under this restriction these projections can be represented by the following relationships: (is ) = ia (a is ) = ib (ais ) = ic
2

(B.109) (B.110) (B.111)

In the particular case where the currents are of the form (B.33B.35) then

B.4 Space Vector Model

B-23

Figure B.7: Resolving the current space vector onto the abc axes. the space vector can be written as follows: is = 2 2 2 2 Ipk [cos t + (cos + j sin ) cos(t ) 3 3 3 3 4 4 2 + (cos + j sin ) cos(t + )] 3 3 3 2 3 1 1 = Ipk [cos t ( cos t + sin t) 3 2 2 2 1 1 3 1 3 3 ( cos t + sin t) ( cos t sin t) +j 2 2 2 2 2 2 3 1 3 j ( cos t sin t) 2 2 2 = Ipk (cos t + j sin t) (B.112)

is = Ipk ejt

Therefore the resultant current vector has a constant magnitude and the angle s is changing at the constant rate of , i.e. the vector is rotating around the machine at a constant angular frequency. The space vector representation can be simply related back to the dq representation. From (B.48) it can be seen that: is = d 1 1 2 ia ib ic 3 2 2 1 is = [ib ic ] q 3 (B.113) (B.114)

B-24

Introduction to Space Vectors

Figure B.8: Relationship between the dq-axes and current space vectors. If one takes the real and imaginary components of (B.108) then one can write the following: (is ) = 2 (ia + aib + a2 ic ) 3 2 2 2 4 4 = (ia + (cos + j sin )ib + (cos + j sin )ic ) 3 3 3 3 3 2 1 1 = ia ib ic = is (B.115) d 3 2 2 1 (is ) = [ib ic ] = is q 3

Similarly: (B.116)

These projections can be seen in Figure B.8. Note that the dq projections are not as restrictive as the projections onto the abc axes. For example, if there are zero sequence currents then (B.115) does not equal (B.109). Zero sequence currents require the presence of an additional space vector equation, as was the case with the dq equations. However, the discussion in this book shall be focussed on balanced (and usually star connected) machines that do not have zero sequence current components. B.4.1.2 Rotating Frame Current Vectors

Similar space vector expressions can be derived for frames that are not stationary to the rotor. Consider the situation shown in Figure B.9. Here we have the original is vector as in Figure B.8, as well as the same vector projected onto another frame which is possibly rotating.

B.4 Space Vector Model

B-25

Figure B.9: Space vector rotating frame transformations. The current vector can be written with reference to the rotating frame as: ir = |ir | ej = |ir | ej(s rs ) Now is = |is | ejs = |ir | ej(rs +) (as |is | = |ir | ) = |ir | ej ejrs is = ir ejrs = ir ejsr and ir = is ejrs = is ejsr (B.117)

The sign of the angle in (B.117) is dependent on the reference axis for the angle dierence between the two reference frames. The normal convention adopted is that the old frame is taken as the reference, therefore the sign convention is: xnew = xold ejnewold where: newold the angle between the new and old axes with reference to the old axis. Therefore in (B.117) rs is the the angle of the rotating reference frame with respect to the stationary frame, and sr is the stationary reference frame measured with reference to the rotating reference frame. The relationships in (B.117) are general and can be applied to all space vector axis transformations. (B.118)

B.4.2

Flux Linkage Space Vector

a = Laa ia + Lab ib + Lac ic b = Lbb ib + Lba ia + Lbc ic c = Lcc ic + Lca ia + Lcb ib (B.119) (B.120) (B.121)

The total ux linking the phases in a three phase machine are:

B-26

Introduction to Space Vectors Dene the ux linkage space vector as follows: s = 2 (a + ab + a2 c ) 3 (B.122)

The justication for the denition of the space ux vector is that the fundamental of the ux linkage to a single phase varies as a sinusoidal function of the current angle to the axis of any particular phase. Therefore the ux linkage has similar spatial sinusoidal properties to the mmf of the machine, and the same techniques can therefore be applied. Substituting (B.119B.121) into (B.122)and assuming that Lab = Lba Lac = Lca Lbc = Lcb one obtains: s = 2 1 (2Laa Lab Lac ) ia + (2Lab Lbb Lbc ) ib 3 2

+ (2Lac Lcc Lbc ) ic 3 +j (Lbb Lbc )ib + (Lab Lac )ia + (Lbc Lcc )ic 2

(B.123)

This expression for a cylindrical rotor machine (i.e. the self inductances are equal, and the mutual inductances are equal) can be simplied greatly. For the reluctance machine the expression is much more complicated. Substituting the inductance expressions (C.56) and (C.57) into (B.123), and after considerable manipulation one obtains the following expression for the ux space vector in a stationary reference frame: s = (L1 + L2 cos 2pd )ia + ( + ( L1 + L2 cos 2(pd ))ib 2 3

L1 + L2 cos 2(pd + ))ic 2 3 1 3 3 3 ( 3L2 sin 2pd )ia + ( L1 L2 ( cos 2pd + +j sin 2pd ))ib 2 2 2 3 3 3 3 + ( L1 + L2 ( cos 2pd sin 2pd ))ic (B.124) 2 2 2

The validity of this expression can be checked as follows. If (B.124) is calculated for pd = 0 and ia = Ipk , ib = Ipk /2, ic = Ipk /2, (i.e. the mmf vector lies coincident with the a-phase) then the real part of the inductance is 3/2(L1 +L2 ) as expected from the dq analysis. A similar result can be found for the imaginary component for pd = 90 , ia = 0, ib = 3/2Ipk , ic = 3/2Ipk (in this case the mmf is at 90 and the rotor d-axis is also in this position). If the currents are in the form of (B.132B.134) then (B.124) can be simpli-

B.4 Space Vector Model ed to the following expression: s

3 currents

B-27

3 Ipk (L1 cos(pd + ) + L2 cos (pd )) 2

(B.125)

+ j (L1 sin(pd + ) + L2 sin(pd )) 3 (B.126) Ipk L1 ej(pd +) + L2 ej(pd ) 2 This special case for the currents has been chosen because it is the form of the currents that are applied to a vector controlled machine. It can be seen that the resultant current is synchronized to the rotor position such that the resultant current vector has an angle of radians with the rotor high permeance axis (see Figure B.9). Notice that because the current amplitude only appears as Ipk in (B.126), as opposed to 3/2Ipk , which is the value of the three phase current vector. The 3/2 that does appear in (B.126) is due to the inductance part of the expression. Therefore the magnitude of the ux linkage is 2/3rds of the ux linkage for the three phase machine, as was indicated from the denition of the ux linkage expression (B.122). =

B.4.3

Voltage Space Vector

In a manner analogous to the denitions of the current and ux space vectors one can dene the voltage space vector: 2 (va + avb + a2 vc ) (B.127) 3 where va ,vb ,vc are the individual phase voltages. The concept of the voltage space vector is quite abstract. However, its existence can be justied from the vectors already dened. The voltage in a machine is made up of two components; the resistive drop, and the induced voltage from changing ux linkages. We have already dened the current vector, and the resistive drop is simply this vector multiplied by the resistance (which is a scalar). The ux linkages have also been dened as a vector, and taking their derivative in vector sense also results a vector. Therefore both components of the voltage are vectors, and consequently the voltage can be considered to be a vector. It is easy to demonstrate that if one takes components of a voltage vector for a set of three phase windings one does get the individual abc components of the voltages. Note that this process requires that there are no zero sequence voltages present. vs =

B.4.4

Example SYNCREL Space Vector Model

We have assembled enough of the space vector model machinery to construct the space vector electrical model for the SYNCREL (Synchronous Reluctance Machine). This machine has been chosen because it is very simple, in fact about as simple a model as one can get for a machine. The simplicity results from the space vector notation. A SYNCREL has only one set of three phase windings on the stator, therefore the expression for the stator voltage in space vector notation using stationary frame variables is: v s = Ris + d s dt (B.128)

B-28

Introduction to Space Vectors It is a straight forward process to verify this expression from the denitions already presented for the various space vectors. Evaluation of the voltage from (B.128) is complex due to the nature of the ux linkage term in a stationary reference frame. A great simplication can be achieved by converting this expression into a rotating frame synchronized with the rotor (as was done with the dq equations). Applying (B.118) to the voltage, current and ux linkage vectors, one can write the following relationship between the stationary and rotating reference frame vectors: v s = v r ejpd is = ir ejpd (B.129) s = r ejpd Substituting (B.129) into (B.128) gives: d r ejpd dt d r j dpd = Rir ejpd + e pd + r ejpd j dt dt d r + jpd r v r = Rir + dt dpd where pd = rotor angular velocity dt pd angle from stationary to rotating frame v r ejpd = Rir ejpd +

(B.130)

(B.131)

Assuming that the currents being applied to the machine are of the form: ia = Ipk cos(pd + ) 2 ) ib = Ipk cos(pd + 3 2 ic = Ipk cos(pd + + ) 3 then it is not dicult to show that: is = Ipk ej(pd +) Therefore the rotating frame current space vector is, using (B.117): ir = Ipk ej Applying a similar transformation to (B.126), one obtains: r = 3 Ipk [(L1 + L2 ) cos + j(L1 L2 ) sin ] 2 3 = Ipk L1 ej + L2 ej 2 (B.136) (B.135) (B.132) (B.133) (B.134)

(B.137)

B.4.5

Space Vector Power Expression

Now that we have the space vector representations for the dynamic equations we are in a position to calculate the input stator power for the machine in

B.4 Space Vector Model terms of space vectors. Assuming that there are no zero sequence components the following expression can be written for the instantaneous real three phase power of the machine: P3 = va ia + vb ib + vc ic = (v s ) (is ) + (a2 v s ) (a2 is ) + (av s ) (ais ) This equation can also be written in a more compact form: P3 = 3 2 (v s i ) s (B.139) (B.138)

B-29

where the means complex conjugate. Because the space vectors are closely related to the time domain phasors in steady state the similarity of this expression with the time domain complex power expression should not be surprising. This expression can be conrmed by the following expansion: (v s i ) = s = j = 2 3 2 3
2

va + avb + a2 vc
2

ia + a ib + a2 ic

3 3 3 va ia + vb ib + vc ic 2 2 2

3 ((ic ib )va + (ia ic )vb + (ib ia )vc ) 2 (B.140)

2 (va ia + vb ib + vc ic ) 3

As can be seen from (B.140) the space vector representation of the machine is absorbing 2/3rds the power of the three phase machine. Hence the space vector transformations we have developed are power variant transformations, as was the case for the dq transformations.

B.4.6

Space Vector Expression for SYNCREL Torque

The classic way of calculating the power or torque produced by an electrical machine is to write the equation for the energy balance in the machine. The following discussion is based on that in [28]. The expressions developed are for electrical to mechanical energy conversion. Mechanical to electrical conversion is the dual of this, and will not be discussed separately. The energy balance equation is based on the conservation of energy principle i.e. the input energy must be balanced by the losses (both electrical and mechanical), any energy transiently stored in the system (both mechanical and electrical), and the output energy in the form of mechanical work. Therefore the energy balance can be written as: Electrical energy input = Electrical losses + Stored energy in elds + Mechanical energy (B.141)

In symbol form this may be written as: Ee = Ele + Ef e + Eme (B.142)

B-30

Introduction to Space Vectors The mechanical energy component may not appear as mechanical work, but some of it may be stored in forms such as kinetic energy and various forms of potential energy. Therefore the actual output mechanical energy is: Emo = Eme Elm Esm where: Elm Esm the mechanical losses the stored mechanical energy (B.143)

Therefore (B.142) may be written as: Ee = Ele + Elm + Ef e + Esm +Emo

Losses Stored

(B.144)

The power expression developed above can be used as a means to calculate the torque produced by the machine. A general expression for torque is: T = P (B.145)

where T the mechanical shaft torque, and P the mechanical shaft power, and the shaft angular velocity. This expression can be used to develop the electro-magnetic torque for the space vector model of the machine by utilizing the energy balance expressed in (B.142). If one can identify the loss and eld storage terms then they can be subtracted from the total input energy to give the mechanical output energy. This can then be substituted into (B.145) to give the electromagnetic torque. Remark B.6 Note that (B.145) has been dened in terms of the mechanical output shaft quantities. However, in transient situations the mechanical torque and the electro-magnetic torque are not equal, since some of the electro-magnetic torque is absorbed in accelerating the self inertia of the rotor itself. However, the expression is still valid if all the quantities are dened at the point of the air gap of the machine i.e. in terms of the electro-magnetic torque and the electro-magnetic power. This is the approach taken in this analysis. Consider the expression (B.128). The power expression for the machine can be written using the relationship (B.139) as follows: P3 = 3 2 (v s i ) = s 3 2 Ris i + s d s dt i s (B.146)

Clearly the Ris i term is related to the power losses in the machine, therefore s the dts i term must be related to stored eld energy and mechanical output s power. Considering the last term for the special case of currents in the form (B.132B.134), with Ipk constant with respect to time, and using (B.126) we
d

B.4 Space Vector Model can write: d s dt = d dt 3 Ipk L1 ej(pd +) + L2 ej(pd ) 2 3 Ipk L1 ej(pd +) + L2 ej(pd ) 2 (B.147)

B-31

= j

= jpd s where pd dpd = dt

Therefore the power expression under this steady state condition becomes: P3 = 3 2 Ris i + jpd s i s s (B.148)

Clearly there is only one term related to the rotational power and that is jpd s i . Expanding this using i = Ipk ej(pd +) and (B.126) one gets: s s 3 3 2 jpd Ipk L1 + L2 ej2 2 2 9 2 = pd Ipk L2 sin 2 4 9 2 T e = Ipk L2 sin 2 4 P3 =

(B.149) (B.150)

If we remove the restriction that Ipk has to be constant, then we would end up with Ldi/dt type terms in (B.147). These terms are not related to pd in any way, and result in change of stored eld energy terms in (B.146). Therefore (B.149) is valid for the transient condition as well as for steady state. The same expression can be obtained if the torque is calculated using the rotating reference frame expression of (B.130). In this case the rotational power term is even more easily identied. Consider the power expression in this frame: P3 = 3 jpd r i r 2 3 3 = jpd Ipk L1 ej + L2 ej Ipk ej 2 2 9 2 = Ipk jpd L1 + jpd L2 ej2 4 9 2 = pd Ipk L2 sin 2 4

(B.151)

as found in the stationary frame case. Therefore the power and torque produced is reference frame independent (as one should expect). Remark B.7 Note that (B.149) is converted to (B.150) by dividing by pd . However, pd is in electrical radians/sec, therefore this will only give the correct expression if the machine is a two pole machine (one pole pair). To make the expression appropriate for any number of poles, equation (B.150) must be multiplied by the number of pole pairs.

B-32

Introduction to Space Vectors

B.4.7

Relationship Between Space Vectors and dq Models

Clearly the space vector model and the dq model of a machine are very closely related. The Real and Imaginary axes of the space vector model can be considered to be the same as the dq axes. Therefore, by taking the components of the space vectors (i.e. taking the Re and Im parts) onto these axes one can obtain the dq representation of the variable or equation. For example, consider the (B.126) representation for the ux linkage. Taking the and parts we obtain: s s 3 Ipk [L1 cos(pd + ) + L2 cos(pd )] 2 3 = Ipk [L1 sin(pd + ) + L2 sin(pd )] 2 = (B.152) (B.153)

3 currents

3 currents

Calculating the ux linkage using (B.93) and (B.104) one gets the following:
s d s q

3 Ipk 2

L1 cos(pd + ) + L2 (cos 2pd cos(pd + ) + sin 2pd sin(pd + )) L1 sin(pd + ) + L2 (sin 2pd cos(pd + ) cos 2pd sin(pd + )) (B.154)

Since: cos 2pd cos(pd + ) + sin 2pd sin(pd + ) = cos(pd ) sin 2pd cos(pd + ) cos 2pd sin(pd + ) = sin(pd ) then the space vector and dq expressions are equivalent. This equivalence is more easily veried if the rotating versions of the two models are compared. Consider (B.137). If Re and Im parts are taken we have: r r 3 Ipk [(L1 + L2 ) cos ] = Ld id 2 3 = Ipk [(L1 L2 ) sin ] = Lq iq 2 = (B.155) (B.156)

3 currents

3 currents

since we know that Ld = 3/2(L1 + L2 ) and Lq = 3/2(L1 L2 ), and id = Ipk cos , iq = Ipk sin from the dq model theory. Finally it can be shown that the space vector and dq model theory give the same torque expressions. Consider the following relationships:
2 2 Ipk sin 2 = 2Ipk cos sin

= 2id iq 2 3 3 2L2 = (L1 + L2 ) (L1 L2 ) 3 2 2 2 = (Ld Lq ) 3

(B.157)

(B.158)

Substituting these into (B.150) gives the normal dq torque expression (B.102).

Appendix C

Calculation of Inductances for a Synchronous Reluctance Machine

C.1 Calculation of Inductances

One of the fundamental parameters of any machine model is the inductance of the armature windings of the machine under all operating conditions. Later in this chapter we shall that the variation of inductances with respect to the mechanical position of the rotor is directly connected with electromagnetic energy conversion in all machines, and hence with the production of torque. Therefore the calculation of the SYNCREL inductances is fundamental to understanding the machines operation. In the case of the SYNCREL, the armature is on the stator, since the rotor does not have any windings. We will nd that the inductance of a particular winding varies depending on the position of the rotor in relation to the winding, and the degree of magnetic saturation of the stator and the rotor iron. This section will determine the self and mutual inductances for the stator windings of the SYNCREL. The derivation of these inductances will be carried out in a detailed and formal manner using a traditional approach. The following standard assumptions are made in the following analysis: a. The stator windings are sinusoidally distributed. When excited with current a sinusoidal spatial distribution of mmf is produced. b. The machine does not exhibit any stator or rotor slotting eects. c. The machine iron is a linear material, i.e. it is not subject to magnetic saturation eects. The permeability of the material is very large in comparison to air. Therefore the permeance of the magnetic paths is dominated by the air gaps. d. The air gap ux density waveforms can be adequately represented by their fundamental component. e. The stator turns are all full pitched (i.e. they cover electrical radians).

C-2

Calculation of Inductances for a Synchronous Reluctance Machine

Figure C.1: Two pole three phase Syncrel conceptual diagram f. There is no leakage ux i.e. there is perfect coupling between the windings. Figure C.1 is a conceptual schematic of a two pole, three phase SYNCREL. Note that the rotor shape does not represent a realistic rotor, but is drawn in this manner to accentuate the variable reluctance in the d and q axes. The axis of the rotor which oers the minimum reluctance to the passage of ux across the air gap from the stator to the rotor is called the d-axis. The maximum reluctance path is denoted as the q-axis. Note that following development will use the concept of dq axes before the concept has been rigorously developed in a more general framework. This will occur later in section B.3. In the following development the dq axes are closely associated with the physical conguration of the rotor, therefore the general development can be left to later without having too many problems understanding this material. A few preliminary conjectures, based on heuristics, can be made about the variation of the winding inductance with respect to the angular rotor position: Conjecture C.1 The winding self inductance will be a maximum when the daxis of the rotor is aligned with the axis of the winding. Remark C.1 This conjecture concurs with ones intuitive understanding of ux interacting with iron. The presence of iron in a coil will result in more ux per unit of current. When the d-axis is aligned with the axis of a coil then there will be more iron in the ux path for the coil. Conjecture C.2 The winding self inductance will be a minimum when the qaxis of the rotor is aligned with the axis of the winding.

C.1 Calculation of Inductances Remark C.2 If there is less iron in the coils ux path then it is harder to produce ux for a given amount of current in the coil. Clearly if the q-axis is aligned with the axis of the coil then there is a larger air path and less iron for the ux to travel through. Conjecture C.3 As the rotor is rotated between these two positions the self inductance varies. The period of the phase inductance variation is half the period of the mmf variation for the phase winding. Remark C.3 This is fairly obvious since the phase inductance is a maximum when a d-axis rotor pole aligns with the phase axis, and this occurs when the rotor has rotated through electrical radians. Conjecture C.4 There is mutual inductance between the three phase stator windings that is a function of the rotor position. Remark C.4 Clearly as the rotor is rotated the amount of iron in the paths that would be taken by the mutual ux will vary, and hence the amount of ux linking the windings will vary. A complete analysis of this situation involves computing of all the harmonics of the ux density waveform and then calculating the total ux linkage with the winding. One then obtains inductance expressions containing a number of harmonic terms. The harmonic term amplitudes decrease rapidly with increasing harmonic number, allowing the approximation of considering only the fundamental to be made. The constant reluctance path approximation made in the following analysis is essentially the same approximation. If the winding function technique is use to calculate the inductances then the harmonic eects are sometimes more readily included.

C-3

C.1.1

Self Inductances

Firstly consider the self inductance of the a-phase sinusoidally distributed winding. A useful technique to calculate inductances in situations like this is to consider that the stator mmf can be broken into two sinusoidally distributed components which can be considered to be acting along the d-axis and the qaxis of the rotor.(this is possible because of the assumed sinusoidal nature of the mmf, which implicitly allows components to be taken). Let us consider a few simple cases of the application of this concept. Figure C.1 can be used as an aid to visualise the situation. If, for example. the rotor d-axis is aligned with the axis of the a-phase winding then the total a-phase mmf acts on the d-axis permeance, and there is no component acting on the q-axis permeance. Since the stator mmf is spatially sinusoidally distributed, then this means that the air gap ux density waveform would be sinusoidally distributed. Similarly if the rotor q-axis is aligned with the a-phase axis, then the total a-phase mmf acts on the q-axis permeance. Between these two rotor positions the permeance seen by the winding is, in general, a complex function of the rotor angular position. Consequently, the air gap ux density distribution is also a complex function of the rotor angle. The sinusoidally distributed mmf on the stator of the machine can be broken into two sinusoidal components which are centred on the d and q-axes respectively, regardless of the position of the rotor. These component mmfs are then

C-4

Calculation of Inductances for a Synchronous Reluctance Machine acting on the d and q-axis permeances, Pd and Pq . Since these permeances are constant, this is equivalent to saying that the component mmfs are acting on two constant air gaps, gd and gq , for the d and q-axes [28]. Therefore the resultant component air gap ux densities should be spatially sinusoidal, and consequently the resultant total air gap ux density should also be sinusoidal. This contradicts the statements made in the previous paragraph about the complex nature of the air gap ux density. However, the fundamental of the actual air gap ux density is, in practice, very close to that obtained using this approximation, and measured inductances for real machines are in reasonable agreement with the calculated values based on the approximation. The reason for this is that sinusoidally distributed windings will only link to the components on a ux density waveform that have the same pole number as the winding, as was previously shown in Section B.2. Therefore, for an ideal sinusoidally distributed winding only the fundamental component of the ux density can link to the winding, and consequently harmonic ux densities only contribute to leakages. Remark C.5 An ideal sinusoidally distributed winding cannot be constructed all true windings have winding space harmonics. These winding harmonics can therefore link to harmonic ux densities of the same poll number. This can lead to the generation of harmonic voltages, and more complex inductance variations with rotor position. Addition Could add a section here examining the assumption that the d and q-axes air gaps can be modeled as constant air gaps. Could consider an ideal 2 pole axially laminated machine, looking at the eective air gap seen by the mmf in both the axes. The following is with reference to Figure C.2, which is a laid out diagram of Figure C.1. This diagram shows the two ctitious air gaps, with the component mmfs acting on the d and q-axes respectively. The resultant air gap ux density distributions are shown for the two axis waveforms. Notice that the resultant air gap ux density waveform is distorted away from the d-axis of the rotor by the q-axis ux waveform, the degree of distortion being related to the dierence between the air gap lengths and the mmf applied in the axes. In order to calculate the self inductance of the a-phase winding the total self ux linkage must be calculated for the winding. This self ux linkage has separate components contributed by both the d and q-axis uxes. Using the approach in [28] we calculate the ux due to one of the component mmfs acting on one of the air gaps by proceeding in the following manner: a. Calculate the ux in an incremental area at some angular position in the machine accounting for the spatial distribution of the mmf. b. One then integrates up these incremental uxes for a total span of a single coil. This gives the total ux linking one coil. c. Calculate the ux linking all the coils that have their axes at some angular position around the machine. This is achieved by multiplying the value obtained in point b by the number of turns that lie in the same position as the single coil. d. Finally integrate up the previous value over the coil span accounting for the change in the number of turns with angular spatial variation.

C.1 Calculation of Inductances

C-5

Figure C.2: Developed diagram of a Syncrel.

e. Once the ux linkage for each air gap is found then the total ux linkage to the a-phase is found by adding together the linkages due to the d and q axes.

Consider the d-axis, as shown in Figure C.3. The expression for the ux over a 180 electrical span of the d-axis mmf can be found as follows. Consider the incremental permeance over an angle of d:

dPd =

o dA gd

(C.1)

C-6

Calculation of Inductances for a Synchronous Reluctance Machine

Figure C.3: d axis developed diagram for Syncrel where: dA lm r o the incremental area. = lm r d machine periphery angle relative to the d axis. the length of the machine. the radius of the machine at the centre of the air gap. the permeability of free space.

Therefore the incremental ux can be written as: dd = dPd Fd cos = Fd o lm r cos d gd (C.2)

where Fd cos is the d-axis component mmf. To nd the total ux linking a single coil whose most clockwise coil side starts at radians relative to the d-axis position, we integrate the d-axis incremental

C.1 Calculation of Inductances uxes dd for the dA elements using the following integration:
+

C-7

d =
+

dd Fd o lm r cos d gd (C.3)

2Fd o lm r sin gd

where: Fd = Fa cos pd the component mmf at pd , and Fa the peak mmf of the a-phase. pd

(C.4)

the angle of the d-axis around the machine periphery (elec-rad) (C.5)

Remark C.6 Note that the above denition of the ux linkage per turn implies that the normal vector for the coil area is at the angle +/2 radians. Realising this is important in getting the correct sign for the total ux linkage of the coil. Clearly the maximum ux of 2Fd o lm r/gd is obtained when the coil side = /2 this means that the coil axis is a 0 radians and hence aligns with the component mmf axis. Equation (C.3) can be written in terms of the total d-axis permeance by utilising the following expression:
2

Pd = = = therefore (C.3) can be written as:

2 2 2

dPd o lm r d gd (C.6)

o lm r gd

2Fd Pd sin (C.7) If a coil side starts at some angle with respect to the d-axis then the coil axis is at + /2. Dene: d () = a and hence: a = + and consequently: = a angle of the coil axis relative to the d-axis 2 (C.8)

(C.9) 2 Substituting this into (C.7) we can write the ux for a single turn whose axis is at a with respect to the d-axis as: d (a ) = 2Fd Pd sin(a ) 2 2Fd Pd = cos a

(C.10)

C-8

Calculation of Inductances for a Synchronous Reluctance Machine This expression can be further manipulated so that the ux is a function of the angle of the d-axis and the coil axis with respect to the axis of the a-phase. Let: a therefore: a = a pd Substituting this into (C.10) we can write the following: d (a , pd ) = 2Fd Pd cos(a pd ) (C.12) (C.11) the angle of the coil axis with respect to the a-phase

+ = sin

(C.13)

We are now in a position to calculate the ux linkage to the turns of a-phase at some particular coil axis angle a for some constant d-axis. The number of turns that have their coil axis at angle a can be deduced from the turns density function (B.1) as: nta (a ) = na cos a (C.14) Remark C.7 Clearly nta (a ) can be negative. The concept of a negative number of turns/radian at a particular coil axis angle is related to the concept of a negative number of conductors around the periphery of the machine (the sign in this case arising from the direction of current in the conductors at that point).The turns density function expressed in a is essentially the mmf/ampere for the winding at a particular position. This is also known as a winding function. Therefore the negative sign indicates that the ux produced is in the opposite direction across the air gap (i.e. from the stator to the rotor instead of from the rotor to the stator). Therefore the total ux linkage for the number of turns at a is: d (a ) = 2Fd Pd na cos a cos(a pd ) (C.15)

We are now in the position to calculate the total ux linkage of the d-axis ux to the a-phase by integrating the ux linkage d (a ) at each position a for the coil span of the winding. Therefore the total ux linkage is: ad (pd ) = 2Fd Pd na
+

cos a cos(a pd )da

(C.16)

Carrying out this integration and simplifying the result we obtain: ad (pd ) = Fd Pd na cos pd (C.17)

In a similar fashion, the ux linkage of the q-axis ux with the a-phase can be found. The procedure is identical to the above so it will not be presented in detail. Instead we will simply state the results of the intermediate steps and then present the nal ux linkage result.

C.1 Calculation of Inductances The incremental permeance for the q-axis is: dPq = o lm r d gq (C.18)

C-9

and therefore the total permeance of over a coil span is:

Pq =
0

dPq o lm r gq (C.19)

The q-axis is at an angle of /2 radians with respect to the d-axis. Therefore the variation of the q-axis mmf is: Fq = Fq cos( ) 2 Therefore the q-axis incremental ux linkage is: dq = dPq Fq cos( ) 2 Since cos( ) = sin , and substituting for dPq in (C.21) gives: 2 dq = o Fq lm r Fq Pq sin d sin d = gq (C.22) (C.21) (C.20)

Consequently the expression for the ux linkage for a single coil can be written as:
+

q () =

dq Fq P q 2Fq Pq
+

= =

sin d

cos

(C.23)

where an angle relative to the d-axis. Carrying out the angle conversion to the coil axes relative to the a-phase as was done in the d-axis case we can write: q (a ) = 2Fq Pq sin(a pd ) (C.24)

The total ux linkage of the q-axis ux to the a-phase can therefore be written as:
+

aq (pd ) =

nta (a )q (a ) da

2Fq Pq na + cos a sin(a pd ) da aq (pd ) = Fq Pq na sin pd =

(C.25)

C-10

Calculation of Inductances for a Synchronous Reluctance Machine In the above expressions the peak values of the d and q-axes mmfs are found by taking components of the a-phase mmf onto the d and q-axes respectively as follows: Fd = Fa cos(pd ) = Fa cos pd Fq = Fa sin(pd ) = Fa sin pd (C.26) (C.27)

where Fa the peak of the a-phase mmf = na ia (from (B.2)). Note that the negative sign in front of the pd terms results from the fact that the angle is measured relative to the d-axis, and not the a-phase axis,since we are projecting the a-phase mmf onto the d and q axes. The total ux linkage to the a-phase can now be calculated by using superposition and adding the components linking to it from the d and q-axes. Using (C.17) and (C.25) we get: aa (d ) = ad (d ) + aq (d ) = na Fa (Pd cos2 pd + Pq sin2 pd ) = n2 ia (Pd cos2 pd + Pq sin2 pd ) a = n2 ia a [(Pd + Pq ) + (Pd Pq ) cos 2pd ] 2 (C.28)

The rotor self inductance can therefore be calculated as a function of the d-axis position as: aa Laa = = L1 + L2 cos 2pd (C.29) ia where: L1 = N2 (Pd + Pq ) 8 N2 L2 = (Pd Pq ) 8 N total number of turns in sinusoidal winding = 2na

Figure C.4 shows a plot of (C.29). Notice that the inductance varies as a function of cos 2pd with a constant oset as mentioned in conjecture C.3. The self inductances for the other two phases can be found similarly as: Lbb = L1 + L2 cos 2 pd Lcc 2 3 2 = L1 + L2 cos 2 pd + 3 (C.30) (C.31)

Addition Perhaps a remark about the fact that this analysis gives accurate inductance results since only the fundamental components of the ux density distribution link to the sinusoidal winding, as proved in a previous section.

C.1 Calculation of Inductances

C-11

Figure C.4: a phase inductance plot.

C.1.2

Mutual Inductances

In addition to the self inductance of the winding there is also mutual inductance between the a, b, and c-phases. These inductances are also a function of the position of the rotor, since its position clearly changes the reluctance of the ux paths between the windings. The process of calculating the general expressions for these inductances is very similar to that for the self inductances. We shall work out in detail the mutual inductance between two windings and then simply state the relationships between the other windings. Let us consider the mutual inductance between the a-phase and the b-phase. The spatial sequence of the phases is as shown in Figure B.5. The winding conductor density distribution for the b-phase is: nb (p ) = nb sin(p 2 ) 3 (C.32)

Therefore the number of coils with their axes at some angle a with respect to the a-phase (i.e. the winding function) is: ntb () = nb cos(a 2 ) 3 (C.33)

As with the self inductance we shall work out the ux linkage for the d and q axes separately, and then use superposition to calculate the total ux linkage. We can write the expression for the ux linkage for a single turn using the expression (C.10) calculated for the self inductance case: d (a ) = 2Fd Pd cos a (C.34)

C-12

Calculation of Inductances for a Synchronous Reluctance Machine Again we can say: a = a pd allowing us to again write the ux expression as: d (a , pd ) = 2Fd Pd cos(a pd ) (C.36) (C.35)

We can now write the ux expression for the coils that have their axis at a as: d (a , pd ) = 2Fd Pd nb 2 cos(a ) cos(a pd ) 3 (C.37)

Finally we now nd the total linkage of the d -axis ux by integrating over a coil span of the b-phase: dba = 2Fd Pd nb
+

cos(a

2 ) cos(a pd )da 3

(C.38)

After considerable manipulation this expression can be written as: 2 ) dba = Fd Pd nb cos(pd 3 Using (C.26) the expression becomes: 2 dba = Fa Pd nb cos pd cos(pd ) 3 (C.40) (C.39)

Now let us consider the q-axis contribution to the b-phase ux. Using (C.10) we can again write an expression for the q-axis ux linking a single turn centred at the angle aq relative to the q-axis: q (aq ) = 2Fq Pq cos aq (C.41)

The aq angle con be converted to angle relative to the a-phase: a = pd + aq + and therefore: aq = a (pd + Hence q can be written as: q (a , pd ) = 2Fq Pq cos(a pd ) 2 2Fq Pq = sin(a pd ) (C.44) (C.45) 2 ) 2 (C.42)

(C.43)

Now using the winding function we can write: q (a , pd ) = 2Fq Pq nb 2 cos(a ) sin(a pd ) 3 (C.46)

C.1 Calculation of Inductances Integrating over the coil span: qba = 2Fq Pq nb
+

C-13

cos(a

2 ) sin(a pd )da 3

(C.47)

After considerable manipulation we arrive at the expression for the ux linkage from the q-axis to the b-phase: qba = Fq Pq nb cos(pd ) 6 Using (C.27) this expression can be written as: qba = Fa Pq nb sin pd cos(pd ) 6 (C.49) (C.48)

We are now in a position to calculate the total mutual ux linkage to the b-phase from the a-phase as follows: ba = dba + qba 2 ) Pq sin pd cos(pd )] = Fa nb [Pd cos pd cos(pd 3 6 3 1 = Fa nb Pd (1 + cos 2pd ) + sin 2pd + 4 4 3 1 Pq sin 2pd + (1 cos 2pd ) 4 4

(C.50)

After manipulation we get the following expression for this mutual inductance: ba = 2 na nb ia (Pd + Pq ) + (Pd Pq ) cos(2pd ) 2 2 3 (C.51)

For a balanced machine na = nb , therefore the term in front of this expression is n2 ia /2. Therefore this expression is the same as that for the self inductances a and hence we can write the mutual inductance in the same form as that for the self inductances: ba = N 2 ia (Pd + Pq ) 2 + (Pd Pq ) cos(2pd ) 8 2 3 (C.52)

Dividing (C.52) by ia gives the inductance expression: Lba = Lab = L1 + L2 cos 2(pd ) 2 3 (C.53)

where L1 and L2 are as dened in (C.29). By a similar process it can be shown that the other mutual inductances are: Lca = Lac = Lcb = Lbc L1 + L2 cos 2(pd + ) 2 3 L1 = + L2 cos 2pd 2 (C.54) (C.55)

C-14

Calculation of Inductances for a Synchronous Reluctance Machine

C.1.3

Summary

Assuming that the mmf for each phase varies sinusoidally around the machine, and that the resultant mmf in the machine acts on two dierent air gaps for the low and high permeance axes, then the self and mutual inductances of a phase winding vary as follows with pd (the angle of the d-axis with the a-phase). In the above derivations we did not take into account the leakage inductance term in each of the self inductances. If we assume that the leakage does not change with rotor position (which may not be a valid assumption) then the leakage can be included by the addition of the term Ll as shown below: Self Inductances Laa = Ll + L1 + L2 cos 2pd Lbb = Ll + L1 + L2 cos 2 pd 2 (C.56) 3 Lcc = Ll + L1 + L2 cos 2 pd + 2 3 Mutual Inductances Lba = Lab = L1 + L2 cos 2(pd ) 2 3 Lcb = Lbc = L1 + L2 cos 2pd 2 Lca = Lac = L1 + L2 cos 2(pd + ) 2 3 where: L1 = N2 (Pd + Pq ) 8 N2 L2 = (Pd Pq ) 8 N total number of turns in sinusoidal winding = 2na Ll the leakage inductance of each phase (C.57)

Appendix D

Introduction to Instantaneous Imaginary Power

D.1 Introduction

It is dicult to gain a satisfying physical understanding of the concept of instantaneous imaginary power. In this appendix we shall discuss several ways of interpreting instantaneous imaginary power.

D.1.1

Single Phase Reactive Power

Let us begin with single phase power expressions. The diculties in interpreting the instantaneous imaginary power begin with the interpretation of reactive power in sinusoidal steady state systems. We will nd that single phase reactive power is not the same as the instantaneous three phase imaginary power. Consider the following time domain expressions for current and voltage owing into some arbitrary network: v = V cos t i = I cos(t + ) Using the denition of instantaneous power we can write: P = vi = [V cos t][I cos(t + )] V I cos = [1 + cos 2t] V I sin cos t sin t 2 Using the trig relation: cos t sin t = 1 sin 2t 2 VI cos(2t + ) 2
Oscillatory component

(D.1)

(D.2)

we can modify the last term of (D.1) so that the expression becomes: P = V I cos 2
Average Real power

(D.3)

D-2

Introduction to Instantaneous Imaginary Power

Imag
Q = VI sin
r I
P = VI cos

r V

I sin

I cos

Real

Figure D.1: Phasor relationship for complex power. The oscillatory power component represents the power owing into and out of the storage element of the particular circuit.1 The average real power component essentially causes an oset in this oscillation component so that there is an average value of power over a complete cycle. The other way of representing the power expression for sinusoidal steady state systems is in the form of the complex power: S = I V (D.4)

where represents the complex conjugate, and the means that x is a phasor. x Let us assume that: I = Iej V = Vej where I and V represent the current and voltage RMS values. Substituting (D.5) and (D.6) into (D.4) we can write: S = V I cos + j V I sin where = .2 Equation (D.7) is broken up into two components: P = V I cos Q = V I sin One can see the vector relationship of these components in Figure D.1.
1 As we shall later this component consists of two dierent parts, one belonging to the real power and the other to the imaginary power. 2 The angle is the angle from the reference voltage vector to the current vector.

(D.5) (D.6)

(D.7)

(D.8) (D.9)

D.1 Introduction The correspondence between (D.8) and the average real power component of (D.3) is easy to see. However, the correspondence between (D.9) and the oscillatory power part of (6.35) is not immediately obvious. Clearly Q is the component of current that is orthogonal (in a temporal sense) to the voltage, multiplied by that voltage. This correspondence is more easily seen by manipulating (6.32) into the form: P= V I cos V I cos + cos 2t 2 2
Real power component

D-3

V I sin sin 2t 2
Reactive power component

(D.10)

where V and I are the peak values of the voltage and current. We can see from this expression that the real power actually oscillates (with the oscillation being unipolar), and has an average value of (V I/2) cos . The reactive power component on the other hand does not have an oset term and its average value is zero. The amplitude of this term is equal to the Q term in the complex power expression. Remark D.1 The concept of reactive power for single phase systems is based on sinusoidal steady state conditions. The Q value dened in (D.9) is in terms of RMS values of time phasor quantities. If one is to consider instantaneous reactive power then it is the second part of (D.10), which is a sinusoidally varying quantity. Therefore, it is not possible to have a constant value of instantaneous imaginary power in a single phase system, but only a value related to the peak of a sinusoidal waveform. I Remark D.2 Because the reactive power component of (D.10) is a symmetric bipolar waveform its integral represents energy that is following into a circuit in one half of the cycle, and then back out again in the other half. This could be the energy, for example, that is being stored and returned from capacitive or inductive components of the circuit. It can be seen from the expressions derived the value of the reactive power ((V I/2) sin ) is independent of the frequency of the supply. I

D.1.2

Three Phase Instantaneous Imaginary Power

We shall gradually approach the concept of instantaneous imaginary power by rstly considering the sinusoidal steady state power expressions. Let us assume that the phase currents and voltages to the star connected system are:3 va vb vc ia ib ic
3 The

= = = = = =

V cos t V cos(t + 2 ) 3 V cos(t 2 ) 3 I cos(t + ) I cos(t + 2 + ) 3 I cos(t 2 + ) 3

(D.11)

star connection means that there are no zero sequence currents owing.

D-4

Introduction to Instantaneous Imaginary Power These voltages and currents can be multiplied together to give the three phase power expression: P = va ia + vb ib + vc ic 3V I cos V I cos 2 2 = + (cos 2t + cos(2t ) + cos(2t + )) 2 2 3 3 V I sin 2 2 (sin 2t + sin(2t ) + sin(2t + )) (D.12) 2 3 3 Terms two and three in (D.12) are zero because the cosine and sine terms each add to be zero. Therefore the power expression becomes: P = 3V I cos 2 (D.13)

which is simply three times the average power in (D.10) (as one would expect). The question that naturally arises from the above analysis is where do the terms for the instantaneous imaginary power exist in these expressions? Let us consider the last part of (D.12). Rewriting this term one can see that: V I sin 2 2 V I sin sin 2t = sin(2t ) + sin(2t + ) 2 2 3 3 (D.14)

which means that the reactive power in one phase is being absorbed by two other phases. Therefore the reactive power is cycling around between the three phases, and hence is not seen on the external three phase power (although there is obviously still the single phase reactive power there in each of the individual phases). One can understand what is happening here by a change in the representation of the currents and voltages. Let us convert the time domain quantities of (D.11) into space vectors:4 v = |v| ejt i = |i| e
j(t+)

(D.15) (D.16)

The complex power expression can now be written in terms of the space vectors dened above:5 3 S = i v (D.17) 2 Substituting for v and i into (D.17) and simplifying we get: 3 (iv cos + jiv sin ) (D.18) 2 The real power and imaginary power components can readily be seen from (D.18): s= p= 3 |i| |v| cos 2 3 q = |i| |v| sin 2 (D.19) (D.20)

conversion to space vectors is not an obvious step since we are dealing with power system values of current and voltage that may not be associated with an electrical machine with a sinusoidally distributed winding. 5 Note that this space vector denition is dened in this way to conform with the Akagi [29] denition of power.

4 The

D.1 Introduction Remark D.3 The q term in (D.20) is obviously three times the reactive term in (D.10). I Remark D.4 In this derivation of the real and reactive powers we have used space vectors. This has an important implication the concept of the reactive power has been generalised because there is no requirement on space vectors that they represent sinusoidally varying quantities.6 In the phasor representation the vectors (by denition) represent temporal sinusoidal quantities. The non-sinusoidal character of space vectors means that the Q term is a measure of the degree of orthogonality of the current vector with respect to the voltage space vector. It should be noted that in the case of sinusoidal steady state waveforms the space vector representation corresponds to the traditional phasor complex power as derived in (D.8) and (D.9). I Using the space vector representation we can dene all the expressions that appear in [29]. Consider Figure D.2. This gure shows the voltage and current space vectors at a specic instant of time. The current vector can be resolved into a component that lies along the voltage space vector (ip ), and an orthogonal component (iq ). The real power in the system is: p = |v| ip = v ip and the imaginary power is: q = |v| iq = v iq (D.22) (D.21)

D-5

Remark D.5 The denition of q in (D.22) gives one a physical picture of the main components of the imaginary power. As can be seen from this diagram the q value is a measure of the length of the current vector orthogonal to the voltage vector. If the space vector diagram is for an electrical machine (such as an induction machine) then the iq current is essentially the ux producing vector of the machine. The ux vector of the machine would be coincident with iq . The voltage vector is always at /2 rad from this vector if the vectors are rotating in space and its magnitude is related to that of the ux vector i.e. |v| = || = 3 Lm iq where Lm is the magnetising inductance of the ma2 chine. Therefore, in the particular situation of an electrical machine the q value is directly related to the energy storage in the magnetic elds of the machine: q = |v| iq 3 Lm iq iq 2 3 = Lm i2 q 2 1 = 3 Lm i2 q 2 =

(D.23)

The 3 Lm i2 term is the classic energy stored in an inductor term. Therefore, q 2 in the case of an electrical machine the q is related directly to the rate at which
6 It should be noted that we are assuming in this presentation that there are no zero sequence currents owing i.e. ia + ib + ic = 0.

D-6

Introduction to Instantaneous Imaginary Power

- axis

iq v

iq
v
ip

ip

iq
- axis

ip

Figure D.2: Space vector diagram. energy is being transferred between the three phase inductances (since Lm Ls , the self inductance of a phase) In the case of a power electronic system there may not be an identiable inductive or capacitive element that is causing the phase dierence between the voltage and the current. In this case it is a little more dicult to gain a physical understanding of what the imaginary power actually relates to. I Remark D.6 Examination of Figure D.2 shows that i space vector and the phase and orthogonal components of the current vector can be resolved onto the stationary axes. Notice that both i and i can be considered to be composed of two components. For example, i = ip +iq . The ip component is the real power component of the i current, and iq component is the imaginary current component of i . Similar observations can be made for the i current. These same current components were identied in [29]. I As we noted above in the case of an inductive load the Q can be seen to correspond to the energy stored in the elds of the inductors. However, as noted by Akagi [29], one can generate q using just power electronic switches. One immediately asks the question where does the energy go in this case?. If there was an energy storage component in the power electronic system then the energy could be stored there, but in the compensator application described in [29] there is no energy storage element. This dilemma can be explained by considering Figure D.2. Let us assume that the system is being driven by a two phase source (which is equivalent to a three phase source via the three to two phase transformations) From the gure we can write: v i = e (ip + iq ) = e ip
Real power component

e iq
Imaginary power component

(D.24)

D.1 Introduction and similarly for the axis: v i = v (ip + iq ) = v ip

Real power component

D-7

v iq
Imaginary power component

(D.25)

Remark D.7 From (D.24) and (D.25) one can see that each phase is carrying power components that are related to the real power and the imaginary power.I Let us now relate the iq and iq currents to the iq current. Using trigonometry and Figure D.2 we can write: iq = iq cos( + v = |v| cos iq = iq sin( + ) = iq cos 2 v = |v| sin ) = iq sin 2 (D.26) (D.27) (D.28) (D.29)

Therefore the power associated with the current components of iq can be written as: v iq = viq cos sin = v iq = viq cos sin = viq sin 2 2 (D.30) (D.31)

viq sin 2 2

Therefore one can see under all conditions (i.e. steady state and instantaneously) that: v iq + v iq = viq viq sin 2 + sin 2 = 0 2 2 (D.32)

In other words the so-called imaginary power components always cancel. If the iq is being produced by a power electronic device, then the energy associated with this power is simply being transferred from one of the sources to the other via the power electronics. Therefore, the sources themselves are eectively the energy storage device (as compared to the magnetic eld in the machine case). Clearly the above observation means that: P = v i + v i = v ip + v ip (D.33)

Finally we shall consider the q term as dened in ?? and show that it is the same as the expressions dened using the space vector approach pursued above. Rewriting the Akagi denition for convenience: q = v i v i From Figure D.2 we can see that: ip = ip cos ip = ip sin (D.35) (D.36) (D.34)

D-8

Introduction to Instantaneous Imaginary Power and these, together with previous current denitions, allows use to write (D.34) as follows: q = v ip + v iq v ip v iq = (|v| cos )( ip sin ) + (|v| cos )( iq cos ) (|v| sin )( ip cos ) (|v| sin )( iq sin ) = |v| iq (D.37)

Remark D.8 Equation (D.37) is the same as (D.22), validating that the two axis representation of q is equivalent to the space vector representation. I

Appendix E

Introductory Exercise using Saber Simulator

E.1 Introduction

Saber 1 is a software simulation program. Its main attribute is that it allows the simulation of mixed mode systems i.e. one can have continuous time analogue circuitry, digital circuits, continuous and discrete time transfer functions, magnetic systems (such as electrical machines and magnetic actuators), mechanical systems, and hydraulic systems all in the same simulation. This is unusual since most simulation packages cannot readily handle this mix of systems. They tend to be more specialised i.e. only for electronic circuits, only for power systems, digital simulation packages etc. Simulation packages are very useful for the simulation of electronic systems, since the models of electronic components behave nearly the same as the actual component. In some circumstances simulation is almost mandatory, since a poor design can result in immediate catastrophic failure of the real circuit. An example where this is often true is in the area of power electronics. The Saber simulator consists of four major components: SaberSketch: This provides a means to graphically enter a schematic to be simulated. SaberGuide: To some degree this component is hidden, since it provides the connection between SaberSketch and the Saber Simulator. Simulator: This module is the actual simulation engine. It is activated via SaberGuide. SaberScope: This is the back end post-processing section of the Saber system. SaberScope allows the user to process the les produce by the Saber simulator and produce new les of results, but more importantly it allows the user to generate graphs of the results. In this introductory exercise we shall be using the Saber simulator for circuit simulation. The circuit to be simulated is a very simple one, but it is able
1 Saber

is a registered trademark for Avant!

E-2

Introductory Exercise using Saber Simulator

vd

L
vS

vL

vR

Saber ground node

Figure E.1: Simple single phase, half wave rectier, with an LR load. to demonstrate many of the features of the software. In order to minimise the simulation times we shall be using idealised components from the Saber parts library. If one wanted to work out the power dissipation in semiconductor components then the more realistic real component libraries would have to be used, but use of these makes the simulation times considerably longer. The circuit to be simulated is shown in Figure E.1. It is a simple single phase half wave rectier circuit. The only complication is that it has a load that includes inductance.

E.2

Circuit Schematic Capture

The rst step in the circuit simulation process is to capture the circuit schematic. This is achieved by using the SaberSketch section of the Saber suite. Figure E.2 shows the initial screen that appears when SaberSketch is invoked (via the Start menu).2

The sequence of steps to follow to set-up a design are as follows. Create the design: This is achieved by selecting the FileNewDesign pull2 The drawing area is shown in white in this gure. This has been done to prevent toner wastage when this document is printed.

E.2 Circuit Schematic Capture

E-3

{
Zooming controls Grid control Select to draw a line Invoke SaberGuide Parts menu
Figure E.2: Initial screen upon invoking SaberSketch. down menu. If we wanted to open an existing design then one would use OpenDesign, and then navigate to the desired le. Often if SaberSketch starts it will load the last design le automatically. Place parts on the schematic: The next step is to place the desired components on the blank schematic. The is achieved using the Parts Gallery button. When clicked-on this opens up another window which allows one to select the parts folder to be used. The folder that you will use for this exercise is the Analogy Parts Library. If one double-left-clicks on this then the contents of the Available Categories window will change to a selection of component categories. One can select a category, eventually ending up with a listing of individual parts in the Available Parts list scroll window. An example of this window is shown in Figure E.3, which shows the content of the Inductors & Coupling component category. To place a component in the schematic one selects a particular component from the Available Parts window and then click-on Place. The component will then appear in the middle of the schematic window. An alternative is to left-click-on the part and then go the to schematic window and click the middle mouse button (if there is one).3 One can also access the Parts Gallery via using the right mouse button selecting Get PartsParts Gallery, or from the Schematics main menu.
3 Only

works if a mouse driver that recognises the middle mouse button is installed.

E-4

Introductory Exercise using Saber Simulator

Figure E.3: An example of a parts gallery screen. As a specic example, if we want to place a diode on the schematic then one navigates to the Analogy Parts LibraryElectronicSemiconductor DevicesDiodes category. From the Available Parts window select the Diode, Ideal (PWL) component and then press Place. If you look at the schematic you will nd a green diode in the middle of it. The green colour indicates that the component is selected. If a component is selected then it can be dragged around the schematic to position it where one likes by moving the cursor pointer over it (the component then changes to red), pressing the left mouse button, and then dragging to the desired location. Set a parts properties: Once a part is on the schematic then its properties can be set. This is carried out by double-left-clicking on the part (one can also get the properties of the part by right clicking and then selecting the Symbol Properties on the drop-down menu). One can also obtain help on a part by selecting the Help drop-down menu from the properties screen. The Help explains the meaning and range of values for all the properties listed for the part. The properties window contains three columns Property Name, Property Value and a set of round buttons on the right that denote the visibility of the property on the schematic. The latter two of these can be altered by the user. The Property Value elds can contain undef, or *req*. The undef eld usually means means that the value is undened, but the part will execute correctly with some underlying default value. However, in many cases this does not make sense. For example the resistor component has undef for its value, and clearly one would wish to set the value of a resistor in a particular circuit. If an undef value has to be dened the simulator

E.2 Circuit Schematic Capture will let you know when you try to run the simulation. The *req* eld means that there are no default values dened, and it is mandatory to dene a value. The values of the components can be entered in two main number formats. Saber uses a set of multiplier factors which are shown in Table E.1. One can of course use whole numbers, and also scientic notation if desired e.g. 25e-4 for 0.0025. It should be noted that the ref property name contains a unique name for the part on the schematic. Sometimes if a part is copied on the schematic this name is not changed appropriately (this appears to be a bug in the software). Therefore one gets duplicate part references, and consequently the simulation fails. One has to manually change the ref name if this occurs.4 The visibility eld allows one to nominate whether the property value (the visibility button is half on), or the property name and property value (the visibility full on), are to be displayed on the schematic. If the button is o then nothing about that property is displayed on the schematic. In a manner similar to the placement of the diode all the other components are placed on the schematic. The wires that join the components are drawn by moving the cursor over one of the component node points. The cursor will change to a cross-hair and pressing and holding the left mouse button will allow a wire to be drawn. There is a grid that wires and components lie on, which makes drawing the lines very simple. If for some reason the cursor does not change (for examples one is drawing a line not connected to a component, then the wire drawing tool can be selected (see Figure E.2). A wire which does not terminate on a component node can be terminated by double-left-clicking at the point where one wishes to stop the wire. Place a Saber ground node: A schematic must contain a ground reference designator for the simulator to be able to function. This symbol is called Ground (Saber Node 0) in the parts library. This ground symbol can be located in a number of places in the parts library tree. The ground is connected to the point in the schematic from which all the voltages in the design will be measured. Wires: We have already mentioned how to draw wires on the schematic. One can also select a wire and delete it by pressing delete on the keyboard, or right clicking and selecting Delete Wire on the drop-down menu. One can also alter the properties of a wire by right-clicking on the selected wire and selecting Attributes... on the drop-down menu (see Figure E.4 for an example of the Attributes... window). For example, one can change the name of a wire in the Name eld in the window, and then select whether this name should be displayed on the schematic (which is often very handy for documentation reasons).

E-5

4 A part can be copied by selecting the component and then moving the cursor to the place where one wishes to have the duplicate component, and then clicking the middle mouse button.

E-6 Name femto pico nano micro milli kilo mega

Introductory Exercise using Saber Simulator Scientic Notation 1015 1012 109 106 103 103 106 Saber shortcut f p n u m k meg

Table E.1: Number magnitude speciers in Saber Repeat the above steps until the complete circuit shown in Figure E.1 has been drawn. At this point we are now ready to start the simulation phase of the exercise.

E.3

Executing the Transient Analysis

In order to carry out the simulation of a design one now has to invoke the simulator. This is achieved by pressing the SaberGuide button (see Figure E.2). One then gets the screen shown in Figure E.5. Note the new toolbar at the top of the screen. This toolbar allows one to control the Saber simulator from the SaberSketch window. The main tool used in SaberGuide is the DC/Transient button shown in Figure E.5. If one clicks on this button then the window shown in Figure E.6 appears. The parameters circled should be lled out so that the end time and time step of the simulation are set-up, and the simulator will automatically open SaberScope upon the completion of the simulation. One can see that there are a number of other tabs on the window. In more sophisticated simulations some of these may have to be used. The only other one that we shall look at in this simulation is the Input Output tab, which is shown in Figure E.7. The circled quantities have been altered from the default values. These alterations cause to simulator to save all the signals in the design, and all types of variables (across variables (i.e. voltages) and through variables (i.e. currents)). Remark E.1 One can also select specic signals for the simulator to save. This is essential in large simulations otherwise the output les produced by the simulator are huge. The signals can be selected using the Browse Design... selection from the Input OutputSignal ListSelect sub-menu. Note that the simulator has to be running to carry out this function, therefore it is necessary to start a simulation and stop it (using the Stop button), and then reenter this menu to carry out this function. Once all this information has been lled out then one simply clicks OK at the bottom of the window and the simulation will begin. It rstly netlists the design, and if this is successfully completed it will work out the dc starting

E.4 Plotting and Processing Results

E-7

Figure E.4: The wire attributes window. condition, and then nally start the transient analysis. A rotating icon in the top right corner of the Saber window indicates that the simulator is running. When it nishes, which is very fast in the case of this simulation, the simulator will automatically open up SaberScope to allow the results of the simulation to be post-processed.

E.4

Plotting and Processing Results

If SaberScope has not been set to automatically open then it can be opened manually via the ResultsView Plotles in Scope... menu item. If SaberScope opens automatically it loads the plot le just generated by the simulator (because of the setting made in the DC/Transient screen), and then displays the plot le opened in the Signal Manager window, and the signals in this plot le in a second window named after the plot le. The SaberScope opening window is shown in Figure E.8. Notice in the Diode_LR_cct.tr signal window that some of the signals have a + next to them. This means that if one double-left-clicks on them then another more detailed signal list will expand from this root. One can then select one of these signals to plot, and then left-click the Plot button. Figure E.9 shows the inductor component expanded, and the i(m) signal plotted. Remark E.2 From Figure E.9 one can see the advantage of naming signals

E-8

Introductory Exercise using Saber Simulator

DC and transient analysis button

Figure E.5: An example of SaberSketch with the Saber guide toolbar activated. with meaningful names, as opposed to the default names given to the signals by Saber. The default names in the signal list window do not make much sense. When one is scanning through the signal list for complex designs, it is much easier to nd the signals/components of interest if the names make sense. If one wishes to plot a number of variables, then left-click the desired signals holding down the Ctrl key on the keyboard, and then left-click Plot. The selected signals will all be plotted on separate axes. One can also superimpose several plots on the one set of axes. This can be achieved in two dierent ways, dependent on whether one has already plotted the signals on separate axes. If one wishes to plot two signals on the same axis then select one of the signals and plot it, and then select the other, and go the the plot window and press the centre mouse button over the graph upon which one wishes the second signal to be plotted. The other way of plotting two or more signals on the same axis, is to rstly plot the signals on separate axes, and then use the Stack Region feature. This is activate by selecting one of the signals to be stacked on the same axis (this is achieved by placing the mouse cursor over the signal name to the right of the plot the plot will go red, and then left-click), and then right-click and go the drop-down sub-menu Stack Region. At the bottom of this yout one can see a number of Analog signals listed (the number dependent on the number of signals plotted on the graph window), with Analog 0 being the one at the

E.4 Plotting and Processing Results

E-9

Changed fields

Figure E.6: An example dc/transient simulation set-up window. bottom of the graph window. Select the analog signal number that corresponds to the axis that one wishes to plot onto. If one plots a signal and wants to delete it, then select the signal in the graph window, and then right click to get the drop-down menu and select the Delete Signal option.

E.4.1

Manipulating Results

One of the very powerful features of the SaberScope system is its ability to perform calculations on the results of the simulation, and also to take accurate measurements on the waveforms produced. Let us rstly consider the calculation capability. The waveform calculator allows one to subtract, add, multiply, divide, and perform a number of other manipulations on signals. The calculator is activated by pushing the Calcula-

E-10

Introductory Exercise using Saber Simulator

Changed variables

Figure E.7: The input-output table of the dc/transient analysis window.

tor button at the bottom of the screen. The signals that one wishes to carry out the calculations on are selected by left-clicking them in the signal window, and then middle clicking in the area just below the toolbar in the calculator. The signal name should appear in this window and the scrolling window immediately below it. The calculator works using reverse polish notation (like a HP calculator), therefore before selecting an operation we need to select the two signals to operate on. In the example shown in Figure E.10, we have selected the inductor voltage (vl) and current (i), and then selected the multiply function of the calculator (*) i.e. we are working out the instantaneous power ow into the inductor. The result then appears in the top window of the calculator. We can then plot this result by left clicking the small graph icon at the extreme left of the calculator toolbar.

E.4 Plotting and Processing Results

E-11

Figure E.8: The initial SaberScope window. In order to look at a waveform in more detail one can expand the horizontal or vertical axis by simply selecting the axis by left-clicking, and then holding down the button to extend a yellow bar along the region of the axis that one wishes to expand. One can do this more precisely by right-clicking on the axis of interest and then using the drop-down menu to carry out a more precise numerical expansion of the axis (or alternatively go back to the original axis scaling). In addition to expanding the axes using the mouse cursor, one can also zoom in on the waveforms by simply clicking the mouse over the section of the waveform of interest, and then dragging out a square marque over the area. This area will then be zoomed on the plot. All plotted curves have properties that can be altered. This is achieved by selecting the plot of interest, and then right-clicking and selecting Attributes.... The contents of the resultant window are self explanatory. The other major facility that is of use for processing plots is the measurement tool. This is activate by left clicking the Caliper button at the bottom of the SaberScope screen. This tool allows one to measure the precise absolute values of the quantities on the screen, rise time of steps etc. There are too many features to document here, so it is suggested that you have a look at the features, and try them to see what happens.

E.4.2

Fourier Analysis

The Fourier Analysis facility allows one to get frequency response plots for data produced by the simulator. A Fourier Analysis can only be performed after the simulator has run, and therefore falls into the post-processing category. In order to perform a Fourier Analysis one must rstly return to the Saber-

E-12

Introductory Exercise using Saber Simulator

Figure E.9: A signal plotted in SaberScope. Guide window (dont close the SaberScope window, simply iconise it to keep it out of the way). The following steps are carried out to perform a Fourier Analysis on a periodic waveform. a. Select the AnalysesFourierFourier... menu. b. The left window in Figure E.11 will show up. I have lled in some values for this window. The Fundamental Frequency of the output waveforms is known as it was set by the frequency of the sine wave source in the circuit. The 80 millisecond time next to the Period End dialogue indicates that we are to analyse the period of the output ending at 80 milliseconds. Finally the Number of Harmonics stipulates the maximum number of harmonics that that analysis will calculate. c. Another tab in the Fourier window is the Input Output tab. Its contents appear as the right window in Figure E.11. In this case I have set the Signal List to be /... which means all signals, and the Include Signal Types is set to all, meaning that through and across variables are to be included. d. Finally we left click OK or Apply and the Fourier analysis is carried out on the signals selected. Remark E.3 If one is analysing a non-periodic waveform or a pulse then the Fast Fourier Transform option should be used. In order to plot the results of the Fourier analysis go back to SaberScope and via the Signal Manager window open a le dialogue. One should see a new le with a fou.ai_pl extension. Click on this le and click on Open. Another

E.5 A Practice Exercise

E-13

Figure E.10: An example of a waveform calculation in SaberScope. signal list box should open with the signals listed for which frequency data is available. These signals can then be plotted in a fashion similar to the time domain signals.

E.5

A Practice Exercise

In order to test your understanding of the above concepts it is suggested that you carry out the following on the circuit of Figure E.1. I suggest that you dont blindly carry out the simulation, but try and understand what you are seeing in the results. For a simple circuit, it has surprising results, and you might learn something! a. Execute the simulation and plot graphs of vs , vR , vL and i. b. Measure the average and rms load current from the plots. c. Measure the average voltage across the inductor, and try and explain the result. d. Measure the voltage across the diode. What is the maximum reverse voltage it is subject to? e. Plot graphs of the power dissipated in the load and the energy stored in the inductor. Measure the average power dissipation. f. Measure the ac source power, and compare this value with the value dissipated in the load resistor. Why is there a discrepancy?

E-14

Introductory Exercise using Saber Simulator

Figure E.11: Fourier analysis dialogues in Saber. g. Perform a frequency analysis of the rectier output voltage and current. Why is the spectrum of the current dierent from that of the voltage? h. Replace the load resistor with a 300 volt dc source. Plot vS , i and vL . Note that current only ows for part of the half cycle of the voltage supply. Note where the peak current occurs. i. Measure the average and rms values of the load current and voltage. Also measure the average power transferred to the load. Note that the average load power is now the product of the average current and average load voltage. j. Perform a frequency analysis of the load current and voltage, and compare the results with the resistive load case. If the above exercise is carried out successfully then you should have a good preliminary working knowledge of the operation of the Saber simulation system. There are many other aspects of the system that we have not considered you will need to know these for more sophisticated simulations.

Acknowledgment
This tutorial is partially based on a Saber tutorial written by Dr. B.J. Cook of the Department of Electrical and Computer Engineering, University of Newcastle, Australia.

F-2

PV Related Information

Appendix F

PV Related Information
F.1 SunnyBoy Transformerless PV Inverter

SUNNY BOY 3000TL / 4000TL / 5000TL

SB 3000TL-20 / SB 4000TL-20 / SB 5000TL-20

High Yields
Maximum efficiency of 97 % Multi-String technology* Transformerless, with H5 topology Shade management with OptiTrac Global Peak

Safe
Integrated ESS DC switchdisconnector

Simple
Easily accessible connection area Cable connection without tools DC plug system SUNCLIX

Communicative
Bluetooth technology as standard Multilingual graphic display Multi-function relay as standard

SUNNY BOY 3000TL / 4000TL / 5000TL

Perfection Plus. Usability. The transformerless Sunny Boy generation
More communicative, easier to use and more efficient than ever: this Sunny Boy is setting new standards in inverter technology. A modern graphic display, readout of daily values even after sunset, simplified installation concept and wireless communication via Bluetooth: The new Sunny Boys fulfill every wish. With the new OptiTrac Global Peak shade management and an optimal efficiency of 97 %, the inverters ensure optimum solar yield. As transformerless, multi-string devices, the Sunny Boy 4000TL and 5000TL provide maximum flexibility for plant design, and are the first choice for demanding generator designs.

*Sunny Boy 4000TL / 5000TL

F.1 SunnyBoy Transformerless PV Inverter

F-3

Input (DC) Max. DC power (@ cos =1) Max. DC voltage MPP voltage range DC nominal voltage Min. DC voltage / start voltage Max. input current / per string Number of MPP trackers / strings per MPP tracker Output (AC) AC nominal power (@ 230 V, 50 Hz) Max. AC apparent power Nominal AC voltage; range

3200 W 550 V 188 V 440 V 400 V 125 V / 150 V 17 A / 17 A 1/2 3000 W 3000 VA 220, 230, 240 V; 180 280 V 50, 60 Hz; 5 Hz 16 A 1 1/1

4200 W 550 V 175 V 440 V 400 V 125 V / 150 V 2 x 15 A / 15 A 2 / A: 2, B: 2 4000 W 4000 VA 220, 230, 240 V; 180 280 V 50, 60 Hz; 5 Hz 22 A 1 1/1

4200 W 550 V 175 V 440 V 400 V 125 V / 150 V 2 x 15 A / 15 A 2 / A: 2, B: 2 3680 W 4000 VA 220, 230, 240 V; 180 280 V 50, 60 Hz; 5 Hz 22 A 1 1/1

5300 W 550 V 175 V 440 V 400 V 125 V / 150 V 2 x 15 A / 15 A 2 / A: 2, B: 2 4600 W 5000 VA 220, 230, 240 V; 180 280 V 50, 60 Hz; 5 Hz 22 A 1 1/1

AC grid frequency; range Max. output current Power factor (cos ) Phase conductors / connection phases Eciency Max. eciency / Euro-eta 97.0 % / 96.3 % 97.0 % / 96.4 % 97.0 % / 96.4 % 97.0 % / 96.5 % Protection devices DC reverse-polarity protection ESS switch-disconnector AC short circuit protection Ground fault monitoring Grid monitoring (SMA Grid Guard) Galvanically isolated / / / / / all-pole sensitive fault current monitoring unit Protection class / overvoltage category I / III I / III I / III I / III General data Dimensions (W / H / D) in mm 470 / 445 / 180 470 / 445 / 180 470 / 445 / 180 470 / 445 / 180 Weight 22 kg 25 kg 25 kg 25 kg Operating temperature range 25 C +60 C 25 C +60 C 25 C +60 C 25 C +60 C Noise emission (typical) 25 dB(A) 29 dB(A) 29 dB(A) 29 dB(A) Internal consumption: (night) < 0.5 W < 0.5 W < 0.5 W < 0.5 W Topology transformerless transformerless transformerless transformerless Cooling concept Convection OptiCool OptiCool OptiCool Electronics protection rating / connection area IP65 / IP54 IP65 / IP54 IP65 / IP54 IP65 / IP54 (as per IEC 60529) Climatic category (per IEC 60721-3-4) 4K4H 4K4H 4K4H 4K4H Features DC connection: SUNCLIX AC connection: screw terminal / plug connector / // // // // spring-type terminal Display: text line / graphic / / / / Interfaces: RS485 / Bluetooth / / / / Warranty: 5 / 10 / 15 / 20 / 25 years //// //// //// //// Certificates and permits (more available on request) CE, VDE 0126-1-1, DK 5940, RD 1663, G83/1-1, PPC, AS4777, EN 50438*, C10/C11, PPDS * Does not apply to all national deviations of EN 50438 Standard features Optional features not available Data at nominal conditions Type designation SB 3000TL-20 SB 4000TL-20 SB 4000TL-20/V 0159 SB 5000TL-20

Accessories
RS485 interface DM-485CB-10

www.SMA-Solar.com

SMA Solar Technology AG

SB5000TL-DEN102030 SMA and Grid Guard are registered trademarks of SMA Solar Technology AG. Bluetooth is a registered trademark owned by Bluetooth SIG, Inc. SUNCLIX is a registered trademark owned by PHOENIX CONTACT GmbH & Co. KG. Text and illustrations reflect the current state of the technology at the time of publication. Technical modifications reserved. No liability for printing errors. Printed on chlorine-free paper.

Technical data

Sunny Boy 3000TL

Sunny Boy 4000TL

Sunny Boy 4000TL/V

Sunny Boy 5000TL

F-4

PV Related Information

F.2

Tianwei PV Array Datasheet

F.2 Tianwei PV Array Datasheet

F-5

F-6

PV Related Information

F.3

Australian Standards for PV Inverter Connections

AS4777.2-2005: Grid connection of energy systems via inverters Part 2: Inverter Requirements

F.3.1

AS 4777.22005

CONTENTS
Page SCOPE........................................................................................................................ 4 NORMATIVE REFERENCES ................................................................................... 4 DEFINITIONS............................................................................................................ 5 INVERTER REQUIREMENTS.................................................................................. 5

1 2 3 4

APPENDICES A POWER FACTOR TEST ............................................................................................ 9 B HARMONIC CURRENT LIMIT TEST .................................................................... 10 C TRANSIENT VOLTAGE LIMIT TEST.................................................................... 12

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F.3 Australian Standards for PV Inverter Connections

F-7

AS 4777.22005

STANDARDS AUSTRALIA Australian Standard Grid connection of energy systems via inverters Part 2: Inverter requirements
1 SCOPE This Standard specifies the requirements for inverters, with ratings up to 10 kVA for singlephase units or up to 30 kVA for three-phase units, for the injection of electric power through an electrical installation to the electricity distribution network.
NOTES: 1 2 Although this Standard does not apply to larger systems, similar principles can be used for the design of such systems. Although this Standard is written on the basis that the renewable energy is from a d.c. source (e.g. photovoltaic array), this Standard may be used for systems where the energy is from a variable a.c. source (e.g. wind turbine or micro-hydro system) by appropriate changes to the tests. This Standard does not include EMC requirements. These are mandated by the Australian Communications Authority (ACA). Users attention is drawn to Australian Communication Authoritys document Electromagnetic CompatibilityInformation for suppliers of electrical and electronic products in Australia and New Zealand for guidance.

2 NORMATIVE REFERENCES The following normative documents contain provisions which, through reference in this text, constitute provisions of this Standard. AS 4777 4777.3 60038 AS/NZS 3100 60950 60950.1 Grid connection of energy systems via inverters Part 3: Grid protection requirements Standard voltages Approval and test specificationGeneral requirements for electrical equipment Information technology equipmentSafety Part 1: General requirements

Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

61000 Electromagnetic compatibility (EMC) 61000.3.3 Part 3.3: LimitsLimitation of voltage fluctuations and flicker in public low-voltage supply systems, for equipment with rated current less than or equal to 16 A per phase and not subject to conditional connection 61000.3.5 Part 3.5: LimitsLimitation of voltage fluctuations and flicker in low-voltage power supply systems for equipment with rated current greater than 16 A IEC 60255 60255-5 Electrical relays Part 5: Insulation coordination for measuring equipmentRequirements and tests

relays

and

protection

Standards Australia

www.standards.com.au

F-8

PV Related Information

AS 4777.22005

ACA

Electromagnetic CompatibilityInformation for suppliers of electrical and electronic products in Australia and New Zealand

3 DEFINITIONS For the purpose of this Standard, the following definitions apply. 3.1 Electricity distribution network The portion of an electrical system that is operated by an electrical distributor. 3.2 Grid An alternative term for an electricity distribution network. 3.3 Grid protection device A device complying with the requirements of AS 4777.3. 3.4 Inverter A device that uses semiconductor devices to transfer power between a d.c. source or load and an a.c. source or load.
NOTE: This Standard is written on the basis that the renewable energy is from a d.c. source (e.g. photovoltaic array), but the energy may be from a variable a.c. source (e.g. wind turbine or micro-hydro system) and hence, for the purposes of this Standard, a.c. to a.c. converters that use semiconductor devices are considered to be inverters, as the requirements in this Standard are applicable to such systems.

3.5 Inverter energy system A system comprising one or more inverters together with one or more energy sources (which may include batteries for energy storage), controls and one or more grid protection devices. 3.6 Islanding Any situation where the electrical supply from an electricity distribution network is disrupted and one or more inverters maintains any form of electrical supply, be it stable or not, to any section of that electricity distribution network. 3.7 Nominal grid voltage The definitions of AS 60038 shall apply.
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3.8 Ripple control A means of one-way communication based on transmitting electrical signals over an electricity distribution network. 3.9 Uninterruptible power supply (UPS) system A power system comprising inverters, switches, control circuitry and a means of energy storage (e.g. batteries) for maintaining continuity of electrical supply to a load in the case of a disruption of power supply from an electricity distribution network. 4 INVERTER REQUIREMENTS 4.1 General The inverter shall comply with the appropriate electrical safety requirements of AS/NZS 3100.
NOTE: AS/NZS 3100 allows that if an individual Standard dealing with specific features of the design, construction and testing of any particular class or type of equipment is issued, it supersedes the general requirements of AS/NZS 3100 that are specifically dealt with in that individual Standard.
www.standards.com.au Standards Australia

F.3 Australian Standards for PV Inverter Connections

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AS 4777.22005

4.2 Compatibility with electrical installation The inverter shall have a.c voltage and frequency ratings compatible with AS 60038.
NOTE: The nominal voltage at the point of supply is 230 V a.c. single phase line-to-neutral and 400 V a.c. three phase line-to-line with a tolerance of +10% -6% and a frequency of 50 Hz.

4.3 Power flow direction Power flow between the energy source and the grid may be in either direction. 4.4 Power factor The power factor of the inverter, considered as a load from the perspective of the grid, shall be in the range from 0.8 leading to 0.95 lagging for all output from 20% to 100% of rated output. These limits shall not apply if the inverter is approved by the relevant electricity distributor to control power factor outside this range for the purpose of providing voltage support. Compliance shall be determined by type testing in accordance with the power factor test described in Appendix A.
NOTE: Lagging power factor is defined to be when reactive power flows from the grid to the inverter; that is, when the inverter acts as an inductive load from the perspective of the grid.

4.5 Harmonic currents The harmonic currents of the inverter shall not exceed the limits specified in Tables 1 and 2 and the total harmonic distortion (THD) (to the 50th harmonic) shall be less than 5%. Compliance shall be determined by type testing in accordance with the harmonic current limit test specified in Appendix B.
NOTE: The inverter should not significantly radiate or sink frequencies used for ripple control by the local electrical distributor. The distributor should be consulted to determine which frequencies are used.

TABLE 1 ODD HARMONIC CURRENT LIMITS

Odd harmonic order number 3, 5, 7 and 9 11, 13 and 15 17, 19 and 21
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Limit for each individual odd harmonic based on percentage of fundamental 4% 2% 1.5% 0.6%

23, 25, 27, 29, 31 and 33

TABLE 2 EVEN HARMONIC CURRENT LIMITS

Even harmonic order number 2, 4, 6 and 8 10 32 Limit for each individual even harmonic based on percentage of fundamental 1% 0.5%

NOTE: The harmonic limits in Tables 1 and 2 are based on those in IEEE 929-2000 IEEE Recommended Practice for Utility Interface of Photovoltaic (PV) Systems.

Standards Australia

www.standards.com.au

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PV Related Information

AS 4777.22005

4.6 Voltage fluctuations and flicker The inverter shall conform to the voltage fluctuation and flicker limits as per AS/NZS 61000.3.3 for equipment rated less than or equal to 16 A per phase and AS/NZS 61000.3.5 for equipment rated greater than 16 A per phase. Compliance shall be determined by type testing in accordance with the appropriate Standard. 4.7 Impulse protection The inverter shall withstand a standard lightning impulse of 0.5 J, 5 kV with a 1.2/50 waveform. Compliance shall be determined by type testing in accordance with the impulse voltage withstand test of IEC 60255-5. 4.8 Transient voltage limits When type tested in accordance with the transient voltage limit test described in Appendix C, the voltage-duration curve derived from measurements taken at the a.c. terminals of the inverter shall not exceed the limits listed in Table 3.
NOTE: The voltage-duration limits listed in Table 3 are graphically illustrated in Figure 1.

TABLE 3 TRANSIENT VOLTAGE LIMITS

Duration Seconds 0.000 2 0.000 6 0.002 0.006 0.02 0.06 0.2 0.6 Volts 910 710 580 470 420 390 390 390 Instantaneous voltage Line-to-neutral Line-to-line Volts 1 580 1 240 1 010 810 720 670 670 670

4.9 Direct current injection

Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

In the case of a single-phase inverter, the d.c. output current of the inverter at the a.c. terminals shall not exceed 0.5% of its rated output current or 5 mA, whichever is the greater. In the case of a three-phase inverter, the d.c. output current of the inverter at the a.c. terminals, measured between any two phases or between any phase and neutral, shall not exceed 0.5% of its rated per-phase output current or 5 mA, whichever is the greater. If the inverter does not incorporate a mains frequency isolating transformer, it shall be type tested to ensure the d.c. output current at the a.c. terminals of the inverter is below the above limits at all power levels.

www.standards.com.au

Standards Australia

F.3 Australian Standards for PV Inverter Connections

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AS 4777.22005

FIGURE 1 VOLTAGE-DURATION CURVE OF TRANSIENT VOLTAGE LIMITS

4.10 Data logging and communications devices Any electronic data logging or communications equipment incorporated in the inverter should comply with the appropriate requirements of AS/NZS 60950.1. Particular attention is drawn to requirements for electrical insulation and creepage and clearance distances.

Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

Standards Australia

www.standards.com.au

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PV Related Information

AS 4777.22005

APPENDIX A

POWER FACTOR TEST

(Normative) A1 TEST SPECIFICATIONS The power factor test shall be carried out as follows: (a) (b) (c) (d) The inverter shall be connected into a test circuit similar to that shown in Figure A1. The grid voltage shall equal the nominal voltage to within 5%. The d.c. supply shall be varied until the a.c. output of the inverter, measured in volt-amperes, equals (20 5)% of its rated output. The power factor of the inverter output shall be measured. Steps (b) and (c) shall be repeated with the inverter operating at (30 5)%, (40 5)%, (50 5)%, (60 5)%, (70 5)%, (80 5)%, (90 5)% and (100 5)% of its rated output, measured in volt-amperes.

When subjected to the test described above, the power factor shall comply with the limits specified in Clause 4.4.

NOTE: This test circuit applies to a single-phase system. To test a three-phase system, an equivalent threephase circuit is required.

FIGURE A1 CIRCUIT FOR POWER FACTOR TEST

Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

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Standards Australia

F.3 Australian Standards for PV Inverter Connections

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AS 4777.22005

10

APPENDIX B

HARMONIC CURRENT LIMIT TEST

(Normative) B1 TEST SPECIFICATIONS The harmonic current limit test shall be carried out as follows: (a) (b) (c) The inverter shall be connected into a test circuit similar to that shown in Figure B1. The d.c. supply shall be varied until the a.c. output of the inverter, measured in volt-amperes, lies in the range (100 5)% of its rated output. The harmonic current content of the inverter output shall be measured.

NOTE: This test circuit applies to a single-phase system. To test a three-phase system, an equivalent threephase circuit is required.

FIGURE B1 CIRCUIT FOR HARMONIC CURRENT LIMIT TEST OF A SINGLE-PHASE SYSTEM.

B2 HARMONIC CURRENT LIMITS When the inverter is subjected to the test described in Clause B1 above, the harmonic currents of the inverter shall not exceed the limits specified in Table 1 and Table 2. B3 SUPPLY SOURCE DURING HARMONIC TESTS
Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

While the harmonic current measurements are being made, the test voltage at the a.c. terminals of the inverter shall meet the following requirements: (a) (b) (c) (d) The test voltage shall be maintained at the nominal voltage 5% at the discretion of the testing authority. The test frequency shall be maintained at (50 1)Hz. In the case of a three-phase supply, the angle between the fundamental voltages of each pair of phases shall be maintained at (120 1.5). The harmonic ratios of the test voltage shall not exceed the limits listed in Table B1.

Standards Australia

www.standards.com.au

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PV Related Information

11

AS 4777.22005

TABLE B1 HARMONIC LIMITS OF TEST VOLTAGE

Harmonic order number 3 5 7 9 even harmonics 210 11 50 Total harmonic distortion (to the 50th harmonic) Limit based on percentage of fundamental 0.9% 0.4% 0.3% 0.2% 0.2% 0.1% 5%

Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

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Standards Australia

F.3 Australian Standards for PV Inverter Connections

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AS 4777.22005

12

APPENDIX C

TRANSIENT VOLTAGE LIMIT TEST

(Normative) C1 GENERAL To prevent damage to electrical equipment connected to the same circuit as the inverter, disconnection of the inverter from the electricity distribution network shall not result in transient overvoltages beyond the limits specified in Table 3. C2 TEST SPECIFICATIONS The transient voltage limit test shall be carried out as follows: (a) (b) (c) (d) (e) The inverter shall be placed in a test circuit similar to that shown in Figure C1. The voltage at the a.c. terminals of the inverter before the switch is opened, shall be maintained at the nominal voltage 5% at the discretion of the testing authority. The d.c. supply shall be varied until the a.c. output of the inverter, measured in voltamperes, equals (10 5)% of its rated output. The switch S shall be opened. The voltage across the a.c. terminals of the inverter shall be recorded at a sample frequency of at least 10 kHz. If the inverter has multiple sets of a.c. terminals, only the a.c. terminals used to connect the inverter to the test circuit (grid connection) shall be monitored. Steps (b) to (e) shall be repeated with the inverter operating at (50 5)% and (100 5)% of its rated output, measured in volt-amperes.

(f)

Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

C = 100F R = 560 k

NOTE: This test circuit applies to a single-phase system. To test a three-phase system, an equivalent threephase circuit is required.

FIGURE C1 CIRCUIT FOR TRANSIENT VOLTAGE LIMIT TEST

Standards Australia

www.standards.com.au

F-16

PV Related Information

13

AS 4777.22005

C3 TRANSIENT VOLTAGE LIMITS When subjected to the test described in Clause C2, the voltage-duration curve derived from the sampled a.c. voltage at the inverter terminals shall not exceed the limits specified in Table 3.
NOTE: A voltage-duration curve is calculated using the sampled instantaneous voltage over the complete trip time of the inverter. For each voltage (maximum voltage step 10 V), the number of samples greater than that voltage are counted. This number is then multiplied by the sample interval to derive a duration for that voltage. The voltage-duration curve is the locus of all points derived from this process. The inverter is deemed to comply with the transient voltage limit test if the derived voltage-duration curve lies beneath the appropriate curve of Figure 1 at all points.

Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

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Standards Australia

F.3 Australian Standards for PV Inverter Connections

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F.3.2

AS4777.3-2005 Grid connection of energy systems via inverters Part 3: Grid protection requirements

AS 4777.32005

CONTENTS
Page SCOPE........................................................................................................................ 4 NORMATIVE REFERENCES ................................................................................... 4 DEFINITIONS............................................................................................................ 5 GENERAL AND SAFETY REQUIREMENTS.......................................................... 6 GRID PROTECTION REQUIREMENTS .................................................................. 6

1 2 3 4 5

APPENDICES A LIMITS FOR SUSTAINED OPERATION.................................................................. 9 B GRID PROTECTION DEVICE TESTS .................................................................... 10

Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

F-18

PV Related Information

AS 4777.32005

STANDARDS AUSTRALIA Australian Standard Grid connection of energy systems via inverters Part 3: Grid protection requirements
1 SCOPE This Standard specifies the requirements for grid protection devices intended to be used in inverter energy systems, with ratings up to 10 kVA for single-phase units, or up to 30 kVA for three-phase units, and for the injection of electric power through an electrical installation to the electricity distribution network.
NOTES: 1 2 3 Although this Standard does not apply to larger systems, similar principles can be used for the grid protection of such systems. These devices do not replace devices used for protection and/or isolation as required in AS/NZS 3000. Although this Standard is written on the basis that the renewable energy is from a d.c. source (e.g. photovoltaic array), this Standard may be used for systems where the energy is from a variable a.c. source (e.g. wind turbine or micro-hydro system) by appropriate changes to the tests. This Standard does not include EMC requirements. These requirements are mandated by the Australian Communications Authority (ACA). Users attention is drawn to Australian Communications Authoritys document Electromagnetic CompatibilityInformation for suppliers of electrical and electronic products in Australia and New Zealand for guidance.

2 NORMATIVE REFERENCES The following normative documents contain provisions which, through reference in this text, constitute provisions of this Standard. AS 60038
Accessed by UNIVERSITY OF NEWCASTLE on 21 Apr 2011

Standard voltages Electrical Installations (known as the Australian/New Zealand Wiring Rules) Approval and equipment test specificationGeneral requirements for electrical

AS/NZS 3000 3100 60950 60950.1 61000 61000.3.3

Information technology equipmentSafety Part 1: General requirements Electromagnetic compatibility (EMC) Part 3.3: LimitsLimitation of voltage fluctuations and flicker in public low-voltage supply systems, for equipment with rated current less than or equal to 16 A per phase and not subject to conditional connection Part 3.5: LimitsLimitation of voltage fluctuations and flicker in lowvoltage power supply systems for equipment with rated current greater than 16 A

61000.3.5

Standards Australia

www.standards.com.au

F.3 Australian Standards for PV Inverter Connections

F-19

AS 4777.32005

IEC 60255 60255-5 ACA

Electrical relays Part 5: Insulation coordination for measuring relays and protection equipmentRequirements and tests Electromagnetic CompatibilityInformation for suppliers of electrical and electronic products in Australia and New Zealand

3 DEFINITIONS For the purpose of this Standard, the following definitions apply. 3.1 Active anti-islanding protection A method of preventing islanding by actively varying the output of the inverter energy system. 3.2 Electricity distribution network The portion of an electrical system that is operated by an electrical distributor. 3.3 Grid An alternative term for an electricity distribution network. 3.4 Inverter A device that uses semiconductor devices to transfer power between a d.c. source or load and an a.c. source or load.
NOTE: This Standard is written on the basis that the renewable energy is from a d.c. source (e.g. photovoltaic array), but the energy may be from a variable a.c. source (e.g. wind turbine or micro-hydro system) and hence, for the purposes of this Standard, a.c. to a.c. converters that use semiconductor devices are also considered to be inverters, as the requirements in this Standard are applicable to such systems.

3.5 Inverter energy system A system comprising one or more inverters together with one or more energy sources (which may include batteries for energy storage), controls and one or more grid protection devices. 3.6 Islanding Any situation where the electrical supply from an electricity distribution network is disrupted and one or more inverters maintains any form of electrical supply, be it stable or not, to any section of that electricity distribution network. 3.7 Nominal grid voltage The definition of AS 60038 shall apply. 3.8 Passive anti-islanding protection A method of preventing islanding based on monitoring the electricity distribution network. 3.9 Electromechanical switch An electrical switch in which the OFF state results in the physical separation of conductors (e.g. a mechanical relay). This DOES NOT include transistors or similar semiconductor devices. 3.10 Uninterruptible power supply (UPS) system A power system comprising inverters, switches, control circuitry and a means of energy storage (e.g. batteries) for maintaining continuity of electrical supply to a load in the case of a disruption of power supply from an electricity distribution network.
www.standards.com.au Standards Australia

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PV Related Information

AS 4777.32005

4 GENERAL AND SAFETY REQUIREMENTS 4.1 General Grid protection of the inverter energy system shall be provided by a grid protection device. This does not preclude the grid protection device being integral to the inverter, nor a single grid protection device being used to protect an inverter energy system comprising multiple inverters. Compliance with this Standard shall be determined by type testing the grid protection device on its own and, if necessary, in combination with an inverter. Compliance of this combination shall be conditional on their being used together in the same manner in which they have been type tested. Compliance of one combination of inverter and grid protection device does not preclude compliance of either device as part of a different combination. 4.2 Electrical safety The grid protection device shall comply with appropriate electrical safety requirements of AS/NZS 3100.
NOTE: AS/NZS 3100 allows that if an individual Standard dealing with specific features of the design, construction and testing of any particular class or type of equipment is issued, it shall supersede the general requirements of AS/NZS 3100 that are specifically dealt with in that individual Standard.

4.3 Connection to low-voltage distribution network The grid protection device shall be compatible with the low-voltage distribution network.
NOTE: The nominal voltage is 230 V a.c. single phase line-to-neutral and 400 V a.c. three phase line-to-line with a tolerance of +10% -6% at a frequency of 50 Hz.

4.4 Voltage flicker The grid protection device shall conform to the voltage flicker limits specified in AS/NZS 61000.3.3 for equipment rated less than or equal to 16 A (a.c. current) or AS/NZS 61000.3.5 for equipment rated at greater than 16A (a.c. current). Compliance shall be determined by type testing in accordance with the appropriate Standard. 4.5 Impulse protection The grid protection device shall withstand a standard lightning impulse of 0.5 J, 5 kV with a 1.2/50 waveform. Compliance shall be determined by type testing in accordance with the impulse voltage withstand test of IEC 60255-5. 4.6 Data logging and communications devices
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Any electronic data logging or communications equipment incorporated in the inverter should comply with the appropriate requirements of AS/NZS 60950.1. Particular attention is drawn to requirements for electrical insulation and creepage and clearance distances. 5 GRID PROTECTION REQUIREMENTS 5.1 General The grid protection device shall operate (a) (b) (c) if supply from the grid is disrupted; or when the grid goes outside preset parameters (e.g. under/over voltage, under/over frequency); or to prevent islanding.

Specific requirements are contained in Clauses 5.2 to 5.5.

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5.2 Disconnection device The grid protection device shall incorporate a disconnection device which shall prevent power (both a.c. and d.c.) from the inverter energy system entering the grid when the disconnection device operates.
NOTE: The disconnection device need not disconnect sensing circuits.

The disconnection device shall incorporate an electromechanical switch if (a) (b) there is no galvanic isolation between the energy source(s) and the grid; or the inverter system continues to provide electrical power to any portion of the electrical installation (i.e. it operates as an uninterruptible power supply (UPS) system) in the event of the disruption of the grid supply.
Galvanic isolation can be achieved by using either a two winding high-frequency transformer or a two winding mains frequency transformer. Galvanic isolation is not required on sensing circuits.

NOTES: 1 2

Any disconnection device intended for use with a UPS system shall only break the active conductor(s). The disconnection device may incorporate semiconductor devices if galvanic isolation exists between the energy source(s) and the grid and the system does not operate as an uninterruptible power supply system. 5.3 Voltage and frequency limits (passive anti-islanding protection) The grid protection device shall incorporate passive anti-island protection in the form of under- and over-voltage and under- and over-frequency protection. If the voltage goes outside the range V min to V max or its frequency goes outside the range fmin to f max , the disconnection device (see Clause 5.2) shall operate within 2 s, where (a) (b) (c) (d)
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V min shall lie in the range 200-230 V for a single-phase system or 350-400 V for a three-phase system; V max shall lie in the range 230-270 V for a single-phase system or 400-470 V for a three-phase system; f min shall lie in the range 45-50 Hz; and f max shall lie in the range 50-55 Hz.

The limits V max , V min , f max and f min may be either preset or programmable. The values V max , V min , f max and f min may be negotiated with the relevant electricity distributor. The settings of the grid protection device shall not exceed the capability of the inverter. 5.4 Limits for sustained operation The introduction of limits for sustained operation is under consideration.
NOTE: See Appendix A for further information about the proposal.

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5.5 Active anti-islanding protection The grid protection device shall incorporate at least one method of active anti-islanding protection. Examples of such methods include shifting the frequency of the inverter away from nominal conditions in the absence of a reference frequency (frequency shift), allowing the frequency of the inverter to be inherently unstable in the absence of a reference frequency (frequency instability), periodically varying the output power of the inverter (power variation) and monitoring for sudden changes in the impedance of the grid by periodically injecting a current pulse (current injection).
NOTE: Active anti-islanding protection is required in addition to the passive anti-islanding protection described in Clause 5.3 above to prevent the situation where islanding may occur because multiple inverters provide a frequency and voltage reference for one another.

The active anti-islanding protection system shall operate the disconnection device (see Clause 5.2) within 2 s of disruption to the power supply from the grid. 5.6 Reconnection procedure Only after all the following conditions have been met shall the disconnection device operate to reconnect the inverter to the electricity distribution network (a) (b) (c) the voltage of the electricity distribution network has been maintained within the range V min V max for at least 1 m, where V min and V max are as defined in Clause 5.3; and the frequency of the electricity distribution network has been maintained within the range f min f max for at least 1 m, where f min and f max are as defined in Clause 5.3; and the inverter energy system and the electricity distribution network are synchronized and in-phase with each other.

5.7 Security of protection settings The internal settings of the grid protection device shall be secured against inadvertent or unauthorized tampering. Changes to the internal settings shall require use of a tool and special instructions not provided to unauthorized personnel.
NOTE: Special interface devices and passwords are regarded as tools.

5.8 Compliance with grid protection requirements Compliance with the anti-islanding protection requirements shall be determined by type testing in accordance with the anti-islanding protection tests described in Appendix B.

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APPENDIX A

LIMITS FOR SUSTAINED OPERATION

(Informative) It is considered that equipment intended for operation at nominal voltages of 230 V (singlephase) or 400 V (three-phase) can endure operation near 200 V and 270 V (single-phase) and 350 V and 470 V (three-phase) but this equipment should not be expected to operate for extended periods at these extreme voltages. Consideration is being given to introducing graded trip requirements whereby operation at, or near, extreme voltages is permitted for limited periods with the permitted duration reducing as the operating voltage nears the limit. Thus if the grid voltage moves towards a limit value (per Clause 5.3), disconnection could be required if the voltage stays near the limit for an extended duration (even if it never passes the limit). Users of this Standard are requested to consider this Proposal and Committee EL-042, Renewable Energy Power Systems and Equipment would welcome comments on this proposal. Comments should be forwarded to Projects Manager Committee EL-042 Standards Australia GPO Box 5420 SYDNEY NSW 2001 or by e-mail to mail@standards.org.au with the first line stating: For Projects Manager EL-042

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APPENDIX B

GRID PROTECTION DEVICE TESTS

(Normative) B1 GENERAL To protect the electricity distribution network from islanding, the inverter shall disconnect from the electricity distribution network whenever the supply from the electricity distribution network is disrupted. Anti-islanding protection shall be assessed by means of the following tests. B2 UNDER-AND OVER-VOLTAGE TRIP SETTINGS AND RECONNECTION TEST B2.1 Tests The under- and over-voltage trip settings and reconnection test shall be carried out as follows: (a) (b) (c) The inverter and grid protection device shall be connected into a test circuit similar to that shown in Figure B1. The under-voltage trip setting of the grid protection device shall be set to its minimum value, or 200 V, whichever is the greater. The variable a.c. supply shall be set so that the voltage at the a.c terminals of the device under test equals the nominal grid voltage and its frequency equals (50 0.2) Hz, and the input supply shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 5)% of its rated output or 1 kVA, whichever is the lesser. The variable a.c. supply shall be slowly adjusted to decrease the voltage at the a.c. terminals of the device under test until the device under test disconnects from the variable a.c. supply. The a.c. voltage at which disconnection occurs shall be recorded. The variable a.c. supply shall be adjusted to return the voltage at the a.c. terminals of the device under test to the nominal grid voltage. The time taken for the device under test to reconnect to the variable a.c. supply shall be recorded. The output voltage of the variable a.c. supply shall be set to a voltage equal to the under-voltage trip setting, as recorded at step (d), plus 2 V. The voltage shall then be decreased as rapidly as possible but at a rate less than any dV/dt protection incorporated in the device under test. The time interval between the voltage passing through the voltage measured at step (d) and the device under test disconnecting from the variable a.c. supply shall be recorded. The over-voltage trip setting of the grid protection device shall be set to its maximum value, or 270 V, whichever is the lesser. The conditions of step (c) shall be re-established. The voltage of the variable a.c. supply shall be adjusted slowly to increase the voltage at the a.c. terminals of the device under test until the device under test disconnects from the variable a.c. supply. The a.c. voltage at which disconnection occurs shall be recorded. Step (e) shall be repeated.

(d)

(e)

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(f)

(g) (h) (i)

(j)

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(k)

The output voltage of the variable a.c. supply shall be set to a voltage equal to the over-voltage trip setting, as recorded at step (i), less 2 V. The voltage shall then be increased as rapidly as possible but at a rate less than any dV/dt protection incorporated in the device under test. The time interval between the voltage passing through the voltage measured at step (i) and the device under test disconnecting from the variable a.c. supply shall be recorded.

B2.2 Criteria for acceptance When subjected to the tests described in Paragraph B2.1, the voltage recorded at step (d) shall equal the under-voltage set point 5 V, the voltage recorded at step (i) shall equal the over-voltage set point 5 V, the disconnection times recorded at steps (f) and (k) shall each be less than or equal to 2 s and the reconnection times recorded at steps (e) and (j) shall each be 1 min or greater.

NOTE: The above test circuit applies to a single-phase system. To test a three-phase system, an equivalent three-phase circuit is required.

FIGURE B1 TEST CIRCUIT FOR UNDER- AND OVER-VOLTAGE AND UNDER- AND OVER-FREQUENCY TRIP SETTINGS AND RECONNECTION TESTS

B3 UNDER- AND OVER-FREQUENCY TRIP SETTINGS AND RECONNECTION TEST B3.1 Tests
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The under- and over-frequency trip settings and reconnection test shall be carried out as follows: (a) (b) (c) The inverter and grid protection device shall be connected into a test circuit similar to that shown in Figure B1. The under-frequency trip setting of the grid protection device shall be set to its minimum value, or 45 Hz, whichever is the greater. The variable a.c. supply shall be set so that the voltage at the a.c terminals of the device under test equals the nominal grid voltage and its frequency equals (50 0.2) Hz, and the input supply shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 5)% of its rated output power or 1 kVA, whichever is the lesser. The frequency of the variable a.c. supply shall be adjusted slowly to decrease the frequency at the a.c. terminals of the device under test until the device under test disconnects from the variable a.c. supply. The frequency at which disconnection occurs shall be recorded.
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(e)

The frequency of the variable a.c. supply shall be adjusted to return the frequency at the a.c. terminals of the device under test to (50 0.2) Hz. The time taken for the device under test to reconnect to the variable a.c. supply shall be recorded. The output frequency of the variable a.c. supply shall be set to a frequency equal to the under-frequency trip setting, as recorded at step (d), plus 0.1 Hz. The frequency shall then be decreased as rapidly as possible but at a rate less than any df/dt protection incorporated in the device under test. The time interval between the frequency passing through the frequency measured at step (d) and the device under test disconnecting from the variable a.c. supply shall be recorded. The over-frequency trip setting of the grid protection device shall be set to its maximum value, or 55 Hz, whichever is the lesser. The conditions of step (c) shall be re-established. The frequency of the variable a.c. supply shall be adjusted slowly to increase the frequency at the a.c. terminals of the device under test until the device under test disconnects from the variable a.c. supply. The frequency at which disconnection occurs shall be recorded. Step (e) shall be repeated. The output frequency of the variable a.c. supply shall be set to a frequency equal to the over-frequency trip setting, as recorded at step (i), less 0.1 Hz. The frequency shall then be increased as rapidly as possible but at a rate less than any df/dt protection incorporated in the device under test. The time interval between the frequency passing through the frequency measured at step (i) and the device under test disconnecting from the variable a.c. supply shall be recorded.

(f)

(g) (h) (i)

(j) (k)

B3.2 Criteria for acceptance When subjected to the test described above, the frequency recorded at step (d) shall equal the under-frequency set point 0.1 Hz, the frequency recorded at step (i) shall equal the over-frequency set point 0.1 Hz and the disconnection times recorded at steps (f) and (k) shall each be less than or equal to 2 s and the reconnection times recorded at steps (e) and (j) shall each be 1 min or greater. B4 GRID TRIP TEST B4.1 General
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For the grid trip test, the inverter and grid protection device shall be connected into a test circuit similar to that of Figure B2. The test shall be carried out using three different load conditions (a) (b) (c) light electronic load; load match; and load match plus 10%.

For load condition (a), a test load circuit similar to that shown in Figure B3 shall be used. This consists of a full-wave rectifying bridge connected to a 100 F capacitive element and a 560 k resistive element in parallel. For load conditions (b) and (c), a test load circuit similar to that of Figure B4 shall be used. This consists of resistive, inductive and capacitive loads in parallel. In both cases, the inductive load shall be chosen such that it draws 100 VAR from the grid and the capacitive load shall be chosen such that it supplies 100 VAR to the grid. For load condition (b), the resistive load shall be chosen such that it draws a load equal to the real power output of the inverter. For load condition (c), the resistive load shall be chosen such that it draws a load that exceeds the real power output of the inverter by 10%.
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Values for L and C can be calculated using the following formulae:

L = V2 2f 100
100 2f V 2

where V f C L = = = = grid voltage grid frequency capacitance inductance

NOTE: This test circuit applies to a single-phase system. To test a three-phase-system, an equivalent three-phase circuit is required.

FIGURE B2 CIRCUIT FOR GRID TRIP TEST

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C=100F R=560 k

NOTE: This load applies to a single-phase system. To test a three-phase system, an equivalent three-phase load is required.

FIGURE B3 TEST LOAD FOR GRID TRIP TEST UNDER LOAD CONDITION (A)

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B4.2 Grid trip test under load condition (a) The grid trip test under load condition (a) shall be carried out as follows: (a) The inverter and grid protection device shall be connected into a test circuit similar to that shown in Figure B2 with a load similar to that shown in Figure B3. The grid voltage shall equal the nominal grid voltage 5%. The input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (10 5)% of its rated output. The switch S shall be opened and the time for the device under test to disconnect from the test circuit shall be recorded. Switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 5)% of its rated output. Step (c) shall be repeated. Switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (100 5)% of its rated output. Step (c) shall be repeated.

(b) (c) (d)

(e) (f)

(g)

When subjected to the above test, all three disconnection times shall be less than 2 s.

NOTES: 1 2
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This load applies to a single-phase system. To test a three-phase system, an equivalent three-phase load is required. The C and L form a resonant load where the reactive power of each component is approximately equal to 100 VAR, i.e. L = C = 100 VAR. C v and L v are the components used in steps B 4.3 (d) and B 4.4 (d) and are not part of the resonant loads.

FIGURE B4 TEST LOAD FOR GRID TRIP TEST UNDER LOAD CONDITIONS (B) AND (C).

B4.3 Grid trip test under load condition (b) The grid trip test under load condition (b) shall be carried out as follows: (a) The inverter and grid protection device shall be connected into a test circuit similar to that of Figure B2 with a test load similar to that shown in Figure B4. The resistive load shall be chosen to draw a load approximately equal to the real power output of the device under test required in each of the following three power level tests. The inductive load shall be chosen such that it draws approximately 100 VAR from the grid. The capacitive load shall be chosen such that it supplies approximately 100 VAR to the grid. The grid voltage shall equal the nominal grid voltage 5%.

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(b)

The input supply to the device under test, measured in volt-amperes, shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (10 5)% of its rated output. The resistive load (R) shall be increased or decreased until the real power consumption of the test load matches the real power output of the inverter to within 5%. Either the inductive or capacitive load shall be adjusted until the reactive power consumption of the test load matches the reactive power output of the device under test (Q Load + Q Testload = Q Inverter output) to 5%.
NOTE: The purpose of the procedure up to this point is to bring the 50 Hz components of power at the utility disconnection switch to zero. System harmonic voltages will result in harmonic currents in the test circuit. The harmonic currents will typically make it very difficult to make the measurement of power or current flow at the disconnection switch equal to zero.

(c)

(d)

(e) (f)

The switch S shall be opened and the time for the device under test to disconnect from the test circuit shall be recorded. The switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 5)% of its rated output. Steps (c) to (e) shall be repeated. The switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output power of the device under test, measured in volt-amperes, equals (100 5)% of its rated output. Steps (c) to (e) shall be repeated.

(g) (h)

(i)

When subjected to the above test, all three disconnection times shall be less than 2 s. B4.4 Grid trip test under load condition (c) The grid trip test under load condition (c) shall be carried out as follows: (a) The inverter and grid protection device shall be connected into a test circuit similar to that shown in Figure B2 with a test load similar to that shown in Figure B4. The resistive load shall be chosen such that is draws a load 1.1 times the real power output of the device under test required in each of the following three power level tests. The inductive load shall be chosen such that it draws approximately 100 VAR from the grid. The capacitive load shall be chosen such that it supplies approximately 100 VAR to the grid. The grid voltage shall equal the nominal grid voltage 5%. The input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (10 5)% of its rated output. The resistive load (R) shall be increased or decreased until the real power consumption of the test load matches 110% of the real power output of the device under test (i.e. overloads the device under test by 10%) to 5%. Either the inductive or capacitive load shall be varied until the reactive power consumption of the test load matches the reactive power output of the device under test to 5%.
NOTE: The purpose of the procedure up to this point is to bring the 50 Hz components of power at the utility disconnection switch to zero. System harmonic voltages will result in harmonic currents in the test circuit. The harmonic currents will typically make it very difficult to make the measurement of reactive power at the disconnection switch equal to zero.

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(b) (c)

(d)

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(e) (f)

The switch S shall be opened and the time for the device under test to disconnect from the test circuit shall be recorded. The switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (50 5)% of its rated output. Steps (c) to (e) shall be repeated. The switch S shall be closed and the input supply to the device under test shall be varied until the a.c. output of the device under test, measured in volt-amperes, equals (100 5)% of its rated output. Steps (c) to (e) shall be repeated.

(g) (h)

(i)

When subjected to the above test, all three disconnection times shall be less than 2 s.

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Appendix G

Python Listing for Two Phase PLL

#= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # # $Id : e l e c 3 2 5 0 _ n o t e s . l y x 513 20120429 1 4 : 2 7 : 0 6 Z r e b 5 3 8 $ # # $ R e v i s i o n : 513 $ # # Two Phase PLL Program . # # DESCRIPTION # """ This program has been d e v e l o p e d from t h e program t h a t was w r i t t e n f o r t h e AUPEC 2009 paper . I t was used b e c a u s e i t c o n t a i n s most o f t h e n e c e s s a r y c l a s s e s t o e a s i l y implement t h e two phase PLL . I have l e f t o f l o t o f t h e o t h e r i n f r a s t r u c t u r e i n t h e program ( most o f which i s commented o u t or not used ) j u s t i n c a s e I want t o d e v e l o p t h e s o f t w a r e f u r t h e r . The program s i m p l y implements t h e b a s i c two phase PLL and d e m o n s t r a t e s how i t works . The waveforms b e i n g i n p u t t o t h e PLL can be from a two phase source , or a l t e r n a t i v e l y from a s i n g l e phase s o u r c e w i t h inq u a d r a t u r e waveform g e n e r a t i o n . The inq u a d r a t u r e g e n e r a t i o n i s not a s i m p l e t a s k t o g e t r i g h t either . """ # # Written by : Robert Betz # Created on : June 13 , 2011 # L a s t m o d i f i e d on : $Date : 20110629 1 7 : 4 5 : 4 3 +1000 (Wed, 29 Jun 2011) $ # L a s t m o d i f i e d by : $Author : r e b 5 3 8 $ # # #= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = from __future__ import p r i n t _ f u n c t i o n from p y l a b import import o s # The f o l l o w i n g c o n d i t i o n a l import i s t o a l l o w t h i s code t o work c o r r e c t l y on # b o t h Windows machines and UNIX machines such as Macs o f Linux machines . i f o s . name == nt : # The machine i s a Windows machine so import a p l a t f o r m s p e c i f i c module # import m s v c r t opSys = Windows e l i f o s . name == p o s i x : # A p o s i x system . # import s e l e c t opSys = UNIX

G-2

Python Listing for Two Phase PLL

# EXECUTION SWITCHES # # V a r i a b l e t o i n d i c a t e t h a t synchronous d e m o d u l a t i o n i s t o occur . # SYNC_DEMOD = True

# Add t h e f o l l w o i n g t o kee p t h e m a t p l o t l i b windows a l i v e i n t h e d e b u g g e r . # # See added l i n e s as bottom o f t h e program as w e l l . # from T k i n t e r import Tk w = Tk ( ) w . withdraw ( )

#= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # # CONSTANTS # #= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # # INITIALISE THE MAIN VARIABLES OF THE SIMULATION # # Form up t h e t h r e e phase waveforms . # # F i r s t l y t h e a m p l i t u d e s o f t h e waveforms . # # Fundamental X1 = 1 0 0 . 0 # Harmonic a m p l i t u d e # XH = 3 0 . 0 # Fundamental F r e q u e n c i e s FREQ = 5 0 . 0 # This i s t h e i n i t i a l f r e q u e n c y FREQ_ALTERED = 6 0 . 0 # This i s t h e changed f r e q u e n c y # The b o o l e a n b e l o w c o n t r o l s t h e i n c l u s i o n o f harmonic p o l u t i o n i n t o t h e # waveforms # HARMONIC_POLUTION = F a l s e # The p a r t i c u l a r harmonic j u s t and i n t e g e r number . # HARMONIC_NUM = 5 . 0

# S e t up t h e s a m p l i n g f r e q u e n c y i n H e r t z . # SAMPLING_FREQ = 5 0 0 0 . 0

# # N W DEFINE THE PI CONSTANTS FOR f e e d b a c k i n t h e PLL O # # Kpf = 1 . 0 Kif = 1.0

# Amplitude LPF c o e f f i c i e n t s ) .

G-3
# The RECURSIVE_COEFFICIENT_F must be < 1 , and t h e s m a l l e r i t i s t h e # h i g h e r t h e bandwidth o f t h e low p a s s f i l t e r . Note t h a t t h i s f i l t e r # 1 s t order . # RECURSIVE_COEFFICIENT_F = 0 . 9 9 2 NONRECURSIVE_COEFFICIENT_F = 1 . 0 RECURSIVE_COEFFICIENT_F

i s only

# The r e c u r s i v e c o e f f i c e n t f o r t h e low p a s s f i l t e r used i n t h e PLL l o o p # f i l t e r s t h e o u t p u t o f t h e PI c o n t r o l l e r p r i o r t o a d d i n g t o t h e c e n t r e f r e q u e n c y # and i n t e g r a t i o n . # # The nonr e c u r s i v e c o e f f i c e n t i s formed by 1 . 0 t h e r e c u r s i v e c o e f f i c i e n t . # S e t t h i s v a l u e t o z e r o i f you do not want a low p a s s f i l t e r i n t h e # f r e q u e n c y f e e d b a c k o f t h e SynchronousTwoPhasePLL c l a s s . # FREQ_LPF_RECU_COEFF = 0 . 0

#= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # # SOME USEFUL LAMBDA FUNCTIONS # #= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Scalar rectangular to polar conversion # r e c t 2 P o l a r = lambda x : ( abs ( x ) , a r c t a n 2 ( x . imag , x . r e a l ) ) # P o l a r t o r e c t a n g u l a r . The i n p u t i s a t u p l e as produced by r e c t 2 P o l a r o f t h e # form ( a b s ( x ) , a n g l e o f x ) # p o l a r 2 R e c t = lambda x : x [ 0 ] e ( x [ 1 ] 1 . 0 j ) # Park t r a n s f o r m a t i o n . The thetaNew2Old v a l u e i s t h e a n g l e between t h e new a x e s and # the old axes . # parkXform = lambda x , thetaNew2Old : x e ( thetaNew2Old 1 . 0 j ) # C l a r k Transformation ( power v a r i a n t form ) . This # v a r i a b l e s and c o n v e r t s them t o two phase v a l u e s # frame . # c l a r k X f o r m = lambda xa , xb , xc : ( 2 . 0 / 3 . 0 ( xa ((1 / sqrt (3.0) accepts three input in a s t a t i o n a r y reference 0 . 5 xb 0.5 xc ) + ( xb xc ) ) 1 . 0 j ) )

# I n v e r s e C l a r k transform , Returns t h e t h r e e phase v a l u e s as a t u p l e . # i n v C l a r k X f o r m = lambda x : ( x . r e a l , ( 0.5 x . r e a l + s q r t ( 3 . 0 ) / 2 . 0 x . imag ) , \ ( 0.5 x . r e a l s q r t ( 3 . 0 ) / 2 . 0 x . imag ) ) # A l l o w s wrapping o f an # so t h a t i t w i l l be i n # w r a p S c a l a r = lambda x : i f (x > pi ) i n p u t v a r i a b l e w i t h a range o f \pm \ p i or 0 t o 2\ p i t h e range o f \pm\ p i ( fmod ( x , ( 2 p i ) ) 2 . 0 p i ) \ e l s e ( ( fmod ( x , ( 2 p i ) ) + 2 p i ) ( x < p i ) e l s e x )

if

# Create an a r r a y form o f t h e wrapping r o u t i n e . # wrapArray = f r o m p y f u n c ( w r a p S c a l a r , 1 , 1 )

#= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # # Class d e c l a r a t i o n s # #= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

G-4

Python Listing for Two Phase PLL

#= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # # Class d e c l a r a t i o n s # #= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = class Integrator : """ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > INPUTS : i n t e g r a t o r G a i n t h e g a i n o f t h e i n t e g r a t o r . This v a l u e has t o be t h e d i g i t a l gain value . i n t e g I n i t V a l u e t h e initial value of the integrator ( Default = 0.0)

i n t e g L i m i t s a t u p l e c o n t a i n i n g t h e ( l o w e r l i m i t , upper l i m i t ) o f t h e i n t e g r a t o r . ( d e f a u l t i s ( 0 . 0 , 0 . 0 ) which i s i n t e r p r e t e d as u n l i m i t e d ) . wrapping True means t h a t t h e i n t e g r a l v a l u e w i l l be wrapped t o t h a t t h e v a l u e l i e s between \pm \ pi , F a l s e means t h a t no wrapping o c c u r s . This i s a p p l i e d b e f o r e t h e i n t e g r a t o r l i m i t s . DEFAULT: F a l s e < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < This i s a s i m p l e c a l l t h a t implements a d i g i t a l i n t e g r a t o r . I t has been implemented as a c l a s s b e c a u s e a c l a s s r e t a i n s i t s p a s t v a l u e s and t h e r e f o r e one d oes not have t o worry a b o u t t h i s i s s u e i n t h e code . """ def __init__ ( s e l f , i n t e g r a t o r G a i n , i n t e g I n i t V a l u e = 0 . 0 , \ i n t e g L i m i t s = ( 0 . 0 , 0 . 0 ) , wrapping = F a l s e ) : s e l f . kiGain = i n t e g r a t o r G a i n s e l f . integValue = integInitValue s e l f . integLowerLimit = integLimits [ 0 ] s e l f . integUpperLimit = integLimits [ 1 ] s e l f . limitReached = False s e l f . wrapping = wrapping # A l l o w s wrapping o f an i n p u t v a r i a b l e w i t h a range o f \pm \ p i or 0 t o 2\ p i # so t h a t i t w i l l be i n t h e range o f \pm\ p i # s e l f . w r a p S c a l a r = lambda x : ( fmod ( x , ( 2 p i ) ) 2 . 0 p i ) \ i f ( x > p i ) e l s e ( ( fmod ( x , ( 2 p i ) ) + 2 p i ) i f ( x < p i ) e l s e x ) # def i n t e g r a t o r ( s e l f , i n p u t V a l u e ) : """ INPUTS : i n p u t V a l u e i n p u t t o be i n t e g r a t e d OUTPUTS: ( i n t e g V a l u e , l i m i t R e a c h e d ) t h e o u t p u t o f t h e i n t e g r a t o r , and a b o o l e a n i n d i c a t i n g t h a t one o f t h e i n t e g r a t o r l i m i t s has been r e a c h e d . """ s e l f . i n t e g V a l u e += s e l f . k i G a i n i n p u t V a l u e if s e l f . wrapping == True : s e l f . integValue = s e l f . wrapScalar ( s e l f . integValue )

s e l f . limitReached = False if s e l f . i n t e g L o w e r L i m i t != 0 . 0 or s e l f . i n t e g U p p e r L i m i t != 0 . 0 i f s e l f . integValue > s e l f . integUpperLimit : s e l f . integValue = s e l f . integUpperLimit s e l f . l i m i t R e a c h e d = True e l i f s e l f . integValue < s e l f . integLowerLimit : :

G-5
s e l f . integValue = s e l f . integLowerLimit s e l f . l i m i t R e a c h e d = True return ( s e l f . i n t e g V a l u e , s e l f . limitReached )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c l a s s Pi : """ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Initialisation : kpGain Kp p r o p o r t i o n a l g a i n kiGain Ki i n t e g r a l g a i n t h e i n i t I n t e g V a l u e i n i t i a l d i g i t a l gain value . set to 0.0)

integrator value ( default

i n t e g L i m i t s a t u p l e c o n t a i n i n g t h e ( n e g a t i v e l i m i t , p o s i t i v e l i m i t ) o f t h e i n t e g r a t o r . ( d e f a u l t i s ( 0 . 0 , 0 . 0 ) which i s i n t e r p r e t e d as u n l i m i t e d . Returns : ( piOutput , i P a r t , l i m i t R e a c h e d ) Tuple c o n t a i n i n g t h e o u t p u t o f t h e a d d i t i o n o f t h e P and I p a r t s , t h e i n t e g r a l o u t p u t p a r t , and a b o o l e a n i n d i c a t i n g i f t h e i n t e g r a t o r l i m i t has been r e a c h e d . < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < This c l a s s implements t h e PI p a r t o f a PI c o n t r o l l e r . The i n t e g r a t o r has l i m i t s t o t h e v a l u e t h a t i t w i l l i n t e g r a t e t o . The l i m i t s do not have t o be symmetrical about zero . """ def __init__ ( s e l f , kpGain , kiGain , i n i t I n t e g V a l u e = 0 . 0 , i n t e g L i m i t s = ( 0 . 0 , s e l f . kpGain = kpGain s e l f . kiGain = kiGain s e l f . intValue = initIntegValue s e l f . integNegativeLimit = integLimits [ 0 ] s e l f . integPositiveLimit = integLimits [ 1 ] s e l f . limitReached = False s e l f . outputValue = i n i t I n t e g V a l u e s e l f . i n t e g r a t o r = I n t e g r a t o r ( s e l f . kiGain , i n i t I n t e g V a l u e , i n t e g L i m i t s ) # def p i ( s e l f , i n p u t V a l u e ) : returnTuple = s e l f . i n t e g r a t o r . i n t e g r a t o r ( inputValue ) s e l f . intValue = returnTuple [ 0 ] s e l f . limitReached = returnTuple [ 1 ] s e l f . o u t p u t V a l u e = s e l f . i n t V a l u e + s e l f . kpGain i n p u t V a l u e # Now make s u r e t h a t t h e o u t p u t i s l i m i t e d as w e l l . Note t h a t t h i s can # occur even t h o u g h t h e i n t e g r a t o r i t s e l f i n not i n l i m i t . # i f s e l f . i n t e g N e g a t i v e L i m i t != 0 . 0 or s e l f . i n t e g P o s i t i v e L i m i t != 0 . 0 : i f s e l f . outputValue > s e l f . i n t e g P o s i t i v e L i m i t : s e l f . outputValue = s e l f . i n t e g P o s i t i v e L i m i t elif s e l f . outputValue < s e l f . i n t e g N e g a t i v e L i m i t s e l f . outputValue = s e l f . i n t e g N e g a t i v e L i m i t :

0.0))

return ( s e l f . outputValue ,

s e l f . intValue ,

s e l f . limitReached )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

class Lpf1stOrder : """ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Initialisation :

G-6

Python Listing for Two Phase PLL

( r e c u r s i v e C o e f f , n o n r e c u r s i v e C o e f f ) t u p l e c o n t a i n i n g t h e r e c u r s i v e and non r e c u r s i v e c o e f f i c i e n t s . < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < Returns : The f i l t e r value of the input quantity .

""" def __init__ ( s e l f , f i l t e r C o e f f s ) : self . filterCoeffs = filterCoeffs s e l f . pastOutputs = 0 # def l p f ( s e l f , i n p u t Q u a n t i t y ) : """ Inputs : i n p u t Q u a n t i t y r e a l or complex number t h e i s t h e i n p u t t o t h e filter . Returns : The f i l t e r e d input value .

""" s e l f . pastOutputs = s e l f . f i l t e r C o e f f s [ 0 ] s e l f . pastOutputs + \ s e l f . f i l t e r C o e f f s [ 1 ] inputQuantity return s e l f . p a s t O u t p u t s

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c l a s s SinglePhaseEPLL : """ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > INITIALISATION INPUTS : a m p F i l t e r C o e f f s ( r e c u r s i v e c o e f f i c i e n t , nonr e c u r s i v e t h e a m p l i t u d e low p a s s f i l t e r . coefficient ) for

p h a s e F i l t e r C o e f f s ( r e c u r s i v e c o e f f i c i e n t , nonr e c u r s i v e f o r t h e phase f e e d b a c k low p a s s f i l t e r .

coefficient )

piGains ( kp gain , k i g a i n ) f o r t h e PI f e e d b a c k c o n t r o l l e r ampIntegGain c o n t i n u o u s time g a i n o f t h e i n t e g r a t o r u s i n g i n t h e amplitude estimation s e c t i o n of the c o n t r o l l e r . vcoCentreFreq c e n t r e f r e q u e n c y o f t h e VCO e x p r e s s i o n i n H e r t z . sa m pl es Pe r Ce nt re Fr e qP er io d number o f sa mp le s i n one c y c l e o f a waveform w i t h t h e p e r i o d c o r r e s p o n d i n g t o t h e vcoCentreFreq . p i I n t e g r a t o r L i m i t s ( l o w e r i n t e g r a t o r l i m i t , upper i n t e g r a t o r l i m i t ) . The l o w e r and upper l i m i t s o f t h e i n t e g r a t o r . D e f a u l t i s ( 0 . 0 , 0 . 0 ) which means t h a t t h e r e a r e no i n t e g r a t o r l i m i t s . estAmpPhase ( e s t i m a t e d i n i t i a l a m p l i t u d e , e s t i m a t e d i n i t i a l phase ) . t u p l e c o n t a i n i n g v a l u e s o f t h e i n i t i a l e s t i m a t e d a m p l i t u d e and phase o f t h e waveform . The d e f a u l t v a l u e i s ( 0 . 0 , 0 . 0 ) . < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < DESCRIPTION This c l a s s d i g i t a l l y implements t h e Enhance Phase Locked Loop as p r o p o s e d by KarimiGhartemani . This v a r i a n t o f t h e EPLL c o n t a i n s two l p f , one f e e d i n g d a t a i n t o t h e PI b l o c k , and t h e o t h e r i n t h e p a t h o f t h e i n t e g r a l v a l u e i n t h e a m p l i t u d e e s t i m a t i o n p a r t o f t h e EPLL. """

G-7
def __init__ ( s e l f , a m p F i l t e r C o e f f s , p h a s e F i l t e r C o e f f s , p i G a i n s , ampIntegGain , vcoCentreFreq , samplesPerCentreFreqPeriod , p i I n t e g r a t o r L i m i t s = ( 0 . 0 , 0 . 0 ) , estAmpPhase = ( 0 . 0 , 0 . 0 ) ) : # Create t h e low p a s s f i l t e r s f o r t h e a m p l i t u d e and phase f e e d b a c k p a t h s . # s e l f . ampLpf = L p f 1 s t O r d e r ( a m p F i l t e r C o e f f s ) s e l f . phaseLpf = Lpf1stOrder ( p h a s e F i l t e r C o e f f s ) # The a m p l i t u d e f e e d b a c k g a i n i s i n an a n a l o g u e form . For t h e d i g i t a l # v e r s i o n o f t h e i n t e g r a t o r t o have t h e same e f f e c t i v e g a i n have t o # m u l t i p l y t h e g a i n by t h e time i n t e r v a l between t h e s am pl es . # s e l f . ampIntegGain = ampIntegGain 1 . 0 / ( v c o C e n t r e F r e q s a m p l e s P e r C e n t r e F r e q P e r i o d ) # Gain o f t h e pure i n t e g r a t o r t o g e n e r a t e t h e phase from t h e f r e q u e n c y e r r o r and t h e # centre frequency . # s e l f . phaseFeedbackIntegGain = 1 . 0 / ( vcoCentreFreq samplesPerCentreFreqPeriod ) # Now f i n a l l y s c a l e t h e p i i n t e g r a l g a i n and s a v e t h e p r o p o r t i o n a l g a i n . # s e l f . piIntegGain = piGains [ 1 ] 1 . 0 / ( vcoCentreFreq samplesPerCentreFreqPeriod ) s e l f . piPropGain = p i G a i n s [ 0 ] # Now c r e a t e t h e PI p a r t o f t h e c o n t r o l l e r . Note t h a t under t h i s # i t has been c r e a t e d w i t h no i n t e g r a l l i m i t s . # s e l f . piFreqFdbk = Pi ( s e l f . piPropGain , s e l f . p i I n t e g G a i n ) # Now form t h e a m p l i t u d e i n t e g r a t o r # s e l f . ampInteg = I n t e g r a t o r ( s e l f . ampIntegGain , instantiation

integLimits = piIntegratorLimits )

# Form t h e a n g u l a r f r e q u e n c y i n t e g r a t o r # s e l f . phaseInteg = I n t e g r a t o r ( s e l f . phaseFeedbackIntegGain , \ 0 . 0 , ( 0 . 0 , 0 . 0 ) , wrapping = True ) # Now d e f i n e some v a r i a b l e s used i n t h e s o f t w a r e . # s e l f . waveformErr = 0 . 0 s e l f . e s t P h a s e = estAmpPhase [ 1 ] s e l f . estAmp = estAmpPhase [ 0 ] s e l f . sinePhi = sin ( s e l f . estPhase ) s e l f . cosPhi = cos ( s e l f . estPhase ) s e l f . estWaveform = s e l f . estAmp s e l f . c o s P h i s e l f . vcoCentreOmega = 2 . 0 p i v c o C e n t r e F r e q s e l f . freqCorrection = 0.0

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . def e P l l ( s e l f , i n p u t S i g n a l ) : """ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > INPUTS : i n p u t S i g n a l t h e c u r r e n t sample o f t h e waveform b e i n g p r o c e s s e d .

OUTPUTS: ( e s t P h a s e , estAmp , estwaveform , waveformErr ) a t u p l e c o n t a i n i n g t h e values indicated . < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < This i s t h e a c t u a l EPLL code i t s e l f . This implements t h e KarimiGhartemani a l g o r i t h m w i t h t h e a d d i t i o n o f low p a s s f i l t e r s and p o s s i b l e l i m i t s on t h e f r e q u e n c y PI i n t e g r a t o r ( d e p e n d i n g on t h e i n i t i a l i s a t i o n o f t h e class ). The code i s d i v i d e d i n t o t h r e e s e c t i o n s t h e phase d e t e c t o r s e c t i o n ,

G-8

Python Listing for Two Phase PLL

which i n c l u d e s t h e a m p l i t u d e e s t i m a t i o n , t h e PI f r e q u e n c y e r r o r and low p a s s f i l t e r s e c t i o n , and f i n a l l y t h e v o l t a g e c o n t r o l l e d o s c i l l a t o r s e c t i o n . I w i l l a t t e m p t t h e c l e a r l y i d e n t i f y t h e s e as t h e code i s d e v e l o p e d . Note t h a t t h e s e s e c t i o n names f o l l o w t h o s e used i n t h e o r i g i n a l KarimiGhartemani p a p e r s w r i t t e n on t h i s . """ # This i s t h e code f o r t h e phase d e t e c t o r and a m p l i t u d e e s t i m a t i o n s e c t i o n # o f t h e system . # s e l f . waveformErr = i n p u t S i g n a l s e l f . estWaveform i n p u t T o I n t e g r a t o r = s e l f . waveformErr s e l f . c o s P h i ( s e l f . estAmp , l i m i t R e a c h e d ) = s e l f . ampInteg . i n t e g r a t o r ( i n p u t T o I n t e g r a t o r ) if limitReached : print ( " I n t e g r a t o r

l i m i t r e a c h e d i n EPLL Amplitude i n t e g r a t o r " )

# F i l t e r the amplitude estimate # s e l f . estAmp = s e l f . ampLpf . l p f ( s e l f . estAmp ) # Now form t h e new e s t i m a t e o f t h e o u t p u t waveform f o r # the algorithm . # s e l f . estWaveform = s e l f . estAmp s e l f . c o s P h i this i te ra ti on of

# Now f e e d t h e e r r o r i n t o t h e PI c o n t r o l l e r and VCO # i n p u t T o P i = s e l f . waveformErr s e l f . s i n e P h i ( inputToVco , s e l f . freqCorrection , limitReached ) = \ s e l f . piFreqFdbk . p i ( s e l f . p h a s e L p f . l p f ( i n p u t T o P i ) )

if

limitReached : print ( " L i m i t r e a c h e d i n t h e EPLL p h a s e f e e d b a c k i n t e g r a t o r " )

# ( inputToVco , f r e q C o r r e c t i o n , l i m i t R e a c h e d ) = s e l f . piFreqFdbk . p i ( inputToPi )

# Now f e e d t h r o u g h t o t h e VCO # ( s e l f . e s t P h a s e , l i m i t R e a c h e d ) = s e l f . p h a s e I n t e g . i n t e g r a t o r ( inputToVco + s e l f . vcoCentreOm if limitReached : print ( " L i m i t r e a c h e d i n t h e EPLL VCO i n t e g r a t o r " )

s e l f . sinePhi = sin ( s e l f . estPhase ) s e l f . cosPhi = cos ( s e l f . estPhase ) return ( s e l f . e s t P h a s e , s e l f . estAmp , s e l f . estWaveform , s e l f . waveformErr )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c l a s s TwoPhasePLL : """ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Class i n i t i a l i s a t i o n : f b F i l t e r C o e f f s t u p l e c o n t a i n i n g t h e two f e e d b a c k f i l t e r c o e f f i c i e n t s , w i t h t h e o r d e r i n t h e t u p l e b e i n g ( r e c u r s i v e c o e f f i c i e n t , nonr e c u r s i v e coefficient ). piGains t u p l e c o n t a i n i n g t h e two PI c o n t r o l l e r g a i n s , w i t h t h e o r d e r i n the t u p l e being ( p r o p o r t i o n a l gains , i n t e g r a l gain ) . fundamentalFreq t h e e s t i m a t e d FUNDAMENTAL f r e q u e n c y . Frequency i s e x p r e s s e d i n Hz . NOTE THAT THIS IS THE FUNDAMENTAL FREQUENCY, AND IF HARMONCS ARE BEING CONSIDERED THEN SEE BELOW FOR OTHER PARAMETER. samplesPerFundCycle t h e number o f s am p les p e r c y c l e o f t h e e s t i m a t e d fundamental f r e q u e n c y .

G-9
harmonicNumberToLockTo t h e harmonic o f t h e fundamental t o l o c k t o . This harmonic number i s used t o d e t e r m i n e t h e c e n t r e f r e q u e n c y o f t h e VCO. DEFAULT VALUE IS 1 ( t h e fundamental ) . Returns : t u p l e ( e s t i m a t e d i n p u t phase ( r a d i a n s ) , f r e q u e n c y c o r r e c t i o n ( Hz ) ) < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < This c l a s s implements a b a s i c two phase phase l o c k e d l o o p (PLL ) . The o u t p u t o f t h e PLL i s t h e phase a n g l e o f t h e i n p u t and t h e f r e q u e n c y e r r o r term f e d around t h e PLL t o c o r r e c t f o r e r r o r s i n t h e phase . This phase l o c k e d l o o p i s implemented i n a d i g i t a l form so t h a t t h e phase d e t e c t o r i s a " pure " phase d e t e c t o r i . e . i t doe s NOT use a m u l t i p l i e r and f i l t e r t o d e t e c t t h e phase e r r o r , b u t i n s t e a d u s e s t r u e phase d i f f e r e n c e . This approach means t h a t 2 p i wrap around must be a p p r o p r i a t e h a n d l e d . The use o f t h e t r u e phase e r r o r approach means t h a t i n p r i n c i p l e t h e r e would not be ac components f l o w i n g t h r o u g h t h e f e e d b a c k p a t h o f t h e PLL . However , t h e r e w i l l be phase n o i s e i n t h i s path , and f o r t h i s r e a s o n a LPF i s a l s o i n t h e phase e r r o r f e e d b a c k . The o t h e r i n t e r e s t i n g p a r t o f t h e PLL i s t h a t i t i n c o r p o r a t e s a PI c o n t r o l l e r i n t h e phase f e e d b a c k p a t h . This means t h a t t h e phase l o c k e d l o o p i s c a p a b l e o f l o c k i n g onto t h e phase o f t h e i n p u t waveform w i t h a z e r o phase e r r o r . The c e n t r e f r e q u e n c y p a s s e d i n t o t h e c l a s s i s t h e fundamental f r e q u e n c y o f t h e system . However , t h e PLL may be used t o e x t r a c t harmonic f r r e q u e n c i e s o f t h e fundamental , and t h e r e f o r e t h e harmonic number i s p a s s e d i n . The methods i n s i d e t h i s c l a s s a r e d e s i g n e d t o be c a l l e d from a l o o p . This i s b e c a u s e t h e PLLs a r e used i n a f e e d b a c k s t r u c t u r e t h a t r e q u i r e s t h e i n p u t o f k n o w l e d g e from o t h e r PLLs .

Usage : To use t h e c l a s s c a l l t h e method p l l i n s i d e a l o o p . The v a l u e s p a s s e d a r e t h e i n s t a n t a n e o u s v a l u e s o f a two phase v a r i a b l e , p a s s e d i n as a complex number . """ # def __init__ ( s e l f , f b F i l t e r C o e f f s , p i G a i n s , f u n d a m e n t a l F r e q , samplesPerFundCycle , harmonicNumberToLockTo = 1 ) : self . fbFilterCoeffs = fbFilterCoeffs s e l f . piGains = piGains s e l f . fundamentalFreq = fundamentalFreq s e l f . fundamentalOmega = 2 . 0 p i f u n d a m e n t a l F r e q s e l f . i n t e g r a t o r G a i n F a c t o r = 1 . 0 / ( s e l f . f u n d a m e n t a l F r e q s a m p l e s P e r F u n d C ycle ) s e l f . piIntegratorGain = s e l f . piGains [ 1 ] s e l f . integratorGainFactor s e l f . omegaCorrection = 0.0 s e l f . estSignalPhase = 0.0 s e l f . filteredFeedback = 0.0 s e l f . piIntegralValue = 0.0 s e l f . piIntegralValuePrev = 0.0 s e l f . phaseError = 0.0 s e l f . p h a s e F i l t e r = Lpf1stOrder ( f b F i l t e r C o e f f s ) s e l f . harmonicNumber = harmonicNumberToLockTo s e l f . piReturn = 0. 0 # # # # # # # # # # Now c a l c u l a t e t h e c e n t r e f r e q u e n c y o f t h e VCO. Note t h a t t h e PLL i s b e i n g used t o e x t r a c t phase o f a two phase r e p r e s e n t a t i o n o f a s e t o f t h r e e phase waveforms . T h e r e f o r e we need t o c o n s i d e r t h e f a c t t h a t h i g h e r o r d e r harmonics o f t h e fundamental may c o n s t i t u t e a n e g a t i v e s e q u e n c e i . e . t h e s p a c e v e c t o r r o t a t e s i n t h e o p p o s i t e d i r e c t i o n as compared t o t h e fundamental . The a l g o i r t h m t o c a l c u l a t e t h e phase s e q u e n c e i s b a s e d on c a l c u l a t i n g t h e e f f e c t i v e phase o f t h e harmonic waveform f o r each o f t h e phase bac k a t t h e z e r o a n g l e . For example , f o r t h e 5 t h harmonic

G-10
# # # # # # # # # # # # # # # # # # # # # # # # # # # #

Python Listing for Two Phase PLL

t h e r e i s 72 d e g s f o r a c o m p l e t e p e r i o d ( on t h e o r i g i n a l t h e t a a x i s f o r t h e fundamental ) . The a phase 5 t h harmonic s t a r t s as z e r o d e g r e e s a t t h e z e r o d e g r e e s on t h e fundamental t h e t a a x i s . The b phase harmonic s t a r t s a t an o f f s e t z e r o d e g r e e s a t 120 d e g r e e s on t h e fundamental t h e t a a x i s . S i n c e a p e r i o d o f t h e 5 t h harmonic i s 72 degs , t h e n t h e r e a r e 1 2/3 r d s p e r i o d s o f t h e 5 t h harmonic i n 120 d e g s o f t h e fundamental . T h e r e f o r e i f one s l i d e s ba ck t h e waveform o f t h e 5 t h harmonic t h a t s t a r t s a t t h e b phase ( i . e . 120 d e g s ) t h e n t h e r e w i l l be 1 2/3 r d s c y c l e s t o g e t ba ck t o z e r o d e g r e e s . The 2/3 r d s p a r t o f t h i s i s t h e i m p o r t a n t p a r t , i n t h a t i t means t h a t t h i s b phase harmonic l o o k s l i k e a waveform t h a t i s s h i f t e d by 120 d e g s . S i m i l a r l y t h e c phase o f f s e t 5 t h harmonic w i l l have 3 1/3 rd c y c l e s o f t h e 5 t h harmonic t o g e t ba ck t o z e r o d e g r e e s . The n e t r e s u l t i s t h a t t h e a p p a r e n t phase s e q u e n c e o f t h e 5 t h harmonic i s t h e r e v e r s e o f t h e fundamental . I f a s i m i l a r s t r a t e g y i s a p p l i e d t o t h e 7 t h harmonic , t h e n we have 2 1/3 c y c l e s p e r 120 d e g s . The 1/3 rd remainder p a r t means t h a t t h e b phase a l i g n e d v e r s i o n w i l l be i n t h e same phase r e l a t i o n s h i p as t h e normal p o s i t i v e phase s e q u e n c e . The g e n e r a l r u l e t h e r e f o r e i s t h a t i f remainder ( 1 2 0 / ( d e g s f o r harmonic c y c l e ) ) = 1/3 rd t h e n phase s e q u e n c e i s p o s i t i v e , e l s e 2/3 r d s t h e n n e g a t i v e .

if

There a r e i s s u e s w i t h d o i n g t h e c o m p a r i s i o n s w i t h t h i s due t o t h e i n a c c u r a t e r e p r e s e n t a t i o n o f numbers i n computers .

i f round ( modf ( 1 2 0 . 0 / ( 3 6 0 . 0 / s e l f . harmonicNumber ) ) [ 0 ] ) == 1 . 0 : # The phase s e q u e n c e i s n e g a t i v e # s e l f . centreOmega = s e l f . harmonicNumber s e l f . fundamentalOmega else : # Phase s e q u e n c e p o s i t i v e # s e l f . centreOmega = s e l f . harmonicNumber s e l f . fundamentalOmega

# A c o u p l e o f u t i l i t y r o u t i n e s t h a t a r e used . They a r e c a r r i e d h e r e so t h a t # the c l a s s i s s e l f contained . # A l l o w s wrapping o f an i n p u t v a r i a b l e w i t h a range o f \pm \ p i or 0 t o 2\ p i # so t h a t i t w i l l be i n t h e range o f \pm\ p i # s e l f . w r a p S c a l a r = lambda x : ( fmod ( x , ( 2 p i ) ) 2 . 0 p i ) \ i f ( x > p i ) e l s e ( ( fmod ( x , ( 2 p i ) ) + 2 p i ) i f ( x < p i ) e l s e x ) # Scalar rectangular to polar conversion # s e l f . r e c t 2 P o l a r = lambda x : ( abs ( x ) , a r c t a n 2 ( imag ( x ) , # I n s t a n t i a t e a PI c l a s s # s e l f . p i = Pi ( s e l f . p i G a i n s [ 0 ] ,

real (x )))

s e l f . piIntegratorGain )

# I n s t a n t i a t e t h e f r e q u e n c y t o phase i n t e g r a t o r # s e l f . freqIntegrator = Integrator ( s e l f . integratorGainFactor , \ 0 . 0 , ( 0 . 0 , 0 . 0 ) , wrapping = True ) # def p l l ( s e l f , inputSignal ) :

""" The PLL code . Inputs : i n p u t S i g n a l a complex number ( two phase ) r e p r e s e n t a t i o n o f the signal . Returns : ( s i g n a l phase , c e n t r e f r e q u e n c y e r r o r )

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""" s e l f . phaseError = s e l f . wrapScalar ( s e l f . rect2Polar ( inputSignal ) [ 1 ] \ s e l f . estSignalPhase ) # # Now low p a s s f i l t e r t h e phase e r r o r # # HAVE COMMENTED OUT THE FILTER FOR THE MOMENT. ADDED LINE BELOW TO # COPY THE VALUES IN THE s e l f . f i l t e r e d F e e d b a c k # s e l f . f i l t e r e d F e e d b a c k = s e l f . p h a s e F i l t e r . l p f ( s e l f . p h as e Er ro r ) s e l f . filteredFeedback = s e l f . phaseError # Apply a PI c o n t r o l l e r t o t h i s filtered error

s e l f . piReturn = s e l f . pi . pi ( s e l f . f i l t e r e d F e e d b a c k ) s e l f . estSignalPhase = s e l f . f r e q I n t e g r a t o r . i n t e g r a t o r ( s e l f . piReturn [ 0 ] + s e l f . centreOmega ) [ 0 ] return ( s e l f . e s t S i g n a l P h a s e , s e l f . piReturn [ 1 ] / ( 2 . 0 pi ) )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class SynchronousAmplitudeExtraction : """ Initialisation : a m p F i l t e r C o e f f s = ( r e c u r s i v e c o e f f , nonr e c u r s i v e c o e f f ) : A t u p l e > c o n t a i n i n g t h e f i l t e r c o e f f i c i e n t s f o r t h e 1 s t o r d e r low p a s s f i l t e r t o f i l t e r t h e o u t p u t o f t h e synchronous d e m o d u l a t i o n .

used

Description : This c l a s s e x t r a c t s t h e a m p l i t u d e o f a two phase q u a n t i t y u s i n g a synchronous frame c o n v e r s i o n and f i l t e r i n g t e c h n i q u e . The main method o f t h e c l a s s i s " f i l t e r e d A m p " . The complex v a l u e t o be f i l t e r e d and t h e a n g l e o f t h e synchronous frame a r e p a s s e d i n t o t h e r o u t i n e . I t i s d e s i g n e d t o be c a l l e d on each p a s s t h r o u g h a p r o c e s s i n g l o o p , each time p a s s i n g i n a complex number t h a t r e p r e s e n t s a two phase s t a t i o n a r y frame r e p r e s e n t a t i o n o f a t h r e e phase v a l u e . The v a l u e i s t h e n c o n v e r t e d t o a s y n c h r o n o u s l y r o t a t i n g frame , and t h e n t h e DC component i s f i l t e r e d o u t . """ def __init__ ( s e l f , a m p F i l t e r C o e f f s ) : s e l f . ampFilterCoeffs = ampFilterCoeffs # Create t h e low p a s s f i l t e r t o be used . s e l f . ampFilter = Lpf1stOrder ( ampFilterCoeffs ) # def f i l t e r e d A m p ( s e l f , twoPhaseValue , thetaFrameAngle ) : """ Input : A complex number r e p r e s e n t i n g a s t a t i o n a r y frame two phase v a l u e . thetaFrameAngle a n g l e between t h e new and t h e o l d frame . Returns : Tuple ( f i l t e r complex dq v a l u e , filtered amplitude )

""" # Convert t h e two phase v a l u e from t h e s t a t i o n a r y frame t o t h e # t h e t a a n g l e frame . # syncFrameValue = parkXform ( twoPhaseValue , thetaFrameAngle ) # Now f i l t e r t h e v a l u e . # f i l t e r e d C o m p l e x V a l u e = s e l f . a m p F i l t e r . l p f ( syncFrameValue )

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Python Listing for Two Phase PLL

return ( f i l t e r e d C o m p l e x V a l u e , a bs ( f i l t e r e d C o m p l e x V a l u e ) )

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c l a s s AkagiFeedForward : """ INITIALISATION Tuple ( r e c u r s i v e c o e f f , nonr e c u r s i v e c o e f f ) . This t u p l e c o n t a i n s t h e c o e f f i c i e n t s f o r t h e low p a s s f i l t e r e d used i n t h e f e e d f o r w a r d d e m o d u l a t i o n . This c o e f f i c i e n t s a r e f o r a s i m p l e low p a s s 1 s t o r d e r f i l t e r t h a t i s meant t o f i l t e r o u t t h e DC component o f t h e waveform .

DESCRIPTION This c l a s s implements a s y n c h r o n o u s l y r o t a t i n g frame f i l t e r f o r a p a r t i c u l a r harmonic . This t e c h n i q u e f o r harmonic e x t r a c t i o n i s commonly used , and has been used e x t e n s i v e l y by Akagi f o r h i s a c t i v e f i l t e r s . Hence t h e name o f t h e class . R e f e r t o t h e methods o f t h e c l a s s t o s e e what t h e y do . """ def __init__ ( s e l f , l p F i l t e r C o e f f s ) : # Create an i n s t a n c e o f t h e S y n c h r o n o u s A m p l i t u d e E x t r a c t i o n c l a s s . # s e l f . dq5thHarmonic = S y n c h r o n o u s A m p l i t u d e E x t r a c t i o n ( l p F i l t e r C o e f f s ) s e l f . dqWaveform = z e r o s ( numPoints , complex ) s e l f . i = 0.0 # def __rotatingDqComponents ( s e l f , alphaBetaComponents , f r a m e A n g l e ) : """ > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > PARAMETERS alphaBetaComponents complex number r e p r e s e n t a t i o n t h e two phase s t a t i o n a r y frame components o f a harmonic r i c h waveform . frameAngle a r e a l number r e p r e s e n t i n g t h e a n g l e o f t h e r o t a t i n g frame r e l a t i v e t o t h e s t a t i o n a r y frame i n r a d i a n s .

RETURNS Complex number r e p r e s e n t i n g t h e dq components o f t h e harmonic i n t h e a l p h a + j b e t a components t h a t a r e s y n c h r o n i s e d w i t h t h e r o t a t i o n o f t h e frame . """ return s e l f . dq5thHarmonic . f i l t e r e d A m p ( alphaBetaComponents , f r a m e A n g l e ) # def harmonicComponent ( s e l f , alphaBetaComponents , f r a m e A n g l e ) : """ PARAMETERS alphaBetaComponents complex number a l p h a + ( b e t a j ) which r e p r e s e n t s t h e two phase s t a t i o n a r y frame components o f a harmonic r i c h waveform . frameAngle a r e a l number r e p r e s e n t i n g t h e a n g l e o f t h e r o t a t i n g frame r e l a t i v e t o t h e s t a t i o n a r y frame i n r a d i a n s .

RETURNS

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Complex number r e p r e s e n t i n g dq component sample o f t h e harmonic waveform whose f r e q u e n c y c o r r e s p o n d s t o t h e r a t e o f change o f t h e frameAngle . """ s e l f . dqWaveform [ s e l f . i ] = s e l f . __rotatingDqComponents ( alphaBetaComponents , frameAngle ) [ 0 ] # Now c o n v e r t t h e v a l u e ba ck t o a s t a t i o n a r y frame and r e t u r n # temp = parkXform ( s e l f . dqWaveform [ s e l f . i ] , f r a m e A n g l e ) s e l f . i += 1 return temp

#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c l a s s SynchronousTwoPhasePLL : """ INITIALISATION Ki t h e i n t e g r a l g a i n o f t h e f e e d b a c k PI t h e a n a l o g u e v a l u e . Kp t h e p r o p o r t i o n a l g a i n o f t h e f e e d b a c k PI fundamentalFreq t h e e s t i m a t e d FUNDAMENTAL f r e q u e n c y . Frequency i s e x p r e s s e d i n Hz . NOTE THAT THIS IS THE FUNDAMENTAL FREQUENCY, AND IF HARMONCS ARE BEING CONSIDERED THEN SEE BELOW FOR OTHER PARAMETER. samplesPerFundCycle t h e number o f s am p les p e r c y c l e o f t h e e s t i m a t e d fundamental f r e q u e n c y . f r e q L p f C o e f f a t u p l e c o n t a i n i n g t h e r e c u r s i v e and nonr e c u r s i v e f o r t h e low p a s s f i l t e r on t h e f r e q u e n c y e r r o r term . DEFAULT = ( 0 . 0 , 1 . 0 ) = f i l t e r not a c t i v e > coefficients

harmonicNumberToLockTo t h e harmonic o f t h e fundamental t o l o c k t o . This harmonic number i s used t o d e t e r m i n e t h e c e n t r e f r e q u e n c y o f t h e VCO. DEFAULT VALUE IS 1 ( t h e fundamental ) . i n i t i a l P h a s e an e s t i m a t e o f t h e DEFAULT VALUE i s 0 . 0 . i n i t i a l phase o f t h e d a x i s .

DESCRIPTION This c l a s s implements a c l a s s i c a l t h r e e phase synchronous PLL . The PLL i s b a s i c a l l y t h e one p u b l i s h e d i n a paper by Kaura and B l a s k o i n 1 9 9 7 . """ def __init__ ( s e l f , Ki , Kp , f u n d a m e n t a l F r e q , samplesPerFundCycle , f r e q L p f C o e f f = ( 0 . 0 , 1 . 0 ) , harmonicNumberToLockTo = 1 , initialPhase = 0.0) : s e l f . fundamentalFreq = fundamentalFreq s e l f . harmonicNumber = harmonicNumberToLockTo # Calculate the centre frequency in rads / sec # s e l f . fundamentalOmega = 2 . 0 p i s e l f . f u n d a m e n t a l F r e q # # # # # # Now c a l c u l a t e t h e c e n t r e f r e q u e n c y o f t h e VCO. Note t h a t t h e PLL i s b e i n g used t o e x t r a c t phase o f a two phase r e p r e s e n t a t i o n o f a s e t o f t h r e e phase waveforms . T h e r e f o r e we need t o c o n s i d e r t h e f a c t t h a t h i g h e r o r d e r harmonics o f t h e fundamental may c o n s t i t u t e a n e g a t i v e s e q u e n c e i . e . t h e s p a c e v e c t o r r o t a t e s i n t h e o p p o s i t e d i r e c t i o n as compared t o t h e fundamental .

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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #

Python Listing for Two Phase PLL

The a l g o r i t h m t o c a l c u l a t e t h e phase s e q u e n c e i s b a s e d on c a l c u l a t i n g t h e e f f e c t i v e phase o f t h e harmonic waveform f o r each o f t h e phase b ac k a t t h e z e r o a n g l e . For example , f o r t h e 5 t h harmonic t h e r e i s 72 d e g s f o r a c o m p l e t e p e r i o d ( on t h e o r i g i n a l t h e t a a x i s f o r t h e fundamental ) . The a phase 5 t h harmonic s t a r t s as z e r o d e g r e e s a t t h e z e r o d e g r e e s on t h e fundamental t h e t a a x i s . The b phase harmonic s t a r t s a t an o f f s e t z e r o d e g r e e s a t 120 d e g r e e s on t h e fundamental t h e t a a x i s . S i n c e a p e r i o d o f t h e 5 t h harmonic i s 72 degs , t h e n t h e r e a r e 1 2/3 r d s p e r i o d s o f t h e 5 t h harmonic i n 120 d e g s o f t h e fundamental . T h e r e f o r e i f one s l i d e s ba ck t h e waveform o f t h e 5 t h harmonic t h a t s t a r t s a t t h e b phase ( i . e . 120 d e g s ) t h e n t h e r e w i l l be 1 2/3 r d s c y c l e s t o g e t ba ck t o z e r o d e g r e e s . The 2/3 r d s p a r t o f t h i s i s t h e i m p o r t a n t p a r t , i n t h a t i t means t h a t t h i s b phase harmonic l o o k s l i k e a waveform t h a t i s s h i f t e d by 120 d e g s . S i m i l a r l y t h e c phase o f f s e t 5 t h harmonic w i l l have 3 1/3 rd c y c l e s o f t h e 5 t h harmonic t o g e t ba ck t o z e r o d e g r e e s . The n e t r e s u l t i s t h a t t h e a p p a r e n t phase s e q u e n c e o f t h e 5 t h harmonic i s t h e r e v e r s e o f t h e fundamental . I f a s i m i l a r s t r a t e g y i s a p p l i e d t o t h e 7 t h harmonic , t h e n we have 2 1/3 c y c l e s p e r 120 d e g s . The 1/3 rd remainder p a r t means t h a t t h e b phase a l i g n e d v e r s i o n w i l l be i n t h e same phase r e l a t i o n s h i p as t h e normal p o s i t i v e phase s e q u e n c e . The g e n e r a l r u l e t h e r e f o r e i s t h a t i f remainder ( 1 2 0 / ( d e g s f o r harmonic c y c l e ) ) = 1/3 rd t h e n phase s e q u e n c e i s p o s i t i v e , e l s e 2/3 r d s t h e n n e g a t i v e .

if

There a r e i s s u e s w i t h d o i n g t h e c o m p a r i s i o n s w i t h t h i s due t o t h e i n a c c u r a t e r e p r e s e n t a t i o n o f numbers i n computers .

i f round ( modf ( 1 2 0 . 0 / ( 3 6 0 . 0 / s e l f . harmonicNumber ) ) [ 0 ] ) == 1 . 0 : # The phase s e q u e n c e i s n e g a t i v e # s e l f . centreOmega = s e l f . harmonicNumber s e l f . fundamentalOmega else : # Phase s e q u e n c e p o s i t i v e # s e l f . centreOmega = s e l f . harmonicNumber s e l f . fundamentalOmega

# A c o u p l e o f u t i l i t y r o u t i n e s t h a t a r e used . They a r e c a r r i e d h e r e so t h a t # the c l a s s i s s e l f contained . # A l l o w s wrapping o f an i n p u t v a r i a b l e w i t h a range o f \pm \ p i or 0 t o 2\ p i # so t h a t i t w i l l be i n t h e range o f \pm\ p i # s e l f . w r a p S c a l a r = lambda x : ( fmod ( x , ( 2 p i ) ) 2 . 0 p i ) \ i f ( x > p i ) e l s e ( ( fmod ( x , ( 2 p i ) ) + 2 p i ) i f ( x < p i ) e l s e x ) # Scalar rectangular to polar conversion # s e l f . r e c t 2 P o l a r = lambda x : ( abs ( x ) , a r c t a n 2 ( x . imag , x . r e a l ) ) # P o l a r t o r e c t a n g u l a r . t h e i n p u t i s a t u p l e as produced by r e c t 2 P o l a r o f t h e # form ( a b s ( x ) , a n g l e o f x ) # s e l f . p o l a r 2 R e c t = lambda x : x [ 0 ] e ( x [ 1 ] 1 . 0 j ) # Park t r a n s f o r m a t i o n . The thetaNew2Old v a l u e i s t h e a n g l e between t h e new a x e s and # the old axes . # s e l f . parkXform = lambda x , thetaNew2Old : x e ( thetaNew2Old 1 . 0 j ) # C l a r k Transformation ( power v a r i a n t form ) . This a c c e p t s t h r e e i n p u t # v a r i a b l e s and c o n v e r t s them t o two phase v a l u e s i n a s t a t i o n a r y r e f e r e n c e # frame . # s e l f . c l a r k X f o r m = lambda xa , xb , xc : ( 2 . 0 / 3 . 0 ( xa 0 . 5 xb 0.5\ xc ) + ( ( 1 / s q r t ( 3 . 0 ) ( xb xc ) ) 1 . 0 j ) ) # I n v e r s e C l a r k transform , Returns t h e t h r e e phase v a l u e s as a t u p l e .

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# s e l f . i n v C l a r k X f o r m = lambda x : ( x . r e a l , ( 0.5 x . r e a l + s q r t ( 3 . 0 ) / 2 . 0 x . imag ) , \ ( 0.5 x . r e a l s q r t ( 3 . 0 ) / 2 . 0 x . imag ) )

# Create an i n s t a n c e o f t h e PI c o n t r o l l e r used i n t h e f e e d b a c k p a t h # s e l f . f d B a c k P i = Pi (Kp , Ki / ( s e l f . f u n d a m e n t a l F r e q s a m p l e s P e r F u n d C y c l e ) ) # Create an i n s t a n c e o f a s i n g l e p o l e low p a s s # f i l t e r o s c i l l a t i o n s out of the frequency . # s e l f . freqLPF = L p f 1 s t O r d e r ( f r e q L p f C o e f f ) # Create an i n s t a n c e o f t h e f r e q u e n c y i n t e g r a t o r # s e l f . f r e q I n t e g = I n t e g r a t o r ( 1 . 0 / ( s e l f . f u n d a m e n t a l F r e q s a m p l e s P e r F u n d C y cle ) , \ i n i t i a l P h a s e , ( 0 . 0 , 0 . 0 ) , wrapping = True ) # Use t o s t o r e t h e phase o f t h e i n p u t . # s e l f . phase = i n i t i a l P h a s e # Used t o s t o r e t h e f r e q u e n c y e r r o r # s e l f . freqErr = 0.0 # The f r e q u e n c y e s t i m a t e # s e l f . freqEst = 0.0 # def p l l ( s e l f , a r g s ) : """ This method implements t o c o r e o f t h e t h r e e phase synchronous PLL . The r e f e r e n c e v a l u e f o r t h e d a x i s i s f i x e d a t z e r o ( by t h e f e e d b a c k ) , which means t h a t t h e a c t u a l phase a n g l e o f t h e waveform i s 90 d e g r e e s from t h i s i e . t h e q a x i s a l i g n s w i t h t h e synchronous frame . I n p u t s : Two phase s t a t i o n a r y frame q u a n t i t y i n a t u p l e as xd and xq , OR t h r e e phase q u a n t i t y i n a t u p l e as xa , xb , xc Returns : Tuple c o n t a i n i n g : [ 0 ] t h r e e phase q u a n t i t i e s as a t u p l e xa , xb , xc ; [ 1 ] phase : t h e phase o f t h e s p a c e v e c t o r ; [ 2 ] two phase synchronous frame v a l u e as a complex v a l u e ; NB: The phase v a l u e s a r e n o r m a l i s e d peak v a l u e i s 1 . 0 . [ 3 ] t h e e s t i m a t e d f r e q u e n c y e r r o r between t h e c e n t r e f r e q u e n c y and the actual frequency """ l e n ( a r g s ) == 2 : twoPhaseValues = a r g s [ 0 ] + a r g s [ 1 ] 1 . 0 j else : # F i r s t l y c o n v e r t t o a two phase r e c t a n g u l a r form u s i n g t h e C l a r k # transformation # twoPhaseValues = s e l f . c l a r k X f o r m ( a r g s [ 0 ] , a r g s [ 1 ] , a r g s [ 2 ] ) # Now c a r r y o u t t h e park t r a n s f o r m a t i o n t o t h e e s t i m a t e d t h e t a a x i s . # syncTwoPhaseValue = s e l f . parkXform ( twoPhaseValues , s e l f . p h a s e ) # Get t h e d a x i s component as t h e f e e d b a c k v a l u e # f d b c k E r r = syncTwoPhaseValue . r e a l # Feed t h e e r r o r i n t o t h e PI c o n t r o l l e r and t h e n f i l t e r i t . # s e l f . f r e q E r r = s e l f . freqLPF . l p f ( s e l f . f d B a c k P i . p i ( f d b c k E r r ) [ 0 ] ) if filter t o be used t o

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Python Listing for Two Phase PLL

# Now add t h e c e n t r e f r e q u e n c y ( a l s o known as t h e f e e d f o r w a r d component ) # s e l f . f r e q E s t = s e l f . f r e q E r r + s e l f . centreOmega # Now i n t e g r a t e t h e f r e q u e n c y e s t i m a t e t o g e t t h e e s t i m a t e d phase . Note # t h a t t h i s i n t e g r a t o r w i l l a l s o c a r r y o u t p i < Theta <= p i wrapping . # s e l f . phase = s e l f . f r e q I n t e g . i n t e g r a t o r ( s e l f . f r e q E s t ) [ 0 ] # Now c o n v e r t t h e two phase v a r i a b l e s from t h e synchronous frame b ack # t o a t h r e e phase s t a t i o n a r y frame . # twoPhaseValues = s e l f . parkXform ( syncTwoPhaseValue , s e l f . p h a s e ) t h r e e P h a s e V a l u e s = s e l f . i n v C l a r k X f o r m ( twoPhaseValues ) return ( t h r e e P h a s e V a l u e s , s e l f . phase , syncTwoPhaseValue , s e l f . freqErr )

#@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ # # MAIN PROGRAM START # #@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ i f __name__ == __main__ :

#= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # # De r iv ed V a r i a b l e D e f i n i t i o n s # #= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = omega = 2 . 0 p i FREQ # Fundamental a n g u l a r f r e q u e n c y o f t h e s u p p l y f u n d _ c y c l e s = 1 0 0 . 0 # Number o f c y c l e s o f f r e q u e n c y f o r s i m u l a t i o n t o run # S e t up f o r 5kHz s a m p l i n g i . e . 100 sa mp le s p e r 2 p i r a d i a n s o f t h e 50Hz # waveform . # s a m p l e s P e r C y c l e = SAMPLING_FREQ / FREQ # Samples p e r c y c l e o f FREQ Hz waveform d e l t a T = 1 . 0 / (FREQ s a m p l e s P e r C y c l e ) # time s e p e r a t o n o f sa mp le s d e l t a T h e t a = 2 p i / s a m p l e s P e r C y c l e # s e p a r a t i o n o f s am pl es a t 50Hz # Now we want t o s i m u l a t i o n a change i n t h e f r e q u e n c y o f t h e i n p u t waveform # a t a b o u t t h e h a l f w a y p o i n t t h r o u g h t h e a r r a y . This change i n f r e q u e n c y # i s s i m u l a t e d i n t h i s program by e f f e c t i v e l y c h a n g i n g t h e d e l t a t h e t a o f # t h e t h e t a a r r a y . This can be a c h i e v e d by u s i n g a s c a l i n g f a c t o r t o # m u l t i p l e a s u b s e t o f t h e a r r a y by t h e f a c t o r . This f a c t o r i s r e p r e s e n t e d # as a r e l a t i v e v a l u e o f t h e o r i g i n a l d e l t a T h e t a v a l u e . # r e l a t i v e F r e q C h a n g e = FREQ_ALTERED / FREQ deltaThetaAltered = 2 pi relativeFreqChange / samplesPerCycle # S e p a r a t i o n o f s am pl es i n r a d i a n s f o r t h e nominal f r e q u e n c y o f 50Hz w i t h # 100 s am pl es p e r p e r i o d o f t h e waveform . Note t h a t t h e i n i t i a l a r r a y i s # f o r t h e i n i t i a l f r e q u e n c y FREQ and o n l y f o r h a l f t h e t o t a l number o f c y c l e s . # A second a r r a y i s formed a t t h e new a l t e r e d f r e q u e n c y FREQ_ALTERED, and # t h i s a r r a y i s t h e n appended t o t h e f i r s t one t o form t h e c o m p l e t e t h e t a # array # t h e t a F r e q = [ x d e l t a T h e t a f o r x in r a n g e ( i n t ( f u n d _ c y c l e s / 2 s a m p l e s P e r C y c l e ) ) ] # The f o l l o w i n g l i s t f o r m a t i o n i s a l i t t l e t r i c k y t o e n s u r e t h a t t h e r e i s a # c o r r e c t t r a n s i t i o n from t h e i n i t i a l f r e q u e n c y waveform t o t h e new f r e q u e n c y # waveform . # t h e t a F r e q A l t e r e d = [ x d e l t a T h e t a A l t e r e d + t h e t a F r e q [ l e n ( t h e t a F r e q ) 1 ] f o r x in range (1 , i n t ( fund_cycles / 2 samplesPerCycle ) 1 , 1 ) ] thetaFreq . extend ( thetaFreqAltered )

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theta = array ( thetaFreq ) # Have t o change t h e t y p e s i n c e t h e r e s u l t o f t h e wrapArray i s o f d t y p e # o b j e c t which cannot be used i n t h e s i n e and c o s i n e f u n c t i o n s t h a t f o l l o w . # t h e t a = wrapArray ( fmod ( t h e t a , 2 p i ) ) . a s t y p e ( f l o a t ) # Get t h e di m en si on s o f t h e a r r a y so t h a t t h e d a t a s t o r a g e can be d e f i n e d # and l o o p v a r i a b l e d e f i n e d . # numPoints = t h e t a . s h a p e [ 0 ] # # Note t h a t t h e waveforms b e l o w a r e as g e n e r a t e d i n t h e book # " Grid C o n v e r t e r s f o r P h o t o v o l t a i c and Wind Power Systems " by # Teodorescu , L i s e r r e and R o d r i g u e z . # # The waveforms b e l o w a r e assuming t h a t we have t h e q u a d r a t u r e waveforms . # However i n t h e c a s e o f a s i n g l e phase system , t h e v_beta waveform would # be g e n e r a t e d by an inq u a d r a t u r e waveform g e n e r a t o r . There would n o r m a l l y # be a t r a n s i e n t a s s o c i a t e d w i t h t h e g e n e r a t i o n o f t h i s waveform . # i f not HARMONIC_POLUTION : v_alpha = X1 s i n ( t h e t a ) v_beta = X1 c o s ( t h e t a ) else : # Harmonic p o l u t i o n v_alpha = X1 s i n ( t h e t a ) + XH s i n (HARMONIC_NUM t h e t a ) v_beta = (X1 c o s ( t h e t a ) + XH c o s (HARMONIC_NUM t h e t a ) ) s t a t i o n a r y F r a m e C o m p l e x V a l u e = v_alpha + v_beta 1 . 0 j # DATA STORAGE ARRAYS # # Now s e t up some s t o r a g e a r r a y s f o r v a r i o u s p ar am e te rs t h a t a r e c a l c u l a t e d # and may need t o be s u b s e q u e n t l y p l o t t e d . # f e e d b a c k _ f = z e r o s ( numPoints ) p h a s e _ e r r _ f = z e r o s ( numPoints ) est_fundamental_phase = z e r o s ( numPoints ) i n t _ f e e d b a c k _ f = z e r o s ( numPoints ) pi_output_f = z e r o s ( numPoints ) i n t _ p i _ f = z e r o s ( numPoints ) realImagComponents = z e r o s ( numPoints , complex ) e s t T h e t a = z e r o s ( numPoints ) e s t F r e q E r r = z e r o s ( numPoints ) e s t S p a c e V e c t o r P h a s e = z e r o s ( numPoints ) amplReturnValue = z e r o s ( numPoints , t u p l e ) # Low p a s s f i l t e r c o e f f i c i e n t s f o r t h e l p f used i n t h e two phase PLL . # f r e q L p f C o e f f s = (FREQ_LPF_RECU_COEFF, 1 . 0 FREQ_LPF_RECU_COEFF) # # CLASS INSTANTIATIONS # # # NB: Note t h a t we a r e c h e a t i n g a l i t t l e h e r e i n t h a t we a r e i n i t i a l i s i n g # t h i s c l a s s w i t h k n o w l e d g e o f t h e waveforms t h i s i s i n t h e form o f t h e # i n i t i a l phase . # i n q u a d P l l = SynchronousTwoPhasePLL ( K if , Kpf , FREQ, s a m p l e s P e r C y c l e , f r e q L p f C o e f f s , i n i t i a l P h a s e = p i ) # Create t h e synchronous a m p l i t u d e e x t r a c t i o n c l a s s . This i s not p a r t o f t h e # c l a s s i c two phase p l l s t r a t e g y , b u t i s t h e r e so t h a t t h e e s t i m a t e d # o r i g i n a l waveform can be r e c o n s t r u c t e d f o r comparison . # inquadAmp = S y n c h r o n o u s A m p l i t u d e E x t r a c t i o n ( (RECURSIVE_COEFFICIENT_F, NONRECURSIVE_COEFFICIENT_F) )

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# # MAIN LOOP # f o r i in r a n g e ( numPoints 1 ) :

Python Listing for Two Phase PLL

# Execute t h e PLL code . # p l l R e t u r n V a l u e = i n q u a d P l l . p l l ( v_alpha [ i ] , v_beta [ i ] ) # Now c a r r y o u t t h e a m p l i t u d e e x t r a c t i o n so t h a t t h e e s t i m a t e d waveform # can be p l o t t e d . # amplReturnValue [ i +1] = inquadAmp . f i l t e r e d A m p ( s t a t i o n a r y F r a m e C o m p l e x V a l u e [ i ] , pllReturnValue [ 1 ] ) # The a m p l i t u d e r e t u r n e d from t h e above method s h o u l d be e q u a l t o t h e # q a x i s v a l u e from t h e i n q u a d P l l . p l l method when e v e r y t h i n g s e t t l e s # down . # The v a l u e o f t h e t h e t a a n g l e r e t u r n e d from i n q u a d P l l . p l l s h o u l d be # t h e a n g l e o f t h e d a x i s once t h e system has c o n v e r g e d p r o p e r l y . # T h e r e f o r e t h e c o r r e c t a n g l e f o r t h e phase o f s p a c e v e c t o r i t s e l f # s h o u l d be 90 d e g r e e s f u r t h e r than t h i s . # e s t T h e t a [ i +1] = p l l R e t u r n V a l u e [ 1 ] + p i / 2 . 0 # Estimated frequency error # e s t F r e q E r r [ i +1] = p l l R e t u r n V a l u e [ 3 ] # Save t h e e s t i m a t e d phase o f t h e s p a c e v e c t o r # e s t S p a c e V e c t o r P h a s e [ i +1] = p l l R e t u r n V a l u e [ 1 ] # Now c o n v e r t t h e s p a c e v e c t o r i n a s t a t i o n a r y frame ba ck t o t h e two # phase component v a l u e s . This i s a c h i e v e d by r e a l i s i n g t h e t h a t # e s t _ t h e t a v a l u e ( which was d e r i v d from t h e fram a n g l e ) i s t h e a n g l e # o f t h e s p a c e v e c t o r . The r e a l and imaginary components a r e t h e # s i n e and c o s i n e e s t i m a t e d components . # realImagComponents [ i +1] = p o l a r 2 R e c t ( ( amplReturnValue [ i + 1 ] [ 1 ] , e s t T h e t a [ i + 1 ] ) )

# PLOT RESULTS # figure () p l o t ( v_alpha , k ) g r i d ( True ) h o l d ( True ) p l o t ( r e a l ( realImagComponents ) , t i t l e ( r "$\ alpha$ a x i s values " ) figure () p l o t ( v_beta , k ) g r i d ( True ) h o l d ( True ) p l o t ( imag ( realImagComponents ) , t i t l e ( r "$\ beta$ a x i s values " )

k )

k )

figure () p l o t ( e s t F r e q E r r , k ) g r i d ( True ) t i t l e ( " E s t i m a t e d Frequency E r r o r " ) # Now g e n e r a t e t h e a n g l e o f t h e q a x i s o f t h e r e f e r e n c e frame . Note t h a t t h e # t y p e has t o be changed b e c a u s e t h e r e s u l t o f t h e u n i v e r s a l a r r a y f u n c t i o n # i s o f t y p e d t y p e and not f l o a t . # t h e t a P l o t = wrapArray ( fmod ( t h e t a + p i , 2 p i ) ) . a s t y p e ( f l o a t ) figure () plot ( estSpaceVectorPhase , g r i d ( True ) k )

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h o l d ( True ) p l o t ( t h e t a P l o t , k ) t i t l e ( " R e a l and E s t i m a t e d Space V e c t o r Phase " )

# The f o l l o w i n g l i n e s a r e i n t h e code t e f f e c t i v e l y pause t h e s i m u l a t i o n # b u t a t t h e same time k eep t h e m a t p l o t l i b windows a c t i v e so t h a t t h e y can # be i n t e r a c t e d w i t h by t h e u s e r i n terms o f e x p a n d i n g e t c t o l o o k a t t h e # detail . # # The u s e r can h i t any key t o c a u s e t h e program t o e x i t . # i f opSys == Windows : print ( " H i t any key t o s t o p " ) while not m s v c r t . k b h i t ( ) : w . update ( ) e l i f opSys == UNIX : keyHit = False print ( " H i t any key t o s t o p " ) while not k e y H i t : i , o , e = s e l e c t . s e l e c t ( [ sys . stdin ] , [ ] , [ ] , 0 . 0 ) i f i == [ ] : w . update ( ) else : k e y H i t = True close ( all )

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Python Listing for Two Phase PLL

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