EE 680- Spring 2002

Dr Ramin Roosta

Clock, Power and Ground routing

Brandon Fernandes 887 70 7933 Dhananjay Raghavan 613 27 2936 Sandeep Das Venkatadas 886-39-4531

Abstract: In this term paper, we study the different routing algorithms for the most critical signals in any given electrical environment, namely the clock, power and ground lines. The emphasis of our study is towards understanding both the algorithmic aspects, as well as the electrical factors that motivate the routing algorithms. Clock, power and ground signals are critical and are fed to almost all the circuit elements, hence their ability to tolerate signal irregularities is far less than the other less critical signals routed on a given chip surface. The algorithms we studied for clock distribution are motivated towards making the clock skew zero and minimizing the dynamic power dissipated by clocked circuit modules. On the other hand, the power and ground routing algorithms are designed mainly to maintain signal integrity levels while reaching the most distant circuit modules. The routing algorithms also ensure that transient effects on the power and ground lines are minimized.

Issues in clock distribution:

1) Skew Lets consider the case of a FSM, with distributed State memory Flip Flops; if the clock does not reach all the flip flops at the same time, then some of the flip flops will change state earlier in time. It could be possible that the Next state logic recomputes a new next state for the remaining flip flops, and the FSM goes into the wrong state.

2) Power The clock is power hungry In case of registers, not every loads a new value. So in order to conserve power , we do gated clocking. The question is not only How do you route the clock ?, but also How do you route the control Signals to gate the clock.

The DME Deferred Merge Embedding Algorithm: referenced to [2][3][4] Lets assume that we have to route a Clock source S0 to destinations S1 S2 S3 Sn The manner in which the clock is distributed from the sinks to sources is predefined in terms of a Binary tree G.(shown below)

A clock Tree is defined as an embedding of the topology G in the a 2 dimensional region ,in which each node in G is assigned a position . The DME algorithm provides a ZST (zero skew clock tree ) from S0 to any sink , with minimum wire length.

We define the following: Manhattan distance

Cost Function e(v) Cost of edge used to connect B to parent A e(B) is simply the wire length. Relationship between Manhattan distance and wire length: Wire length eB >= Manhattan distance.

Delay ,Skew and ZST: Let t (a,b) denote the delay from points a to b, then Skew is the maximum of mod ( t(S0,Si)-t (S0,Sj)) If in the tree T with t(S0,Si)-t (S0,Sj) = 0 for all Si, Sj belong to {S1,S2Sn} then the tree T is said to be a ZST (Zero Skew Tree)

Manhattan arc It is a line segment with a slope of 1 or -1.

Tilted Rectangular Region TRR A set of points at a fixed distance from a Manhattan Arc is called a TRR.

A TRR has a Core and a radius. A Manhattan arc is a TRR with Radius =0, Merging segments: ms (v) It defines the possible location for the internal node v. If the node v is a sink node then the merging segment is the node itself. If v is an internal node, then the merging segment is defined as the intersection of the TRRs of the children segments

The Two Phases of DME

The DME algorithm has two phases: 1 The bottom up phase and 2 The top down phase

We start with the Bottom up phase : Start From the Bottom most node , and work upwards, finding the merging segments. For a leaf node, the merging segment is the location is the location of the node itself.

Now we wish to determine the merging segments corresponding to the internal nodes a and b.

Draw minimum sized Diamond shaped boxes around S1 and S2 , and keep expanding them , till they touch. The common region of intersection ie ms(a) Similarly We get ms(b) By observation , from the grid above, e(s1)=e(s2)=3 and e(s3)=e(s4)=2.

Continue to find the merging segments of the internal nodes node v

d(a,b)= 7 Find the locus of V such that e(a) + e(b) >= 7 -----------------1 We have t(a) =3 and t(b) =2 The condition for Skew = 0 is e(a) + t(a) = e(b) + t(b) --------2 Solving 1 and 2 we get e(a)=3 and e(b)=4 Draw the corresponding TRRs of ms(a) and ms(b) and find the intersection . This gives ms(v)

The end of the bottom up phase:

At the end of the Bottom Up phase, we get the above looking output.

The top down phase Start from the topmost internal node (v) If a Clock source is specified , then DME selects a point on ms(v) which is closest to the clock source, and joins it. It a clock source is not specified , then DME selects any point on ms(v). To get l(a) , select a point on ms(a) whose distance is <= ea. But ea=3, and hence only one point on ms(a) satisfies this. To get l(b) , select a point on ms(b) whose distance is <= eb, with eb =4. The resulting tree is as shown below

One can verify that t(S1,S0)= t(S2,S0)=t(S3,S0)=t(S0,S4) =9. Thus t(S0,Si)-t(S0,Sj)=0 for all i , j. and we have achieved a ZST.

Procedure Bottom Top (referenced to [2][3][4]

Input Topology G and locations of sinks and sources

Algorithm 1 For each v in G 2 If v is a sink node, 3 Then the merging segment is the node itself 4 else 5 let a, b be children of v 6 Compute the edge costs e(a) and e(b) 7 find the TRRs of a and b 8 find the intersections of the TRRs, this will give you the merging segments

Output : Tree of Merging segments , with the cost function (e(v)) for all v.

Procedure Top Down

Input : Tree of Merging segments, with the cost function mod (e(v)) for all v.

Algorithm 1 For each internal v in G 2 If v is the root node 3 Choose any location in the merging segment 4 else 5 if v is the internal node , choose any point in v at a distance (e(v)) or less 6 from the parent node.

Output ZST

AN ALGORITHM FOR GATED CLOCK ROUTING:

Introduction: A standard design practice in low power design is to gate the clock i.e. control the clock to a given circuit module, so that it is fed through only when the module is active and is inhibited at all other times. This approach has led to considerable reduction in the dynamic power dissipation, because the clock signal generally displays a high switching activity, making two transitions in a single cycle. In their publications, the authors have proposed an approach for clock tree routing, that ensures zero skew and reduces the power dissipation by minimizing the effective switched capacitance at the internal nodes of the tree. Their results are based on instruction level simulation of the processors in question, by executing a number of benchmark programs.

Problem Definition: Topology of the clock distribution network: A typical clock tree along with the controller is shown in figure (figure number) . The controller enables the different gates, allowing the clock signal to transmit to a module (sink) only when it is needed to.

All figures referenced to Peddram and Oh

Our clock distribution tree is a binary tree, which means that every internal node, or non- leaf node has exactly two descendants. Some important terms are: 1. Let the given binary tree topology be denoted as T. 2. This clock tree distributes the clock signal to N modules, {M1 , M2 ,,M N }. These are the leaves of the binary tree. Since there are N leaves, there must be N-1 internal nodes. Let {v1 , v2 ,,v2N-1 } be the nodes of the tree, in which case {v1 , v2 ,,vN} are the leaves and the rest are the internal nodes of the tree. Let {e1 , e2 ,,e2N-2 } be the edges of the tree. We identify each point vi, except the root, of the rooted topology T with edge ei so that ei connects vi to its parent in T. Let | ei | be the length of edge ei. An example of the clock tree topology is shown in the figure(figure number). 3. The controller is assumed to be at the center of the chip, and routed using the STARshortest path routing technique. The controller tree is designated as S. Edge ENi of the control tree controls the gate on edge ei of the clock tree. Let | ENi | be the length of edge
ENi .

All figures referenced to Peddram and Oh

4. The signal probability of ENi (probability that ENi is 1) is denoted as P(ENi ), and the transition probability of ENi (probability that ENi changes logic value per cycle) is denoted as Ptr (ENi ).

Development of the Cost Function: The key difference between this algorithm and many of the other routing algorithms is that the cost function that constrains the routing of the clock tree is closely related to the power dissipated. This algorithm combines the twin goals of reducing the power dissipated by the distribution network, and ensuring zero clock skew. The cost function in this case is the total switched capacitance over all the edges of the tree. This quantity is directly linked to the total power dissipated as will be shown in the following analysis: 1. Power dissipated per edge of the clock tree is given by:

power ( ei) = 1 / 2 * c 0 * ei * *Vdd ^2

Where C0 is the capacitance per unit length and a is the switching activity, for an edge of the tree transmitting the clock, a = 2. Hence the power dissipated per edge of the clock tree is :
power (ei ) = c 0 * ei * f *Vdd ^ 2

2. However, using a gated clock, power is dissipated only when the clock is enabled, hence the above equation gets modified as:
power ( ei) = c0 * ei * P( Eni) * f *Vdd ^ 2

If Ci is the load capacitance on the edge ei, then we can define the effective switched capacitance at any edge as:
w( ei) = ( c 0 * ei + Ci ) * P ( Eni )

3. The total switched capacitance over the entire clocked tree can thus be calculated as :
W (T ) = ( c 0 * ei + Ci ) * P ( Eni )
ei

4. Using similar considerations, and noting that the input capacitance of an AND gate in the network is Cg, the total switched capacitance over all edges of the controller tree is:
W ( S ) = 1 / 2 * ( c0 * Eni + Cg ) * Ptr ( Eni )
Eni

The switched capacitance of the controller tree depends on the transition probability, because the controller tree is switching only for a 1 0 or a 0 1 transition on the enable lines. 5. From the above equations, we observe that Vdd and f are fixed parameters at the synthesis stage, so the total switched capacitance gives an accurate measure of the power dissipated by the distribution networks. 6. Hence the objective of the gated clock routing algorithm can be restated as: For a particular set of source and sinks, we have to find trees T and S, such that the total switched capacitance over both the clock as well as control trees, W = W (t ) + W ( s) is minimized under the constraint of zero clock skew.

Probability Calculation: One of the major steps in the implementation of the above algorithm is the calculation of the probabilities P(ENi) and Pt r(Eni). These can be evaluated using instruction level simulation of the processor executing benchmark programs. To find P(Eni): We start by assuming that the above system has 4 instructions I1 , I2 , I3 and I4 six circuit modules, M1 , M2 , M3 , M4 , M5 , and M6 . The modules used by each instruction are given by the following table: Instruction Modules used I1 M1, M2, M3 I2 M2 and M5 I3 M5, M6 I4 M3 and M4 benchmark program we are running has the following instruction stream: I1,I1,I3,I2,I4,I1,I1,I2, I3,I1,I4,I2,I3,I2,I2,I3,I4,I4,I3,I3,I4,I3,I1,I3,I2,I1. From this instruction stream, we can find the probability of occurrence of any instruction, which is displayed in a table called the instruction frequency table (IFT). Instruction I1 I2 I3 I4 Probability of Occurrence 0.27 0.23 0.30 0.20

Sup pos e the

For any node vii, if it has modules Mk attached to its nodes, then Eni must be active (high), when any one of the modules are active.
P( Eni) = P( Mi U Mj U ..... U Mk )

Where Mi.Mk are the modules attached to node vi. Hence, using the IFT, it is possible to compute P(Eni) for all the edges Eni of the control tree. The algorithm for estimating these probabilities is given below: Algorithm: 1. Initialize probability, P=0. 2. For each node vk do: 2.a. If modules attached to node vk are used during estimation of Ii, P=P+IFT(Ii) b. Perform operation 2.a over all the instructions. 3. Return P Complexity: If K is the number of instructions in the analysis and L is the maximum number of modules per instruction, then the complexity of the above probability calculation is O(NKL), where N is the total number of modules.

To find Ptr(Eni):

In order to compute the probability of transition, we have to compute the Activity Tag (AT) of each module, which is a two bit vector, indicating the state of the module for two consecutive clock cycles. For example an AT of 11 indicates that the module has been active for two consecutive cycyles, an AT of 10 indicates a module that has been active and has switched to inactive and so on. We are concerned only with transitions hence only the cases where the ATs of modules are either 10 or 01 are of concern to us. Our computation is made easier by the construction of an Instruction Transition Module Activity Table (ITMAT), which is shown as follows:

Instruction transition

Probability M1

Module activity M2 M3 M4 M5 M6

I1-I1 I1-I2 I1-I3 I1-I4 I2-I1

0.08 0.04 0.08 0.04 0.04

11 10 10 10 01

11 11 10 10 11

11 10 10 11 01

00 00 00 01 00

00 01 01 00 10

00 00 01 00 00

For each row in the table, if the corresponding modules activation tags cause ENi to make a transition, the probability on that row should be added to the transition probability of ENi. This is the way we use the above table to calculate the transitional probability.

Algorithm: 4. Initialize probability, Ptr=0. 5. For each node vk do: 2.a. If modules attached to node vk bear an activity tag of 01 or 10, Ptr=Ptr +Ptr(Ii) b. Perform operation 2.a over all the instructions. 6. Return Ptr.

Complexity: If the total number of instructions is K and N is the number of modules, the complexity of calculating transitional probability is O(K 2 N2 ).

Clock Tree Construction: We use a greedy heuristic based on minimizing switched capacitance and ensuring zero clock skew. The main features of this algorithm are: 1. It is based on the DME algorithm, which is a bottom-top followed by a top-down heuristic to estimate merging segments based on Elmore delay. 2. Our method is greedy and merges two nodes when the switched capacitance between them is the minimum. 3. Let ms(vi) be the merging sector of vi. Suppose we try to merge ms(vi) and ms(vj) and the root of the merged tree is vk. We can uniquely determine |ei|, |ej| suc h that the zero skew constraint is satisfied.

3. We assume that the controller is at the center of the chip given by location CP. Since we do not know the exact location of the Steiner points, and only their locus, we estimate switched capacitance between the position CP and the midpoint of the merging segment of a given node. This approximation is used to compute the switched capacitance.

Algorithm: 1. Scan the instruction stream to generate the tables IFT and ITMAT. 2. Compute the absolute and transitional probabilities for each edge 3. Compute the switched capacitance between every pair of sinks 4. Bottom-up merge procedure: 4.a. Pick the pair ms(vx) and ms(vy) whose switched capacitance is minimum. 4.b. Create a new node vk, compute the probabilities for that node and find ms(vk) 4.c. Remove nodes vx and vy, find |ek| and |en| for all other nodes en, that satisfy zero skew. Compute the switched capacitance between vk and vn for all the other nodes. 5. Repeat step 4 for all nodes until only the root node is left. 6. Top down placement: place each node vk within ms(vk). Complexity: If B is the number of instructions in the instruction stream, K is the number of different instruction types and N is the number of modules, then : 1. The first step has a complexity of O(B). 2. The second step has a complexity of O(NKL+K2 N2 ). Since L<N, the dominating complexity is O(K 2 N2 ). 3. The third step has a complexity of O( N2 ). 4. The loop iterates N times and each time the dominating complexity is the probability computation which is O(K 2 N ). Hence, the overall complexity is O(B+ K2 N2 ).

Perfect- Balance Planar Clock routing with Minimal Path Length

Introduction Clock nets have certain unique characteristics which makes its routing special and more complex. As the clock forms the heart of all the synchronous devices and defines the frequency of operation of chip, care should be taken to meet the following specifications. Low delay Reduction of Skew or Zero Skew Low waveform distortion. Motivation : We all know that different metal layers have different R and C delay constants. With the world moving towards high speed digital design one has to exploit every possible way to extract more and more speed. As speed of any chip depends on its clock speed. We use the above strategy to route the clock on a layer which has least RC delay, this avoids the complexity involved of having different electrical parameters on different layers and more importantly eliminates the delay and attenuation of the clock signal through vias. But this can be achieved only with planar clock routing which is possible only if the clock signals dont cross each other. The authors here thus consider each of these factors and have formed this algorithm. This algorithm provides the designers with a good initial topology of clock routing upon which the engineers can work on achieving zero skew. Features : This algorithm assures the following They always construct planar trees. The length of the paths from source of the clock to all the terminals or sink is exactly same. The path length from clock source to each of its terminals is minimum. The clock source may be at any arbitrary location i.e clock source may be a pad at the side of the chip or the may be locally generated at the centre.

Partial Steiner Trees : Given a single source and set of sinks, to find a planar Steiner tree is a NP-complete problem.Thus a concept of constructing partial Steiner tree is used in implementing this algorithm . A clock source and a series of First the source point is selected, now a sink is selected , then partial Steiner tree is formed. With each addition of sinks the partial Steiner tree is grown this is called planar equal path length Steiner tree.

Terms and definitions

Free sink : a sink which is not yet a part of the partial Steiner tree i.e. not yet connected to the source. Connected sink: once the free sink becomes part of the tree it is called a connected sink. tj (1<j<n): represents a sink to which the source must be connected. Ti :is a partial tree in which first i sinks are connected to the source This become complete when i=n, i.e. all the sinks are connected to the source. Branch bk : is the branch formed in order to connect the newly selected sink tj to the source. Balance point Sjk : is called a balance point for a sink tj and exits on the branch bk. The new Steiner point is said to be a balance point if it has equal Manhattan distance from source to sink tj and tj- m , such that 1=m<j. Note : all the distances considered are Manhattan distances. Feasible balance points : these are subsets of balance points . These are those balance points for which there is no cross section between the edge connecting itself and tj and any other existing branches. Visiblity : Two free sinks a,bS are visible if a straight line between them crosses no other tree branches(required to ensure planar property). i.e ab Reachable : this based on the concept of visibility. 2 sinks are reachable if -ab this is direct visibility. - there exits a set of free sink (p1,p2,p3.pk)S, such that ap1 and bpk and pipi+1 for 1=i<k. this is indirect visibility.

Implementation A free sink tj is first selected , then its corresponding feasible balance points is found. Generally for a given sink we get more than one feasible balance point , among those we choose the balance point which has the minimal feasible Manhattan distance between itself and the sink tj.

Fig 1 We can see this in fig1 that there are 2 feasible balancing points b42 and b41 , now here But only one minimal feasible balance point b42 , thus we choose b42 . Order of selection of sink This should be done very carefully, if an improper order to select the free sink is choosen or if sinks are selected randomly , we may end up not getting a planar routing and also a non minimal path to one of the sinks.

Fig 2 demonstrates the need for ordering. Assume the a free sink t5 is selected first .Now if find its corresponding balance point and connect it through branch b5 .let the 2 balance points for t6 be s1 and s2 as shown. But we also see that the minimal feasible point for t6 is s1 which is on branch 1 .Due to the presence of branch b5 the balance point s1 cannot be used as that would result in non planar routing, thus not feasible. Thus in order to properly route using minimal path length we follow 2 rules Min rule : always use the minimal feasible balance point to connect a free sink. Max rule : At each iteration select the maximum of the minimal feasible balance point of each of the remaining cells.

So we see that the Max rule selects the routing order of the free sinks, while the Min rule makes sure that the tree cost is minimal.

This algorithm is iterative in nature and with every iteration we increase the length of our partial Steiner tree. At a partial tree Ti, a free sink is selected and connect using the Min Max rule thus making a partial tree of T . thus now this free sink becomes a connected i+1 sink.

Hierarchical Max-Min Optimization.

Fig 3 As shown in the above fig with each iteration , the tree grows and thus divides the free sinks in to clusters. Every sink present in the same cluster should and must be reachable to each other. Sinks of different cluster are not reachable. Initially when I start there are no clusters and all are free sinks, so when I start the iterations, tree starts growing by adding new branches ,with addition of each new branch the reachability of the remaining free sinks reduces resulting in cluster formation. thus we can say that each cluster is surrounded by a set of branches. Only on these branches can a free sink in the cluster possibly find feasible balance points if not then it would result in crossing thus violating the planarity property. These branches are called bounding branches. From fig 3 we can see that free sink s are partitioned into 4 clusters. The dotted line from t1 to t4 shows the indirect visibility of t1 to t4 , thus they are part of the same cluster. Let us consider cluster4 , its bounding branches are b4,b5 and b7. so for all the free sinks in this cluster feasible balance points will be found on one of these bounding branches. Cluster 4 {b4,b5,b7} Cluster 2 { b6,b7} Parallelism This is one of the main features of this Algorithm as now that every cluster has its own corresponding bounding branches. It transforms into no. of independent routing problems and thus can be tackled in parallel. Thus this is divide and conquer method. Thus we now apply Min-Max rule locally to each cluster. As we need to select the order among each free sink in a cluster(Max rule).

While looking for minimal balance points we need to check the feasible balance on the bounding branches of the cluster. Thus at every iteration we end up selecting a free sink in each of the clusters. Which might again result more clusters. As a result the tree grows faster and faster by applying Min-Max rule locally. maxj{mini{d(tj,bi), bi is a bounding branch of tj}.tj C} d(tj,bi) gives the Manhattan distance of free sink tj to a feasible point on the bounding branch bi.

Algorithm Planar clock routing algorithm based on hierarchical Max-Min optimization. Input : a source s, and a set of sinks D Output : a planar equal path length Steiner tree T Procedure PlanarClockRouter(s,D,T) { Co = D; T=({s}, ); Create branch(Co,T); } procedure CreateBranch(C,T) { find t*,b* such that d(t*,b*) = maxj{mini{d(tj,bi), bi is a bounding branch of tj}.tj C}; Create a branch from t* to its minimal balance point on b* resulting in new T; If (C-{t*} ? ) { Partition C {t*} into subclusters C1,C2,..Ck using the reachable relation; For each i [1,k] Create branch(Ci,T); } }

Time Complexity: The time complexity of this algorithm depends upon if the no. sinks per cluster reduces or not. If ni is the no. of free sinks in Ci. For each cluster Ci, the branch creatipn can be done in O(1) time, and the selection of t*i and the updating of minimal balance points for remaining free sinks can be done in O(ni) time. So, the total time required at each level is i O(ni) = o(n), where n is the total number of sinks. Overall time complexity is O(l.n) Where l is the number level of the tree growing. In the worst case at each level , branches are connected to the tree in such a way that no new clusters are formed. This implies l=n and the order of algorithm becomes O(n2 ).

Issues in Power / Ground Distribution

1. Electromigration Wires Should be thick enough so that they can supply the required amount of current to power hungry modules without being worn away. 2. Ground Bounce/Power Supply Droop (Pin Inductances and SSN ) Pin Inductances cause spikes and droops on the Vdd and Ground that are seen by the IC. Lets assume that Vdd and ground Buses run horizontally across a PCB. The chip is connected to Vdd and ground through the Vdd and ground pins, each having an inductance L. L is in the order of nH.

4. Another issue in power and ground routing is that we must try to route these lines onto a single plane of metal. This is to minimize the number of contacts(vias), which have high resistivity, low reliability and hot spot generation.

5. A good approach where planar routing is not possible would be the use of multiple small vias instead of one large via.

Planar Power and Ground routing If a line is drawn through each cell , dividing the Vdd and Vss points. Now if the placement tool places the cells such that all the Vdd points are on the same side, then there exists a method of planar routing.

Moultons approach to planar power and ground routing: This approach partitions the chip into the Vdd region and GND region, and then routes each net into the appropriate region. The idea being that if all modules are visited just once while traversing from Vdd to GND, a cucle can be drawn, which helps in routing the modules to their respective power pads. A Hamiltonian cycle is drawn and the algorithm also accounts for the layout of the trees. The width of the wires are modulated according to the current they are bearing. Wires at the terminals bear the maximum current from the terminal, while other wires bear the sum of their childrens currents. After estimating the current the minimum wire width is determined by using design rules.

Interdigitation If power and ground are interdigitated , then , the routing can be planar. It can be used for standard cells, and enables sharing of wells, along with power and ground lines, while maintaining a single layer of routing.

Grid routing: A common method of routing power and ground would be to use different layers of metal for each, M4 for ground and M5 for Vdd. These can be connected to the respective pins of the different modules, without the use of vias. This is a useful technique in cell based design, where Vdd and GND connections are predictably placed.

Figure referenced to Sherwani

Heruyama and Fussels greedy algorithm: In this algorithm, we arrange the modules in decreasing order of power consumption. These modules are placed so that the most active modules are closest to Vdd and GND lines. We then place other modules, getting a tree whose root is the power pin. This is a greedy algorithm. It ensures that blockage of wide high current density lines is avoided by placing them first, hence congestion can be overcome.

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