Quiz #1

18349 Embedded Real-Time Systems

September 26, 2007 90 minutes

Instructions: This quiz is open-book, open-notes. You are not allowed to use the lab equipment to solve the problems in the quiz. Cheating will be severely dealt with and will result in 0 points for this quiz. For additional space to do some rough work before entering in your nal answer, please use the pages (marked Scratch Work Here) at the end.

Name:

Q I.: Q II.: Q III.: Total:

/ 20 points / 24 points / 56 points / 100 points

GOOD LUCK!
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I. Multiple-Choice Questions (Total: 20 points)

For each question, there is only one correct answer. Please circle the correct answer (2 points each).

1. The purpose of a pseudo-instruction on the ARM is to (A) Support operations with a full descending stack. (B) Support loading 32-bit values in 32-bit instructions. (C) Support complex CISC-like operation. (D) Support switching between ARM (32-bit) and Thumb (16-bit) modes. 2. Which of the following can cause a negative instruction-cache effect? (A) Function inlining (B) Aligned/packed data structures (C) Induction variables (D) Deadcode elimination 3. Which of the following instructions will change the contents of the cpsr, given that cpsr = nzcvqift USER to start with? (A) MOVS r1, #0x08 (B) ADD r1, r1, LSL #2 (C) BX <label> (D) LDMIA r0!, r1-r3 4. FIQs are faster to handle than IRQs because (A) The processor always uses the barrel shifter in FIQ mode. (B) Memory accesses are not permitted in FIQ mode. (C) FIQ mode has more banked registers. (D) The FIQ interrupt handler is conveniently stored at 0x0. 5. Which of these features makes the ARM processor suited to memory-constrained embedded systems? (A) Barrel shifter. (B) Conditional execution of instructions. (C) Load-store-multiple instructions. (D) All of the above. 6. The ARM is a RISC processor that doesnt take the RISC concept too far. What non-RISC features does the ARM support? (A) Arithmetic instructions (B) Logical instructions (C) Branch instructions (D) Load-store-multiple instructions 2

7. An SWI instruction is used to handle (A) Software bugs that lead to interrupts. (B) Memory alignment problems. (C) System calls to the kernel. (D) Atomic swap operations. 8. A context switch involves (A) Saving the address space of a process. (B) Switching between two different processes. (C) Saving the registers of a process. (D) All of the above. 9. Which of the following instructions modies both the lr and the pc? (A) MOV pc, lr (B) BL <label> (C) LDR pc, [pc, #offset] (D) None of the above. 10. (Free points) Which of these players do you think will be the key to getting the Steelers to the playoffs this year? (A) Willy Parker #39 (B) Hines Ward #86 (C) Ben Roethlisberger #7 (D) Santonio Holmes #10

II. Short Answers (Total: 24 points)

You should not need more than one sentence (or a phrase) to answer each of the following questions.

1. What does LSL #n effectively accomplish? (3 points)

2. How does the pipeline in the ARM architecture affect the pc? (3 points)

3. We want to perform the operation Y * 191. Register r1 holds the value of Y. Register r2 holds the value 191. We expect register r1 to hold the result of the operation. (A) Write a single instruction to perform the operation using the multiply instruction. (3 points)

(B) Write assembly code to perform the operation, without using the multiply instruction. Try to use as few instructions as possible. (3 points)

4. In a program, suppose that the ARM instruction BL myFunction is stored at the address 0x12345678, in what ranges of memory addresses can myFunction never be located? (3 points)

5. Suppose that data processing instructions take 1 clock cycle, and the LDR instruction takes 3 clock cycles on the ARM processor. How would you load the value 0xFF00C300 in register r0 in 2 clock cycles or less? (3 points)

6. What is the size of the address space accessible to the ARM processor? (3 points)

7. Provide an example of a data-processing instruction that operates on registers as its operands, and that modies the cpsr but that leaves the registers unmodied after the instruction completes execution. (3 points)

III. Slightly Longer Answers (Total: 56 points)

1. Below is a function to calculate the GCD (Greatest Common Denominator) of two positive integers. For example, the GCD of 16, 36 and 44 is 4, because 4 is the largest integer that divides 16, 36 and 44 without a remainder. Write the assembly-language equivalent of the function below, keeping in mind to write the most optimized code that you can (15 points). int gcd(int a, int b) { while (a != b) { if (a > b) a = a - b; else b = b - a; } return a; }

2. You have just joined a company that is trying to develop the worlds fastest factorial (n!) routine. For your reference, n! = n*(n-1)*(n-2)*...*2*1. Here is the code that the company has developed for this purpose. int factorial(int n) { int i; int result = 1; for ( i = n ; i > 0 ; i--) result = result * i; return result; } The company nds that this function performs fairly well. However, the company wants to do better. Market research shows that most of the companys customers are interested in a factorial function (n!) where n < 100. Of course, one of the companys programmers has taken the one and only, simply amazing 18-349 course at CMU and knows all the nest optimizations in the world. He generates the following code. int myFineFactorial (int n) { int i; int result = 1; for ( i = n ; i > 0 ; i -= 2) result = (result * i) * ( i - 1 ); return result; } (A) What is the name for this optimization? (2 points)

(B) Unfortunately, this programmer had slept through half of the 18-349 lecture when Priya talked about optimization. So, he inadvertently introduced a bug in the myFineFactorial() function. What is the bug? (2 points)

(C) How would you x this bug? You dont need to write the entire function here. Just write down the x that you would make. (2 points)

(D) Being from CMU, our programmer simply doesnt give up. After doing some analysis of customer data, he nd that some inputs are more common than others. He nds that customers use an n of 0, 1, and 5 most often. How would our CMU friend now further optimize the bug-free version of myFineFactorial() from part (C) above? Write the entire new program here as the new myPhenomenalFactorial() function. (10 points) int myPhenomenalFactorial (int n)

3. Here is an assembly program that runs on an ARM/XScale processor such as the gumstix. We have edited out the parts that are not all that relevant (e.g., the alignment operations).

.LC0: .ascii "sillyFunction returns %d00" .text .global main main: str lr, [sp, #-4]! mov r0, #520 add r0, r0, #2 mov r1, #255 bl sillyFunction mov r1, r0 ldr r0, .L2 bl printf ldr pc, [sp], #4 .L2: .word .LC0 .global sillyFunction sillyFunction: mov r0, r0, asl #2 b lr What do you expect to see on the screen when this program runs? Justify your answer, or you will not receive the points. (10 points)

4. Rewrite the following high-level program in ARM assembly language. Try to write code that is as optimized as possible. You do not need to worry about generating code with the GNU assembler primitives. We are only looking for a sequence of ARM assembly instructions. (15 points) int yetAnotherFunction(int x, int y) { if (x >= 0 && y >= 0) return (x+y); else if (x >= 0 && y < 0) return (x-y); else if (x < 0 && y >= 0) return (y-x); else return (x-y); }

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