DIGITAL ELECTRONICS COURSE, SPRING 2008

Switch Level Simulation

Mohammad Reza Najafi 810184285

AbstractThis report consider logic of some gates like NOR, NAND, XOR, INVERTER (NOT), MUX 2 to 1 and also DLATCH and D-FLIPFLOP constructed from above gates.

other words, it produces a value of true if and only if at least one of its operands is false.

I. INTRODUCTION

Fig. 3. NAND symbol [1].

ost important subject in of digital electronic components is that the component work true functionally and other parameters are in lowers degree of importance.Here well simulate functionally some logical components with CMOS technology in VERILOG language. Well consider NOR, NAND, XOR, INVERTER (NOT), MUX 2 to 1 in A section and D-LATCH and D-FLIPFLOP in B section and results will be available in appendix part. II. SOME NOTES

INVERTER: In digital logic, an inverter is a logic gate which inverts the digital signal driven on its input. It is also called NOT gate [1].

Fig. 4. NOT symbol [1].

A. Sections NOR Logic Gate: In boolean logic, logical nor or joint denial is a truthfunctional operator which produces a result that is the inverse of logical or. That is, a sentence of the form (A NOR B) is true precisely when neither A nor B is true.

MUX 2 to 1: In electronics, a multiplexer is a device that performs multiplexing; it selects one of many analog or digital input signals and outputs that into a single line [1].

Fig. 1. NOR symbol [1].

Fig. 5. MUX 2 to 1 symbol [1].

XOR Logic gate The XOR gate (sometimes EOR gate) is a digital logic gate that implements exclusive disjunction. A HIGH output (1) results if one, and only one, of the inputs to the gate is HIGH (1). If both inputs are LOW (0) or both are HIGH (1), a LOW output (0) results [1].

B. Section D-LATCH: It is also known as transparent latch, data latch, or simply gated latch. It has a data input and an enable signal (sometimes named clock, or control). The word transparent comes from the fact that, when the enable input is on, the signal would propagate directly through the circuit, from the input D to the output Q.

Fig. 2. XOR symbol [1].

NAND Logic gate: The NAND operation is a logical operation on two logical values, typically the values of two propositions, that produces a value of false if and only if both of its operands are true. In
Submitted May 3, 2008.

Fig. 6. D-LATCH symbol [1].

DIGITAL ELECTRONICS COURSE, SPRING 2008 IV. RESULTS NOR gate result: Input A 0 0 1 1 Input B 0 1 0 1 Output 1 0 0 0

Fig. 7. D-LATCH structure [1].

Fig. 11. Truth table of NOR [1].

Master-slave D flip-flop: The Q output always takes on the state of the D input at the moment of a rising clock edge, and never at any other time. [4] It is called the D flip-flop for this reason, since the output takes the value of the D input or Data input, and Delays it by one clock count. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line.

Fig. 8. D-FlipFlop symbol [1]. Fig. 12.NOR architecture [3].

NAND gate result:

Fig. 9. Master-slave D flip-flop [1].

Edge-triggered D flip-flop:

Fig. 13. Truth table of NAND [1].

Fig. 10. Edge-triggered D flip-flop [1].

III. METHODOLOGY Basic of this report is on gate level architecture but here is some transistor designs too. In prior reports we worked on transistor level with more depth.
Fig. 14. NAND architecture [1].

DIGITAL ELECTRONICS COURSE, SPRING 2008 NOT gate result:

Fig. 15. Truth table of NOT [1]. Fig. 19. NAND architecture [1].

D-latch result:

Fig. 16. NOT architecture [1]. Fig. 20. Truth table of D-LATCH [1].

XOR gate result: D flip-flop result:

Fig. 21. Truth table of D

flip-flop [1].

V. SUMMARY AND CONCLUSION

Fig. 17. Truth table of XOR [1].

MUX gate result: Input c 0 1 Output Input d0 Input d1

The basic concept from this report was design of logic circuit independent of electronic challenges. We should remember in stages of design a component put the complexity of every stage on its place, in this way there will be a clear steps for design. REFERENCES
[1] [2] [3] http://en.wikipedia.org. www.sccs.swarthmore.edu/.../engin/e77vlsi/lab3/ www.cs.uiowa.edu/~jones/assem/notes/08arith.shtml

Fig. 18. Truth table of MUX 2 to 1 [1].

DIGITAL ELECTRONICS COURSE, SPRING 2008

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