A NEW METHOD TO STABILIZE HIGH FREQUENCY HIGH GAIN CMOS LNA

Seyed Hossein Miri Lavasani, Student Member: Sayfe Kiaei, IEEE Fellow
Telecommunications Research Center, Arizona State University, AZ 85287-7206 USA ABSTRACT A new technique to improve stability of high frequency high gain CMOS Low Noise Amplifiers (LNA) has been introduced. A 0.18 um CMOS LNA for WLAN 5.2 GHz is designed and its performance is compared to typical CMOS cascode LNA for the same frequency. New filter architecture at load has caused a sharp notch in in-hand S12 of the LNA. This method significantly increases the stability of the LNA while benefits from the high forward gain (16.6 dB) and low noise figure (1.4 dB) ofthe cascode topology. New LNA shows input IP3 of 0.6dBm while consumes 9mA out of 1 .8V supply voltage. used in LNA design. This extra stability is achieved through providing a low-impedance path for the signal coming back to the input of the LNA from the output that provides a notch in S12. As a result, SI2 has been decreased by about 20dB in comparison with a typical cascode S I 2 of about-35dB at52 GHz. The section on LNA Design Approach explains LNA design approach and new filtering architecture used to increase the stability of the LNA. A brief explanation of the noise factor of the LNA is presented in the section for noise factor. The next section provides nonlinear simulation results performed by Cadence.

2. LNA DESIGN APPROACH

In this section, the method to stabilize a typical cascode CMOS LNA is presented.
2.1. Topology

1.

lNTRODUCTION

The design of the LNA is one of the most critical tasks in building an RF front-end, as the LNA has the maximum contribution towards setting the overall Noise Figure of the system [I], [2]. Advances in CMOS technology continuously shrink the geometries of transistors, leading to ever-higher levels of integration [3], [4]. Recent efforts have concentrated on pushing CMOS LNAs to work at higher frequency bands for newer generation wireless systems. One of the current issues that prevent CMOS processes to be used in the design of very high frequency CMOS LNAs is the stability of the LNA as an amplifier in the higher band. This problem gets more severe when the designer has to meet high gain and low voltage requirements too. One of the most popular topologies used for the design of CMOS LNAs is cascode topology. While cascode topology provides almost minimum noise figure and high gain at the deshed frequency, it shows less stability at high frequencies (e.g. more than 5 GHz). The most important reason is that the impedance asscociated with the parasitic capacitors of the MOS device, cgd, cannot be neglected as usual. To ensure enough stability for the LNA, designer usually has to do a trade-off between gain and stability of the circuit. Throughout this paper, a new filtering technique to help increasing the stability of the LNA at the desired frequency while not sacrificing the gain of the LNA has been introduced and

Cascode architecture with inductive source degeneration is used for its high gain, almost minimum noise figure. Although Cascode device provides some isolation between input and output that increases the stability, the LNA becomes less stable when the operation frequency approaches to fT of the device. To increase the stability, a small inductor is used in the gate of the cascode device, as shown in Figure I, to shape the reverse gain (S12).

I
Figure 1. LNA Topology

0-7803-8163-7/03/$17.00 0 2003 IEEE

ICECS-2003

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2.1. lnput Impedance and Gain Transfer Function

Simple inductive source degeneration is used to realize the optimum noise figure and match the input to real impedance at desired frequency hand. Neglecting the gate drain capacitances, the input impedance of the LNA shown in Figure 1 is:

cascode, LZ,does not affect the gain of the amplifier from a typical cascode topology. The expression for Voltage Gain can be derived using small signal model of CS amplifier assuming that bulk is ac-grounded. Neglecting body effect, gate drain capacitance and considering optimized NI' condition:
(4)

By appropriate choice of C,,,

L,,Ls, it is possible to

Where

ZL= Lp.s 11 (cp.s)-'i!i

the impedance of LC tank

decrease the sum their impedances to its smallest real part, R _in for the best power matching. Minimizing R ~n also s helps minimizing the overall noise figure of LNA a it is described in the section for Noise Figure (NF). If R ~n is considered to be small which is usually the case, and therefore can he neglected, it can be proven that , h can be matched to a real valued impedance (typically ? 5 O Q ) by choosing L such that:

and ZSin the impedance of source induclorLs To maximize gain at the frequency of interest, it is desirable to use a resonant load at the output. This resonant circuit provides high impedance at desired frequency. Therefore, the output impedance of amplifier used in gain calculation will be maximized. LC tank has been used as load.

2.3. Stability
The stabilitv factor of an amnlitier is defined as:

and Lz such that:

( L pfL.).C,, = 1
As technology improves, ?T increases -this leads to a reduction in inductor 5. size, making the system more suitable for on-chip integration. For our design, the value of LS is about 0.5nH that can be easily achieved by bond wire inductors. The most important advantage of bond wire inductors is their high Q at microwave frequencies (as high as 20 at 5GHz in CMOS process). Having high Q and small value, the thermal noise associated with its parasitic resistor can be easily neglected. A 1.8nH spiral inductor for Lg provides proper matching condition at the desired band. Simulation results in cadence with accurate models for inductors show SI I ofabout-15dB in the whole band. Considering the small signal model of the circuit shown in Fig. 2, it can be seen that due to the small value of gate drain capacitance of cascode device, the effect of gate inductor LZcan be approximately ignored on the output impedance of the circuit. The signal path from node X to output consists of two parallel paths shown in Figure 2, the first one only includes the voltage controlled current source, @.Vi and the second one includes gate source and gate drain capacitances of the cascode device. This path has very high impedance. Therefore, the signal wave travels from node X to output node using the first path. Therefore, the impedance seen from output node is the impedance seen due to the first path in parallel with the impedance seen from the second path that can be ignored due to inherent high impedance of gate drain capacitance. Since the gain of the amplifier equals to the transconductance of the amplifier multiplied by the impedance seen from the load (output impedance), it can then be concluded that the added inductor at the gate of the

Where A = SI 15'22 - Si?Szi, LNA will be unconditionally stable when K > 1,1 A 1. The input and output are matched to !source and load impedance, respectively. Therefore, their value can be well approximated as 0. Here, it is desirable to decrease S12 of the LNA to improve stability of the LNA. When SI2 decreases, Si?szi decrease!;. Since 1 A I< 1 for typical

cascode structure, I A lwill be even less fix this case. Considering ( 5 ) and the fact that LNA is matched at both input and output, when SI2 decreases but S21 is kept constant, the stability factor, K, will increase. Therefore, the LNA will be more stable. Putting the notch frequency of SI2 at the center frequenoy of LNA will provide maximum stability at highest ga.in, unlike usual case that stability decrease when gain is increased. According to (9,20dB decrease in SI2 will result in ten times increase in stability factor. Stability factors for two cases (with and without cascode gate inductor,L=)have been shown in Figure 4. This method can be used to stabilize any kind of CMOS amplifier that has hand pass transfer function. It can also be generalized to improve the stability of other type of CMOS amplifiers such as LP or HP amplifiers. To decrease the reverse gain (Sl2) as much as possible, it is desired to shaps SI2 to get more isolation between input and output at desired band while maintaining high gain and low noise feahues ofthe circuit. This has been done by means of adding a simple low value inductor in the gate of the cascode device as shown in Figure 1. This inductor along with inherent capacitors of the device will provide a low impedan'cepath at desired band for signal that comes from output to ground,

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preventing it to leak back to the input. In other words this LC network will provide a zero in reverse transmission path to reduce the effect of output signal at the input of LNA. The simplified small-signal equivalent circuit of the is LNA has been shown in Figure 2. The impedance, Z, the equivalent impedance seen from the drain of the input transistor while input is shorted to ground. This method when used in cascode topology will help further decreasing the reverse gain of the LNA at desired band without decreasing the forward gain. The transfer function, H ( s ) = -

F=l+lI+E(Z,+(~~,)-1+w~d/2
g,'

i2 n
.

I( G x ) I

4 2

Ir

(n
the

Where Y , is the admittance of input source voltage, Z g is the impedance of gate inductor&, Z = (wZ,)-'is ,, impedance associated with gate source capacitance of the device and ind is the noise associated with MOS drain. Due to high gain of input device, cascode device does not contribute to the noise figure by a considerable amount, therefore, the noise factor of cascode topology can be approximated as that of a simple common source structure. 7, According to ( ) to minimize noise figure, one must minimize the sum of , Z,, and ZS . =& I

H (s) = ZL 11

(6) l]zS Velocity saturation in short-channel devices sets the C,C8*LS.S' + 2 g ~ c ~ L ~ s ' + g ~ ( c ~ ~ + g ~ L = ) . s + g ~ - g ~limit for g m , allowing the NF to he optimized for the upper z
cgd(cg.S

Looking at real axis in Figure 3, it can be seen that the real part of the zero is between two poles. This type of polelzero location in the T.F. will result in a notch in I H ( s ) I spectrum at h e frequency of zero. Since SI2 is proportional to 1 H(s) a notch will appear in SI2 too.
Cgd

F;-y
+ gm)[-2c&.Sz
- g&.S

V,.(s)

Jw he written as: ,can

+ gm-

z ,

maximum gmwith the lowest power dissipation. Then, the

1,

optimum device width to optimize NF can he found [I]. Computer simulation has been done to find the optimum value for since Z, is not completely resistive. Resistive part of input impedance includes parasitic resistances associated with L g and L, inductors. Since LSis a small bond wire inductor, its parasitic resistance can be neglected, so to have lower noise figure, it is desired to reduce the value of onship inductor, LE.Increasing W of the input device will result in higher power consumption that in velocity saturation corresponds to an almost fixed trans-conductance. Therefore, the noise figure of the device will not change, however, this increase in W will result in the increase in cgsof the device that in turns

VX
i . .

/ . - A
5

zr

Figure 2. SrnaU-Signal equivalent circuit ofLNA

leads to a reduction in the value of 4 . Using this technique, a NF of less than 1.5 dB can he achieved for the drain current of 9mA out of 1.8 V supply. Another important advantage of this method is that since the value of Lg is low, the parasitic resistance associated with it will he small although it is an on-chip low Q (Q 4 0 ) inductor. Therefore, the performance of the LNA after fabrication will be close to what is shown in simulation.
4.

SIMULATIONRESULTS

Figure 3. PolelZero location for simplified T.F,

3. NOISE FACTOR For a typical common source amplifier the expression for noise figure will be [5]:

Simulation results show SI 1 of less than -14dB over the entire bandwidth. The circuit is unconditionally stable over the whole frequency range with absolute gain of more than 1. S21 and SI2 plots have been shown in Figure 5 . LNA shows more than 16.6 dB gain at 5.25 GHz (center frequency) while gives a very low reverse gain of more than -50 dB in the worst case at desired frequency hand. The zero location has been modified to achieve stability over the whole frequency range of amplification.

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Table 1. LNA performance

5.25

5 (1.05 GHz
-53.2

Minimum In-band
Devices DC Power

26. I
0.18pm CMOS

Figure 4. Nonlinear Simulation results for NF

5.

CONCIXJSION

..
, ,

.., ,

, , ,

.. .

, , ,

.,,.

.,..

, .,.

m
.
, , ,,

, , , ,

, , , , ,

.
,, ,,

, ,,, ,

.,,
,

, .,.

..
, ,

Figure 5. Simulated SI2 and S21 of LNA

This work presents a new CMOS LNA for WLAN 5.2 GHz applications. Forward gain of above 165dB and reverse d gain (S12) of less than -50 4 B have been achieved in desired frequency hand, with Noise Figurq: below I .4dB. A new filtering architecture has been used at the load of LNA to increase the stability of the LNA by decreasing S I 2 of the LNA while keeping forward gain at high level. This method can he used to stabilize any kind of CMOS hand pass amplifier. New circuit technique used in this work in conjunction with improvements in CMOS technology makes it possible to design high gain, stable CMOS LNAs for high frequency cellular applications (millimeter-wave app1ications:l. Future work can be directed on employing this technique in design of tunable LNAs where the frequency ofoperation varies over a wide range.

LNA shows a low value for Noise Figure (NF). The value for NF is less than 1.4 dB at 5.25 GHz. Its because of maximizing the gain at the output while minimizing the value of NF and parasitic resistance associated with input matching circuit using small inductors. 4 can be realized with multi-layer spiral inductor. Since the value of this inductor is small (less than 2nH), the associated parasitic resistance will be small even when the inductor Q is low (less than IO). Therefore, the NF does not increase significantly. Nonlinear noise has been included in results obtained with Cadence. Noise performance of the circuit has not been affected by adding an inductor to the gate of cascode device since the forward transmission gain of the LNA has not being affected. Careful consideration and adjustments on the gain has resulted in an excellent IP3 for the LNA. Two-tone harmonics simulation shows IP3 for the LNA. The input IP3 of more than O.6dbm has been shown. The most important reason is that the biasing of cascode device has been done such that the voltage maximum output voltage swing is achieved for the given gain and NF.

6 REFRENCFS .
[I] Shaeffer, D.K.; Lee, T.H, A 1.5-V, I.I,-GHz CMOS low
noise amplifier, IEEE J m r m l qf Solid-Sfare Circuics, Volume: 32 Issue: 5, May 1997 Page($: 145 -759

[2] Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge Uuiversity Press, 2001
[3] Leroux, P.; Janssens, I.; Ste:(aert, M, A 0.8-dBNF ESDProtected %mW CMOS LNA operating at 1.23 GHz [for GPS receiver], IEEE J o w l o Solid-Sute Cir.cuiLv, Volume: 37 f Issue: 6, June 2002 Page@):760 -765

[4] Gramegna, G.; Papam, M.; Erratico, P.G.; D Vita, P, A e sub-I-dB NF/spl plusmd2.3-kV ED-protected 900-MHz f icis CMOS LNA, IEEE Journal o Solid-Sure C r u t ,Volume: 36 Issue: 1,July2W1 Page(s): 1010--1017.
[5] Hashemi, H.; Hajimiri, A, Concurrent multkband lownoise amplifiers: theory, desip,& and applications, IEEE Transactions on Microwave Theojy and Techniques, Volume: 50 Issue: I Part: 2 Jan. 2002 Pape(s): 288 -301

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