Circuit Diagram CE Amplifier with Fixed Bias

Pin Diagram Bottom view of BC107

B E C

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Ex. no: Date: Aim

1. COMMON EMITTER AMPLIFIER WITH FIXED BIAS

To design and construct BJT Common Emitter Amplifier using fixed bias . To measure the gain and to plot the frequency response and to determine the Gain Bandwidth product (GBW). Apparatus Required S.No 1. 2. 3. 4. 5. 6. Equipments / Components Power Supply Resistor Capacitor Transistor AFO CRO Range / Details (0 30) V Qty 1

BC 107

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5.1 K , 3M

1 1 1 1 1

Fixed Bias with Emitter Resistor

The fixed bias circuit is modified by attaching an external resistor to the emitter. This resistor introduces negative feedback that stabilizes the Q-point. From Kirchhoff's voltage law, the voltage across the base resistor is VRb = VCC - IeRe - Vbe

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(0 1) MHz (0 20) MHz

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Tabulation

Frequency (Hz)

Vo (V)

Gain = Vo / Vs

Gain = 20log(Vo/Vs)dB

Model Graph

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From Ohm's law, the base current is Ib = VRb / Rb. The way feedback controls the bias point is as follows. If Vbe is held constant and temperature increases, emitter current increases. However, a larger Ie increases the emitter voltage Ve = IeRe, which in turn reduces the voltage VRb across the base resistor. A lower baseresistor voltage drop reduces the base current, which results in less collector current because Ic = IB. Collector current and emitter current are related by Ic = Ie with 1, so increase in emitter current with temperature is opposed, and operating point is kept stable. Similarly, if the transistor is replaced by another, there may be a change in IC (corresponding to change in -value, for example). By similar process as above, the change is negated and operating point kept stable. For the given circuit, IB = (VCC - Vbe)/(RB + (+1)RE). Merits:

Demerits:

In this circuit, to keep IC independent of the following condition must be met:

Usage: The feedback also increases the input impedance of the amplifier when seen from the base, which can be advantageous. Due to the above disadvantages, this type of biasing circuit is used only with careful consideration of the trade-offs involved.

As -value is fixed for a given transistor, this relation can be satisfied either by keeping RE very large, or making RB very low. If RE is of large value, high VCC is necessary. This increases cost as well as precautions necessary while handling. If RB is low, a separate low voltage supply should be used in the base circuit. Using two supplies of different voltages is impractical. In addition to the above, RE causes ac feedback which reduces the voltage gain of the amplifier.

which is approximately the case if ( + 1 )RE >> RB.

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The circuit has the tendency to stabilize operating point against changes in temperature and value.

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Design Choose = 250, VCC = 12V, IC = 1 mA By applying KVL to output side, VCC ICRC VCE = 0 VCC = ICRC VCE Assume equal drops across RC and VCE VRC = VCE = 6V, ICRC = 6V RC = 6V/10-3 = 6K Choosing a standard value for RC as 5.1 By applying KVL to the input side, VCC IBRB VBE = 0 IB = IC/ = 1mA/250 = 4A RB = (VCC VBE) / IB = (12 0.7)/4x10-6 = 2.825M 3M Design of input capacitor F = 1/2hieC Take F = 100Hz and hie = 1.6 K C1 = 1/ (2 X 1.6 K X 100) = 0.9F 1F

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Calculation Bandwidth = fH - fL

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Procedure 1) Connect the circuit as per the circuit diagram 2) Set Vin = 50mV in the signal generator. Keeping input voltage constant, vary the frequency from 1Hz to 1MHzin regular steps. 3) Note down the corresponding output voltage. 4) Plot the graph: Gain in dB Vs Frequency in Hz. 5) Calculate the Bandwidth from the Frequency response graph

To plot the Frequency Response 1) The frequency response curve is plotted on a semi-log scale.

frequency response curve.

4) The lower frequency point is called the lower 3dB point.

The bandwidth is found to be __________________

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the frequency response curve is plotted.

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Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and

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Result

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6) From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH - fL

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scale gives the bandwidth of the amplifier.

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5) The difference between the upper 3dB point and the lower 3dB point in the frequency

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3) The high frequency point is called the upper 3dB point.

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2) The mid frequency voltage gain is divided by 2 and these points are marked in the

Circuit Diagram CE Amplifier with Self Bias

Ex. no:

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2. COMMON EMITTER AMPLIFIER WITH SELF BIAS

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Date:

Frequency (Hz) Aim

Vo (V)

Gain = Vo / Vs

Gain = 20log(Vo/Vs)dB

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias) with and without bypassed emitter resistor. To measure the gain and to plot the frequency response and to determine the Gain Bandwidth product (GBW). Apparatus Required

1. 2. 3. 4. 5. 6.

Power Supply Resistor Capacitor Transistor AFO CRO

(0 30) V

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S.No

Equipments / Components

Range / Details

Qty 1 1 1 1 1 1

1K , 61K , 10K , 4.7K 1 F

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Theory

Voltage divider bias (Self bias) A combination of fixed and self-bias can be used to improve stability and at the same time overcome some of the disadvantages of the other two biasing methods. One of the most widely used combination-bias systems is the voltage-divider type. The voltage divider is formed using external resistors R1 and R2. The voltage across R2 forward biases the emitter junction. By proper selection of resistors R1 and R2, the operating point of the transistor can be made independent of . In this circuit, the voltage divider holds the base voltage fixed independent of base current provided the divider current is large compared to the base current. However, even with a fixed base voltage, collector current varies with temperature (for example) so an emitter resistor is added to stabilize the Q-point. However, to provide long-term or dc thermal stability, and at the same time, allow minimal ac signal degeneration, the bypass capacitor (Cbp) is placed across R3. If Cbp is large enough, rapid signal variations will not change its charge materially and no degeneration of the signal will occur. Merits

Unlike above circuits, only one dc supply is necessary. Operating point is almost independent of variation. Operating point stabilized against shift in temperature.
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BC 107 (0 1) MHz (0 20) MHz

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Tabulation

Model Graph

Design
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Drop across RE (VRE) is assumed to be 1V. Drop across VCE with the supply of 12V is given by 12V 1V = 11V Assume equal drops across ICRC and VCE So ICRC = VRC = 11/2 = 5.5V Assume IC = 1 mA, Then RC = VRC / IC = 5.5V / 1mA = 5.5 K Instead of using 5.5 K , we can use a standard value of 4.7 K VRE = 1V, IE IC = 1mA

Drop across VBE = 0.7V Drop across R2 (VR2) = VBE + VRE = 1.7V Assume R2 = 10 K VR2 = VCC.R2/ (R1+R2)

R1 = (12 X 10) / (1.7 10) = 60.5 K R1 is assumed to be 61 K

F = 1/2hieC

C1 = 1/ (2 X 1.6 K X 100) = 0.9F 1F

Calculation
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Take F = 100Hz and hie = 1.6 K

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Design of input capacitor

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Design of R1 and R2

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RE = VRE/IE = 1V/1mA = 1K

Bandwidth = fH - fL

Procedure To plot the Frequency Response

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1) The frequency response curve is plotted on a semi-log scale. 2) The mid frequency voltage gain is divided by 2 and these points are marked in the frequency response curve. 3) The high frequency point is called the upper 3dB point. 4) The lower frequency point is called the lower 3dB point. 5) The difference between the upper 3dB point and the lower 3dB point in the frequency scale gives the bandwidth of the amplifier. 6) From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH - fL

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency response curve is plotted. Bandwidth =

Circuit diagram:

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VCC = 12 V R1 8 K

- +
BC 107 47 F AFO 5 mV a R2 10 K RE 6 K + 47 F

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VO (CRO)

Ex. no: Date: Aim:

3. COMMON COLLECTOR TRANSISTOR AMPLIFIER

To design and construct BJT Common Collector Amplifier using voltage divider bias (self-bias). 2. To measure the gain and to plot the frequency response & to determination of Gain Bandwidth Product Apparatus required: 1. 2. 3. 4. 5. 6. Transistors Regulated Power Supply Audio Frequency Oscillator Resistors Capacitors CRO BC107

1.

Drop across RE is assumed to be VRE =6V Drop across VCE is VCC VRE =6V We know that ICQ =IE, Now RE = VRE = 6V = 6K IE 1X 10-3 Design of R1 & R2 Drop across RE is 6V Drop across VBE is 0.6V Drop across the resistance R2 is VR2 = VBE + VRE =6.6V Assume R2 =10K

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VCC R2 = 6.6 V R1 + R2 12 X 10 X 103 = 6.6V R1 + 10 X 103 120 X 103 = R1 + 10 X 103 6.6 18.18 X 103 = R1 + 10 X 103 R1 = 8 K (3.3 K + 4.7 K)
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Design: Since voltage amplification is done in the transistor amplifier circuit, we assume equal drops across VCE and Emitter Resistance RE. VRE = 6V. The quiescent current of 1mA is assumed. We assume a standard supply of Vcc = 12V.

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6K, 8K, 10K (all are W) 47F

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Tabular column Vs = Frequency (Hz) VO (Volts) Gain = VO / VS Gain = 20 log (VO/VS) (dB)

Model graph (frequency response)

A/max 3dB Line

Gain dB

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fH frequency (Hz)
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Procedure

1. Connect the circuit as per the circuit diagram. 2. Set VS = 5 mV using AFO. 3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular steps and note down the corresponding output voltage. 4. Plot the graph gain Vs frequency. 5. Calculate bandwidth from the graph.

Result

response curve is plotted. Bandwidth =

Specifications: 1. Transistor BC107, 50V 1A, 3W, 300 MHz 2. Regulated Power Supply (0- 30), 1A

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

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Circuit diagram:

VCC = 12 V R1 47 K RC 4.7 K + 47 F

- +
BC 107 47 F AFO 5 mV a R2 10 K RE1 4.7 K RE 1 K BC 107

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+ CE - 100 F

VO (CRO)

Ex. no: Date: Aim: 1. 2.

4. DARLINGTON COMMON EMITTER AMPLIFIER

To design a Darlington amplifier using BJT and to measure the gain and input resistance. To plot the frequency response and to calculate the Gain Bandwidth Product (GBW).

Apparatus required: 1. Transistors BC 107 2. Resistors 1K, 4.7K, 47K, 10K (all are W) 3. Capacitors 47F, 100F 4. CRO 5. AFO 6. RPS 7. Connecting wires & Breadboard

Assume R2 = 10K and Ic = 1mA. Since voltage amplification is done in the Darlington transistor amplifier circuit, we assume equal drops across VCE and load resistance RC. The ICQ = 1mA is assumed. We assume standard supply of 12V. Drop across Re is assumed to be 1V. The drop across VCE with a supply of 1.2 V is given by 12 1 = 1V. It is equal to VRC & VCE = 5.5V RC = VRC = 5.5 K (4.7 K) IC Design of R1 & R2: Drop across RE is 1V. Drop across VBE1 & VBE2 is 0.6V. Drop across the resistance R2 is VRE + VBE1 + VBE2

Tabular column:
~ 18 ~ EC2208 - Electronic Circuits I LAB

Biasing Design:

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This current will get double with every 100 rise in temperature. So to reduce the effect of ICBO the 1st stage ICBO flowing through the emitter of the 1st stage is not allowing to enter the 2nd stage by paralleling a resistor between B & E of the 2nd stage T2. So the ICBO(+1) will flow through this resistance and a part of this current might flow through hie + dcRE. This shunting resistance will be the range of 1 to 4.7 K.

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Such a DC the ICBO of the 1st stage is multiplied by (+1) times and this will be input Base current for the 2nd stage. Hence the 2nd stage IE current will be IE = (+1)2ICO For silicon transistor ICBO is the order of 10nA at room temperature = 100. Now, IE = (101)2 X 10 nA IE 105 nA 0.1mA

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Design:

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Vs = Frequency (Hz) VO (Volts) Gain = VO / VS Gain = 20 log (VO/VS) (dB)

Model graph (frequency response): Gain dB A/max 3dB Line

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fH frequency (Hz)
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= 1 + 0.6 + 0.6 VR2 = 2.2V R2 is assumed to be 10 K VCC R2 = 2.2V R1 + R2 1.2 X 10 X 103 = 2.2 R1 + 10 X 10
3

120 X 103 = R1 + 10 X 103 2.2 54.5 X 103 = R1+ 10 X 103 R1 = 54.5 X 103 10 X 103 R1 = 44.5 X 103 R1 is rounded to be 47 K Procedure:

Result:

Specifications: 1. Transistor BC107, 50V 1A, 3W, 300 MHz

2. Regulated Power Supply (0- 30), 1A

Circuit diagram:
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Bandwidth = fH - fL =

1. The frequency response curve is plotted on a log scale. 2. From the graph the bandwidth is obtained

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1. Connect the circuit as per the circuit diagram. 2. Set VS = 5 mV using AFO. 3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular steps and note down the corresponding output voltage. 4. Plot the graph gain Vs frequency. 5. Calculate bandwidth from the graph.

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Ex. no:

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5. COMMON DRAIN AMPLIFIER

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Pin Details

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Date: Aim: To design a common drain amplifier and to measure the gain, input resistance and output resistance with and without Bootstrapping. Apparatus required: 1. Transistor - BC-107 2. Regulated Power supply 3. Audio Frequency Oscillator 4. Resistors - 4.7K, 2.7K, 1M 5. Capacitor - 1 F 6. CRO 7. Bread board and connecting wires Bias design:

Theory:

Here input is applied between gate and source & output between source and Drain. Here Vs = VG + VGS. When a signal is applied to JFET gate via Cin,VG varies with the signal. As VGS is fairly constant and Vs varies with Vi. Here output voltage follows the change in the signal voltage applied to the gate, the circuit is also called as Source follower

Tabulation
~ 22 ~ EC2208 - Electronic Circuits I LAB

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VDD = 12 V, IDSS = 9.5mA, ID = 1mA, VP = -4V, Ci = 1F VGS = ID RS ,ID = IDSS{1-(VGS/VP)}2 RS = 2.7K , Voltage drop across R S = 2.7V VRD + VDS = VDD-VRS = 12-2.7=9.3V. Assume equal drops across VRD & VDS VRD = VDS = 4.65V RD = VRD/ID = 4.65K Instead of 4.65K, we can select standard value = 4.7K FET input is always reverse bias. So choose the value of resistance RG very large with in The range of 1M to 10M

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Frequency (Hz)

Vo (V)

Gain = Vo / Vs

Gain = 20log(Vo/Vs)dB

Procedure:
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Model Graph

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1. Connect the circuit as shown in the circuit diagram 2. Set Vs= 50 mv in AFO 3. Keeping the input voltage constant, vary the frequency from 0 Hz to1MHz in regular steps and note down the corresponding output voltage. 4. Plot the graph: gain Vs Frequency 5. Calculate the bandwidth from the Graph

Result: Thus a common drain amplifier is designed and the gain, input resistance and output resistance are calculated using the measured parameters.

Circuit Diagram Differential Amplifier

~ 24 ~ EC2208 - Electronic Circuits I LAB

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Common mode Configuration

Differential mode Configuration

Ex. no:

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6. DIFFERENTIAL AMPLIFIER
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Date: Aim To construct the Differential Amplifier in a) Common mode and b) Differential mode, and to find the common mode rejection ratio (CMRR). Apparatus required 1. 2. 3. 4. 5. Power Supply CRO Function Generator Transistors Resistors -

Formula C.M.R.R = Ad/Ac

Higher the value of C.M.R.R, better the performance of the differential amplifier. To improve C.M.R.R we have to increase differential mode gain and decrease common mode gain

Theory The Differential amplifier amplifies the difference between two input voltage signals. Hence it is called differential amplifier.V1 and V2 are input voltages, Vo is proportional to difference between two input signals. If we apply two input voltages equal in all respects then in ideal case output should be zero. But output voltage depends on the average common level of the inputs. Such an average level of two input signals is called common mode signal

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Ad = Differential mode gain Ac = Common mode gain

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C.M.R.R in dB = 20 log Ad/Ac

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BC107 1K 470

-1 no - 2 nos. -1 no.

Model Calculation For common mode signal Gain Ac = Vo / Vi Ac =

For differential mode signal Gain Ad = Vo / Vi Ad =

CMRR = 20 log (Ad / Ac) =

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Procedure 1. Connections are given as per the circuit diagram 2. Set Vi=5mV and note down Vo in both differential mode & common mode 3. Calculate the gain for both the modes 4. Calculate C.M.R.R Formulae

For common mode signal: Gain Ac = Vo / Vi For differential mode signal: Gain Ad = Vo / Vi

Result Thus a differential amplifier is constructed in both common mode and differential mode and the corresponding gains are obtained and the CMRR is calculated. CMRR =

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Common Mode Rejection Ratio: CMRR = 20 log (Ad / Ac)

Circuit diagram:

Vcc=12V

Rc = 4.7K R1 = 61K

CRO

100F -

3-d view

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Pin Diagram

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Vi= 10mv `

R2= 10K RE 1K

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1F - +

Ex. no: Date: Aim

7. CLASS - A AMPLIFIER

To design and construct a Class A power amplifier. To observe the output waveform and to measure the maximum power output and to determine the efficiency Apparatus required: 1. 2. 3. 4. 5. 6. 7. Transistor BC107 1 Resistors 1K,4.7K,61K,10K(all are watts) Capacitors 1f,100f(all are electrolytic) CRO (0-20MHz) AFO (0-1MHz) Regulated Power Supply Breadboard & Connecting Wires

Bias design: Since voltage amplification is done in the transistor amplifier circuit, We as equal drops across VCE & load resistance RE. The quiescent current of 1mA is assumed, we assume a standard supply of 12V. Drop across RE is assumed to be 1V,the drop across VCE with a supply of 12V is given by 12V1V=11V It is equal to 11/2=5.5V Now the voltage across the resistance RE is 5.5V VCE = 5.5V VC = 5.5V IC = 1mA RC = 5.5V/1mA = 5.5K Instead of using 5.5K , We can use a standard value of 4.7K. It is assumed that RBB / (dc+1) = RE / 10 Hence RBB / (dc+1) is neglected when compared RE. Hence VBB = IERE+VBE Hence VBE is neglected when compared to IERE Hence IE = VBB / RE. DESIGN OF R1 & R2: Voltage drop across RE = VRE = 1V Drop across VBE = 0.7V Drop across the resistance R2 = VBE +VRE = VR2 VR2=1.7V ; R2 is assumed to be 10K VCCR2 / (R1 + R2 ) = VR2 10*12K/(R1+10K)=1.7V R1=60.5V61K

Model graph:
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gain (dB)

A 0.707 A

fL Tabular column: VI =

fh

f (Hz)

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Frequency (KHz)

V0 (mV)

Gain = V0 / Vi

Gain (dB) = 20 log V0 / Vi dB

Theory: The Power amplifier is said to be class-A amplifier if the Q-point & the input signal are selected such that the output signal is obtained for a full input cycle. For this, position of the Qpoint is approximately at the midpoint of the load line. For all the values of input signal, the transistor remains in the active region &never enters into cut-off or saturation region. When an a.c input signal is applied, the collector voltage varies sinusoidally hence the collector current also varies sinusoidally. The collector current flows for 360(full cycle)of the input signal. In other words, the angle of the collector current flow is 360 i.e. one full cycle. Procedure: 1. Connect the circuit as per the circuit diagram. 2. Set VS=10mV using AFO. 3. Keeping the input voltage constant, vary the frequency from few Hz to 1MHz in regular steps & note down the correspondingly output voltage. 4. Plot the graph: gain Vs frequency. 5. Calculate bandwidth from the graph.

Result: The class-A amplifier is designed, constructed and the output waveform is observed. The maximum power output and the efficiency are determined.

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Circuit diagram

Pin Diagram

Bottom view of BC 107 / BC 178

B E C

3-d view

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8. CLASS B POWER AMPLIFIER

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Date: Aim: To design and construct a Class B (complementary symmetry) power amplifier.To observe the output waveform with crossover Distortion and to measure the maximum power output and to determine the efficiency. Apparatus required: 1. Power Supply 2. CRO 3. Function Generator 4. Resistor 5. Transistors (0 30) V (0 20) MHz (0 1) MHz 47 K 1 K BC 107 BC 178

Procedure:

1. Connect the circuit as per the diagram. 2. Set VS = 50mV(say) using the signal generator. 3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz. In regular steps. Note down the corresponding output voltage. 4. Plot the graph i.e., gain (dB) Vs frequency (on a semi log graph)

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some advantages of the circuit are that the transformer less operation saves on weight and cost and balanced push pull input signals are not required. The disadvantage is obtaining pause of transistor matched closely enough to achieve low distortion.

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Theory: The figure illustrates a Class B Power Amplifier, which employs one PNP, and one NPN transistor and require no transformed. This type of amplifier uses complementary symmetry. i.e., the two transistor have identical characteristics but one is PNP and the other NPN. Its operation can be explained by referring to the figure. When the signal voltage is positive, T1 (the NPN transistor) conducts, while T2 (the PNP transistor) is cut off. When the signal voltage is negative, T2 conducts while T1 is cut off. The load current is

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1No 1No 1No 1No

EC2208 - Electronic Circuits I LAB

Model graph:

Tabular column: VI = 50 mV Frequency (KHz) V0 (mV)

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I = 1 mA Gain (dB) = 20 log V0 / Vi dB Gain = V0 / Vi

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Formulae

Efficiency, =

V min 1 4 Vcc

Powergain =

1 Vcc 2 2 2 RL

Result Thus a Class B (complementary symmetry) power amplifier is constructed and the output waveforms are observed and the maximum power output and efficiency is calculated.

Circuit diagram:
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Half Wave Rectifier without filter 12 1N 4007 230 V 0 12 500 R

a

+ Vdc -

+ -100 F /25V
a

Vac

12 1N 4007 230 V 0

12

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500 R

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100 F CRO - 25 V Vac
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Half Wave Rectifier with filter

Ex. no: Date: Aim

9. HALF WAVE RECTIFIER

1. To design a Half wave rectifier with simple capacitor filter. 2. To measure the DC voltage under load and ripple factor and to compare with calculated
values.

Apparatus Required 1. CRO 2. Multimeter 3. Diode 4. Transformer 5. Resistor 6. Capacitor 1N4007 (0-20 MHz)

500-1/4W(carbon film resistors)

7. Connecting Wires and Bread Board

observe the AC waveform of rated value without any distortion at the secondary of the transformer.

2. Connect the half wave rectifier as shown in figure. 3. Measure the Vdc & Vac using DC and AC Voltmeters.

Note: The rectifier output consists of both AC & DC components. To block DC component 100f (Electrolytic) Condenser is used. 5. Compare the theoretical ripple factor with the practical ripple factor.

4. Calculate the Ripple factor

.e

ee

ex

cl u

1. Test your transformer: Give 230v, 50Hz source to the primary coil of the transformer and

si

(i) Without Capacitor

r =

ve

Half wave rectifier

.b l
Vac Vdc
~ 38 ~

Procedure

og
EC2208 - Electronic Circuits I LAB

sp ot

100F /25V

.c o

230V / 12 0- 12v, 200 mA

Model Graph VI(v)

T(m sec)

Vo (V)

cl u

si

ve

.b l

og

sp ot
Without filter

With filter

.c o
T(m sec)

.e

ee

ex

Half Wave Rectifier Output

~ 39 ~

m
EC2208 - Electronic Circuits I LAB

Input Wave Form

(ii) With capacitor

1. Connect the half wave rectifier with filter circuit as shown in fig. 2. Assume r= 10% of ripple peak-to-peak voltage for R= 500. Calculate C using the formula r = 1/23fRC 3. Connect CRO across load. 4. Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the X-axis. 5. Switch the CRO into DC mode and observe the waveform.

Theoretical

ve

.b l
Practical
~ 40 ~

Ripple Factor

1. Diode 1N4007 2. RPS

Specifications:

.e

ee

ex

cl u

(700V- PIV, Idc = 1A) (0-30),1A

si

og
EC2208 - Electronic Circuits I LAB

sp ot

Thus the Full wave rectifier is designed with and without capacitor filter and the corresponding dc output voltages and the ripple factors are measured and verified with the theoretical values.

.c o

Result

Circuit diagram: Full Wave Rectifier without filter 12V D1 230 V D3 1N 4007 D4 R 500 + Vdc + 100 F - 25 V
a

D2

Vac

12V D1 230 V D3 1N 4007

si

ve

.b l
D2 D4 R + 100 F CRO 25 V
~ 41 ~

.e

ee

ex

cl u

og
EC2208 - Electronic Circuits I LAB

sp ot

Full Wave Rectifier with filter

.c o

Ex. no: Date: Aim

10. FULL WAVE RECTIFIER

1. To design a Full wave rectifier with and without simple capacitor filter. 2. To measure the DC voltage under load and ripple factor and to compare with calculated
values.

Apparatus Required 1. CRO 2. Multimeter 3. Diode 4. Transformer 5. Resistor 6. Capacitor 1N4007 (0-20 MHz)

500-1/4W(carbon film resistors)

7. Connecting Wires and Bread Board Procedure Full wave rectifier (i) Without Capacitor 1.

and observe the AC waveform of rated value without any distortion at the secondary of the transformer. 2. 3. 4.

Connect the full wave rectifier as shown in figure.

Calculate the Ripple factor

.e

Measure the Vdc & Vac using DC and AC Voltmeters.

ee

ex

cl u

Test your transformer: Give 230v, 50Hz source to the primary coil of the transformer

Note: The rectifier output consists of both AC&DC components. To block DC component 100f (Electrolytic) Condenser is used. 5. Compare the theoretical ripple factor with the practical ripple factor.

si

ve

r = Vac Vdc

.b l
~ 42 ~

og
EC2208 - Electronic Circuits I LAB

sp ot

100F /25V

.c o

230V / 12 0- 12v, 200 mA

Model graph: VI(v)

t (m sec)

VO (V)

.b l

og
Without filter

.e

ee

ex

cl u

si

Full Wave Rectifier Output

ve

t (m sec)

~ 43 ~

sp ot

.c o
With filter
EC2208 - Electronic Circuits I LAB

Input Wave Form

(ii) With capacitor:

1. To plot ripple peak-to-peak voltage Vs. Idc to choose C a ripple factor of 0.15 is assumed. 2. To get a variable load resistance a number of 500, 5W of resistance are to be connected in parallel. Hence Idc = Vdc /( N X 500). Where N is number of 500 resistances connected in parallel. 3. Plot the graph Idc Vs ripple peak to peak. 4. The above steps are repeated for the various values of capacitance.

Result Thus the Full wave rectifier is designed with and without capacitor filter and the corresponding dc output voltages and the ripple factors are measured and verified with the theoretical values. Ripple Factor Theoretical

.b l cl u
(700V- PIV, Idc = 1A) (0-30), 1A

og
Practical
EC2208 - Electronic Circuits I LAB

1. Diode 1N4007 2. RPS

.e

ee

Specifications:

ex

si

ve

~ 44 ~

sp ot

.c o