Implementing logic gates in CMOS

Logic gates are implemented via transistors. One popular technology for implementing transistors is Complementary Metal Oxide Semiconductor (CMOS) technology. Transistors effectively implement switches. There are two types of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), namely the n-channel (NMOS) and pchannel (PMOS) transistor. CMOS uses both NMOS and CMOS transistors to implement logic gates in a complementary way.

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Voltages and logic levels

Logic levels are represented with voltages. The logic level 0 is represented by the lowest voltage (GND) The logic level 1 is represented by the highest voltage (VDD) Transistors are used as switches to open or close and connect wires to either VDD or GND.

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NMOS transistor
Simplified NMOS transistor has 3 terminals: 1) the Gate (G); 2) the Source (S) and 3) the Drain (D). The source is at a lower voltage; The drain is at a higher voltage. When a high voltage is applied to G (w.r.t. to S) and VGS is above some threshold voltage VT the switch closes and D is connected to S (current flows from D to S). This pulls down the voltage at D to the voltage at S.

When the voltage between G and S is less than some threshold voltage VT the switch opens and D is disconnected from S (no current flows from D to S).

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PMOS transistor
Simplified PMOS transistor has 3 terminals: 1) the Gate (G); 2) the Source (S) and 3) the Drain (D). The source is at a higher voltage; The drain is at a lower voltage. When a low voltage is applied to G (w.r.t. to S) and VSG is above some threshold voltage VT the switch closes and S is connected to D (current flows from S to D). This pulls up the voltage at D to the voltage at S.

When the voltage between S and G is less than some threshold voltage VT the switch opens and S is disconnected from D (no current flows from S to D).

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CMOS structure
CMOS combines NMOS and PMOS transistors in a structure which consists of a Pull-Up Network (PUN) and a Pull-Down Network (PDN) to implement logic functions. PUN and PDN are duals of each other. A current path (connection) from VDD to VF means VF is high (f is logic 1) A current path (connection) from VF to GND means VF is low (f is logic 0). AND corresponds to transistors in series OR corresponds to transistors in parallel

!f

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CMOS inverter
When VX is high (logic 1): 1) NMOS is closed; 2) PMOS is open;3) current flows from VF to GND VF is GND (logic 0). When VX is low (logic 0): 1) NMOS is open; 2) PMOS is closed;3) current flows from VDD to VF VF is VDD (logic 1).

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CMOS NAND

!x + !y

4 transistors !(xy)

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CMOS NOR

!x!y

!(x+y) 4 transistors

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CMOS AND
Uses a CMOS NAND followed by a CMOS inverter

6 transistors

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Whats this?

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Transmission gates
When S is high (!S is low), both NMOS and PMOS are closed f = x. When S is low (!S is high), both NMOS and PMOS are open f is disconnected from x (high impedence).

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XOR (using transmission gates)

8 transistors

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