Advanced Digital Design Combinational Logic Design Sequential Logic Design State machines Advanced Design Issues Metastability

Noise margins Power Fan-out Design rules Skew Timing considerations System Architectures System Building Blocks Computer Architecture Memory Architectures Introduction to a system bus (PCI- Express) Introduction to a peripheral Introduction to LAN (Ethernet) Communication Fundamentals Few other topics of Industry relevance FPGA Architecture Architecture study of some popular FPGA families Detailed study of a Xilinx FPGA family( Virtex 6)

24 Hours

44 Hours 25Hours

19Hours

Architecture of Microcontrollers in FPGA( ARM)

The Backend tools Integrating Non-HDL modules : Building Macros Programming Fundamentals Introduction to C Arrays Functions Strings Structures & unions Introduction to C++ Classes & Objects Inheritance Virtual functions High Level Design Methodology HDL Simulation and Synthesis The concept of Simulation HDL Simulation and Modeling The Synthesis Concept Synthesis of high level constructs Timing Analysis of Logic Circuits Combinatorial Logic Synthesis State Machine Synthesis Efficient Coding Styles Hierarchical and flat designs Constraining Designs Partitioning for Synthesis Pipelining Resource sharing Optimizing arithmetic expressions Design reuse The Simulation and Synthesis Tools VHDL (In accordance with standard IEEE 1076-2008) Introduction to HDL VHDL Flow Language constructs Concurrent constructs 20 Hours

384 Hours 24Hours

360Hours

Sequential Constructs Subprogram Packaging Timing Issues Verilog (In accordance with IEEE 1364-2005 and 2009) Data types Modeling concepts, Task and Functions Specify block and Timing checks Verification and Writing test benche ASIC Design Issues

154 Hours

10 Hours

ASIC design flow Testability: Test principles, fault models, fault coverage, test vectors Design for test Reliability considerations Different technology options Power calculations Package selection Clock methodologies
CMOS VLSI Design Introduction to the MOS technology and fabrication process flow CMOS combinational logic design Design of Basic gates, transmission gates etc Design of complex logic Device sizing, timing parameters & estimation of layout resistance & Design rules for CMOS layout Introduction to layout and simulation tools Place and Route Extraction, LVS Netlist to GDS-II flow Device Generator Libraries Verification using SystemVerilog Introduction to Verification Types of verification Code coverage Introduction to SystemVerilog Introduction to task & functions in SystemVerilog OOPs Terminology Implementation of OOPs Concepts in SystemVerilog Randomization Case Studies Assertions property Assertions Time Functional Coverage Linux Shell Scripting Linux Commands Linux File System Vi editor The Shell Shell Programming 40 Hours

capacitance

86 Hours

30 Hours