J111, J112 JFET Chopper Transistors

NChannel Depletion
Features

PbFree Packages are Available*

MAXIMUM RATINGS
Rating Drain Gate Voltage Gate Source Voltage Gate Current Total Device Dissipation @ TA = 25C Derate above = 25C Lead Temperature Operating and Storage Junction Temperature Range Symbol VDG VGS IG PD TL TJ, Tstg Value 35 35 50 350 2.8 300 65 to +150 Unit Vdc Vdc mAdc mW mW/C C C

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1 DRAIN

3 GATE

2 SOURCE

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1 2 3

TO92 CASE 2911 STYLE 5

MARKING DIAGRAM

J11x AYWW G G

J11x = Device Code x = 1 or 2 A = Assembly Location Y = Year WW = Work Week G = PbFree Package (Note: Microdot may be in either location)

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2006

March, 2006 Rev. 2

Publication Order Number: J111/D

J111, J112
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Gate Source Breakdown Voltage (IG = 1.0 mAdc) Gate Reverse Current (VGS = 15 Vdc) Gate Source Cutoff Voltage (VDS = 5.0 Vdc, ID = 1.0 mAdc) DrainCutoff Current (VDS = 5.0 Vdc, VGS = 10 Vdc) ON CHARACTERISTICS ZeroGateVoltage Drain Current(1) (VDS = 15 Vdc) IDSS J111 J112 rDS(on) J111 J112 Cdg(on) + Csg(on) Cdg(off) Csg(off) 30 50 28 pF 20 5.0 2.0 W mAdc J111 J112 ID(off) V(BR)GSS IGSS VGS(off) 3.0 1.0 10 5.0 1.0 nAdc 35 1.0 Vdc nAdc Vdc Symbol Min Max Unit

Static DrainSource On Resistance (VDS = 0.1 Vdc) Drain Gate and Source Gate OnCapacitance (VDS = VGS = 0, f = 1.0 MHz) Drain Gate OffCapacitance (VGS = 10 Vdc, f = 1.0 MHz) Source Gate OffCapacitance (VGS = 10 Vdc, f = 1.0 MHz) 1. Pulse Width = 300 ms, Duty Cycle = 3.0%.

5.0 5.0

pF pF

ORDERING INFORMATION
Device J111RL1 J111RL1G J111RLRA J111RLRAG J111RLRP J111RLRPG J112 J112G J112RL1 J112RL1G J112RLRA J112RLRAG Package TO92 TO92 (PbFree) TO92 TO92 (PbFree) TO92 TO92 (PbFree) TO92 TO92 (PbFree) TO92 TO92 (PbFree) TO92 TO92 (PbFree) 2000 Units / Tape & Reel 2000 Units / Tape & Reel 1000 Units / Bulk 2000 Units / Tape & Reel 2000 Units / Tape & Reel 2000 Units / Tape & Reel Shipping

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

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J111, J112
TYPICAL SWITCHING CHARACTERISTICS
1000 t d(on), TURNON DELAY TIME (ns) 500 200 100 50 20 10 5.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 RK = 0 RK = RD J111 J112 J113 TJ = 25C VGS(off) = 12 V = 7.0 V = 5.0 V 1000 500 200 t r , RISE TIME (ns) 100 50 20 10 5.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 RK = 0 RK = RD J111 J112 J113 TJ = 25C VGS(off) = 12 V = 7.0 V = 5.0 V

Figure 1. TurnOn Delay Time

1000 t d(off), TURNOFF DELAY TIME (ns) 500 200 100 50 20 10 5.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 RK = 0 RK = RD TJ = 25C J111 J112 J113 VGS(off) = 12 V = 7.0 V = 5.0 V 1000 500 200 t f , FALL TIME (ns) 100 50 20 10 5.0 2.0 1.0 0.5 0.7 1.0 RK = 0

Figure 2. Rise Time

TJ = 25C RK = RD J111 J112 J113 VGS(off) = 12 V = 7.0 V = 5.0 V

2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA)

20

30

50

Figure 3. TurnOff Delay Time

Figure 4. Fall Time

NOTE 1
+VDD RD SET VDS(off) = 10 V INPUT RGEN 50 W 50 W VGEN RK RT OUTPUT RGG VGG 50 W

The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (VGG). The DrainSource Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or GateDrain Capacitance (Cgd) is charged to VGG + VDS. During the turnon interval, GateSource Capacitance (Cgs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (RD) and DrainSource Resistance (rds). During the turnoff, this charge flow is reversed. Predicting turnon time is somewhat difficult as the channel resistance rds is a function of the gatesource voltage. While Cgs discharges, VGS approaches zero and rds decreases. Since Cgd discharges through rds, turnon time is nonlinear. During turnoff, the situation is reversed with rds increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK is equal to RD, which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator.

INPUT PULSE tr 0.25 ns tf 0.5 ns PULSE WIDTH = 2.0 ms DUTY CYCLE 2.0%

RGG & RK RD(RT ) 50) RD + RD ) RT ) 50

Figure 5. Switching Time Test Circuit

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J111, J112
y fs, FORWARD TRANSFER ADMITTANCE (mmho 20 J112 10 J111 10 7.0 5.0 Tchannel = 25C VDS = 15 V C, CAPACITANCE (pF) J113 7.0 5.0 Cgd Cgs 15

3.0 2.0 0.5 0.7

3.0 2.0 1.5

Tchannel = 25C (Cds IS NEGLIGIBLE)

1.0

2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA)

20

30

50

1.0 0.03 0.05

0.1

0.3 0.5 1.0 3.0 5.0 VR, REVERSE VOLTAGE (VOLTS)

10

30

Figure 6. Typical Forward Transfer Admittance

Figure 7. Typical Capacitance

200 rds(on), DRAINSOURCE ONSTATE RESISTANCE (OHMS)

rds(on), DRAINSOURCE ONSTATE RESISTANCE (NORMALIZED)

IDSS = 10 160 mA

25 mA

50 mA

75 mA 100 mA

125 mA

2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 70 40 10 20 50 80 110 Tchannel, CHANNEL TEMPERATURE (C) 140 170 ID = 1.0 mA VGS = 0

120

80 Tchannel = 25C

40

1.0

2.0 3.0 4.0 5.0 6.0 VGS, GATESOURCE VOLTAGE (VOLTS)

7.0

8.0

Figure 8. Effect of GateSource Voltage On DrainSource Resistance

Figure 9. Effect of Temperature On DrainSource OnState Resistance

NOTE 2

100 rds(on), DRAINSOURCE ONSTATE RESISTANCE (OHMS) 90 80 70 60 50 40 30 20 10

9.0 8.0

rDS(on) @ VGS = 0 VGS(off)

7.0 6.0 5.0 4.0 3.0 2.0 1.0

VGS, GATESOURCE VOLTAGE (VOLTS)

Tchannel = 25C

10

The ZeroGateVoltage Drain Current (IDSS), is the principle determinant of other J-FET characteristics. Figure 10 shows the relationship of GateSource Off Voltage (VGS(off) and DrainSource On Resistance (rds(on)) to IDSS. Most of the devices will be within 10% of the values shown in Figure 10. This data will be useful in predicting the characteristic variations for a given part number. For example: Unknown rds(on) and VGS range for an J112 The electrical characteristics table indicates that an J112 has an IDSS range of 25 to 75 mA. Figure 10, shows rds(on) = 52 W for IDSS = 25 mA and 30 W for IDSS = 75 mA. The corresponding VGS values are 2.2 V and 4.8 V.

0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 IDSS, ZEROGATEVOLTAGE DRAIN CURRENT (mA)

Figure 10. Effect of IDSS On DrainSource Resistance and GateSource Voltage

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J111, J112
PACKAGE DIMENSIONS

TO92 (TO226) CASE 2911 ISSUE AL

A R P L
SEATING PLANE

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 0.250 0.080 0.105 0.100 0.115 0.135 MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 6.35 2.04 2.66 2.54 2.93 3.43

X X G H V
1

D J C SECTION XX N N

DIM A B C D G H J K L N P R V

STYLE 5: PIN 1. DRAIN 2. SOURCE 3. GATE

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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J111/D