ESSCIRC 2002

Rail-to-Rail Op Amp with using Replica Gain Enhancement

THD

Friedel Gerfers, Christian Hack Institute of Microelectronics University of Saarland gerfers,chhack@ee.uni-sb.de Abstract
This paper presents an architecture for a high-swing low-power fully differential class-AB amplier with a DC-gain of . A low-voltage differential input stage is applied as the basic architecture. The replica gain enhancement technique is used to increase the DC-gain by without degrading the output swing. Furthermore, this gain enhancement concept does not increase the minimal supply voltage and also allows scaling of the replica providing a amplier. The power dissipation is at a capacitive load gainbandwidth (GBW) of of and a THD of .

Maurits Ortmanns, Yiannos Manoli Institute of Microelectronics University of Freiburg maurits,manoli@imtek.de

1.

Introduction

In recent years the power supply of portable electronic systems diminished from several volts to approximately one volt. The main driving force for low-voltage CMOS design arises from the continuing trend towards deep submicron transistor dimensions with power supplies of [1]. Op amps for low-power high resolution A/D converters require high open-loop gain, high output swing and high GBW to minimize errors in the output voltage. Several techniques have been investigated with respect to these goals, e.g. cascade of amplier stages (two or multi-stage concepts), active or passive-cascoding, positive feedback [2], [3] or replica amplier gain enhancement [4]. The optimal method, that combines all requirements is the replica amplier gain enhancement technique [5].

and MA. The output voltage is already very close to the ideal output voltage with a nite gain error , where represents the DC open loop of gain. Since CA is connected in parallel to the RA, the coupling amplier generates the same current , which is introduced into the output resistance of the MA. Therefor, is also very close the ideal output voltage. Consequently, the MA has only to produce a very small error to bring even closer to the ideal output current voltage. is If output resistance mismatch is taken into account, no longer zero, the low frequency output voltage is given by (1) with the closed loop gain ment factor . Assuming plies to: and the gain enhanceEq. 1 sim-

2.

Replica Amplier Gain Enhancement

This concept (Fig. 1) does not degrade the output swing or increase the minimal supply voltage. Furthermore, it leads to a high gain op amp with a low power consumption due to the feasibility of scaling the replica amplier (RA). Fig. 1 shows the concept of the unscaled replica gain enhancement technique with the main amplier (MA) and the coupling amplier (CA). The RA and MA have the ). First assume . same feedback network ( The principle of the replica amplier gain enhancement technique works such that is applied to both RA

(2)

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with the error factor [4]. If is zero the error factor is approximately . Consequently, output resistance mismatch degrades the gain enhancement by the factor . Other sources of mismatch like or are negligible.

3.

Basic Amplier Architecture

In order to combine the low supply voltage and highswing requirements the differential input stage shown in Fig. 2 was used as the basic architecture [6]. The tranand form the input transistors which are sistors represents a loconnected in a cascode conguration. cal feedback loop so that measures the drain voltage of and feedbacks a current to the input node through . As a result, controls the current in the stage. This local feedback loop assures a low input impedance at node . Thus node can be deemed as virtual ground. The gate of is also connected to node . Consequently a proportional current is generated at the output of this differential input stage. Subsequently, it is necessary to determine the frequency behavior and the stability of the feedback conguration to ensure proper operation [6]. (the left branch of Fig. 2) by a current If you replace source, you obtain a low voltage current mirror with a low input impedance. This block is also necessary to understand the functioning of the complete op amp introduced in the following chapter.

two low voltage current mirrors, that obtain the required current by the transistors and . The output transistors of the input stages and the current mirrors ) form a push-pull ( output stage. The common-mode feedback circuit for stabilizing the common-mode voltage of the fully differential system is . Each amplier connected at the nodes has its own common-mode feedback.

5. Common-Mode Feedback Circuit

The CMFB uses the same basic architecture as the op amp, however the current sources are stacked with two PMOS transistors biased in linear region. These transistors measure the output common-mode voltage of the amplier and vary accordingly the bias currents and (see Fig. 4). This results in a variation of the node voltage and consequently in a modication of the CMFB output current. The current shift will set the amplier commonmode output voltage to the desired value.

6. Measuring Results
The amplier is implemented in a triple-well CMOS process, with and . The low-power op amp operates with a single supply voltage of and consuming only including the common mode feedback circuit. In Fig. 5(a) the magnitude and phase response are rep, the GBW is resented. The DC-gain is about at a capacitive load of approximately . Fig. 5(b) shows the results of a transient analysis with a input level of peak-peak around analog ground and a frequency of . The op amp - opof erating as a rst order low pass lter - drives a capacitive and a resistive one of . The effect of load of the replica concept is apparent, because even though both ampliers have the same , the amplication of the main amplier in the closed-loop conguration is higher than the amplication of the replica. If the amplication

4.

The Complete Structure Of The Op Amp

To realize the mode of operation of the op amp in Fig. 3, it is necessary to divide it in smaller structures. The main amplier is shown in the upper part, connected in parallel with the coupling amplier (grey box). The lower part represents the replica amplier with the dummy load (grey box) to match the output resistance to that of the MA, CA combination. Both the MA and the RA are built up in the same way. In the upper part of each amplier you can see two input stages, in the lower part

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of both ampliers is calculated with the following equation: (3) a gain benet between appears with depen. Comparing to the transfer function of dency on a single op amp the error factor has been reduced by the factor . In Fig. 5(c) the total harmonic distortion for two different and ) is represented. input frequencies ( The input level varies from to , at lower levels no distortion could be measured because the sensitivity of the measuring equipment only features a linearity the distortion of 14 bit. Even for a full scale input of is still around . In Fig. 5(d) the effect of the variation of at an input and a frequency of level of is shown. Increasing the supply voltage from to

the THD performance increases up to an optimum at . For all other values of the operof ating points differ from their ideal position and therefor a lower THD is the consequence.

Supply voltage Open loop DC gain Gain enhancement (dep. on Unity gain freq. Phase margin THD input noise voltage input noise voltage Power dissipation Core area

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0.1 0.08 0.06 0.04 0.02 0 0.02 0.04 0.06 0.08 0.1 0 0.05 0.1 0.15 0.2

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(a) AC response

(b) Transient response of the MA and RA

(c) THD of the MA

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(d) THD as a function of

(e) Input referred noise of the MA

(f) Chip photo

Fig. 5(e) shows the input referred noise of the MA. The corner frequency resides at about . The chip photo of the implemented operational ampliers with replica gain enhancement is shown in Fig. 5(f). The concept was implemented twice. The closed loop and the caversion including the resistors pacitors resides on the right. On the left side in the lower part the open loop amplier is presented with an area of . In addition to both ampliers two buffers are implemented for measuring purposes.

ment, the rail-to-rail input swing, the linearity and the low noise demonstrate that the proposed architecture is a good choice for low-voltage, low-power, high-swing amplier realizations.
[1] SIA. International technology roadmap for semiconductors., 1999. [2] E. Seevinck; et al. Active-Bootstrapped Gain-Enhancement Technique for Low-Voltage Circuits. IEEE Transactions on Circuits and Systems -II, September 1998. [3] M.M.Amourah; et al. Gain And Bandwidth Boosting Techniques For High-Speed Operational Ampliers. IEEE International Symposium on Circuits and Systems, ISCAS, pages 232235, 2001. [4] P. Yu; et al. A High Swing 2V CMOS Operational Amplier with Replica Amp Gain Enhancement. IEEE Journal of Solid-State Circuits, pages 12651272, December 1993. [5] F. Gerfers; et al. A 1.2-V Rail-To-Rail Low-Power Opamp With Replica Amplier Gain Enhancement. IEEE International Symposium on Circuits and Systems, ISCAS, 2002, accepted on. A/D Converter [6] V. Peluso; et al. A 900-mV Low-Power with 77-dB Dynamic Range. IEEE Journal of Solid-State Circuits, pages 18871897, December 1998.

7.

Conclusion

This paper has presented a novel architecture for a rail-to-rail low-power amplier. A low-voltage differential input stage was applied as the basic architecture. The replica gain enhancement technique was used to increase the DC-gain without degrading the output swing. Furthermore, this gain enhancement concept does not increase the minimal supply voltage and also allows scaling of the replica amplier. Experimental results have at a load capacitance shown a GBW of with a power consumption of including the common mode feedback. The amplier has been implemented triple-well CMOS technology. As a rein a sult the low-power consumption, the high gain enhance-

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