Chapt 14

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pt Copyright 2009 Texas I nst rument s, All Right s Reserved 14- 1

Chapt er 14
14. Communi cat i ons

The MSP430 cont ains built - in feat ures for bot h parallel and serial
dat a communicat ion. This chapt er describes t he operat ion of t hese
peripherals, and discusses t he prot ocols, dat a format s and specific
t echniques for each t ype of dat a communicat ion.
The communicat ion modules available for t he MSP430 family of
microcont rollers are USART ( Universal Synchronous/ Asynchronous
Receiver/ Transmit t er) , USCI ( Universal Serial Communicat ion
I nt erface) and USI ( Universal Serial I nt erface) . These provide
asynchronous dat a t ransmission bet ween t he MSP430 and ot her
peripheral devices when configured in UART mode. They also
support dat a t ransmission synchronized t o a clock signal t hrough a
serial I / O port in Serial Peripheral I nt erface ( SPI ) and I nt er
I nt egrat ed Circuit ( I
2
C) modes.

Topi c Page
14.1 I nt r oduct i on .................................................................. 14- 3
14.2 Communi cat i ons sy st em model ..................................... 14- 3
14.3 Tr ansmi ssi on mode........................................................ 14- 3
14.4 Sy nchr onous and asy nchr onous ser i al communi cat i ons 14- 5
14.5 Asy nchr onous ( UART) communi cat i ons ......................... 14- 6
14.5.1 Par i t y bi t .............................................................. 14- 6
14.5.2 Baud r at e ............................................................. 14- 6
14.6 Ser i al Per i pher al I nt er f ace ( SPI ) communi cat i on .......... 14- 8
14. 7 I
2
C ( I nt er - I nt egr at ed Ci r cui t ) pr ot ocol .......................... 14- 8
14.8 MSP430 communi cat i ons i nt er f aces .............................. 14- 9
14.8.1 USART modul e.................................................... 14- 10
14.8.2 USCI modul e ...................................................... 14- 11
14. 8. 3 USI modul e ........................................................ 14- 12
14.9 I ni t i al i zat i on sequence ................................................ 14- 13
14.9.1 USART modul e.................................................... 14- 13
14.9.2 USCI modul e ...................................................... 14- 13
14. 9. 3 USI modul e ........................................................ 14- 14
14.10 Baud Rat e .................................................................... 14- 14
Communicat ions
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14.10.1 USART modul e ................................................... 14- 14
14. 10. 2 USCI modul e ...................................................... 14- 15
14.11 Ser i al communi cat i on modes oper at i on ....................... 14- 17
14.11.1 USART oper at i on: UART mode............................ 14- 17
14.11.2 USART oper at i on: SPI mode............................... 14- 21
14.11.3 USCI oper at i on: UART mode .............................. 14- 23
14.11.4 USCI oper at i on: SPI mode ................................. 14- 28
14.11.5 USCI oper at i on: I
2
C mode .................................. 14- 30
14. 11. 6 USI oper at i on ( SPI and I
2
C modes) ................... 14- 33
SPI mode .............................................................. 14- 35
I
2
C mode............................................................... 14- 36
14. 12 Ot her document at i on .................................................. 14- 40
14.13 Regi st er s ..................................................................... 14- 42
14. 13. 1 USART Per i pher al I nt er f ace ( UART and SPI
modes) ............................................................................ 14- 42
14. 13. 2 USCI per i pher al i nt er f ace ( UART, SPI and I
2
C modes)
....................................................................................... 14- 51
14. 13. 3 USI per i pher al i nt er f ace ( SPI and I
2
C modes) . . . 14- 64
14. 14 Labor at or y 10: Echo t est ............................................. 14- 68
14. 14. 1Lab10a: Echo t est usi ng t he UART mode of t he USCI
modul e ............................................................................ 14- 68
14.14.2 Lab10b: Echo t est usi ng SPI .............................. 14- 72
14.14.3 Lab10c: Echo t est usi ng I
2
C ............................... 14- 77
14. 15 Qui z ............................................................................. 14- 84
14. 16 FAQs ............................................................................ 14- 89

Transmission mode
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14.1 I nt r oduct i on
An import ant feat ure of modern microprocessor based syst ems is
t heir communicat ion capabilit y, t hat is, t heir abilit y t o exchange
informat ion wit h ot her syst ems in t he surrounding environment . The
communicat ions int erfaces can be used for firmware updat e or
loading local paramet ers. At a higher level, t hese int erfaces can be
used t o exchange informat ion in applicat ions wit h dist ribut ed
processes.

14.2 Communi cat i ons sy st em model
Any digit al communicat ion syst em has t hree devices:
Transmit t er: Has t he t ask of processing t he informat ion int o t he
appropriat e format for subsequent t ransmission;
Receiver: I s in charge of collect ing t he informat ion and
ext ract ing t he original dat a;
Communicat ion medium: Provides t he physical medium t hrough
which t he informat ion flows and is commonly implement ed as
t wist ed pair wire, opt ical fibre cable or radio frequency net work.

Figure 14- 1 shows t wo devices part icipat ing in a digit al
communicat ion syst em:
DTE: Dat a Terminal Equipment ;
DCE: Dat a Communicat ions Equipment .

Figure 14- 1. Communicat ion syst em.

DTE DTE DCE DCE
Transmission
medium
Transmitter Receiver
Transmitter Receiver

14.3 Tr ansmi ssi on mode
Communicat ions bet ween digit al devices are divided int o parallel
communicat ions and serial communicat ions. I n parallel
communicat ions syst ems, t he physical t ransmission medium has
independent signal lines for each of t he bit s of t he t ransmit t ed
digit al value. The informat ion t ransmit t ed at a given moment is
represent ed by t he value formed by logical levels on t he various
lines ( see Figure 14- 2) .
Communicat ions
Figure 14- 2. Charact er ASCI I W parallel t ransmission.

I n serial communicat ions, t he physical t ransmission medium needs
only one signal line. The informat ion is sent by t he t ransmit t er as a
sequence of bit s, at a common rat e est ablished bet ween t he
t ransmit t er and t he receiver. Addit ional informat ion is needed t o
enable synchronizat ion bet ween t he communicat ion part icipant s:
St art bit : Added t o t he beginning of t he informat ion t ransmit t ed,
t he funct ion of which is t o t he ident ify t he beginning of a new word;
St op bit : I ndicat es complet ion of t he t ransfer and is added t o
t he end of t he informat ion t ransmit t ed.

Figure 14- 3 gives an example of t he ASCI I charact er W being sent
by serial t ransmission.

Figure 14- 3. Charact er ASCI I W serial t ransmission.

I nf or mat i on f l ow
Synchronous and asynchronous serial communicat ions
The t wo communicat ion modes bot h have t heir advant ages and
disadvant ages ( see Table 14- 1) , but t he parallel communicat ion
medium has been losing import ance t o serial communicat ion. Serial
communicat ions, due t o t echnological advances, have now achieved
high t ransmission rat es, making t hem more at t ract ive for t he most
applicat ions.

Table 14- 1. Advant ages and disadvant ages of parallel and serial communicat ion modes.
Char act er i st i c Par al l el Ser i al
Bus line One line per bit One line
Sequence
All bit s of one word
simult aneously
Sequence of bit s
Transmission
rat e
High Low
Bus lengt h Short dist ances Short and long dist ances
Cost High Low
Crit ical
charact erist ics
Synchronisat ion bet ween
t he different bit s is
demanding
Asynchronous t ransmission needs
st art and st op bit s
Synchronous t ransmission needs
some ot her synchronisat ion

14.4 Sy nchr onous and asy nchr onous ser i al communi cat i ons
Serial communicat ions may be:
Asynchronous: Where t he t ransmission rat e ( baud rat e) is fixed
by t he t ransmit t er. The receiver must know t his rat e and
synchronize it self t o t he t ransmit t er when t he st art bit is det ect ed;
Synchronous: Where t here is a synchronizat ion clock signal
bet ween t he receiver and t he t ransmit t er.

I n synchronous communicat ion, t here is one unit t hat assumes t he
role of mast er and one or more unit s t hat assume t he role( s) of
slave. The clock signal generat ed by t he mast er is used by t he slave
unit s t o carry out t he loading/ unloading of TX and RX regist ers. I n
t his communicat ion mode, it is possible t o t ransmit and receive
simult aneously. I n synchronous communicat ions, bot h t he sender
and receiver are synchronized wit h a clock or a signal encoded int o
t he dat a st ream.

Asynchronous communicat ion requires not hing more t han a
t ransmit t er, a receiver and a wire. I t is t hus t he simplest of serial
communicat ion prot ocols, and t he least expensive t o implement . As
t he name implies, asynchronous communicat ion is performed
bet ween t wo ( or more) devices which operat e on independent
clocks. Therefore, even if t he t wo clocks agree for a t ime, t here is no
guarant ee t hat t hey will cont inue t o agree over ext ended periods.

Communicat ions
14.5 Asy nchr onous ( UART) communi cat i ons
As shown in Figure 14- 3, t he st art bit ident ifies t he beginning of a
t ransfer and is generat ed by a high- t o- low t ransit ion on t he bus.
Following t he st art bit t here are t he seven or eight dat a bit s ( in t his
example, t he ASCI I code for t he t ext t ransfer uses seven bit s) . The
verificat ion bit ( parit y bit ) is sent aft er t he dat a bit s. To t erminat e
t he t ransmission, one or t wo st op bit s are used.

14.5.1 Par i t y bi t
The parit y bit verifies t he int egrit y of informat ion t ransmit t ed. The
bit is added by t he t ransmit t er and indicat es whet her t he t ot al
number of bit s at level "1" in t he message dat a are odd or even. The
t ransmissions can be configured for odd or even parit y ( see Figure
14- 4) .

Figure 14- 4. Odd or even parit y.

1 2 3 4 5 6 7
7 bit ASCII code
0 1 0 0 0 0 1
Bit
B
1 0 0 0 1 0 1
1 1 0 0 1 1 0
0 1 0 1 1 1 1
Q
3
z
Parity
bit odd
Parity
bit even
1 0
0 1
1 0
0 1

14.5.2 Baud r at e
The t ransmission of t he ASCI I charact er "W" 7- bit charact er requires
eleven bit s t o be sent , wit h four addit ional bit s being used for
cont rol. This corresponds t o a baud value of 11. I f t he charact er
t ransmission rat e is 10 charact ers per second, it will give a baud
rat e of 10x11 = 1100 baud/ second.

The baud rat e is a basic paramet er in serial asynchronous
communicat ions. Aft er t he mast er and slave are synchronized
t hrough t he st art bit , t hey must use t he same baud rat e in order t o
know t he appropriat e moment s t o writ e ( mast er) and read ( slave)
t he various bit s of t he word t ransmit t ed.

The most commonly used baud rat es are shown in Table 14- 2. The
usual problem is t hat t hese baud rat es are not generally sub-
mult iples of t he unit s clock sources. The example in Figure 14- 5
illust rat es t his problem and shows how t o solve it . The correct bit
t iming is obt ained in t wo st eps:
Clock init ial division t hrough t he count er;
Using a met hod t o correct t he problem of t he inexact int eger
division of t he clock signal by t he baud rat e.
Asynchronous ( UART) communicat ions
Table 14- 2. St andardized common baud rat es.

Figure 14- 5. Example: Sub- mult iples of t he unit s clock source.

Communicat ions

14.6 Ser i al Per i pher al I nt er f ace ( SPI ) communi cat i on
The SPI ( Serial Peripheral I nt erface) bus is a st andard for
synchronous serial communicat ion developed by Mot orola, which
operat es in full duplex mode. The devices have a mast er/ slave
relat ionship and t he communicat ion is always init iat ed by t he
mast er.

Figure 14- 6. Typical SPI communicat ion syst em.

The SPI communicat ions syst em shown in Figure 14- 6 only support s
one mast er, but can support more t han a slave. The dist ance
bet ween unit s should be minimized, ideally limit ed t o a single PCB.
Special at t ent ion should be given t o t he polarit y and phase of t he
clock signal.

14.7 I
2
C ( I nt er - I nt egr at ed Ci r cui t ) pr ot ocol
The I
2
C prot ocol is a mult i- mast er synchronous serial comput er bus
developed by Philips Semiconduct ors, wit h t he main obj ect ive of
est ablishing links bet ween int egrat ed circuit s and t o connect low-
speed peripherals.
The prot ocol is based on hardware using t wo bi- direct ional open-
drain bus lines pulled up wit h resist ors:
SDA: Serial Dat a;
SCL: Serial clock.

MSP430 communicat ions int erfaces
Typical volt ages used are + 5. 0 V or + 3. 3 V, alt hough syst ems wit h
ot her volt ages are possible.
The communicat ions are always init iat ed and complet ed by t he
mast er, which is responsible for generat ing t he clock signal. I n more
complex applicat ions, t he I
2
C syst em can operat e in mult i- mast er
mode. The slave select ion by t he mast er is made by t he seven- bit
address of t he t arget slave.
The mast er ( in t ransmit mode) sends a st art bit followed by t he 7-
bit address of t he slave it wishes t o communicat e wit h, followed by a
single bit represent ing whet her it wishes t o writ e ( 0) t o or read ( 1)
t o/ from t he slave. The t arget slave will acknowledge it s address.

Figure 14- 7. Typical I
2
C communicat ion syst em.

14.8 MSP430 communi cat i ons i nt er f aces
The MSP430 microcont roller family is equipped wit h t hree different
t ypes of serial communicat ion modules:
USART;
USCI ;
USI .

The comparison bet ween t he t hree MSP430 communicat ion modules
is shown in Table 14- 3.
Communicat ions

Table 14- 3. Comparison of MSP430 communicat ion modes.
USART USCI USI
UART:
- Only one modulat or

- n/ a
- n/ a
- n/ a

UART:
- Two modulat ors support
n/ 16 t imings
- Aut o baud rat e det ect ion
- I rDA encoder & decoder
- Simult aneous USCI _A
and USCI _B ( 2 channels)

SPI :
- Only one SPI available

- Mast er and Slave Modes
- 3 and 4 Wire Modes
SPI :
- Two SPI ( one on each
USCI _A and USCI _B)
- 3 and 4 Wire Modes
SPI :
- Only one SPI available


I
2
C: ( on 15x/ 16x only)

- up t o 400kbps
I
2
C:
- Simplified int errupt
usage
- up t o 400kbps
I
2
C:
- SW st at e machine
needed

14.8.1 USART modul e
The USART ( Universal Synchronous/ Asynchronous
Receiver/ Transmit t er) module is a base unit for serial
communicat ions, support ing bot h asynchronous communicat ions
( RS232) and synchronous communicat ions ( SPI ) .

The USART module is available in t he 4xx series devices, part icularly
in t he sub- series MSP430x42x and MSP430x43x. The sub- series
MSP430x44x and MSP430FG461x have a second USART unit .

The USART module support s:
Low power operat ing modes ( wit h aut o- st art ) ;
UART or SPI mode ( I
2
C on F15x/ F16x only) ;
Double buffered TX/ RX;
Baud rat e generat or;
DMA enabled;
Error det ect ion.
MSP430 communicat ions int erfaces

Figure 14- 8. USART block diagram.

14.8.2 USCI modul e
Alt hough support ing RS232, SPI and I
2
C, t he USCI ( Universal Serial
Communicat ion I nt erface) module is a communicat ions int erface
designed t o int erconnect t o indust rial prot ocols:
LI N ( Local int erconnect Net work) , used in cars ( door modules,
alarm, sunroof, et c. ) ;
I rDA ( I nfrared Dat a Associat ion) , used for remot e cont rollers.

The USCI module is available in t he following devices:
MSP430F5xx;
MSP430F4xx and MSP430FG461x;
MSP430F2xx.

The USCI module support s:
Low power operat ing modes ( wit h aut o- st art ) ;
Two individual blocks:
USCI _A:
o UART wit h Lin/ I rDA support ;
o SPI ( Mast er/ Slave, 3 and 4 wire modes) .
USCI _B:
o SPI ( Mast er/ Slave, 3 and 4 wire mode) ;
o I
2
C ( Mast er/ Slave, up t o 400 kHz) .
Double buffered TX/ RX
Communicat ions
Baud rat e/ Bit clock generat or wit h:
Aut o- baud rat e det ect ;
Flexible clock source.
RX glit ch suppression;
DMA enabled;
Error det ect ion.

Figure 14- 9. USCI block diagram.

14.8.3 USI modul e
The USI ( Universal Serial I nt erface) module offers basic support for
synchronous serial communicat ions SPI and I
2
C. I t is available in t he
MSP430x20xx devices family.

The USI module support s:
SPI mode:
Programmable dat a lengt h ( 8/ 16- bit shift regist er) ;
MSB/ LSB first .
I
2
C mode:
START/ STOP det ect ion;
Arbit rat ion for lost det ect ion;
I nt errupt driven;
Reduces CPU load;
Flexible clock source select ion;

I nit ializat ion sequence

Figure 14- 10. USI block diagram.

14.9 I ni t i al i zat i on sequence
The MSP430x4xx and MSP430x2xx MSP430 Users Guides
recommended t he init ializat ion/ re- configurat ion process for USART,
USCI and USI modules as given below:

The recommended USART init ializat ion/ re- configurat ion process is:
Set SWRST ( BIS.B #SWRST,&UxCTL) ;
I nit ialize all USART regist ers wit h SWRST = 1 ( including UxCTL) ;
Enable USART module via t he MEx SFRs ( URXEx and/ or UTXEx) ;
Clear SWRST via soft ware ( BIC.B #SWRST,&UxCTL) ;
Enable int errupt s ( opt ional) via t he I Ex SFRs ( URXI Ex and/ or
UTXI Ex) ;

14.9.2 USCI modul e
The recommended USCI init ializat ion/ re- configurat ion process is:
Set UCSWRST ( BIS.B #UCSWRST, &UCxCTL1) ;
I nit ialize all USCI regist ers wit h UCSWRST = 1 ( including
UCxCTL1) ;
Configure port s;
Clear UCSWRST via soft ware ( BIC.B #UCSWRST, &UCxCTL1) ;
Enable int errupt s ( opt ional) via UCxRXI E and/ or UCxTXI E.
Communicat ions
14.9.3 USI modul e
The recommended USI init ializat ion process is:
Set t he USI PEx bit s in t he USI cont rol regist er. This will select
t he USI funct ion for t he pin and maint ains t he PxI N and PxI FG
funct ions for t he pin as well;
Set t he direct ion of t he receive and t ransmit shift regist er ( MSB
or LSB first ) by USI LSB bit ;
Select t he mode ( mast er or slave) by USI MST bit ;
Enable or disable out put dat a by USI OE;
Enable USI int errupt s set t ing USI I E;
Set up USI clock configuring t he USI CKCTL cont rol regist er.
Enable USI by set t ing USI SWRST bit ;
Read port input levels via t he PxI N regist er by soft ware;
I ncoming dat a st ream t o generat e port int errupt s on dat a
t ransit ions.

14.10 Baud Rat e
The following sub- sect ion describes t he met hod for set t ing t he baud
rat e for t he support ed asynchronous modules.

The USART module uses a prescaler/ divider and a modulat or as
shown in Figure 14- 11. The bit t iming ( BI TCLK) of t his module must
be smaller t han a t hird of t he clock signal ( BRCLK in Figure 14- 11) .

Figure 14- 11. Example: USART module block diagram.

The bit t iming is implement ed in t wo st ages. For t he BRCLK, t he
division fact or N is given by:
Baud Rat e
baudrat e
BRCLK
N =

The fact or N may not be an int eger, but it s int eger part will be
t reat ed by t he first phase of t he bit t ime. The fract ional part in t his
fact or will be t reat ed by t he modulat or. The new definit ion of N is
given by:

=
+ =
1
0
1
n
i
i
m
n
UxBR N
1

Where:

=
+
= =
1
0
1
n
i
i
m
n
UxBR
BRCLK
N
BRCLK
baudrat e

14.10.2 USCI modul e

Figure 14- 12. USCI module block diagram.

1
Addit ional det ails in sect ion 17. 2.6 of t he MSP430x4xx Users Guide.
Communicat ions

For a specific clock source frequency, t he divider value is given by:

baudrat e
BRCLK
N =

Typically, t he value of N is not an int eger value, so it is necessary t o
use a modulat or.

The USCI module has t wo ways t o generat e t he baud rat e:

Low-Frequency Baud Rate Generation
The Low- Frequency Baud Rat e Generat ion mode is select ed when
UCOS16 = 0. The baud rat e generat ion mode is useful for lowering
power consumpt ion, since it uses a low frequency clock source
( 32. 768 kHz cryst al) .
The baud rat e is obt ained t hrough a prescaler and a modulat or,
similar t o t he one used in t he USART module.
The regist ers are configured using t he equat ions given below.
However, for confirmat ion, it is recommended t hat t he t ables given
in t he Users Guide be consult ed.
prescaler N UCBRx = ) int (

( ) ( ) ( ) port ion fract ional N N round UCBRSx = 8 ) int (

Oversampling Baud Rate Generation
The Oversampling Baud Rat e Generat ion mode is select ed when
UCOS16 = 1. This mode allows precise bit t iming. I t requires clock
sources 16x higher t han t he desired baud rat e.
The baud rat e is generat ed in t wo st eps:
The clock source is divided by 16, and result s in t he BI TCLK16,
being t he source signal divided by t he prescaler, and is applied t o
t he first modulat or;
The BI TCLK is defined by BI TCLK16, t hrough division by 16 and a
second modulat or.
The regist ers are configured using t he equat ions given below.
However, for confirmat ion, it is recommended t hat t he t ables given
in t he Users Guide be consult ed.

( ) prescaler
N
UCBRx =
16
int

Serial communicat ion modes operat ion
( ) ( ) ( ) ( ) ( ) port ion fract ional
N N
round UCBRFx = 16
16
int
16

14.11 Ser i al communi cat i on modes oper at i on
The following sub- sect ions describe t he different operat ing modes of
t he communicat ion int erfaces support ed by t he MSP430.

14.11.1 USART oper at i on: UART mode
Transmit s and receives charact ers at an asynchronous bit rat e
t o/ from ot her devices;

Timing for each charact er is based on t he select ed baud rat e;

Transmit and receive funct ions use t he same baud rat e
frequency;

I nit ializat ion follows t he sequence given earlier;

Define t he charact er format for t he sequence of charact ers:
St art bit ;
Seven or eight dat a bit s;
Even/ odd/ no parit y bit ;
Address bit ( address- bit mode) ;
One or t wo st op bit s.

Figure 14- 13. Charact er format .

Define t he asynchronous communicat ion prot ocol:
I dle- line mult iprocessor communicat ion prot ocol for a
minimum of t wo devices ( see Figure 14- 14) :
o I DLE is det ect ed aft er > 10 periods of cont inuous
marks aft er t he st op bit ;
o The first charact er aft er I DLE is an address;
Communicat ions
o UART can be programmed t o receive only address
charact ers.

Figure 14- 14. UART idle- line mult iprocessor communicat ion prot ocol.

Address- bit mult iprocessor communicat ion prot ocol for a
minimum of t hree devices ( see Figure 14- 15) :
o Ext ra bit st at e in t he received charact er marks an
address charact er;
o UART can be programmed t o receive only address
charact ers.

Figure 14- 15. UART address- bit mult iprocessor communicat ion prot ocol.

Aut omat ic error det ect ion:
Framing error FE:
o FE is set if t he st op bit is missing from a received
frame.
Parit y error PE:
o PE is set if t here is a parit y mismat ch in a received
frame.
Receive overrun error OE:
o OE is set if UxRXBUF is overwrit t en.
Break condit ion BRK:
o BRK is set if all bit s in t he received frame = 0;
Glit ch suppression prevent s t he USART from being
accident ally st art ed;
Any pulse on UxRXD short er t han t he deglit ch t ime
( approximat ely 300 ns) will be ignored.

Enable t he USART receive enable bit URXEx:
The receive- dat a buffer, UxRXBUF, cont ains t he charact er
t ransferred from t he RX shift regist er aft er t he character is
received.

Figure 14- 16. St at e diagram of receive enable.

Enable t he USART t ransmit enable bit UTXEx:
Transmission is init iat ed by writ ing dat a t o UxTXBUF;
The dat a is t hen moved t o t he t ransmit shift regist er on t he
next BI TCLK aft er t he TX shift regist er is empt y, and
transmission begins.

Figure 14- 17. St at e diagram of t ransmit enable.

Communicat ions
Define t he USART baud rat e generat ion ( st andard baud rat es
from non- st andard source frequencies) as described earlier ( See
Figure 14- 18) ;

Figure 14- 18. USART operat ion: Baud rat e generat or.

Set USART int errupt s ( one int errupt vect or for t ransmission and
one int errupt vect or for recept ion) :
UART t ransmit int errupt operat ion:
o UTXI FGx int errupt flag is set by t he t ransmit t er t o
indicat e t hat UxTXBUF is ready t o accept anot her
charact er;
o An int errupt request is also generat ed if UTXI Ex and
GI E are set ;
o UTXI FGx is aut omat ically reset if t he int errupt
request is serviced or if a charact er is writ t en t o
UxTXBUF.
UART receive int errupt operat ion:
o URXI FGx int errupt flag is set each t ime a charact er is
received and loaded int o UxRXBUF;
o An int errupt request is also generat ed if URXI Ex and
GI E are set ;
o URXI FGx and URXI Ex are reset by a syst em reset
PUC signal or when SWRST = 1;
o URXI FGx is aut omat ically reset if t he pending
int errupt is serviced ( when URXSE = 0) or when
UxRXBUF is read.

Receive- st art edge det ect feat ure ( URXSE bit ) . Should be used
when:
BRCLK is sourced by t he DCO;
DCO is off due t o low- power mode operat ion.


14.11.2 USART oper at i on: SPI mode
Serial dat a t ransmit t ed and received by mult iple devices using a
shared clock provided by t he mast er;

STE bit ( cont rolled by t he mast er) enables a device t o receive
and t ransmit dat a;

Three or four signals are used for SPI dat a exchange ( see Figure
14- 19) :
SI MO: Slave I n, Mast er Out ;
SOMI Slave Out , Mast er I n;
UCLK USART SPI clock;
STE slave t ransmit enable.

Figure 14- 19. USART operat ion in SPI mode.


Define mode: Mast er or Slave;

Enable SPI t ransmit / receive, USPI Ex;

Communicat ions

Figure 14- 20. St at e diagram of t ransmit enable for SPI mast er mode.

Figure 14- 21. St at e diagram of t ransmit enable for SPI slave mode.

Figure 14- 22. St at e diagram of receive enable for SPI mast er mode.


Figure 14- 23. St at e diagram of receive enable for SPI slave mode.

Define serial clock cont rol:
UCLK is provided by t he mast er on t he SPI bus.

Define serial clock polarit y ( CKPL bit ) and phase ( CKPH bit ) ;

Set USART int errupt s ( one int errupt vect or for t ransmission and
SPI t ransmit int errupt operat ion ( as UART mode) ;
SPI receive int errupt operat ion ( as UART mode) .

14.11.3 USCI oper at i on: UART mode
I n asynchronous mode, t he USCI _Ax modules connect t he
MSP430 t o an ext ernal syst em via t wo ext ernal pins, UCAxRXD and
UCAxTXD;

UART mode is select ed when t he UCSYNC bit is cleared;

USCI t ransmit s and receives charact ers asynchronously at a bit
rat e t he same as ot her devices;

Timing for each charact er is based on t he select ed baud rat e of
t he USCI ;

The t ransmit and receive funct ions use t he same baud rat e
frequency;

Communicat ions

Figure 14- 24. USCI operat ion in UART mode.


Define t he charact er format specified as USART in UART mode:
UCMSB bit cont rols t he direct ion of t he t ransfer and select s
LSB ( usual in UART communicat ion) or MSB first .

Figure 14- 25. Charact er format in USCI operat ion: UART mode.

Define t he asynchronous communicat ion format as USART in
UART mode;

I f appropriat e, define aut omat ic baud rat e det ect ion
( UCMODEx = 11) as shown in Figure 14- 26:
Dat a frame is preceded by a synchronizat ion sequence:
o Break: Det ect ed when 11 or more cont inuous zeros
( spaces) are received;
o Synch field: Dat a 055h inside a byt e field.
The baud rat e is calculat ed from a valid SYNC;
Aut o baud rat e value st ored in UxBR1, UxBR0 and UxMCTL
( modulat ion pat t ern) ;
BREAK t ime- out det ect in hardware;
Programmable delimit er t ime;

Figure 14- 26. USCI aut omat ic baud rat e det ect ion.

I f appropriat e, use t he I rDA encoder and decoder ( UCI REN = 1) ,
as shown in Figure 14- 27:

Figure 14- 27. USCI in UART mode: I rDA operat ion.

Communicat ions

I rDA encoding:
o Encoder sends a pulse for every zero bit in t he
t ransmit bit st ream coming from t he UART;
o Pulse durat ion ( defined by UCI RTXPLx bit s) specifies
t he number of half clock periods of t he clock
( UCI RTXCLK) ;
o Oversampling baud rat e generat or allows t he
select ion of t he I rDA st andard 3/ 16 bit lengt h.
I rDA decoding:
o Programmable low ( see Figure 14- 28) or high pulse
det ect ion ( UCI RRXPL) by t he decoder;
o Programmable received pulse lengt h filt er adds noise
filt er capabilit y in addit ion t o t he glit ch det ect or.

Figure 14- 28. USCI in UART mode: low pulse det ect ion - I rDA decoding operat ion.

Aut omat ic error det ect ion:
Framing error UCFE:
o UCFE is set if t he st op bit is missing from a received
frame.
Parit y error UCPE:
o UCPE is set if t here is parit y mismat ch in t he received
frame.
Receive overrun error UCOE:
o UCOE is set if RXBUF is overwrit t en.
Break condit ion UCBRK:
o UCBRK is set if all bit s in t he received frame = 0;
o I f UCBRKI E is set , t hen UCAxRXI FG is set if BRK= 1.
Glit ch suppression prevent s t he USCI from being accident ally
st art ed;
Any pulse on UCAxRXD short er t han t he deglit ch t ime
( approximat ely 150 ns) will be ignored.
UART can be programmed t o t ransfer only error free
charact ers t o UCAxRXBUF.

USCI receive enable: Clear UCSWRST;
The falling edge of t he st art bit enables t he baud rat e
generat or;
I f a valid st art bit is det ect ed, a charact er will be received.

USCI t ransmit enable: Clear UCSWRST;
Transmission is init iat ed by writ ing dat a t o UCAxTXBUF;
The baud rat e generat or is enabled;
The dat a in UCAxTXBUF is moved t o t he t ransmit shift
regist er on t he next BI TCLK aft er t he t ransmit shift regist er is
empt y;
UCAxTXI FG is set when new dat a can be writ t en t o
UCAxTXBUF.

Define UART baud rat e generat ion ( st andard baud rat es from
non- st andard source frequencies) as given earlier ( see Figure 14-
29) . Two modes of operat ion ( UCOS16 bit ) :
Low- frequency baud rat e;
Oversampling baud rat e.

Figure 14- 29. USCI operat ion: Baud rat e generat or.

Transmit bit t iming:
The t iming for each charact er is t he sum of t he individual bit
t imings;
The modulat ion feat ure of t he baud rat e generat or reduces
t he cumulat ive bit error.

Communicat ions
Two error sources for receive bit t iming:
Bit - t o- bit t iming error;
Error bet ween a st art edge occurring and t he st art edge being
accept ed by t he USCI module.

Set USCI int errupt s ( one int errupt vect or for t ransmission and
USCI t ransmit int errupt :
o UCAxTXI FG int errupt flag is set by t he t ransmit t er t o
indicat e t hat UCAxTXBUF is ready t o accept anot her
charact er;
o An int errupt request is generat ed if UCAxTXI E and
GI E are also set ;
o UCAxTXI FG is aut omat ically reset if a charact er is
writ t en t o UCAxTXBUF.
USCI receive int errupt :
o UCAxRXI FG int errupt flag is set each t ime a charact er
is received and loaded int o UCAxRXBUF;
o An int errupt request is also generat ed if UCAxRXI E
and GI E are set ;
o UCAxRXI FG and UCAxRXI E are reset by a syst em
reset PUC signal or when UCSWRST = 1;
o UCAxRXI FG is aut omat ically reset when UCAxRXBUF
is read.

14.11.4 USCI oper at i on: SPI mode
Flexible int erface:
3- or 4- pin SPI ;
7- or 8- bit dat a lengt h;
Mast er or slave;
LSB or MSB first .
S/ W configurable clock phase and polarit y;
Programmable SPI mast er clock;
Double buffered TX/ RX;
I nt errupt driven TX/ RX ( USCI _A and USCI _B share TX and RX
vect or) ;
DMA enabled;
LPMx operat ion.


Figure 14- 30. USCI operat ion: SPI mode.

Figure 14- 31. USCI operat ion: SPI connect ions.

Serial dat a is t ransmit t ed and received by mult iple devices using
a shared clock signal t hat is generat ed by t he mast er;

Three or four signals are used for SPI dat a exchange:
UCxSI MO: Slave in, mast er out ;
UCxSOMI : Slave out , mast er in;
UCxCLK: USCI SPI clock;
UCxSTE: Slave t ransmit enable:
o Enables a device t o receive and t ransmit dat a and is
cont rolled by t he mast er;
o 4 wire mast er, senses conflict s wit h ot her mast er( s) ;
o 4 wire slave, ext ernally cont rols TX and RX.
Communicat ions

Define t he charact er format as given earlier;

Define mode: Mast er or Slave;

Enable SPI t ransmit / receive by clearing t he UCSWRST bit :

Define serial clock cont rol:
UCxCLK is provided by t he mast er on t he SPI bus;
Configure serial clock polarit y and phase ( UCCKPL and
UCCKPH bit s) .

Set USCI int errupt s ( one int errupt vect or for t ransmit and one
int errupt vect or for receive) :
SPI t ransmit int errupt operat ion:
o UCxTXI FG int errupt flag is set by t he t ransmit t er t o
indicat e t hat UCxTXBUF is ready t o accept anot her
charact er;
o An int errupt request is also generat ed if UCxTXI E and
GI E are set ;
o UCxTXI FG is aut omat ically reset if t he int errupt
request is serviced or if a charact er is writ t en t o
UCxTXBUF.
SPI receive int errupt operat ion.
o UCxRXI FG int errupt flag is set each t ime a charact er
is received and loaded int o UCxRXBUF;
o An int errupt request is also generat ed if UCxRXI E and
GI E are set ;
o UCxRXI FG and UCxRXI E are reset by a syst em reset
PUC signal or when SWRST = 1;
o UCxRXI FG is aut omat ically reset if t he pending
int errupt is serviced ( when UCSWRST = 1) or when
UCxRXBUF is read.

14.11.5 USCI oper at i on: I
2
C mode
The I
2
C mode support s any I
2
C compat ible mast er or slave
device ( specificat ion v2. 1) ;


Figure 14- 32. USCI operat ion: I
2
C mode.

Each I
2
C device is ident ified by a unique address and can
operat e eit her as a t ransmit t er or a receiver, and eit her as t he
mast er or t he slave;

A mast er init iat es dat a t ransfers and generat es t he clock signal
SCL. Any device addressed by a mast er is t aken t o be a slave;

Communicat ion uses t he bi- direct ional serial dat a ( SDA) and
serial clock ( SCL) pins;

Figure 14- 33. USCI operat ion: I
2
C block diagram.

Communicat ions


I
2
C serial dat a:
One clock pulse is generat ed by t he mast er device for each
dat a bit t ransferred;
Operat es wit h byt e dat a ( MSB t ransferred first ) ;
The first byt e aft er a START condit ion consist s of a 7- bit slave
address and a R/ W bit :
o R/ W = 0: Mast er t ransmit s dat a t o a slave;
o R/ W = 1: Mast er receives dat a from a slave.
The acknowledge ( ACK) bit is sent from t he receiver aft er
each byt e on t he 9t h SCL clock;

I
2
C addressing modes ( 7- bit and 10- bit addressing modes) ;

I
2
C module operat ing modes:
Mast er t ransmit t er;
Mast er receiver;
Slave t ransmit t er;
Slave receiver.

An arbit rat ion procedure is invoked if t wo or more mast er
t ransmit t ers simult aneously st art a t ransmission on t he bus;

I
2
C Clock generat ion and synchronizat ion:
SCL is provided by t he mast er on t he I
2
C bus;
Mast er mode: BI TCLK is provided by t he USCI bit clock
generat or;
Slave mode: t he bit clock generat or is not used.

Set USCI int errupt s ( one int errupt vect or for t ransmission and
I
2
C t ransmit int errupt operat ion:
o UCBxTXI FG int errupt flag is set by t he t ransmit t er t o
indicat e t hat UCBxTXBUF is ready t o accept anot her
charact er;
o An int errupt request is also generat ed if UCBxTXI E
and GI E are set ;
o UCBxTXI FG is aut omat ically reset if a charact er is
writ t en t o UCBxTXBUF or a NACK is received.

I
2
C receive int errupt operat ion.
o UCBxRXI FG int errupt flag is set each t ime a charact er
is received and loaded int o UCxRXBUF;
o An int errupt request is also generat ed if UCBxRXI E
and GI E are set ;
o UCBxRXI FG and UCBxRXI E are reset by a syst em
reset PUC signal or when SWRST = 1;
o UCxRXI FG is aut omat ically reset when UCBxRXBUF is
read.

I
2
C st at e change int errupt flags:
Arbit rat ion- lost , UCALI FG: Flag set when t wo or more
t ransmit t ers st art a t ransmission simult aneously, or a device
operat es as mast er, but is addressed as a slave by anot her
mast er;
Not - acknowledge int errupt , UCNACKI FG: Flag set when an
acknowledge is expect ed but is not received;
St art condit ion det ect ed int errupt , UCSTTI FG: Flag set when
t he I
2
C module det ect s a START condit ion, t oget her wit h it s
own address while in slave mode;
St op condit ion det ect ed int errupt , UCSTPI FG: Flag set when
t he I
2
C module det ect s a STOP condit ion while in slave mode.

14.11.6 USI oper at i on ( SPI and I
2
C modes)
Shift regist er and bit count er t hat includes logic t o support SPI
and I
2
C communicat ion;

USI SR shift regist er ( up t o 16 bit s support ed) :
Direct ly accessible by soft ware;
Cont ains t he dat a t o be t ransmit t ed or t he dat a received ( TX
and RX is simult aneous) ;
MSB or LSB first .

Bit count er:
Cont rols t he number of TX or RX bit s;
Count s t he number of sampled bit s;
Set s t he USI int errupt flag USI I FG when t he USI CNTx value
becomes zero ( decrement ing or writ ing zero t o USI CNTx
bit s) ;
Writ ing USI CNTx > 0 aut omat ically clears USI I FG when
USI I FGCC = 0 ( aut omat ically st ops clocking aft er t he last
bit ) .

Communicat ions
USI init ializat ion:
Reset USISWRST;
Set USI PEx bit s ( USI funct ion for t he pin and maint ains t he
PxI N and PxI FG funct ions for t he pin) :
o Port input levels can be read from t he PxI N regist er
by soft ware;
o The incoming dat a st ream can generat e port
int errupt s on dat a t ransit ions.

USI clock generat ion ( see Figure 14- 34) :
Clock select ion mult iplexer:
o I nt ernal clocks ACLK or SMCLK;
o Ext ernal clock SCLK;
o USI SWCLK ( soft ware clock input bit ) ;
o Timer_A CAP/ COM out put s.
Configurable divider;
Aut o- st op on int errupt : USI I FG;
Select able phase and polarit y.

Figure 14- 34. USI clock generat or block diagram.

Figure 14- 35. USI operat ion- SPI mode: Clock and dat a handling.


SPI mode
Configure USI module in SPI mode ( USI I 2C = 0) ;

Figure 14- 36. USI SPI mode block diagram.

Configure USI CKPL. Select s t he inact ive level of t he SPI clock
( rising or falling edge dat a lat ching) ;

Configure USI CKPH. Select s t he clock edge on which SDO is
updat ed and SDI is sampled ( idle high or low support ed) .

Configure mode:
SPI mast er:
o Set USI MST bit and clear USI I 2C bit ;
o Select clock source;
o Configure SCLK as out put .
SPI slave:
o Clear t he USI MST and t he USI I 2C bit s;
o SCLK is aut omat ically configured as an input ;
o Receives t he clock ext ernally from t he mast er.

SPI int errupt s:
One int errupt vect or associat ed wit h t he USI module;
One int errupt flag, USI I FG:
o Set when bit count er count s t o zero;
Communicat ions
o Generat es an int errupt request when USI I E = 1;
o Cleared when USI CNTx > 0 ( USI I FGCC = 0) , or
direct ly by soft ware;
o St ops t he clock when set .

Figure 14- 37. USI int errupt s- SPI mode.

I
2
C mode
Configure USI module in I
2
C mode ( USI I 2C = 1, USI CKPL = 1,
and USI CKPH = 0) ;

Clear USI LSB and USI 16B ( I
2
C dat a compat ibilit y) ;
Set USI PE6 and USI PE7 ( enables SCL and SDA port funct ions) ;

Figure 14- 38. USI operat ion- I
2
C mode.


Configure mode:
I
2
C mast er:
o Set USI MST and USI I 2C bit s;
o Select clock source ( out put t o SCL line while
USI I FG = 0) .
I
2
C slave:
o Clear t he USI MST;
o SCL is held low if USI I FG = 1, USI STTI FG = 1 or if
USI CNTx = 0.
I
2
C t ransmit t er:
o Dat a value is first loaded int o USI SRL;
o Set USI OE t o enable out put and st art t ransmission
( writ es 8 int o USI CNTx) ;
o Send St art ( or repeat ed St art ) ;
o Define address and set R/ W;
o Slave ACK: ( Dat a TX/ RX + ACK for N byt es) ;
o SCL is generat ed in mast er mode or released from
being held low in slave mode;
o USI I FG is set aft er t he t ransmission of all 8 bit s
( st ops clock signal on SCL in mast er mode or held low
at t he next low phase in slave mode) ;
o St op ( or repeat ed St art ) .

2
C mode: Clock and dat a handling.

I
2
C receiver:
o Clear USI OE ( disable out put ) ;
o Receive by writ ing 8 int o USI CNTx ( USI I FG = 0) ;
o SCL is generat ed in mast er mode or released from
being held low in slave mode;
Communicat ions
o USI I FG is set aft er 8 clocks ( st ops t he clock signal on
SCL in mast er mode or holds SCL low at t he next low
phase in slave mode) .

SDA configurat ion:
Direct ion;
Used for TX/ RX, ACK/ NACK handling and START/ STOP
generat ion;
USI GE: Out put lat ch cont rol;
USI OE: Dat a out put enable.

2
C mode: SDA cont rol.

SCL cont rol:
SCL aut omat ically held low in slave mode if USI I FG = 1 or
USI STTI FG = 1;
Requires I
2
C compliant mast er support ing clock st ret ching;
SCL can be released by soft ware wit h USI SCLREL = 1.

2
C mode: SCL cont rol.

START condit ion ( high- t o- low t ransit ion on SDA while SCL is
high) ;
o Clear MSB of t he shift regist er;
o USI STTI FG set on st art ( Sources USI int errupt ) .
STOP condit ion ( low- t o- high t ransit ion on SDA while SCL is
high) :
o Clear t he MSB in t he shift regist er and load 1 int o
USI CNTx ( finishes t he acknowledgment bit and pull
SDA low) ;
o USI STP set on st op ( CPU- accessible flag) .

2
C mode: St art / St op det ect ion.

Receiver ACK/ NACK generat ion:
o Aft er address/ dat a recept ion;
o SDA = out put ;
o Out put 1 dat a bit : 0 = ACK, 1 = NACK.
Transmit t er ACK/ NACK Det ect ion:
o Aft er address/ dat a t ransmission;
o SDA = input ;
o Receive 1 dat a bit : 0 = ACK, 1 = NACK.

Arbit rat ion procedure ( in mult i- mast er I
2
C syst ems) ;

I
2
C I nt errupt s:
One int errupt vect or associat ed wit h t he USI ;
Two int errupt flags, USI I FG and USI STTI FG;
Each int errupt flag has it s own int errupt enable bit , USI I E and
USI STTI E;
When an int errupt is enabled, and t he GI E bit is set , a set
int errupt flag will generat e an int errupt request ;
USI I FG is set ( USI CNTx = 0) ;
USI STTI FG is set ( START condit ion det ect ion) .
Communicat ions
2
C mode: I nt errupt s management .

Table 14- 4 gives t he procedure for I
2
C communicat ion bet ween a
Mast er TX and a Slave RX.

Table 14- 4. Example: Communicat ion procedure bet ween Mast er TX and Slave RX.
Mast er TX Slave RX
1: Send St art , Address and R/ W bit 1: Det ect St art , receive address and R/ W
2: Receive ( N) ACK 2: Transmit ( N) ACK
3: Test ( N) ACK and handle TX dat a 3: Dat a RX
4: Receive ( N) ACK 4: Transmit ( N) ACK
5: Test ( N) ACK and prepare St op 5: Reset for next St art
6: Send St op

14.12 Ot her document at i on
This chapt er only covers t he main feat ures of t he different
communicat ion modules included in t he MSP430. The TI web page
cont ains Applicat ion Report s and Present at ions covering t he
communicat ions peripherals, recommendat ions for correct handling
and user applicat ions.
Annex E t hat provide a det ailed analysis of each module. A brief
overview of t he document s is included here:

Ot her document at ion
I nt roduct ion t o MSP430 Communicat ion I nt erfaces
< slap117. pdf>
Makes a comparison bet ween t he feat ures of t he USART,
USCI and USI communicat ion modules. Gives t he
charact erist ics of t he RS232, SPI and I
2
C communicat ion
modules.

I n- Dept h wit h MSP430s New Communicat ion I nt erfaces
< slap110. pdf>
Present s t he differences bet ween t he USCI and USI
int erfaces. Provides informat ion concerning t he USCI and USI
communicat ion modes ( SPI and I
2
C) .

Hands- on: The New MSP430 Communicat ion Peripherals
< slap120. pdf>
A dedicat ed laborat ory for SPI using t he USI and I
2
C using
t he USCI .

New High Performance, Dual Communicat ion Module USCI
Describes t he feat ures of t he USCI module and it s different
communicat ion modes: UART/ LinBUS asynchronous mode,
SPI synchronous mode and I
2
C synchronous mode. Highlight s
bus and device select ion.

Powerful Yet Simple: Low- Cost Serial Communicat ion wit h t he
New USI Module
Provides an overview of t he USI and gives t he charact erist ics
of SPI and I
2
C communicat ion modes using t his module. I t
also present s t he syst em- level benefit s of using t he USI .

RF Basics, RF for Non- RF Engineers < slap127. pdf>
Explains RF basics: building blocks of an RF syst em; RF
Paramet ers; RF Measurement and equipment needed.

Select ing t he Right RF Prot ocol for your MSP430 Applicat ion
Provides an int roduct ion t o ult ra- low power wireless
net working and present s t he low power prot ocol select ion
crit eria, focusing on TI devices: 802. 15. 4, ZigBee and
SimpliciTI . Also recommends t he appropriat e prot ocol and
some applicat ion examples.

I mplement ing I rDA Wit h The MSP430 < slaa202a. pdf>
I mplement at ion of t he I rDA Lit e prot ocol ( I rPHY, I rLAP, and
I rLMP) on t he MSP430, as well as Tiny Transfer Prot ocol
( TTP) and I rCOMM 3- wire services as a passive, secondary-
only device. I rPHY implement at ions are provided using a
Timer_A- based approach as well as using t he USCI _A
hardware module.
Communicat ions
Aut omat ic Baud Rat e Det ect ion on t he MSP430 < slaa215. pdf>
Present s t he implement at ion of t he int erface t o t he user
t hrough a serial t erminal via RS- 232, using Aut omat ic Baud
Rat e ( ABR) det ect ion t o mat ch of baud rat es bet ween t he
communicat ion t erminals.

Soft ware I
2
C Slave Using t he MSP430 < slaa330. pdf>
Describes t he design of a soft ware I
2
C slave t hat can run up
t o 100- kbps using an MSP430.

Using t he USCI I
2
C Mast er < slaa382. pdf>
Overview of t he use of t he I
2
C mast er funct ion set ( single-
mast er t ransmit t er/ receiver mode using 7- bit device
addressing) for MSP430 devices wit h t he USCI module.

Using t he USCI I
2
C Slave < slaa383. pdf>
Overview of t he use of t he I
2
C slave funct ion ( t o handle bot h
t ransmit and receive request s from I
2
C mast er) for MSP430
devices wit h t he USCI module.

Using t he USI I
2
C Code Library < slaa368. pdf>
Overview of t he mast er and slave code libraries for I
2
C
communicat ion using t he USI module of t he MSP430F20xx.

14.13 Regi st er s

14.13.1 USART Per i pher al I nt er f ace ( UART and SPI modes)
The universal synchronous/ asynchronous receive/ t ransmit ( USART)
peripheral int erface support s t wo serial modes, in a singe hardware
module.
This sect ion provides t he regist er bit definit ions for bot h USART
peripheral int erfaces:
Asynchronous UART mode;
Synchronous SPI mode.

I n t his sect ion, t he regist ers for bot h modes are described
simult aneously, t aking int o account t hat some of t hem use t he
same mnemonic, only different iat ed by t he regist er number
( UART for UART mode and SPI for SPI mode) . The regist ers
exclusively used for each mode are described separat ely.

Regist ers
UART and SPI modes: Ux CTL, USART Cont r ol Regi st er

Mode 7 6 5 4 3 2 1 0
UART PENA PEV SPB CHAR LI STEN SYNC MM SWRST
SPI Unused Unused I
2
C
( 1)
CHAR LI STEN SYNC MM SWRST

( 1)
Not implement ed in 4xx devices.

Bi t UART mode descr i pt i on SPI mode descr i pt i on
7 PENA Parit y enable when PENA = 1
Parit y bit is generat ed ( UTXDx) and expect ed ( URXDx) .
Unused
6 PEV Parit y select :
PEV = 0 Odd parit y
PEV = 1 Even parit y
Unused
5 SPB St op bit select :
SPB = 0 One st op bit
SPB = 1 Two st op bit s
I
2
C I
2
C or SPI mode select when SYNC = 1.
I
2
C = 0 SPI mode
I
2
C = 1 I
2
C mode
4 CHAR Charact er lengt h:
CHAR = 0 7- bit dat a
CHAR = 1 8- bit dat a
CHAR As UART mode
3 LI STEN List en enable when LI STEN = 1. The t ransmit signal is
int ernally fed back t o t he receiver.
LI STEN As UART mode

2 SYNC Synchronous mode enable:
SYNC = 0 UART mode
SYNC = 1 SPI Mode
SYNC As UART mode
1 MM Mult iprocessor mode select
MM = 0 I dle- line mult iprocessor prot ocol
MM = 1 Address- bit mult iprocessor prot ocol
MM Mast er mode:
MM = 0 USART is slave
MM = 1 USART is mast er
0 SWRST Soft ware reset enable:
SWRST = 0 Disabled. USART reset released for
operat ion
SWRST = 1 Enabled. USART logic held in reset st at e
SWRST As UART mode

Communicat ions
UART and SPI modes: Ux TCTL, USART Tr ansmi t Cont r ol Regi st er

Mode 7 6 5 4 3 2 1 0
UART Unused CKPL SSELx URXSE TXWAKE Unused TXEPT
SPI CKPH CKPL SSELx Unused Unused STC TXEPT

7 Unused CKPH
6 CKPL Clock polarit y select :
CKPL = 0 UCLKI = UCLK
CKPL = 1 UCLKI = invert ed UCLK
CKPL Clock polarit y select :
CKPL = 0 UCLKI = The inact ive st at e is low.
CKPL = 1 UCLKI = The inact ive st at e is high.
5- 4 SSELx BRCLK source clock:
SSEL1 SSEL0 = 00 UCLKI
SSEL1 SSEL0 = 01 ACLK
SSEL1 SSEL0 = 10 SMCLK
SSEL1 SSEL0 = 11 SMCLK
SSELx BRCLK source clock:
SSEL1 SSEL0 = 00 Ext ernal UCLK ( slave mode only)
SSEL1 SSEL0 = 01 ACLK ( mast er mode only)
SSEL1 SSEL0 = 10 SMCLK ( mast er mode only)
SSEL1 SSEL0 = 11 SMCLK ( mast er mode only)
3 URXSE UART receive st art - edge enable when URXSE = 1 Unused

2 TXWAKE Transmit t er wake:
TXWAKE = 0 Next frame t ransmit t ed is dat a
TXWAKE = 1 Next frame t ransmit t ed is an address
Unused
1 Unused STC Slave t ransmit cont rol:
STC = 0 4- pin SPI mode: STE enabled.
STC = 1 3- pin SPI mode: STE disabled.
0 TXEPT Transmit t er empt y flag:
TXEPT = 0 UART is t ransmit t ing dat a and/ or dat a
is wait ing in UxTXBUF
TXEPT = 1 Transmit t er shift regist er and UxTXBUF
are empt y or SWRST= 1
TXEPT Transmit t er empt y flag:
TXEPT = 0 UART is t ransmit t ing dat a and/ or dat a is
wait ing in UxTXBUF
TXEPT = 1 UxTXBUF and TX shift regist er are
empt y

Regist ers
UART and SPI modes: Ux RCTL, USART Recei ve Cont r ol Regi st er

Mode 7 6 5 4 3 2 1 0
UART FE PE OE BRK URXEI E URXWI E RXWAKE RXERR
SPI FE Unused OE Unused Unused Unused Unused Unused

7 FE Framing error flag:
FE = 0 No error
FE = 1 Charact er received wit h low st op bit
FE Mast er mode framing error flag: ( MM = 1 and STC = 0)
FE = 0 No conflict det ect ed
FE = 1 Bus conflict ( STEs negat ive edge)
6 PE Parit y error flag:
PE = 0 No error
PE = 1 Charact er received wit h parit y error
Unused
5 OE Overrun error flag:
OE = 0 No error
OE = 1 A charact er was t ransferred int o UxRXBUF
before t he previous charact er was read.
OE As UART mode
4 BRK Break det ect flag:
BRK = 0 No break condit ion
BRK = 1 Break condit ion occurred
Unused
3 URXEI E Receive erroneous- charact er int errupt - enable:
URXEI E = 0 Err. charact ers rej ect ed ( URXI FGx= 0)
URXEI E = 1 Err. charact ers received ( URXI FGx= 1)
Unused

2 URXWI E Receive wake- up int errupt - enable:
URXWI E = 0 All received charact ers set URXI FGx
URXWI E = 1 Received address charact ers set
URXI FGx
Unused
1 RXWAKE Receive wake- up flag:
RXWAKE = 0 Received charact er is dat a
RXWAKE = 1 Received charact er is an address
Unused
0 RXERR Receive error flag:
RXERR = 0 No receive errors det ect ed
RXERR = 1 Receive error det ect ed
Unused

Communicat ions
UART and SPI modes: Ux BR0, USART Baud Rat e Cont r ol Regi st er 0

Mode 7 6 5 4 3 2 1 0
UART / SPI 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0

UART and SPI modes: Ux BR1, USART Baud Rat e Cont r ol Regi st er 1

Mode 7 6 5 4 3 2 1 0
UART / SPI 2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8

7 UxBRx The valid baudrat e cont rol range is 3 s UxBR < 0FFFFh,
where UxBR = { UxBR1+ UxBR0} .
Unpredict able receive/ t ransmit t iming occurs if UxBR < 3.
UxBRx The baudrat e generat or uses t he cont ent s of
{ UxBR1+ UxBR0} t o set t he baud rat e.
Unpredict able SPI operat ion occurs if UxBR < 2.

UART and SPI modes: Ux MCTL, USART Modul at i on Cont r ol Regi st er

Mode 7 6 5 4 3 2 1 0
UART / SPI m7 m6 m5 m4 m3 m2 m1 m0

7 UxMCTLx Select s t he modulat ion for BRCLK. UxMCTLx Not used in SPI mode and should be set t o 00h.

Regist ers
UART and SPI modes: Ux RXBUF, USART Recei ve Buf f er Regi st er

Mode 7 6 5 4 3 2 1 0
UART / SPI 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0

7 UxRXBUFx The receive- dat a buffer is user accessible and cont ains
t he last received charact er from t he receive shift
regist er.
Reading UxRXBUF reset s t he receive- error bit s, t he
RXWAKE bit , and URXI FGx.
I n 7- bit dat a mode, UxRXBUF is LSB j ust ified and t he
MSB is always cleared.
UxRXBUFx The receive- dat a buffer is user accessible and cont ains
t he last received charact er from t he receive shift
regist er.
Reading UxRXBUF reset s t he OE bit and URXI FGx flag.

I n 7- bit dat a mode, UxRXBUF is LSB j ust ified and t he
MSB is always cleared.

UART and SPI modes: Ux TXBUF, USART Tr ansmi t Buf f er Regi st er

Mode 7 6 5 4 3 2 1 0
UART / SPI 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0

7 UxTXBUFx The t ransmit dat a buffer is user accessible and holds
t he dat a wait ing t o be moved t o t he t ransmit shift
regist er and t ransmit t ed on UTXDx.
Writ ing t o t he t ransmit dat a buffer clears UTXI FGx.
The MSB of UxTXBUF is not used for 7- bit dat a and is
cleared.
UxTXBUFx The t ransmit dat a buffer is user accessible and cont ains
current dat a t o be t ransmit t ed.
When seven- bit charact er- lengt h is used, t he dat a
should be MSB j ust ified before being moved int o
UxTXBUF.
Dat a is t ransmit t ed MSB first .
Writ ing t o UxTXBUF clears UTXI FGx.

Communicat ions
UART and SPI modes: ME1, Modul e Enabl e Regi st er 1

Mode 7 6 5 4 3 2 1 0
UART UTXE0 URXE0
SPI USPI E0

7 UTXE0 USART0 t ransmit enable:
UTXE0 = 0 Module not enabled
UTXE0 = 1 Module enabled

6 URXE0 USART0 receive enable:
URXE0 = 0 Module not enabled
URXE0 = 1 Module enabled
USPI E0 USART0 SPI enable:
USPI E0 = 0 Module not enabled
USPI E0 = 1 Module enabled
The remaining bit s may be used by ot her modules. See device- specific dat a sheet .

UART and SPI modes: ME2, Modul e Enabl e Regi st er 2

Mode 7 6 5 4 3 2 1 0
UART UTXE1 URXE1
SPI USPI E1

7 UTXE1 USART1 t ransmit enable:
UTXE1 = 0 Module not enabled
UTXE1 = 1 Module enabled

6 URXE1 USART1 receive enable:
URXE1 = 0 Module not enabled
URXE1 = 1 Module enabled
USPI E1 USART1 SPI enable:
USPI E1 = 0 Module not enabled
USPI E1 = 1 Module enabled

Regist ers
UART and SPI modes: I E1, I nt er r upt Enabl e Regi st er 1

Mode 7 6 5 4 3 2 1 0
UART / SPI UTXI E0 URXI E0

7 UTXI E0 USART0 UTXI FG0 t ransmit int errupt enable:
UTXI E0 = 0 I nt errupt not enabled
UTXI E0 = 1 I nt errupt enabled
UTXI E0 As UART mode
6 URXI E0 USART0 URXI FG0 receive int errupt enable:
URXI E0 = 0 I nt errupt not enabled
URXI E0 = 1 I nt errupt enabled
URXI E0 As UART mode

UART and SPI modes: I E2, I nt er r upt Enabl e Regi st er 2

Mode 7 6 5 4 3 2 1 0
UART / SPI UTXI E1 URXI E1

7 UTXI E1 USART1 UTXI FG1 t ransmit int errupt enable:
UTXI E1 = 0 I nt errupt not enabled
UTXI E1 = 1 I nt errupt enabled
UTXI E1 As UART mode
6 URXI E1 USART1 URXI FG1 receive int errupt enable:
URXI E1 = 0 I nt errupt not enabled
URXI E1 = 1 I nt errupt enabled
URXI E1 As UART mode
Communicat ions
UART and SPI modes: I FG1, I nt er r upt Fl ag Regi st er 1

Mode 7 6 5 4 3 2 1 0
UART / SPI UTXI FG0 URXI FG0

7 UTXI FG0 USART0 t ransmit int errupt flag. UTXI FG0 is set when
U0TXBUF is empt y.
UTXI FG0 = 0 No int errupt pending
UTXI FG0 = 1 I nt errupt pending
UTXI FG0 As UART mode
6 URXI FG0 USART0 receive int errupt flag. URXI FG0 is set when
U0RXBUF has received a complet e charact er.
URXI FG0 = 0 No int errupt pending
URXI FG0 = 1 I nt errupt pending
URXI FG0 As UART mode

UART and SPI modes: I FG2, I nt er r upt Fl ag Regi st er 2

Mode 7 6 5 4 3 2 1 0
UART / SPI UTXI FG1 URXI FG1

7 UTXI FG1 USART1 t ransmit int errupt flag. UTXI FG1 is set when
U1TXBUF is empt y.
UTXI FG1 = 0 No int errupt pending
UTXI FG1 = 1 I nt errupt pending
UTXI FG1 As UART mode
6 URXI FG1 USART1 receive int errupt flag. URXI FG1 is set when
U1RXBUF has received a complet e charact er.
URXI FG1 = 0 No int errupt pending
URXI FG1 = 1 I nt errupt pending
URXI FG1 As UART mode
Regist ers
14.13.2 USCI per i pher al i nt er f ace ( UART, SPI and I
2
C modes)
The universal serial communicat ion int erface ( USCI ) modules
support mult iple serial communicat ion modes. Different USCI
modules support different modes. Each USCI module is ident ified by
a different let t er ( USCI _A or USCI _B) .
I f more t han one ident ical USCI module is implement ed on one
device, t he modules are ident ified wit h increment ing numbers
( USCI _A0 and USCI _A1) . See t he device- specific dat a sheet t o
det ermine which USCI module, if any, is implement ed on which
device.

The USCI _Ax modules support :
UART mode;
Pulse shaping for I rDA communicat ions;
Aut omat ic baud rat e det ect ion for LI N communicat ions;
SPI mode.

The USCI _Bx modules support :
SPI mode;
I
2
C mode.

This sect ion provides t he regist er bit definit ions for t he USCI
module int erfaces:
Asynchronous UART mode;
Synchronous SPI mode;
Synchronous I
2
C mode;

The regist ers for t he implement ed MSP430 modes are described
simult aneously, t aking int o account t hat some of t hem use t he
same mnemonic, only different iat ed by t he regist er number
( UART for UART mode, SPI for SPI mode and I
2
C for I
2
C
mode) . The regist ers exclusively used for each mode are present ed
separat ely.

Regist ers
UART mode: UCAx CTL0, USCI _Ax Cont r ol Regi st er 0
SPI mode: UCAx CTL0, USCI _Ax Cont r ol Regi st er 0 and UCBx CTL0 USCI _Bx Cont r ol Regi st er 0
I
2
C mode: UCBx CTL0 USCI _Bx Cont r ol Regi st er 0

Mode 7 6 5 4 3 2 1 0
UART UCPEN UCPAR UCMSB UC7BI T UCSPB UCMODEx UCSYNC= 0
SPI UCCKPH UCCKPL UCMSB UC7BI T UCMST UCMODEx UCSYNC= 1
I
2
C UCA10 UCSLA10 UCMM Unused UCMST UCMODEx= 11 UCSYNC= 1

Bi t UART mode descr i pt i on SPI mode descr i pt i on I
2
C mode descr i pt i on
7 UCPEN Parit y enable when UCPEN = 1 UCCKPH Clock phase select :
UCCKPH = 0 Dat a is changed on
t he 1st UCLK edge and capt ured on
t he next one.
UCCKPH = 1 Dat a is capt ured on
t he 1st UCLK edge and changed on
t he next one.
UCA10 Own addressing mode select :
UCA10= 0 7- bit address
UCA10= 1 10- bit address
6 UCPAR Parit y select :
UCPAR = 0 Odd parit y
UCPAR = 1 Even parit y
UCCKPL Clock polarit y select .
UCCKPL = 0 I nact ive st at e: low.
UCCKPL = 1 I nact ive st at e: high.
UCSLA10 Slave addressing mode select :
UCSLA10= 0 7- bit address
5 UCMSB MSB first select :
UCMSB = 0 LSB first
UCMSB = 1 MSB first
UCMSB As UART mode UCMM Mult i- mast er environment select :
UCMM= 0 Single mast er
UCMM= 1 Mult i mast er
4 UC7BI T Charact er lengt h:
UC7BI T = 0 8- bit dat a
UC7BI T = 1 7- bit dat a
UC7BI T As UART mode Unused
3 UCSPB St op bit select :
UCSPB = 0 One st op bit
UCSPB = 1 Two st op bit s
UCMST Mast er mode:
UCMST = 0 USART is slave
UCMST = 1 USART is mast er

UCMST Mast er mode select .
UCMST = 0 Slave mode
UCMST = 1 Mast er mode
2- 1 UCMODEx USCI asynchronous mode:
= 00 UART
= 01 I dle- Line
Mult iprocessor.

= 10 Address- Bit
Mult iprocessor.
= 11 UART wit h ABR.
UCMODEx USCI synchronous mode:
= 00 3- Pin SPI
= 01 4- Pin SPI ( slave enabled
when UCxSTE = 1)
= 10 4- Pin SPI ( slave enabled
when UCxSTE = 0)
= 11 I
2
C
UCMODEx
= 11
USCI Mode:
= 00 3- Pin SPI
= 01 4- Pin SPI ( mast er/ slave
enabled if STE = 1)
= 10 4- Pin SPI ( mast er/ slave
enabled if STE = 0)
= 11 I
2
C
0 UCSYNC= 0 Synchronous mode enable:
UCSYNC = 0 Asynchronous
UCSYNC = 1 Synchronous
UCSYNC= 1 As UART mode UCSYNC= 1 As UART mode
Regist ers
UART mode: UCAx CTL1, USCI _Ax Cont r ol Regi st er 1
SPI mode: UCAx CTL1, USCI _Ax Cont r ol Regi st er 1 and UCBx CTL0 USCI _Bx Cont r ol Regi st er 1
I
2
C mode: UCBx CTL1 USCI _Bx Cont r ol Regi st er 1

Mode 7 6 5 4 3 2 1 0
UART UCSSELx UCRXEI E UCBRKI E UCDORM UCTXADDR UCTXBRK UCSWRST
SPI UCSSELx Unused Unused Unused Unused Unused UCSWRST
I
2
C UCSSELx Unused UCTR UCTXNACK UCTXSTP UCTXSTT UCSWRST

2
7- 6 UCSSELx BRCLK source clock:
= 00 UCLK
= 01 ACLK
= 10 SMCLK
= 11 SMCLK
UCSSELx BRCLK source clock:
= 00 N/ A
= 01 ACLK
= 10 SMCLK
= 11 SMCLK
UCSSELx BRCLK source clock:
= 00 UCLKI
= 01 ACLK
= 10 SMCLK
= 11 SMCLK
5 UCRXEI E Receive erroneous- charact er I E:
= 0 Rej ect ed ( UCAxRXI FG not set )
= 1 Received ( UCAxRXI FG set )
Unused Unused Slave addressing mode select :
4 UCBRKI E Receive break charact er I E:
= 0 Not set UCAxRXI FG.
= 1 Set UCAxRXI FG.
Unused UCTR Transmit t er/ Receiver select :
= 0 Receiver
= 1 Transmit t er
3 UCDORM Dormant . Put s USCI int o sleep mode:
= 0 Not dormant
= 1 Dormant
Unused UCTXNACK Transmit a NACK:
= 0 Acknowledge normally
= 1 Generat e NACK
2 UCTXADDR Transmit address:
= 0 Next frame t ransmit t ed is dat a
= 1 Next frame t ransmit t ed is address
Unused

UCTXSTP Transmit STOP condit ion in
mast er mode:
= 0 No STOP generat ed
= 1 Generat e STOP
1 UCTXBRK Transmit break:
= 0 Next frame t ransmit t ed is not a break
= 1 Next frame t ransmit t ed is a break or a
break/ synch
Unused UCTXSTT Transmit START condit ion in
mast er mode:
= 0 No START generat ed
= 1 Generat e START
0 UCSWRST Soft ware reset enable
= 0 Disabled. USCI reset released for
operat ion
1 Enabled. USCI logic held in reset st at e
UCSWRST As UART mode UCSWRST As UART mode

Communicat ions
UART mode: UCAx BR0, USCI _Ax Baud Rat e Cont r ol Regi st er 0
SPI mode: UCAx BR0, USCI _Ax Bi t Rat e Cont r ol Regi st er 0 and UCBx BR0, USCI _Bx Bi t Rat e Cont r ol Regi st er 0
I
2
C mode: UCBx BR0, USCI _Bx Baud Rat e Cont r ol Regi st er 0

Mode 7 6 5 4 3 2 1 0
UART / SPI / I
2
C UCBRx low byt e

UART mode: UCAx BR1, USCI _Ax Baud Rat e Cont r ol Regi st er 1
SPI mode: UCAx BR1, USCI _Ax Bi t Rat e Cont r ol Regi st er 1 and UCBx BR1, USCI _Bx Bi t Rat e Cont r ol Regi st er 1
I
2
C mode: UCBx BR1, USCI _Bx Baud Rat e Cont r ol Regi st er 1

Mode 7 6 5 4 3 2 1 0
UART / SPI / I
2
C UCBRx high byt e

2
7- 6 UCBRx Clock prescaler set t ing of t he baud rat e
generat or:
Prescaler value ( 16- bit value) =
{ UCAxBR0 + UCAxBR1 x 256}
UCBRx Bit clock prescaler set t ing:

Prescaler value ( 16- bit value) =
{ UCAxBR0 + UCAxBR1 256}
UCBRx As SPI mode

Regist ers
UART mode: UCAx STAT, USCI _Ax St at us Regi st er
SPI mode: UCAx STAT, USCI _Ax St at us Regi st er and UCBx STAT, USCI _Bx St at us Regi st er
I
2
C mode: UCBx STAT, USCI _Bx St at us Regi st er

Mode 7 6 5 4 3 2 1 0
UART UCLI STEN UCFE UCOE UCPE UCBRK UCRXERR UCADDR UCI DLE UCBUSY
SPI UCLI STEN UCFE UCOE Unused Unused Unused Unused UCBUSY
I
2
C Unused UCSCLLOW UCGC UCBBUSY UCNACKI FG UCSTPI FG UCSTTI FG UCALI FG

2
7 UCLI STEN List en enable:
= 0 Disabled
= 1 UCAxTXD is int ernally fed back
t o receiver
UCLI STEN List en enable:
= 0 Disabled
= 1 The t ransmit t er out put
is int ernally fed back t o receiver
Unused
6 UCFE Framing error flag:
= 0 No error
= 1 Charact er wit h low st op bit
UCFE Framing error flag:
= 0 No error
= 1 Bus conflict ( 4w mast er)
UCSCLLOW SCL low:
= 0 SCL is not held low
= 1 SCL is held low
5 UCOE Overrun error flag:
= 0 No error
= 1 Overrun error
UCOE As UART mode UCGC General call address received:
= 0 No general call address
= 1 General call address
4 UCPE Parit y error flag:
= 0 No error
= 1 Charact er wit h parit y error
Unused UCBBUSY Bus busy:
= 0 Bus inact ive
= 1 Bus busy
3 UCBRK Break det ect flag:
= 0 No break condit ion
= 1 Break condit ion occurred
Unused

UCNACKI FG NACK received int errupt flag:
= 0 No int errupt pending
= 1 I nt errupt pending
2 UCRXERR Receive error flag.
= 0 No receive errors det ect ed
= 1 Receive error det ect ed
Unused UCSTPI FG St op condit ion int errupt flag:
1 UCADDR

UCI DLE
Address- bit mult iprocessor mode:
= 0 Received charact er is dat a
= 1 Received charact er is an address
I dle- line mult iprocessor mode:
= 0 No idle line det ect ed
= 1 I dle line det ect ed
Unused UCSTTI FG St art condit ion int errupt flag:
0 UCBUSY USCI busy:
= 0 USCI inact ive
= 1 USCI t ransmit / receive
UCBUSY UCALI FG Arbit rat ion lost int errupt flag:
Communicat ions
UART mode: UCAx RXBUF, USCI _Ax Recei v e Buf f er Regi st er
SPI mode: UCAx RXBUF, USCI _Ax Recei v e Buf f er Regi st er and UCBx RXBUF, USCI _Bx Recei v e Buf f er Regi st er
I
2
C mode: UCBx RXBUF, USCI _Bx Recei v e Buf f er Regi st er

Mode 7 6 5 4 3 2 1 0
UART / SPI / I
2
C UCRXBUFx

2
7- 0 UCRXBUFx The receive- dat a buffer is user
accessible and cont ains t he last
received charact er from t he receive
shift regist er.
Reading UCxRXBUF reset s receive-
error bit s, UCADDR/ UCI DLE bit and
UCAxRXI FG.
I n 7- bit dat a mode, UCAxRXBUF is LSB
j ust ified and t he MSB is always
cleared.
UCRXBUFx As UART mode

Reading UCxRXBUF reset s t he
receive- error bit s, and UCxRXI FG
UCRXBUFx As SPI mode

UART mode: UCAx TXBUF, USCI _Ax Tr ansmi t Buf f er Regi st er
SPI mode: UCAx TXBUF, USCI _Ax Tr ansmi t Buf f er Regi st er and UCBx TXBUF, USCI _Bx Tr ansmi t Buf f er Regi st er
I
2
C mode: UCBx TXBUF, USCI _Bx Tr ansmi t Buf f er Regi st er

Mode 7 6 5 4 3 2 1 0
UART / SPI / I
2
C UCTXBUFx

2
7- 0 UCTXBUFx The t ransmit dat a buffer is user
accessible and holds t he dat a wait ing
t o be moved int o t he t ransmit shift
regist er and t ransmit t ed on UCAxTXD.

Writ ing t o t he t ransmit dat a buffer
clears UCAxTXI FG.
UCTXBUFx The t ransmit dat a buffer is user
accessible and holds t he dat a
wait ing t o be moved int o t he
t ransmit shift regist er and
t ransmit t ed.
Writ ing t o t he t ransmit dat a buffer
clears UCxTXI FG.
UCTXBUFx As SPI mode
Regist ers
UART, SPI and I
2
C modes: I E2, I nt er r upt Enabl e Regi st er 2

Mode 7 6 5 4 3 2 1 0
UART UCA0TXI E UCA0RXI E
SPI UCB0TXI E UCB0RXI E UCA0TXI E UCA0RXI E
I
2
C UCB0TXI E UCB0RXI E

2
3 UCB0TXI E USCI _B0 t ransmit int errupt enable:
UTXI E1 = 0 Disabled
UTXI E1 = 1 Enabled
UCB0TXI E As SPI mode
2 UCB0RXI E USCI _B0 receive int errupt enable:
URXI E1 = 0 Disabled
URXI E1 = 1 Enabled
UCB0RXI E As SPI mode
1 UCA0TXI E USCI _A0 t ransmit int errupt enable:
UTXI E1 = 1 Enabled
UCA0TXI E As UART mode
0 UCA0RXI E USCI _A0 receive int errupt enable:
URXI E1 = 1 Enabled
UCA0RXI E As UART mode

Communicat ions
UART, SPI and I
2
C modes: I FG2, I nt er r upt Fl ag Regi st er 2

Mode 7 6 5 4 3 2 1 0
UART UCA0TXI FG UCA0RXI FG
SPI UCB0TXI FG UCB0RXI FG UCA0TXI FG UCA0RXI FG
I
2
C UCB0TXI FG UCB0RXI FG

2
3 UCB0TXI FG USCI _B0 t ransmit int errupt flag:
UCB0TXI FG As SPI mode
2 UCB0RXI FG USCI _B0 receive int errupt flag:
UCB0RXI FG As SPI mode
1 UCA0TXI FG USCI _A0 t ransmit int errupt flag:
UCA0TXI FG As UART mode
0 UCA0RXI FG USCI _A0 receive int errupt flag:
UCA0RXI FG As UART mode

Regist ers
UART mode: UC1I E, USCI _A1 I nt er r upt Enabl e Regi st er
SPI mode: UC1I E, USCI _A1/ USCI _B1 I nt er r upt Enabl e Regi st er
I
2
C mode: UC1I E, USCI _B1 I nt er r upt Enabl e Regi st er

Mode 7 6 5 4 3 2 1 0
UART Unused Unused Unused Unused UCA1TXI E UCA1RXI E
SPI Unused Unused Unused Unused UCB1TXI E UCB1RXI E UCA1TXI E UCA1RXI E
I
2
C Unused Unused Unused Unused UCB1TXI E UCB1RXI E

2
3 UCB1TXI E USCI _B1 t ransmit int errupt enable:
UTXI E1 = 1 Enabled
UCB1TXI E As SPI mode
2 UCB1RXI E USCI _B1 receive int errupt enable:
URXI E1 = 1 Enabled
UCB1RXI E As SPI mode
1 UCA1TXI E USCI _A1 t ransmit int errupt enable:
UTXI E1 = 1 Enabled
UCA1TXI E As UART mode
0 UCA1RXI E USCI _A1 receive int errupt enable:
URXI E1 = 1 Enabled
UCA1RXI E As UART mode

Communicat ions
UART mode: UC1I FG, USCI _A1 I nt er r upt Fl ag Regi st er
SPI mode: UC1I FG, USCI _A1/ USCI _B1 I nt er r upt Fl ag Regi st er
I
2
C mode: UC1I FG, USCI _B1 I nt er r upt Fl ag Regi st er

Mode 7 6 5 4 3 2 1 0
UART UCA1TXI FG UCA1RXI FG
SPI UCB1TXI FG UCB1RXI FG UCA1TXI FG UCA1RXI FG
I
2
C UCB1TXI FG UCB1RXI FG

2
3 UCB1TXI FG USCI _B1 t ransmit int errupt flag:
UCB1TXI FG As SPI mode
2 UCB1RXI FG USCI _B1 receive int errupt flag:
UCB1RXI FG As SPI mode
1 UCA1TXI FG USCI _A1 t ransmit int errupt flag:
UCA1TXI FG As UART mode
0 UCA1RXI FG USCI _A1 receive int errupt flag:
UCA1RXI FG As UART mode

Regist ers
UART mode: UCAx MCTL, USCI _Ax Modul at i on Cont r ol Regi st er

7 6 5 4 3 2 1 0
UCBRFx UCBRSx UCOS16

Bi t UART mode descr i pt i on
7- 4 UCBRFx First modulat ion pat t ern for BI TCLK16 when UCOS16 = 1
( See Table 19- 3 of t he MSP430x4xx Users Guide)
3- 1 UCBRSx Second modulat ion pat t ern for BI TCLK
( See Table 19- 2 of t he MSP430x4xx Users Guide)
0 UCOS16 Oversampling mode enabled when UCOS16 = 1

UART mode: UCAx I RTCTL, USCI _Ax I r DA Tr ansmi t Cont r ol Regi st er

7 6 5 4 3 2 1 0
UCI RTXPLx UCI RTXCLK UCI REN

7- 2 UCI RTXPLx Transmit pulse lengt h:
t
PULSE
= ( UCI RTXPLx + 1) / ( 2 x f
I RTXCLK
)
1 UCI RTXCLK I rDA t ransmit pulse clock select :
UCI RTXCLK = 0 BRCLK
UCI RTXCLK = 1 BI TCLK16, when UCOS16 = 1
BRCLK, ot herwise
0 UCI REN I rDA encoder/ decoder enable:
UCI REN = 0 I rDA encoder/ decoder disabled
UCI REN = 1 I rDA encoder/ decoder enabled

UART mode: UCAx I RRCTL, USCI _Ax I r DA Recei v e Cont r ol Regi st er

7 6 5 4 3 2 1 0
UCI RRXFLx UCI RRXPL UCI RRXFE

7- 2 UCI RRXFLx Receive filt er lengt h ( minimum pulse lengt h) :
t
MI N
= ( UCI RRXFLx + 4) / ( 2 f
I RTXCLK
)
1 UCI RRXPL I rDA receive input UCAxRXD polarit y. When a light pulse is seen:
UCI RRXPL = 0 I rDA t ransceiver delivers a high pulse
UCI RRXPL = 1 I rDA t ransceiver delivers a low pulse
0 UCI RRXFE I rDA receive filt er enabled:
UCI RRXFE = 0 Disabled
UCI RRXFE = 1 Enabled

Communicat ions
UART mode: UCAx ABCTL, USCI _Ax Aut o Baud Rat e Cont r ol Regi st er

7 6 5 4 3 2 1 0
Reserved UCDELI Mx UCSTOE UCBTOE Reserved UCABDEN

5- 4 UCDELI Mx Break/ synch delimit er lengt h:
UCDELI M1 UCDELI M0 = 00 1 bit t ime
UCDELI M1 UCDELI M0 = 01 2 bit t imes
3 UCSTOE Synch field t ime out error:
UCSTOE = 0 No error
UCSTOE = 1 Lengt h of synch field exceeded measurement
t ime
2 UCBTOE Break t ime out error:
UCBTOE = 0 No error
UCBTOE = 1 Lengt h of break field exceeded 22 bit t imes.
0 UCABDEN Aut omat ic baud rat e det ect enable:
UCABDEN = 0 Baud rat e det ect ion disabled
UCABDEN = 1 Baud rat e det ect ion enabled

I
2
C mode: UCBx I 2COA, USCI Bx I 2C Ow n Addr ess Regi st er

15 14 13 12 11 10 9 8
UCGCEN 0 0 0 0 0 I 2COAx

7 6 5 4 3 2 1 0
I 2COAx

15 UCGCEN General call response enable:
UCGCEN = 0 Do not respond t o a general call
UCGCEN = 1 Respond t o a general call
9- 0 I 2COAx I
2
C own address ( local address of t he USCI _Bx I
2
C cont roller)
Right - j ust ified address
7- bit address Bit 6 is t he MSB, Bit s 9- 7 are ignored.
10- bit address Bit 9 is t he MSB.

Regist ers
I
2
C mode: UCBx I 2CSA, USCI _Bx I 2C Sl av e Addr ess Regi st er

15 14 13 12 11 10 9 8
0 0 0 0 0 0 I 2CSAx

7 6 5 4 3 2 1 0
I 2CSAx

9- 0 I 2CSAx I
2
C slave address ( slave address of t he ext ernal device t o be
addressed by t he USCI _Bx module)
Only used in mast er mode
Right - j ust ified address
7- bit address Bit 6 is t he MSB, Bit s 9- 7 are ignored.
10- bit address Bit 9 is t he MSB.

I
2
C mode: UCBx I 2CI E, USCI _Bx I
2
C I nt er r upt Enabl e Regi st er

7 6 5 4 3 2 1 0
Reserved UCNACKI E UCSTPI E UCSTTI E UCALI E

3 UCNACKI E Not - acknowledge int errupt enable:
UCNACKI E = 0 I nt errupt disabled
UCNACKI E = 1 I nt errupt enabled
2
UCSTPI E
St op condit ion int errupt enable:
UCSTPI E = 0 I nt errupt disabled
UCSTPI E = 1 I nt errupt enabled
1
UCSTTI E
St art condit ion int errupt enable:
UCSTTI E = 0 I nt errupt disabled
UCSTTI E = 1 I nt errupt enabled
0
UCALI E
Arbit rat ion lost int errupt enable:
UCALI E = 0 I nt errupt disabled
UCALI E = 1 I nt errupt enabled

Communicat ions
14.13.3 USI per i pher al i nt er f ace ( SPI and I
2
C modes)

The Universal Serial I nt erface ( USI ) module provides SPI and I
2
C
serial communicat ion using a single hardware module.
This module is implement ed in t he MSP430x20xx devices, i. e. , in t he
eZ430- F2013 hardware development kit and in t he Experiment ers
board.

USI CTL0, USI Cont r ol Regi st er 0

7 6 5 4 3 2 1 0
USI PE7 USI PE6 USI PE5 USI LSB USI MST USI GE USI OE USI SWRST

Bi t Descr i pt i on
7 USI PE7 USI SDI / SDA port enable:
SPI mode I nput
I
2
C mode I nput or open drain out put
USI PE7 = 0 USI funct ion disabled
USI PE7 = 1 USI funct ion enabled
6 USI PE6 USI SDO/ SCL port enable:
SPI mode Out put
I
2
C mode I nput or open drain out put
5 USI PE5 USI SCLK port enable:
SPI slave mode I nput
SPI mast er mode Out put
I
2
C mode I nput
4 USI LSB LSB first select ( direct ion of t he receive and t ransmit shift
regist er) :
USI LSB = 0 MSB first
USI LSB = 1 LSB first
3 USI MST Mast er select :
USI MST = 0 Slave mode
USI MST = 1 Mast er mode
2 USI GE Out put lat ch cont rol:
USI GE = 0 Out put lat ch enable depends on shift clock
USI GE = 1 Out put lat ch always enabled and t ransparent
1 USI OE Dat a out put enable:
USI OE = 0 Out put disabled
USI OE = 1 Out put enabled
0 USI WRST USI soft ware reset :
USI WRST = 0 USI released for operat ion
USI WRST = 1 USI logic held in reset st at e

Regist ers
USI CTL1, USI Cont r ol Regi st er 1

7 6 5 4 3 2 1 0
USI CKPH USI I 2C USI STTI E USI I E USI AL USI STP USI STTI FG USI I FG

7 USI CKPH Clock phase select :
USI CKPH = 0 Dat a is changed on t he first SCLK edge and
capt ured on t he following edge
USI CKPH = 1 Dat a is capt ured on t he first SCLK edge and
changed on t he following edge
6 USI I 2C I
2
C mode enable:
USI I 2C = 0 I
2
C mode disabled
USI I 2C = 1 I
2
C mode enabled
5 USI STTI E START condit ion int errupt - enable:
USI STTI E = 0 I nt errupt on START condit ion disabled
USI STTI E = 1 I nt errupt on START condit ion enabled
4 USI I E USI count er int errupt enable:
USI I E = 0 I nt errupt disabled
USI I E = 1 I nt errupt enabled
3 USI AL Arbit rat ion lost :
USI AL = 0 No arbit rat ion lost condit ion
USI AL = 1 Arbit rat ion lost
2 USI STP STOP condit ion received:
USI STP = 0 No STOP condit ion received
USI STP = 1 STOP condit ion received
1 USI STTI FG START condit ion int errupt flag:
USI STTI FG = 0 No int errupt pending
USI STTI FG = 1 I nt errupt pending
0 USI I FG USI count er int errupt flag:
USI I FG = 0 No int errupt pending
USI I FG = 1 I nt errupt pending

Communicat ions
USI CKCTL, USI Cl ock Cont r ol Regi st er

7 6 5 4 3 2 1 0
USI DI Vx USI SSELx USI CKPL USI SWCLK

7- 5 USI DI Vx Clock divider select :
USI DI V2 USI DI V1 USI DI V0 = 000 Divide by 1
4- 2 USI SSELx Clock source select . Not used in slave mode.
USI SSEL2 USI SSEL1 USI SSEL0 = 000 SCLK
( 1)

USI SSEL2 USI SSEL1 USI SSEL0 = 001 ACLK
USI SSEL2 USI SSEL1 USI SSEL0 = 010 SMCLK
USI SSEL2 USI SSEL1 USI SSEL0 = 011 SMCLK
USI SSEL2 USI SSEL1 USI SSEL0 = 100 USI SWCLK bit
USI SSEL2 USI SSEL1 USI SSEL0 = 101 TACCR0
( 2)

( 1)
Not used in SPI mode

( 2)
Reserved on MSP430F20xx devices
1 USI CKPL Clock polarit y select :
USI CKPL = 0 I nact ive st at e is low
USI CKPL = 1 I nact ive st at e is high
0 USI SWCLK Soft ware clock:
USI SWCLK = 0 I nput clock is low
USI SWCLK = 1 I nput clock is high

USI CNT, USI Bi t Count er Regi st er

7 6 5 4 3 2 1 0
USI SCLREL USI 16B USI I FGCC USI CNTx

7 USI SCLREL SCL line release from low t o idle:
USI SCLREL = 0 SCL line is held low if USI I FG is set
USI SCLREL = 1 SCL line is released
6 USI 16B 16- bit shift regist er enable:
USI 16B = 0 8- bit shift regist er mode. ( Uses USI SRL low byt e)
USI 16B = 1 16- bit shift regist er mode ( Uses bot h USI SRx byt es)
5 USI I FGCC USI int errupt flag clear cont rol:
USI I FGCC = 0 USI I FG aut omat ically cleared on USI CNTx updat e
USI I FGCC = 1 USI I FG is not cleared aut omat ically
4- 0 USI CNTx USI bit count ( Number of bit s t o be received or t ransmit t ed)

Laborat ory 10: Echo t est
USI SRL, USI Low By t e Shi f t Regi st er

7 6 5 4 3 2 1 0
USI SRLx

7- 0 USI SRLx Cont ent s of t he USI low byt e shift regist er

USI SRH, USI Hi gh By t e Shi f t Regi st er

7 6 5 4 3 2 1 0
USI SRHx

7- 0 USI SRHx Cont ent s of t he USI high byt e shift regist er

Communicat ions
14.14 Labor at or y 10: Echo t est

14.14.1 Lab10a: Echo t est usi ng t he UART mode of t he USCI modul e

Pr oj ect f i l es
C source files: Chapt er 14 > Lab10 > Lab10a_st udent . c
Solut ion file: Chapt er 14 > Lab10 > Lab10a_sol ut i on. c

Over vi ew
This laborat ory explores t he USCI module in UART mode t hat will be
connect ed t o a Code Composer Essent ials ( CCE) I O console. When
t he connect ion is est ablished, t he charact er sequence writ t en on t he
keyboard t o t he console will be displayed again on t he console.

A. Resour ces
This laborat ory uses t he USCI module in asynchronous mode. The
RX int errupt act ivat es t he service rout ine t hat reads t he incoming
charact er and sends it out again t o t he PC ( comput er) , allowing t he
inst ant aneous display ( echo) of t he writ t en charact er.
The resources used are:
USCI module;
I nt errupt s;
I O port s:
Syst em clock.

Wit h t he obj ect ive of allowing t he generat ion of t wo different baud
rat es, a funct ion has been added t hat configures t he FLL+ and
select s t he base frequency for t he UART. I n t his example it will be
8 MHz.

B. Sof t w ar e appl i cat i on or gani zat i on
The proposed soft ware is organized as shown in Figure 14- 44. The
main rout ine performs t he necessary hardware configurat ion. Then,
t he hardware t akes command of t he soft ware t hrough t he int errupt
service rout ine generat ed by t he recept ion of a new charact er.
The init ial configurat ion set s t he syst em clock t o a frequency of
8 MHz.

Figure 14- 44. Lab10a: Soft ware applicat ion organizat ion.

C. UART conf i gur at i on

Conf i gur e t he cont r ol r egi st er s
The connect ion will operat e in t he following mode:
Parit y disabled;
LSB first ;
8- bit dat a;
One st op bit .

The module will operat e in t he following mode:
Asynchronous;
SMCLK source clock;
No Receive erroneous- charact er int errupt - enable;
No Receive break charact er int errupt - enable.

Configure t he following cont rol regist ers based on t hese
charact erist ics:

UCA0CTL0 = _______________;
UCA0CTL1 = _______________;

Communicat ions
Baud r at e gener at i on
The module has an 8 MHz clock source and t he obj ect ive is t o
est ablish a connect ion at 9600 Baud. I t is necessary t o select t he
baud rat e generat ion in oversampling mode. Configure t he following
regist ers:

UCA0BR0 = _______________;
UCA0BR1 = _______________;
UCA0MCTL = _______________;

Por t conf i gur at i on
I n order t o set t he ext ernal int erfaces at t he USCI module, it is
necessary t o configure t he I / O port s. Select t he USCI peripheral in
UART mode following t he connect ions provided on t he
Experiment ers board:

P2SEL = __________________;

RX i nt er r upt enabl e
To finish t he module configurat ion, it is necessary t o enable t he
receive int errupt s:

IE2 = ____________________;

D. Anal y si s of oper at i on
Once t he USCI module is configured in accordance wit h t he previous
st eps, init iat e t he experiment by complet ing t he file
Lab10a_st udent .c, compiling it and running it on t he
Experiment ers board. The complet e solut ion can be found in t he file
Lab10a_sol ut i on.c.

For t he correct operat ion, t here must be a connect ion bet ween t he
Experiment ers board and t he PC. I f t he CCE console is disabled, go
t o Wi ndow > Show Vi ew > Consol e t o enable it . I f necessary,
configure t he CCE console opt ions in accordance t o t he connect ion
det ails.

Ver i f i cat i on
Once t he program code is running, any charact er key pressed in t he
PC keyboard will be displayed on t he CCE console.

MSP- EXP430FG4618 SOLUTI ON
Using USCI module in UART mode included in t he MSP-
EXP430FG4618 Development Tool, develop a procedure t o connect
t he development t ool t o t he CCE console. When t he connect ion is
est ablished, t he charact er sequence writ t en by t he keyboard t o t he
console will be displayed again on t he console.

Configure t he cont rol regist ers:
UCA0CTL0 = 0x00;
// UCA0CTL0 =
//UCPEN|UCPAR|UCMSB|UC7BIT|UCSPB|UCMODEx|UCSYNC|
//UCPEN (Parity) = 0b -> Parity disabled
//UCPAR (Parity select) = 0b -> Odd parity
//UCMSB (MSB first select) = 0b -> LSB first
//UC7BIT (Character length) = 0b -> 8-bit data
//UCSPB (Stop bit select) = 0b -> One stop bit
//UCMODEx (USCI mode) = 00b -> UART Mode
//UCSYNC = 0b -> Asynchronous mode

UCA0CTL1 = 0x81;
// UCA0CTL1 =
//UCSSELx|UCRXEIE|UCBRKIE|UCDORM|UCTXADDR|UCTXBRK|UCSWRST|
//UCSSELx (USCI clock source select) = 10b -> SMCLK
//UCRXEIE = 0b -> Erroneous characters rejected
//UCBRKIE = 0b -> Received break characters set
//UCDORM = 0b -> Not dormant
//UCTXADDR = 0b -> Next frame transmitted is data
//UCTXBRK = 0b -> Next frame transmitted is no break
//UCSWRST = 1b -> normally Set by a PUC

Baud rat e generat ion:
UCA0BR0 = 0x34;
UCA0BR1 = 0x00;
//Prescaler = 8MHz/(16 x 9600) = 52 = 0x34
//9600 from 8MHz -> SMCLK

UCA0MCTL = 0x11;
// UCA0MCTL =
//UCBRFx|UCBRSx|UCOS16|
//UCBRFx (1st modulation stage) = 0001b -> Table 19-4
//UCBRSx (2nd modulation stage) = 000b -> Table 19-4
//UCOS16 (Oversampling mode) = 1b -> Enabled
Communicat ions
Configurat ion of port s:
P2SEL |= 0x30;
//P2.4,P2.5 = USCI_A0 TXD,RXD

RX int errupt enable:
IE2 |= UCA0RXIE;
//Enable USCI_A0 RX interrupt

14.14.2 Lab10b: Echo t est usi ng SPI

Pr oj ect f i l es
C source files: Chapt er 14 > Lab10 > Lab10b1_st udent . c
Chapt er 14 > Lab10 > Lab10b2_st udent . c
Solut ion files: Chapt er 14 > Lab10 > Lab10b1_sol ut i on. c
Chapt er 14 > Lab10 > Lab10b2_sol ut i on. c

Over vi ew
This laborat ory explores t he USCI and USI communicat ion int erfaces
in SPI mode. The MSP430 devices included on t he Experiment ers
board will exchange messages bet ween t hemselves, one being t he
MSP430FG4618 ( mast er) t hat will cont rol operat ion of t he ot her
MSP430F2013 device ( slave) . The mast er, by reading t he current
st at e of t he slave, will drive t he slave t o t he new desired st at e,
cont rolling it s act ivit y. I n t his part icular case, swit ching t he st at e of
LED3 will be implement ed.

A. Resour ces
This laborat ory uses t he USCI module of t he MSP430FG4618 device
and t he USI module included on t he MSP430F2013. Bot h unit s
operat e in SPI mode.
The Basic Timer1 of t he mast er device is programmed t o swit ch t he
st at us of t he slave device once every 2 seconds.
The slave is not ified of t he arrival of informat ion t hrough t he
count ing end int errupt of t he USI module.

USCI module;
USI module;
Basic Timer1;
I nt errupt s;
I / O port s.
The soft ware archit ect ure for t his laborat ory is shown in Figure 14-
45.
The mast er unit is composed of t wo soft ware modules:
The "Main mast er t ask" module cont ains t he operat ion algorit hm
of mast er unit ;
The "I SR Basic Timer" module wakes t he "Main mast er t ask"
once every 2 seconds.

The slave unit is also composed of t wo modules:
The "Main slave t ask" module cont ains t he operat ion algorit hm
of t he slave unit ;
The "USI I SR" module reads t he dat a received, prepares t he USI
module for new recept ion and wakes t he "Main slave t ask" t o
execut e t he algorit hm associat ed wit h t he recept ion of t he new
command.

Figure 14- 45. Lab10b: Soft ware archit ect ure.

C. conf i gur at i on

Conf i gur e t he cont r ol r egi st er s USCI _B ( mast er )
The SPI connect ion will operat e in t he following mode:
Clock phase - > Dat a value is updat ed on t he first UCLK edge
and capt ured on t he following edge;
Clock polarit y - > t he inact ive st at e is low;
MSB first ;
8- bit dat a;
Mast er mode;
3- Pin SPI ;
Source clock - > SMCLK.
Communicat ions
charact erist ics:

UCB0CTL0 = _______________:
UCB0CTL1 = _______________;

Dat a r at e USCI _B ( mast er )
The syst em clock is configured t o operat e wit h a frequency of
~ 1048 kHz from t he DCO. This frequency will be t he working base
frequency of t he USCI module. The connect ion operat es at a clock
frequency of ~ 500 kHz. Configure t he following regist ers:

UCB0BR0= ________________;
UCB0BR1= ________________;

Por t conf i gur at i on USCI _B ( mast er )
SPI mode, mat ching t he connect ions provided at t he Experiment ers
board:

P3SEL = __________________;

Conf i gur e t he cont r ol r egi st er s USI ( sl ave)
The SPI connect ion will operat e on t he following mode:
MSB first ;
8- bit dat a.
Slave mode;
Clock phase - > Dat a is changed on t he first SCLK edge and
capt ured on t he following edge;
USI count er int errupt enable.

charact erist ics:

USICTL0 = ________________;
USICTL1 = ________________;

st eps, init iat e t he experiment by complet ing t he files
Lab10b1_st udent . c ( mast er MSP430FG4618) and
Lab10b2_st udent . c ( slave MSP430F2013) , compiling t hem and
running t hem on t he Experiment ers board. The complet e solut ion
can be found in t he files Lab10b1_sol ut i on.c and
Lab10b2_sol uct i on. c.

For t his laborat ory, it is necessary t o set t he following j umper
set t ings:
PWR1/ 2, BATT, LCL1/ 2, JP2;
SPI : H1- 1&2, 3&4, 5&6, 7&8.

Ver i f i cat i on
Once t he program code is running in t he t wo microcont rollers,
monit or LED3 on t he Experiment ers board. I t will blink wit h a period
of 4 seconds.

MSP- EXP430FG4618
( mast er)
SOLUTI ON
Using USCI module in SPI mode included in t he FG4618 ( configured
as mast er) of t he Experiment ers board, est ablish a connect ion t o
t he F2013 by it s USI module in SPI mode. The dat a exchanged is
displayed by t he LED blinking.

Configure t he cont rol regist ers USCI _B ( mast er) :
UCB0CTL0 = 0x29;
//UCB0CTL0 =
// UCCKPH|UCCKPL|UCMSB|UC7BIT|UCMST|UCMODEx|UCSYNC|
//UCCKPH (Clock phase) = 0b -> Data is changed on the
// first UCLK edge and captured on the following edge.
//UCCKPL (Clock polarity) = 0b -> Inactive state is low
//UCMSB (MSB first select) = 1b -> MSB first
//UC7BIT (Character length) = 0b -> 8-bit data
//UCMST (Master mode) = 1b -> Master mode
//UCMODEx (USCI mode) = 00b -> 3-Pin SPI
//UCSYNC (Synch. mode enable) = 1b -> Synchronous mode
Communicat ions

UCB0CTL1 = 0x81;
//UCB0CTL1 =
// UCSSELx | Unused |UCSWRST|
//UCSSELx (USCI clock source select)= 10b -> SMCLK
//UCSWRST (Software reset) = 1b -> normally set by a PUC

Configure t he dat a rat e USCI _B ( mast er) :
UCB0BR0 = 0x02;
UCB0BR1 = 0x00;
// DATA RATE
// Data rate = SMCLK/2 ~= 500kHz
// UCB0BR1 = 0x00 & UCB0BR0 = 0x02

Configure I / O port s:
P3SEL |= 0x0E;
// P3.3, P3.2, P3.1 option select

MSP- EXP430F2013
( slave)
SOLUTI ON
Using USCI module in SPI mode included in t he FG4618 ( configured
t he F2013 by it s USI module in SPI mode. The dat a exchanged is
displayed on t he LED blinking.

USI ( slave) cont rol regist ers:
USICTL0 = 0xE3;
//USICTL0 =
//USIPE7|USIPE6|USIPE5|USILSB|USIMST|USIGE|USIOE|USISWRST|
//USIPE7 (USI SDI/SDA port enable) = 1b -> USI enabled
//USIPE6 (USI SDO/SCL port enable) = 1b -> USI enabled
//USIPE5 (USI SCLK port enable) = 1b -> USI enabled
//USILSB (LSB first) = 0b -> MSB first
//USIMST (Master) = 0b -> Slave mode
//USIGE (Output latch control) = 0b -> Output latch
// enable depends on shift clock
//USIOE (Serial data output enable) = 1b -> Output
enabled
//USISWRST (USI software reset) = 1b -> Software reset

USICTL1 = 0x10;
//USICTL1 =
//USICKPH|USII2C|USISTTIE|USIIE|USIAL|USISTP|USISTTIFG|
//USIIFG|
//USICKPH (Clock phase select) = 0b -> Data is changed
// on the first SCLK edge and captured on the following
// edge
//USII2C (I2C mode enable) = 0b -> I2C mode disabled
//USISTTIE (START condition interrupt) = 0b -> Not used
//USIIE (USI counter) = 1b -> Interrupt enabled
//USIAL (Arbitration lost) = 0b -> Not used
//USISTP (STOP condition received) = 0b -> Not used
//USISTTIFG (START condition int. flag) = 0b -> Not used
//USIIFG (USI counter int. flag) = 0b -> No int. pending

14.14.3 Lab10c: Echo t est usi ng I
2
C

Pr oj ect f i l es
C source files: Chapt er 14 > Lab10 > Lab10c1_st udent . c
Chapt er 14 > Lab10 > Lab10c2_st udent . c
Solut ion files: Chapt er 14 > Lab10 > Lab10c1_sol ut i on. c
Chapt er 14 > Lab10 > Lab10c2_sol ut i on. c

Over vi ew
This laborat ory explores t he USCI and USI communicat ion int erfaces
in I
2
C mode. I t uses t he t wo MSP430 devices included on t he
Experiment ers board: MSP430FG4618 as t he mast er and t he
MSP430F2013 as t he slave. The mast er receives a single byt e from
t he slave as soon as a but t on connect ed t o P1. 0 is pressed.

A. Resour ces
This laborat ory uses t he USCI module of t he MSP430FG4618 device
and t he USI module included in t he MSP430F2013. Bot h unit s
operat e in I
2
C mode.
The int errupt s on t he slave unit are generat ed exclusively by t he USI
module. They are:
START condit ion in t he I
2
C bus;
Dat a recept ion and t ransmission.
The int errupt s on t he mast er unit are provided by t he USCI module.
They are:
Communicat ions
Dat a recept ion;
I nt errupt on Port 1.

USCI module;
USI module;
I nt errupt s;
I / O port s.

The soft ware archit ect ure for t his laborat ory is shown in Figure 14-
46.
The mast er t ask is composed of t wo int errupt service rout ines:
S1 swit ch service rout ine used t o receive a new frame from t he
slave;
USCI module int errupt service rout ine t hat reads t he dat a sent
by t he slave.

Figure 14- 46. Lab10c: Soft ware archit ect ure.

For t he operat ional capabilit y of t he slave unit based on t he USI
module, it is necessary t o implement a st at e machine as shown in
Figure 14- 47. I t is import ant t o not e t hat t he st at es RX Address
and RX ( N) ACK" are t ransient st at es t hat ensure t he USI module is
prepared for t he next act ivit y.


Figure 14- 47. Lab10c: Slave st at e machine.

C. Conf i gur at i on

Conf i gur e t he cont r ol r egi st er s USCI _B ( mast er )
The connect ion via I
2
C bus will operat e in t he following mode:
Address slave wit h 7- bit address;
Mast er mode;
Single mast er;
USCI clock source is SMCLK;

charact erist ics:

UCB0CTL0 = _______________;
UCB0CTL1 = _______________;
Communicat ions

Dat a r at e USCI _B ( mast er )
The syst em clock is configured t o operat e wit h a frequency of
~ 1048 kHz from t he DCO. This frequency will be t he working base
frequency of t he USCI module. The connect ion operat es at a clock
frequency of ~ 95. 3 kHz. Configure t he following regist ers:

UCB0BR0= ________________;
UCB0BR1= ________________;

Por t conf i gur at i on USCI _B ( mast er )
I
2
C mode mat ching t he connect ions provided at t he Experiment ers
board:

P3SEL = __________________;

Conf i gur e t he cont r ol r egi st er s USI ( sl ave)
The connect ion via I
2
C bus will operat e in t he following mode:
Slave mode;
USI count er int errupt enable ( RX and TX) ;
START condit ion int errupt - enable;
USI I FG is not cleared aut omat ically.

charact erist ics:

USICTL0 = _______________;
USICTL1 = _______________;
USICNT = ________________;

The slave unit int errupt service rout ine is not complet e. The port ion
relat ed t o t he I 2C_TX st at e needs t o be complet ed:
Configure t he USI module as out put ;
I nsert t he informat ion t o t ransmit using t he t ransmission
regist er;
Configure t he bit count er.

USICTL0 |=________________;
USISRL =__________________;
USICNT |=_________________;


st eps, init iat e t he experiment by complet ing t he files
Lab10c1_st udent .c ( mast er MSP430FG4618) and
Lab10c2_st udent .c ( slave MSP430F2013) , compiling t hem and
running t hem on t he Experiment ers board. The complet e solut ion
can be found in t he files Lab10c1_sol ut i on. c and
Lab10c2_sol uct i on.c.
For t his laborat ory, t he following j umper set t ings are required:
PWR1/ 2, BATT, LCL1/ 2, JP2;
SPI : H1- 1&2, 3&4.

Ver i f i cat i on
The slave dat a is sent and increment s from 0x00 wit h each
t ransmit t ed byt e, which is verified by t he Mast er. The LED is off for
address or dat a Acknowledge and t he LED t urns on for address or
dat a Not Acknowledge. LED3 blinks at each dat a request . I t is
t urned on wit h a START condit ion and it is t urned off by t he dat a
t ransmit acknowledge by t he slave ( Not e: t he I
2
C bus is not
released by t he mast er since t he successive START condit ions are
int erpret ed as repeat ed START ) .
Verify t he value received set t ing a breakpoint in t he line of code
Rx Buf f er = UCB0RXBUF; of t he USCI int errupt .

MSP- EXP430FG4618
( mast er)
SOLUTI ON
Using USCI module in I
2
C mode included in t he FG4618 ( configured
t he F2013 using it s USI module in I
2
C mode. The mast er receives a
single byt e from t he slave as soon as a but t on connect ed t o P1. 0 is
pressed.

USCI ( mast er) cont rol regist ers:
UCB0CTL0 = 0x0F;

//UCB0CTL0 =
//UCA10|UCSLA10|UCMM|Unused|UCMST|UCMODEx|UCSYNC|
//UCA10 (Own address) = 0b -> Own address (7-bit)
//UCSLA10 (Slave address) = 0b -> 7-bit slave address
//UCMM (Multi-master) = 0b -> Single master
//Unused
//UCMST (Master mode) = 1b -> Master mode
//UCMODEx (USCI mode) = 11b -> I2C Mode
//UCSYNC (Synchronous mode enable) = 1b -> Synchronous
Communicat ions

UCB0CTL1 = 0x81;

//UCB0CTL1 =
//UCSSELx |Unused|UCTR|UCTXNACK|UCTXSTP|UCTXSTT|UCSWRST|
//UCSSELx (USCI clock source select) = 10b -> SMCLK
//Unused
//UCTR (Transmitter/Receiver) = 0b -> Receiver
//UCTXNACK (Transmit a NACK) = 0b -> ACK normally
//UCTXSTP (Transmit STOP condition) = 0b -> No STOP
//UCTXSTT (Transmit START condition) = 0b -> No START
//UCSWRST (Software reset) = 1b -> Enabled

Dat a rat e:
// DATA RATE
// data rate -> fSCL = SMCLK/11 = 95.3kHz
UCB0BR0 = 0x0B; // fSCL = SMCLK/11 = 95.3kHz
UCB0BR1 = 0x00;

Configure port s:
P3SEL |=0x06; // Assign I2C pins to USCI_B0

MSP- EXP430F2013
( slave)
SOLUTI ON
Using USCI module in I
2
C mode included in t he FG4618 ( configured
t he F2013 using it s USI module in I
2
C mode. The mast er receives a
single byt e from t he slave as soon as a but t on connect ed t o P1. 0 is
pressed.

USI ( slave) cont rol regist ers:

USICTL0 = 0XC1;

//USICTL0 =
//USIPE7|USIPE6|USIPE5|USILSB|USIMST|USIGE|USIOE|USISWRST|
//USIPE7 (USI SDI/SDA port enable) = 1b -> USI enabled
//USIPE6 (USI SDO/SCL port enable) = 1b -> USI enabled
//USIPE5 (USI SCLK port enable) = 0b -> SCLK disable
//USILSB (LSB first) = 0b -> MSB first
//USIMST (Master) = 0b -> Slave mode
//USIGE (Output latch control) = 0b -> Output latch
// enable depends on shift clock
//USIOE (Serial data output enable) = 0b -> Output
enabled
//USISWRST (USI software reset) = 1b -> Software reset

USICTL1 = 0x70;

//USICTL1 =
//|USICKPH|USII2C|USISTTIE|USIIE|USIAL|USISTP|USISTTIFG|
//USIIFG|
//USICKPH (Clock phase select) = 0b -> Data is changed
// on the first SCLK edge and captured on the following
// edge.
//USII2C (I2C mode enable) = 1b -> I2C mode enabled
//USISTTIE = 1b -> Interrupt on START condition enabled
//USIIE = 1b -> USI counter interrupt enable
//USIAL (Arbitration lost) = 0b -> Not used
//USISTP (STOP condition received) = 0b -> Not used
//USISTTIFG (START condition int. flag) = 0b -> Not used
//USIIFG (USI counter int. flag) = 0b -> No int. pending

USI Bit Count er Regist er:
USICNT |= 0x20;

//USICNT =
//USISCLREL| USI16B |USIIFGCC |USICNTx|
//USISCLREL (SCL release) = 0b -> SCL line is held low
// if USIIFG is set
//USI16B (16-bit shift register enable) = 0b -> 8-bit
// shift register mode
//USIIFGCC (USI int. flag clear control) = 1b -> USIIFG
// is not cleared automatically
//USICNTx (USI bit count) = 00000b (not relevant)

I
2
C st at e machine:
USICTL0 |= USIOE; // SDA = output
USISRL = SlaveData; // Send data byte
USICNT |= 0x08; // Bit counter = 8, TX data
Communicat ions

14.15 Qui z
1. I n a parallel communicat ion t ransmission mode:
( a) The dat a is t ransferred slower;
( b) Each bit of t he dat a has it s own line;
( c) All of above;
( d) None of above.

2. I n an asynchronous serial communicat ion t ransmission mode:
( a) The dat a bit s arrive sequent ially;
( b) The digit al dat a is t ransferred fast er;
( c) All of above;
( d) None of above.

3. The serial t ransmission mode is t he most widely used digit al dat a
communicat ion met hod because:
( a) I ncreasing bit t ransfer rat es are achieved;
( b) I t is cheaper t han parallel t ransmission mode;
( c) All of above;
( d) None of above.

4. I n serial t ransmission communicat ions, t he frame must include:
( a) St art and st op bit s.
( b) Parit y bit .
( c) All of above;
( d) None of above.

5. Even parit y means t hat an addit ional bit is:
( a) Added t o t he dat a t o make t he sum of t he 1 bit s even;
( b) Subt ract ed from t he dat a t o make t he sum of t he 1 bit s even;
( c) All of above;
( d) None of above.

6. A USART is used:
( a) Only for asynchronous t ransmissions;
( b) Only for synchronous t ransmissions;
( c) I n parallel t ransmission communicat ions;
( d) I n serial t ransmission communicat ions.

Quiz
7. Synchronous communicat ion performed bet ween t wo USART
devices requires:
( a) A common clock eit her in t he t ransmit t er or t he receiver;
( b) No common clock.
( c) An independent clock in t he t ransmit t er;
( d) An independent clock in t he receiver.

8. Asynchronous communicat ion performed by t wo USART devices
requires:
( a) A common clock in t he t ransmit t er and t he receiver;
( b) An independent clock in t he t ransmit t er and t he receiver;
( c) A common clock in t he t ransmit t er or t he receiver;
( d) An independent clock in t he t ransmit t er or t he receiver.

9. I
2
C is a bus:
( a) Synchronous wit h a mast er and a slave where bot h can be t he
t ransmit t er or receiver;
( b) Where t he mast er generat es t he clock;
( c) All of above;
( d) None of above.

10. The USART support s t he following communicat ion modes:
( a) UART and I
2
C;
( b) SPI and I
2
C;
( c) UART and SPI ;
( d) None of above.

11. The USART module has:
( a) One SPI module;
( b) Two SPI modules;
( c) Three SPI modules;
( d) None.

12. The UART:
( a) Transmit s and receives charact ers at a bit rat e synchronous t o
anot her device;
( b) Transmit s charact ers at a bit rat e synchronous t o anot her device
and receives charact ers at a bit rat e asynchronous;
( c) Transmit s charact ers at a bit rat e asynchronous t o anot her
device and receives charact ers at a bit rat e synchronous;
( d) Transmit s and receives charact ers at a bit rat e asynchronous t o
anot her device.
Communicat ions

13. The USART charact er format is composed of:
( a) { St art bit , Seven dat a bit s, Parit y bit , St op bit } .
( b) { St art bit , Eight dat a bit s, Parit y bit , St op bit s} .
( c) { St art bit , Seven dat a bit s, Parit y bit , Address bit ; St op bit }
( d) Each of t he above is possible.

14. The asynchronous communicat ion format s support ed by t he
USART module are:
( a) I dle- line mult iprocessor communicat ion prot ocol;
( b) Address bit mult iprocessor communicat ion prot ocol;
( c) All of above;
( d) None of above.

15. The aut omat ic error det ect ion recognizes:
( a) Framing, Parit y, Receive Overrun and Break condit ion errors;
( b) Framing and Parit y errors;
( c) Receive Overrun and Break condit ion errors;
( d) Framing, Parit y, Receive Overrun errors.

16. The serial clock cont rol in SPI mode when MM = 1 is provided by
t he:
( a) ACLK pin on t he mast er;
( b) BI TCLK USART baud rat e generat or on t he UCLK;
( c) All of above;
( d) UCLK pin on t he mast er.

17. The USCI module has:
( a) One module;
( b) Two modules;
( c) Three modules;
( d) None.

18. The USCI module in UART mode support s:
( a) LI N;
( b) I rDA;
( c) All of above;
( d) None of above.
Quiz

19. The UCMSB bit cont rols:
( a) The direct ion of t he t ransfer;
( b) Select s LSB or MSB first ;
( c) All of above;
( d) None of above.

20. The aut omat ic baud rat e det ect ion is composed by a break
charact er, which is:
( a) Det ect ed when 11 or more cont inuous 0 s are received;
( b) Det ect ed when 4 or more cont inuous 0 s are received;
( c) Det ect ed when 8 or more cont inuous 0 s are received;
( d) None.

21. The aut omat ic baud rat e det ect ion is composed by a synch field,
which is represent ed by:
( a) Dat a 022h inside a byt e field;
( b) Dat a 055h inside a byt e field;
( c) Dat a 044h inside a byt e field;
( d) None.

22. The USCI module in UART mode for I rDA decoding det ect s:
( a) Low pulse;
( b) High pulse;
( c) All of above;
( d) None.

23. The baud rat e can be generat ed by:
( a) Low- frequency;
( b) Oversampling;
( c) All of above;
( d) None of above.

24. I n USCI I
2
C communicat ion, t he ACK bit is sent from t he
receiver aft er:
( a) Each bit on t he 9t h SCL clock;
( b) Each byt e on t he 2nd SCL clock;
( c) Each bit on t he 2nd SCL clock;
( d) Each byt e on t he 9t h SCL clock.
Communicat ions

25. The operat ing modes provided by t he I
2
C mode are:
( a) Mast er t ransmit t er and Slave receiver;
( b) Slave t ransmit t er and Mast er receiver;
( c) All of above;
( d) None of above.

26. The I
2
C st at e change int errupt flags are:
( a) Arbit rat ion- lost and Not - acknowledge;
( b) St art and st op condit ions;
( c) All of above;
( d) None of above.

27. The USI module has:
( a) SPI ;
( b) I
2
C;
( c) All of above;
( d) None of above.

28. The int ernal USI clock generat ion can use:
( a) ACLK and SMCLK;
( b) ACLK and MCLK;
( c) SMCLK and MCLK;
( d) None of above.

29. The USI SR shift regist er support s:
( a) 8 bit s;
( b) 16 bit s;
( c) All of above;
( d) None of above.

30. The USI I FG is set when:
( a) Bit count er count s up t o 0xFF;
( b) Bit count er count s down t o 0x00;
( c) Bit count er count s up t o 0x80;
( d) Bit count er count s up t o 0x08.
FAQs

31. Aft er address/ dat a recept ion t he receiver ACK/ NACK is:
( a) SDA = input : 0 = ACK, 1 = NACK;
( b) SDA = out put : 0 = ACK, 1 = NACK;
( c) SDA = input : 1 = ACK, 0 = NACK;
( d) SDA = out put : 1 = ACK, 0 = NACK.

32. Aft er address/ dat a t ransmission t he t ransmit t er ACK/ NACK is:
( a) SDA = input : 0 = ACK, 1 = NACK;
( b) SDA = out put : 0 = ACK, 1 = NACK;
( c) SDA = input : 1 = ACK, 0 = NACK;
( d) SDA = out put : 1 = ACK, 0 = NACK.

14.16 FAQs
1. How is t he t ransmission mode re- enabled by t he USARTs receiver
in UART mode?
I f t he receiver is disabled ( URXEx = 0) , re- enabling it is
asynchronous t o any dat a st ream t hat may be present on URXDx at
t hat t ime. Synchronizat ion can be performed by t est ing for an idle
line condit ion, before receiving a valid charact er. Set t he URXWI E
and t he URXEI E bit s of t he UxRCTL, USART Receive Cont rol Regist er.
I n t his case, only t he received address charact ers will set URXI FGx.

2. Can a break be det ect ed when t he receive st art - edge det ect
feat ure in USART is used in UART mode?
No. I f t he UART Clock ( BRCLK source) is off, t he break condit ion is
not det ect ed.

3. Why cant I get t he correct dat a t ransmission by writ ing t o t he
UxTXBUF using t he USART in SPI mode?
I t may be an issue of configurat ion errors. Try first t o find if
UTXI FGx = 0 and USPI Ex = 1 when writ ing dat a t o t he UxTXBUF.
This may result in erroneous dat a t ransmission.
Communicat ions

4. What is t he default charact er format for USCI in SPI mode?
The default SPI charact er t ransmission is LSB first . Not e t hat t he
MSB- first mode may be required for communicat ion wit h ot her SPI
int erfaces.

5. I s t here any volt age limit for t he MSP430 SDA and SCL pins levels
when using t he USCI in I
2
C mode?
The MSP430 SDA and SCL pins must not be pulled up above t he
MSP430 VCC level.

6. How can I ensure t hat when init iat ed by t he mast er in a mult iple
consecut ive t ransact ions, t he current t ransact ion is complet ed,
wit hout using a repeat ed st art condit ion in t he USCI I
2
C mode?
Ensure t hat t he t ransmit st op condit ion flag UCTXSTP is cleared
before t he next I
2
C t ransact ion is init iat ed by set t ing UCTXSTT = 1.
Ot herwise, t he current t ransact ion might be affect ed.

7. When working wit h I
2
C dat asheet s, it says t he peripheral does not
ACK. How do I implement t his?
I
2
C always uses an acknowledge of some t ype. Here it means t hat
t he peripheral performs not ACK ( negat ive acknowledge) .

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