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i
FC
(t)(1D) v
Bus
(t)+V
Bus
d(t)
C
1
dv
Bus
(t)
dt
=(1D)
i
FC
(t)I
FC
d(t)
i
load
(t)
(2)
D nominal duty cycle of the PWM FC converter;
i
FC
FC current variation;
i
load
load current variation;
R
L
1
series resistance of L
1
. Note that series resistance of
C
1
is ignored.
For FC current measurement, a rst-order lter is used to
reduce harmonics due to FC converter switching. From (2),
the FC current loop can be modeled, taking into account V
P
,
the amplitude of the PWM saw tooth carrier signal, by the
following open loop transfer function:
i
FCMea
(s)
i
FCREF
(s)
=
PIDcontroller
..
G
C
(1 +T
Ci
s) (1 +T
Cd
s)
T
Ci
s
PWM
..
1
V
P
i
FC
(s)/ d(s)
..
G
i
(1 +T
z
s)
1 +
2
n
s +
_
s
n
_
2
lter
..
K
1
1 +T
1
s
(3)
with
_
G
i
=
I
FC
(1D)
T
z
=
V
Bus
C
1
(1D)I
FC
and
_
_
_
n
=
_
(1D)
2
L
1
C
1
=
R
L
1
C
1
(1D)
2
n
2
. (4)
The derivative time constant T
Cd
is chosen in order to
compensate for the lter pole 1/T
1
associated with the FC
current measurement lter. The gain G
C
and the integral time
constant T
Ci
are set to obtain the desired phase margin.
B. DC Link Voltage Loop
If the losses in both the FC converter and supercapacitor
converter are neglected, the dc link capacitive energy is given
versus supercapacitor power p
SuperC
, FC power p
FC
and load
power p
load
by the following differential equation:
dE
Bus
(t)
dt
= p
SuperC
(t) +p
FC
(t) p
load
(t) (5)
THOUNTHONG et al.: CONTROL STRATEGY OF FUEL CELL AND SUPERCAPACITORS ASSOCIATION 3229
which shows that the transfer function E
Bus
/p
SuperC
is a pure
integrator. The bus energy measurement is carried out by means
of the following calculation:
E
Bus
=
1
2
C
1
v
2
Bus
(6)
associated to a rst-order lter used to reduce harmonics due to
switching. Therefore, as far as the supercapacitor current loop
being much faster than the dc link voltage loop (so that it can be
considered as a pure unity gain), the open loop transfer function
associated to dc link voltage regulation can be written as
E
BusMea
(s)
E
BusREF
(s)
=
PI controller
..
K
E
(1 +T
E
s)
T
Es
E
Bus
/p
SuperC
..
1
s
lter
..
K
2
1 +T
2
s
. (7)
The PI-controller parameter has been designed by means of
the Symmetrical Optimum method.
C. Supercapacitor Voltage Loop
Finally, to obtain the open loop transfer function associated
with the supercapacitor voltage loop, power conservation (with-
out losses) can be written as
v
FC
(t) i
FC
(t) = C
SuperC
v
SuperC
(t)
dv
SuperC
(t)
dt
+ C
1
v
Bus
(t)
dv
Bus
(t)
dt
+p
load
(t) (8)
where C
SuperC
is the supercapacitor capacitance. Note that this
capacitance is known to be nonlinear, so that the system cannot
be made linear by the use of supercapacitor energy. If variations
are introduced, (8) becomes a rst-order system
V
FC
i
FC
(t) + v
FC
(t) I
FC
= C
SuperC
V
SuperC
d v
SuperC
(t)
dt
+C
1
V
Bus
d v
Bus
(t)
dt
+ p
load
(t) (9)
so that the transfer function may be written as a pure integrator,
with a gain depending on the operating point
v
SuperC
(s)
i
FC
(s)
=
V
FC
/V
SuperC
C
SuperC
s
(10)
where V
FC
and V
SuperC
are respectively FC voltage and super-
capacitor voltage at the considered operating point.
Because of the great capacitance of the storage device, using
an integral corrective action will lead to a fairly unstable loop.
A P-controller is sufcient, as far as the gain is high enough to
introduce only a little static error. Therefore, the supercapacitor
voltage loop can be modeled by the following transfer function:
v
SuperMea
(s)
v
SuperCREF
(s)
=
P controller
..
K
V
v
SuperC
/i
FC
..
V
FC
/V
SuperC
C
SuperC
s
lter
..
K
3
1 +T
3
s
.
(11)
Once again, a rst-order lter is used for supercapacitor
voltage measurement, to reduce switching harmonics.
Fig. 9. Hybrid source test bench.
TABLE I
FC CURRENT LOOP PARAMETERS
TABLE II
DC BUS VOLTAGE LOOP PARAMETERS
TABLE III
SUPERCAPACITOR CURRENT LIMITATION FUNCTION PARAMETERS
TABLE IV
SUPERCAPACITOR VOLTAGE LOOP PARAMETERS
IV. EXPERIMENTAL VALIDATION OF THE
HYBRID SOURCE CONTROL
A. Hybrid Source Description
The test bench is presented in Fig. 9. The dc link voltage
reference v
BusREF
is set to 42 V. The dc link capacitance C
1
is
equal to approximately 700 mF. It is composed of output capac-
itances of both the FC converter and supercapacitor converter,
and of input capacitance of the load converter.
The PEMFCsystem(500 W, 40 A, 13 V) was achieved by the
Zentrum fr Sonnenenergie und Wasserstoff-Forschung (ZSW)
society. It is composed of 23 cells of 100 cm
2
in series. It
is supplied using pure hydrogen from bottles under pressure,
and with clean and dry air from a compressor. The super-
capacitive storage device is obtained by means of 12 SAFT
supercapacitors (capacitance: 3500 F, rated voltage: 2.5 V, rated
3230 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 6, DECEMBER 2007
Fig. 10. Hybrid source response during motor starting. Motor speed: (a) 600 r/min, (b) 1000 r/min.
current: 400 A, low frequency equivalent series resistance:
0.8 m) connected in series. Maximum supercapacitor voltage
V
SuperCMax
is then 30 V.
The frequency of the PWM that drives the FC converter is
25 kHz, and its amplitude V
P
is 10 V. Inductor L
1
is obtained
by means of a ferrite core, its inductance is 72 H, and its
series resistance R
L
1
is 10 m. Diode D
1
is a STPS80H100TV
Schottky rectier (100 V, 40 A), and both switches S
1
and S
2
are STE180NE10 power MOSFET transistors (100 V, 180 A).
Table I summarizes FC current loop parameters, which have
been calculated to obtain a phase margin of about 55
.
As mentioned before, the supercapacitor converter is driven
by a hysteresis current controller, with a current ripple of 6 A.
This converter was initially designed for more general purposes,
so that two IGBT SKM200GB123D (1200 V, 200 A) are used
for switches S
3
and S
4
. The inductor L
2
is obtained by means
of a ferrite core, its inductance is 54 H, and its rated current
is 200 A.
B. Control Description
Measurements of the FC current i
FC
, the supercapacitor
current i
SuperC
, the dc link voltage v
Bus
and the supercapacitor
voltage v
SuperC
are carried out by means of zero-ux Hall
effect sensors. Parameters associated with the dc link voltage
regulation loop, for a phase margin of 58
, can be seen in
Table II.
Parameters associated with the supercapacitor current limi-
tation function, and the supercapacitor voltage regulation loop,
are detailed in Tables III and IV, respectively. The FC current
absolute slope limitation is set to 4 A s
1
. This value has been
experimentally determined as the highest current slope of our
FC system, where no fuel starvation occurs.
These two loops, which generate current references
i
SuperCREF
and i
FCREF
, have been implemented in the real-
time card dSPACE DS1104, through the mathematical en-
vironment of MatlabSimulink, with a sampling frequency
of 25 kHz. Moreover, ControlDesk software enables changes
to the parameters of the control. It is also used for driving
the load.
C. Experimental Validation
The experimental tests have been carried out by connecting
the dc link to an active load composed of a current reversible
chopper, loaded by a dc motor coupled with a dc generator. The
motor is current-controlled by means of a hysteresis corrector,
and speed-controlled by means of a P-corrector. Note that
THOUNTHONG et al.: CONTROL STRATEGY OF FUEL CELL AND SUPERCAPACITORS ASSOCIATION 3231
Fig. 11. Hybrid source response during motor braking. Motor speed: (a) 600 r/min, (b) 1000 r/min.
mechanical and magnetic losses are such that the FC rated
operating point is obtained around 750 r/min.
Fig. 10 presents waveforms obtained at motor start. These
are: dc link voltage, motor speed, load power, motor, FC
and supercapacitor currents, FC and supercapacitor voltage.
The initial state is zero for both the FC and supercapacitor
currents, and 25 V for the supercapacitor voltage. In the case
of Fig. 10(a), the nal motor speed is 600 r/min, so that the
nal FC current is less than I
FCRated
. It can be seen that:
1) the storage device supplies most of the power required
during motor acceleration;
2) the peak load power required during motor start is about
500 W, which is comparable with the FC rated power,
and the steady-state load power is about 350 W, entirely
supplied by the FC;
3) the FC current increases with limited slope, up to a level
lower than 40 A;
4) the supercapacitor current, after a sharp increase dur-
ing motor acceleration, decreases slowly down to zero,
simultaneously;
5) the nal supercapacitor voltage is lower than 25 V, be-
cause of the static error introduced by the P-corrector of
the supercapacitor voltage loop.
In the case of Fig. 10(b), the nal motor speed is 1000 r/min,
so that the nal FC current is I
FCRated
. Thus, the storage
device, which once again supplies most of the power required
during motor acceleration, remains in a discharge state after
motor start. In fact, the nal supercapacitor current is 10 A,
because the steady-state load power (about 600 W) is greater
than the FC rated power. Note that the FC current increases up
to 40 A in 10 s (and here slope limitation of 4 A s
1
can be
calculated), and that peak load power is about 1 kW, which is
twice the FC rated power. In both cases, only little perturbations
on the dc link voltage signal can be observed.
Fig. 11 presents waveforms obtained at motor stop. The nal
state is zero for both the FC and supercapacitor currents, and
25 V for the supercapacitor voltage. In the case of Fig. 11(a),
the initial motor speed is 600 r/min. It can be shown that the
storage device rst recovers the power supplied to the dc link
by the FC and by the motor regenerative braking (the motor
current is negative), and then is slightly charged by the FC up to
25 V. The FC current immediately decreases with limited slope,
and in a second phase (supercapacitor nal charge) slowly
decreases down to zero. The peak load power during motor
braking is about 150 W, recovered by the storage device
thanks to the dc link voltage regulation loop, which imposes
negative supercapacitor current.
3232 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 6, DECEMBER 2007
In the case of Fig. 11(b), the initial motor speed is 1000 r/min
and the storage device is more deeply discharged than in the
previous case, demonstrating three phases: rst, the storage
device recovers the power supplied to the dc link by the FC
and the motor regenerative braking; second, it recovers the
constant power supplied to the dc link by the FC; and third,
it is charged by the FC up to 25 V. During the two rst phases,
the FC current is constant and equal to 40 A (I
FCRated
). In
the third phase, it decreases down to zero. The peak load
power during motor braking is about 450 W. Once again,
only little perturbations on the dc link voltage signal can be
seen, which is of major importance in the proposed control
algorithm.
V. CONCLUSION
The most essential objective of this paper is to propose a
new strategy for controlling a distributed dc link supplied by
a hybrid source using supercapacitors as a fast auxiliary source,
in association with a PEMFC as the main source. This strategy
is based on a standard dc link voltage regulation, so that it is
simple and clear-cut. Contrary to what is usually done in the
eld of hybrid source control, no state machine is used, and no
control algorithm permutation is needed.
Experimental results carried out using a hybrid system test
bench, which employs a storage device composed of 12 SAFT
3500 F supercapacitors connected in series, and a ZSW 500-W
PEMFC, have evidently shown the possibility of improving the
transient performance of the FC, and validated the proposed
control principle. This principle can, of course, be applied to
other kinds of auxiliary power source, such as Li-ion batteries,
and with other kinds of main sources. The only condition to
ensure good operation is that the dc link voltage regulation be
much faster than the storage device voltage regulation.
ACKNOWLEDGMENT
The authors would like to thank Dr. I. Sadli for operating the
FC system during experimentations.
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Phatiphat Thounthong received the B.S. and
M.E. degrees in electrical engineering from King
Mongkuts Institute of Technology North Bangkok
(KMITNB), Bangkok, Thailand, in 1996 and 2001,
respectively, and the Ph.D. degree in electrical en-
gineering from Institut National Polytechnique de
Lorraine, Nancy, France, in 2005.
From 1997 to 1998, he was an Electrical Engineer
with E. R. Metal Works, Ltd. (EKARAT Group),
Thailand. From 1998 to 2002, he was an Assistant
Lecturer at KMITNB where he is currently a Lec-
turer. His current research interests include power electronics, electric drives,
and electrical devices (FC, batteries and supercapacitor).
THOUNTHONG et al.: CONTROL STRATEGY OF FUEL CELL AND SUPERCAPACITORS ASSOCIATION 3233
Stphane Ral received the M.E. degree in electrical
engineering from the Ecole Nationale Suprieure
des Ingnieurs Electriciens de Grenoble, Grenoble,
France, in 1992, and the Ph.D. degree in electrical
engineering from the Institut National Polytechnique
de Grenoble, Grenoble, France, in 1996.
Since 1998, he has been an Assistant Professor
at the Institut National Polytechnique de Lorraine,
Nancy, France. His research interests include power
electronic components, supercapacitors, batteries,
and FCs.
Bernard Davat (M89) received the Engineers
degree from Ecole Nationale Suprieure
dElectrotechnique, dElectronique, dInformatique,
dHydraulique et des Telecommunications,
Toulouse, France, in 1975, and the Ph.D. and
Docteur dEtat degrees in electrical engineering
from Institut National Polytechnique de Toulouse,
Toulouse, France, in 1978 and 1984, respectively.
From 1980 to 1988, he was a Researcher at
French National Center for Scientic Research, Lab-
oratoire dElectrotechnique et dElectronique Indus-
trielle. Since 1988, he has been a Professor at Institut National Polytechnique de
Lorraine, Nancy, France. He is the author of Power Semiconductor Converters.
His current research interests include power electronics, drives, and new
electrical devices (FC and supercapacitor).