A New Path-Oriented Effect-Cause Methodology to Diagnose Delay Failures *

Yuan-Chieh Hsu and Sandeep K. Gupta Electrical Engineering - Systems University of Southern California Los Angeles, CA 90089-2562

Abstract
A new methodology to diagnose delay failures is described. Key characteristics of the methodology are (a) path-oriented diagnosis, (b) effect-cause reasoning, and (c) utilization of information obtained from the passing vectors. Two new representations are developed to make manageable the complexity of a path-oriented methodology. The results of diagnosis are (a) proven to include all possible causes of observed delay errors, and (b) empirically found to have very high resolution.

1 Introduction
1.1 Motivation and Applications
Todays applications increasingly require high speed circuits. Aggressive determination of clock frequencies and the use of smaller feature sizes are the two main steps taken to achieve this goal. To achieve high clock frequencies, statistical delays are used instead of worst case delays. In statistical design methodology, the delay of a path is computed by the summation of typical delays (mean delay plus some deviation) of gates along the path. The safety margin resulting from the use of this method is smaller than those for the worst case design methodologies, in which the delay of a path is obtained by adding the worst case delays of all gates along the path. Hence, this aggressive design style is more sensitive to process variations. Also, with rapidly decreasing feature sizes, the device model used for simulation does not capture many secondary effects which become significant in deep submicron technology. Even if the device model is accurate, the time complexity of circuit level simulation, such as SPICE, is impractically high due to the use of a large number of parameters in the device model. Hence, circuit blocks must be simulated at a higher, such as switch or logic, levels. Clearly, the accuracy of high level timing simulation is lower. This simulation inaccuracy, combined with the smaller design safety margin, can cause the delays of actual manufactured ICs to exceed the specification. The methodology of producing a small number of ICs (calledJirst silicon) before commencing volume production is used in industry to detect and diagnose design and/or process errors. Due to the reasons mentioned above, in future, the first
*This research was funded by NSF CAREER Award no. MIP-9502300

silicon yield will become lower, and the problems of diagnosing the desigdprocess error that caused the loss of yield will become complex. Hence, a systematic way to perform delay diagnosis is needed. Even for mass produced ICs, if the yield is low for at-speed delay testing or a large number of field returns occur, delay diagnosis is still needed. There are at least five possible ways in which delay diagnosis can be applied. 1. Mismatches between a design and manufacturing processes may cause excessive delays. When this occurs, delay diagnosis can help designers focus redesign effort on the parts of the circuit which contribute to the excessive delay. 2. The results of delay diagnosis can be used to enhance verification tests. Some worst delay cases may not be exercised during verification if the verification tests are not complete. 3. The results of diagnosis can help identify where and how higher level timing simulation tools can be improved. 4. An important potential application is to change the circuit models to better reflect the characteristics of the silicon fabrication process. Alternately, the results of diagnosis can be used to fine tune the new process if the process itself is the cause of excessive delays. 5. Finally, the results of diagnosis can be used for improving tests, especially in cases where diagnosis was motivated by high volume of field returns. In these cases, the results of diagnosis will help identify additional tests to be added to the original test set.

1.2 Characteristics of the Proposed Method

In the following, we propose a new path-oriented, effectcause methodology to diagnose delay failures. In this section, several characteristics of proposed methodology are given. 1. The proposed methodology is unique in that it uses path delay model which is advantageous for the followingreasons. Firstly, in all the above applications, the target failures we want to diagnose are the subtle ones which can only be captured by considering accumulation of delays along circuit paths. Secondly, paths are the primitives whose delays determine the circuit delay. Hence, it is natural to use path delay model to identify paths suspected of causing the observed errors. In the rest of this paper, a path delay fault will be simply referred to as a

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failure.

2. Another characttristic of the proposed method is the utilization of effect-cause analysis, instead of cause-effect
analysis. There are many difficulties with the use of cause-effect analysis when path delay faults are considered. In the cause-effect analysis, comprehensive fault simulation is required before any observed error is analyzed. In other words, each possible combination of faults must be siinulated to determine the circuit behavior in the presence of these faults. Under path delay fault model, the number of primitive faults, i.e. the path delay faults, can grow exponentially with the circuit size. Furthermore, the prcsence of multiple faults is assumed in path delay fault model, leading to intractably large number of combinations of faults to be simulated. For causeeffect analysis, this leads to significant simulation time and memory complexity. Hence, it is more appropriate to perform effect-cause analysis after the application of tests to the silicoii. 3. The third characteristic of the proposed methodology is the utilization of the knowledge obtained from the passing test vectors in novel ways. The novel ways of using this information (discussed later in this paper) can greatly increase the quality or resolution of the results of the diagnosis. The strong property of robustness implies that the paths that pass robust tests are free of delay faults, and hence these paths can be removed from the suspicious path list obtained using the effect-cause analysis. Previous results in delay diagnosis are limited to gate delay faults [5],which are not suitable for many of the scenarios described above. The effect-cause paradigm, presented in [2, 101, has never bcen explored for delay faults. This paper is organized as follows. Section 2 describes the proposed effect-cause reasoning mechanism. The benefits of taking into account thc information about paths that pass robust and multiple-pathrobust tests are described in Sections 3 and 6, respectively. Sections 4 and 5 describe new representations developed to make manageable the complexity of path oriented delay diagnosis. The overall approach is summarized in Section 7, experimental results are presented in Section 8, and, finally, conclusions are presented in Section 9.

-w-"
I

SaInbd

Figure 1. Circuit for Example 1

2 Effect-CauseAnalysis
The main focus of this section is the reasoning mechanism used by the proposed diagnosis methodology, namely the effect-cause analysis.

21 An Example .
A simple example is used to illustrate the basic concept of the proposed effect-cause analysis.

Example 1 A simple three-gate circuit C is given in Figure 1.

Assume that the valuer; shown in the figure are applied to the four primary inputs, a , b, c, and d. One clock after the seca ond test vector is appliied to C, response is captured at the

primary output line g. For a good circuit (without any delay fault), a rising transition at line g will arrive and settle to the final value (1) before the sampling time. Now, if a 0 is captured at line g, instead of a 1, then one or more delay faults exist in the circuit. (Note that here we assume the circuit to be free of stuck-at faults.) Let us first look at the AND gate GB with outputg. There are two possible scenarios which explain the slow-to-rise problem at line g. One possible explanation is that the delay of gate Gs is larger than the design specification. The other possibility is the transitions at either (or both) of its input lines arrived later than expected. These two potential causes of the slow-to-rise effect at line g are not necessarily mutually exclusive. Based on the known information, we can only conclude that at least one of these potential faults must exist to cause this problem. However, for the purpose of analysis, it is convenient to use delay of subpath e-g to model the combination of sum of the above causes (the excessive delay of gate G3 and the late arrival of the transition at line e). Similarly, delay of subpath f-g can be used to model the excessive delay of gate G3 and the late arrival of the transition at linef. Since therising transitionat lineg cannot occur until both transitions at line e and line f propagating to this line, slow-to-rise problem at either line can cause the slow-to-rise effect at lineg. It is important to note that at least one of the path delay faults, that causes excessive delays along either subpath e-g or f-g, must be present, or no error would occur at line g. An OR condition can be used to describe the relationship between the two causes. Similar analysis can be applied to locate the causes for the slow arrivals of rising transitions at lines e and f . At gate GI, line b has steady non-controlling value and hence does not contribute to the slow-to-rise problem at line e. Hence, line a is the only suspect for this problem. At gate Gz, the time at which the rising transition occurs at line f depends on the earlier of the rising transitions at lines c and d. Hence, the transition at line f can be delayed only if the transition at lines c and d are both delayed. An AND condition can be used to describe the relationship between these two causes. Through such deductive process, paths that are suspected for causing the error at the primary output are identified. In this example, the possible faulty paths are a-e-g (PI),c-f-g (P3), and d-f-g (P4). Faulty path PI alone can explain the error at the primary output. However, neither path P3 nor P4
can alone

explain the error - only simultaneous preaenGe of

faults along both paths, P3 and P4, can explain the error. The result of this diagnosis is represented by the expression Pl +

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PP. 34

It can be seen that when an error is captured at a primary output, only the paths that end at t h s primary output can be the causes of the error. In other words, only the paths within the cone of the primary output must be considered. Bearing this in mind, circuits can be viewed as a combination of multiple cones where each cone can be handled independently. Hence, without loss of generality, in this paper, circuits will be assumed to have single outputs.

2 2 Tracing Method .
In this section, the tracing method that is applied to each failing test vector is described. This tracing method constructs a set which contains all paths suspected of causing the observed error. A five-valued logic (SO, S1, UO, U1, XX) is used here to represent a steady state 0, a steady state 1, a 1 to 0 transition (last transition), and a 0 to 1 transition. Only lines with transitions (with or without hazards) can have excessive delays. After the final transition, the line will stay steady. If an erroneous response is captured at an output, then it is certain that the final transition has arrived late. So, it is necessary only to distinguish between lines with a steady state value and with a transition, during the period of test application; there is no need to consider hazards. Hence, the five-valued logic is sufficient. In Example 1, the tracing w s done starting at the PO. a While it is easier to illustrate the tracing methodology in that manner, due to the representation of the paths, a method that uses the algebra of sets in a breadth-first search (BFS) manner from PISto the PO is used to describe the tracing method. The definitions of set operations used are given in the following. Definition 1 The Union of n sets A I ,Az, . . . , A, is defined as n

Figure 2. Cases for Set Propagationin Tkacing Method Given a test sequence, VI, V2, * Vt-1, vt, let vt be the pattern after whose application an erroneous value was captured, i.e., the path delay faults that caused the error were ex&). Also assume that for cited by the two-pattern test (&-I, all gates g in the circuit, the results obtained by simulating , the failing test ( & - I , V ) are assigned to vaZ(g). Let h be a primary input that has a 0 + 1 transition in pattern pair (&-I,&) (i.e., vaZ(h) = U l ) . The method assigns to this input h a set
s ,

UAi =

{ai

I U, E Aj ,j

= 1 , 2 , . . . , n}.

i=l

(1) S ( h ) = {Pi I Pi E Q ( h ,T)}, where set Q ( h ,t) contains all paths that start at input k with ( rising transitions. S h ) can be similarly defined for a falling transition at the input h. (Note that a path Pi with rising transition at its inputs is different from one with falling transition at its inputs. In the following discussion, which centers around analysis of a single failing vector, we do not explicitly mention this fact, since only one of these paths needs to be discussed.) Three conditions which are used to propagate the sets to the PO in a BFS manner are described in the following. In Figure 2, two simple gates with output g are shown. A is the set of inputs to gate g that have been assigned UO;B is the set of inputs to gate g that are assigned U1; C is the remaining inputs to gate g. Since none of the paths which pass through a line with a value S or S1 could have caused the error, gate O g is of interest only if val(g) # S and val(g) # S1. Under O these conditions, the following rules can be used to compute S(g). First, consider the case where g is A D " N/ gate,
then

Definition2 The Cartesian product of n sets A l , A 2 ,

. . . , An is defined as
= { ( a l , a 2 , .. .,an)I a, E Ai, i = 1 , 2 , . . . n}. The expression ( a l ,az, . . . , a,) is called an ordered rz-tuple. Definition 3 The AND-product of n sets, A I ,A2, . . . , An, is defined as a combined operation of 1. A1 x A2 x x A,, 2. for each ordered n-tuple obtained above, a symbolic AND operation is performed on every element of the tuple, i.e., e t i G h (a1 , a2 , . . . , a n ) obtained via Cartesian product is replaced by a1 ' a 2 * * . . .an. The combined operation is denoted as

A1 x Az x

... x A,

where the and U denote the AND-product and the union operations, respectively. Secondly, if g is ORNOR gate, then

Finally, for an inverter,

S(S) = S ( h ) , (4) where h is the only input to the inverter. In general, the set S(g) assigned to any line has the form of S(g) = { Q p , , q o a , * . . , q p , } ,

UAi={al.az***..a,
i=l

EAj,i=l,2,--.ln}.

where qp, is called a product term since it is product of P's and is given by
90, = pr, p , . . . PYk * ,, The propagating rule for a line g that is a fanout stem is described in the following.

The Union operation is used when an OR condition is satisfied, and the AND-product operation defined above is used when an AND condition is satisfied (Example 1).

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- s

Table 2. The Set of SusDects for Each Line Line Set of Suspects
a
m -

(Po, 9 ,P2) {P3, P4, P5}

Figure 3. Circuit for Example 2 Table 1. Paths of Circuit in Figure 3

Ip.thI

LinesIncluded

I-%

b-g-gl-h-ho- j-k-m b-.q-.ql-h-hl-l-m I Pc I c-i-k-m I d-do-h-ho-j-k-m d-do-h-hl -1-m d-dz-i-1-m f-1-m 9 0

I
I

pF:.

~ Z P S ~ lPsPaPs, P5P,P,o) O, Path p6, which is rooted from primary input c, can not explain the error at line m. Furthermore, consider the AND gate with output line g. The combination of the gate type and transitions at the input lines satisfies the OR condition (Equation 2). Hence, the set of suspects at line g , S(g), is obtained by performing union operation on sets S(a) and S ( b ) . The process continues until the set of suspects is obtained at the primary output. Table 2 shows the sets of suspects at each line in the circuit. 0

3 Robustly Tested Paths

The result of the tracing method presented in the last section gives us the suspect set in which each product term contains the path delay faults whose collective presence can explain the error. We construct one such set for each failing test. However, correct circuit response will be typically obtained for a large majority of test vectors. Results of these tests can be used to improve the diagnostic resolution [3]. According to the property of a robust path delay fault (RPDF) test, if no error is found for a CUT for a given test, then the paths that are robustly tested by this test [ 11,9] are proven to be free of delay faults. If paths which passed robust tests also appear in the set of suspects, then the product terms that contain these paths can be removed from the set of suspects for the obvious reason that these paths cannot explain the error observed. The removal of the product terms from the set of suspects greatly improves the quality of the diagnosis, i.e. the diagnostic resolution [3] is higher. To determine which paths in the set of suspects are tested robustly, RPDF simulation is performed for all passing test vectors. The list of paths that pass robust tests m a y be obtained before the application of tracing method, since the set of robustly tested paths gathered from the RPDF simulation will remain unchanged throughout the application of the trac-

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ing method to all failing test vectors. How to use the knowledge of robustly tested paths in the tracing method will now be shown. For illustrative purposes, we assume that a set of paths that are tested robustly is given (obtainedby RPDF simulation). Recall that the first step in the tracing method is to put d l logical paths starting at aPI h in the set of suspects S(h). Now, some of these paths may have been found to pass robust tests; these paths shouldbe removed from the set of suspects. The set of suspects assigned to a primary input h with a 0 + 1 transition has changed to

S(h) = {Pi I Pi E Q'(h, t)),

(6)

where set Q ( h ,t)contains all paths that start at input h with ' rising transitions that are not tested robustly. S ( h ) can be similarly defined for a falling transition at the input h. Other than this change, all conditionsand procedures remain as described in the previous section. One important advantage of representing suspiciouspaths in the product term form rather than individuallylisting them as single paths is illustrated next (the set that lists all the paths found in the set of suspects without the AND relationshipbetween the paths will be referred as list of suspects). The use of AND terms can lead to the complete eliminationfrom the list of suspects of paths that are not even robustly tested. Higher diagnostic resolution is, hence, achieved. For instance, in Example 1 (Figure l), the set of suspects and the list of suspects were { P I ,P3 P4} and {'I, P3, P4), respectively. Now, assume that path P3 passes a robust test. If this information is directly applied to the list of suspects, paths PI and P4 will remain in the list. The number of suspiciouspaths will decrease down to two from three. However, if the same information is applied to the set of suspects, the term P3P4 will be eliminated. This will result in a set containing only one suspicious path, PI. Hence, the diagnostic resolution is higher when the set of products is used to represent suspects.

Figure 4. Compact Set of Suspects for Example 2 tions to determinethe relation type are described in Equations 2 and 3.) The proposed representation, which will be referred as compact set of suspects, is based on the above ObSeNatiOnS. For a given circuit under test, C, and a failing test vector, a procedure, which is a DFS version of the tracing method, is developed to construct the compact set of suspects ('2,"). As pointed out earlier, paths and the relationships between paths are the two key elements of a set of suspects. In order to efficiently represent the first element, namely, the path, the p new representation C is actually a circuit which maintains the path structure for the suspicous paths in the original circuit C. Since only suspiciouspaths are represented in Cp, the complexity of Cp is no larger than that of C. As for the second key element, the relationship between paths, in the new representation Cp, the gate types in Cp are used to reflect the AND/ORrelationships between paths. Hence, only three gate types exist in C:, namely AND, OR, and BUF; AND (OR) gates are used to represent the AND (OR) relationship between paths, BUF gates are used solely to preserve the path structure. The procedure to find Cp can be found in [6]. The compact set of suspects representation of circuit and failing vector in Example 2 is shown in Figure 4. The set of suspectscan be reconstructedeasily from this circuit representation by a process that is similar to the one described in Section 2. In the compact representationcircuit, the union operation must be performed at each OR gate, and the AND-product operation at each AND gate.

x,

4 Representation
One of the challenges in implementingthe tracing method is the high memory complexity of storing the set of product terms, even after the complexity has been rediiced considerablely compared to that of the cause-effect analysis. In this section, an efficient way of representing the set of suspects is proposed to reduce the memory requirement. This representation can also reduce the run time complexity of the multiple path delay fault (MPDF) simulation which will be d m x i b d in Section 6 .

4.2 Updating Cp with Robustly Tested Paths

In Section 3, we described how robustly tested paths can be used to increase diagnostic resolution. The focus of this section is to show how to change the new proposed representation, Cp, to incorporate the improvement in diagnostic resolution. In the compact representation, suspicious paths are represented implicitly in terms of a sequence of circuit lines. Any
line 1 in the representation can only be
removed

if

none

of

4.1 Compact Representation of Set of Suspects

Paths and relationships (AND/OR) between paths are the two basic elements of a set of suspects. Note that two paths can be related only if they converge at a gate G, and share a common subpath from gate G to the primary output. The type of the relationship is determined by the combination of the gate type of G and the transitions at its inputs. (The condi-

the paths passing through line 1 are suspicious. As pointed out in Section 3, two types of paths can be removed from the list of suspects. One type are the paths that pass a robust test. The other type are the paths that only appear in product terms which contain at least one robustly tested path. Assume S ( C 2 ) is the set of paths in the compact representation C?, STP is the set of paths that passed robust tests, and SgTP is the set of suspicious paths remaining in CF after updating. (Note that paths are represented efficiently using the represen-

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1 2

Figure 5. Update of the Compact Set of Suspects for Example 2 tation proposed in [4, 71.) See [6] for procedures to find and

remove lines that do not belong to any path in SETP. Assume that another test robustly tests path POand P3 of the circuit shown in Figure 3. Figure 5 shows the resulting representation for Example 2. Line m is removed from the original circuit representationas a result of applying the procedure to update C, with the information that POand P3 are tested robustly.

Figure 6. The Ordering of Product Terms for OR Gate pact representation of suspects is not sufficient to represent all possible values of the suspect set. Hence, an additional set called vindicated set, that contains the product terms that should have been removed from C,, needed to complete is the representation. In order to obtain the correct suspect set, a set difference operation must be performed on the reconstructedsuspect set and the vindicated set. In this case, the differencebetween the reconstructed suspect set, {PlP7, P4P7, P2P8P9, P2P8P10, P5P8P9, P5P&o}, and the vindicated set, {PlP7,P4P7}, yields the actual set of suspects, (P2P8P9, P2P8P10, P&P9, PSP8P10). (Note that path P7 is not contained in the suspect set, even though P7 does not pass any robust test. This shows 0 the usefulness of the suspect set.)

5 Vindicated Set 5.1 Motivation

By updating the CR as described in above section, the memory complexity is further reduced. However, this simple circuit representation may not be sufficient for certain cases. A line 1 can be removed from the circuit representation only if all paths passing through 1 are no longer suspicious. In other words, if there exists at least one suspicious path containing line I , then this line can not be removed from this circuit representation. If all lines along a non-suspiciouspath P are nonremovable, then P will remain in the updated circuit representation. As a result, the circuit representation cannot be traversed to obtain the exact set of suspects. In this section, we propose an non-enumerativeauxilary representation that can guarantee that the reconstructed set of suspects will be identical to the ones obtained1using the set operationsgiven in Sections 2 and 3. In the iollowing, first an example is used to show the insufficiency of C,. Example 3 Assume, besides path PO and P3 in Example 2, two more paths, PI ant3 P4, are tested robustly. No line can been removed from the compact set of suspects C, after the application of the updating procedure described in Section 4. This implies that each line in C, belongs to at least one of the suspicious paths which is not tested robustly. Since the compact set of suspects remains unchanged, we can conclude that the reconstrcuted suspect Set, (PlP7, P4P7, P2P8P9,
P2PgP10, PsPgPg, P5l0!&O},

5.2 Non-EnumerativeRepresentation of the Vindicated Set

The memory complexity of the vindicated set is lower but still linear in the size of set of suspects. With the goal of further reducing the storage complextity, we have developed an efficient non-enumerativerepresentationfor the vindicated set. The actual representation and the corresponding proce dures in [ 6 ] . In the following, we will examine the intuitive concepts behind this representation. Consider a two-input OR gate (Figure 6) with inputs, 11 and 12, and output, I,. Assume that input lines lI and Z2 have suspect sets S ( l l ) = {Pa,Pb) and S(l2) = (P,,Pd} respectively. The resulting suspect set, S(l,,), after the union of S(Z1) and S(12) can be { P a ,Pb, PelPd} or any permutation of elements Pa, Pb, P,, and Pd, since the elements in a set are unordered. However, if the order of the elements in the suspect sets, S(Z1)and S(Z2) and the order of the union operation are fixed, the elements in the suspect set S(1,) can be obtained in an unique order. In this example, if the order of product terms in S ( l l ) and S(l2) is given above, and the union operation is carried out accroding to the index of the inputs (from 21 to Z2), then the resulting set can only be { P a lPb, PelPd}. Since the order of the product terms is fixed, we can simply use the integer that describes the position of an element in the set of suspects to represent the product term itself. In this case, we can use 1 to represent the first product term, Par2 for Pb, 3 for P,, and 4 for Pd. If there were a third input line of the OR gate, then the first product term from the suspect set of the third input would be labelled 5, since 1 to 4 are already used. For every input line Zj of an OR gate, a label, N o j j S e t ( Z j )must be defined to reflect the total number , of product terms in the suspect set of input l j , for all j < i.

is the same as the one in Ex-

ample 2. However, since paths PI and P4 are tested robustly, product terms PIP7 and P4P7 should have been removed from the suspect set. This indicates that the proposed com-

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1 2

sampled

Figure 7. The Ordering of Product Terms for AND Gate The first product term in the suspect set of input li will be the ( N o f j s e( l i ) -t I 1)th product term in the suspect set of the output line. In addition, for every line E in the Cp, label NFp(I) must be defined. N f p ( l ) is the number of product terms in the set S(Z) where all paths in these product terms have a common subpath P a from line I to the primary output. Labeling procedures to compute N f p and N , j j s e t can be found in [6]. The concept of numbering the product terms can be applied to an AND gate in a similar manner. Figure 7 shows a twoinput AND gate with inputs, 11 and 1 2 , and output 1,. Line I 1 and 12 have the same suspect sets as the ones in above OR gate example. An AND-product operation is performed on S(l1) and S(Z2) to get the suspect set, S(l,). Now, if we fix the order for this AND-product operation in such a way that the first product term of the lower indexed input is AND with all product terms of the higher indexed input, before the second product term of the lower indexed input is AND with the product terms of other inputs, and so on, then we will generate the product terms of the output set in a fixed sequence. In this example, s ( i o ) = { p ~ p ~ , PbP,,PbPd}. The first product PQPd, term P,P, in S ( P )is the combined product of the first prodP,. uct term in S ( l l ) ,P,, and the first product term in The product terms which contain the second product term in S(11),Pb, will be the third and fourth terms, since two product terms have been produced and are assigned the numbers 1 and 2 after the AND operation of the first product term in S(Z1) with all product terms in S(Z2). By using the concepts described above, we have developed the procedures that allow the use of a non-enumerative representation of every element in the vindicated set. The resulting vindicated set will have much smaller storage complexity. Example 4 Consider again the circuit and the failing test vector shown in Example 2. Assume STP = { P I ,P4) is the set of robustly tested paths. Then, a vindicated set that contains elements 1 and 2 is obtained at the primary output. Now, if the procedure that reconstructs the suspect set follows the predefined order, then 1 represents the first product term, PI P7, and 2 represents the second product term, P4P7, in the suspect set. The set obtained by removing these two product terms from the suspect set reconstructed from C will be : the same as the one obtained using the procedures described 0 in Sections 2 and 3.

I
Figure 8. Circuit for Example 5 product term can be concurrentlyfaulty, then the product term cannot be the cause of the observed error and can be removed from the suspect set. An extreme case of proving that all paths in a product term cannot be concurrentlyfaulty, is when it is demonstrated that a subset that contains only one path is fault f e . We already re have explored this case to improve the diagnostic resolution by utilizing RPDFs. With the objective of improvingdiagnostic resolution, our focus in this section moves from the above special case to a more general case where the passing tests are analyzed to determine whether subsets of a product term with two or more paths, can be determined to be not concurrently faulty. The paths that must be concurrentlyfaulty to create an error at the output are called multiple path delay faults (MPDF) [8, 11. If a test vector for which an MPDF satisfies the robustness criteria, then it is guaranteed that not all paths in the MPDFs can be Concurrently faulty. Definition 5 A set of paths is said to be RMPDF tested, if these paths pass a MPDF test and the test satisfies the criteria of robustness for all the off-path input lines of all gates along its constituentpaths. The criteria of RMPDF test is the same one as the robust test except that multiple on-path inputs have to be considered by RMPDF test. Based on robustness property, paths that pass RMPDF (or simply, RMPDF paths) can be used to improve diagnosticresolution -if any subset of a product term in the suspect set is RMPDF tested, then the product term can be removed. Example 5 To illustrate the concept of RMPDF, an extended version of Example 1, where an additional test vector that is assumed to have passed is shown in Figure 8. Since paths P 3 and P (high-lighted in the figure) together pass the test, it 4 can be concluded that path P3 and P cannot be faulty at the 4 same time (but no conclusion can be drawn for each individual path), else an error would have be observed at the output line g. The suspect set at line g was { P I ,P3P4). Now, P3P4
can be removed from the suspect set, and the resulting suspect

s(!~),

6 Robustly Tested MPDF

As mentioned previously, each product term in a suspect set has the meaning that paths in this product term must all be concurrentlyfaulty to be responsible for the error observed at the primary output. If we can prove that not all paths in a

set is { P I } .Higher diagnostic resolution is hence obtained.0 One key issue that should be borne in mind is the highcomplexity of MPDF simulation. Now, to fulfill the objective of improvingthe diagnosticresolution in the context of RMPDF, the task has been divided into two subtasks. 1. Finding all RMPDFs that are useful for increasing the diagnostic resolution. Limiting MPDF simulation to only these makes practical the computational complexity.

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2. Updating the compact set of suspects representation by eliminating from it the product terms containing supersets of RMPDFs detected by passing tests. We have developed an MPDF fault simulation that is suitable for our application [ 6 ] .

7 Summary of the Overall Algorithm

A brief summary fix the steps of the overall algorithm is given in the following. Assume a circuit C and a test set T (divided into the set of failing and passing tests Tf and Tp, respectively) are given. Perform RPDF si mulation on C for the tests in the passing test set Tp.In this step, a set, STP,of paths that pass robust tests will be obtained. For each test t E Tj , perform the tracing method (Sections 2.2 and 4.1) on C, to obtain a compact set of suspects, for each t. For each Cp, perform the circuit updating procedure (Section 4.2) as well as the procedure that generates vindicated set (Section 5.2) with ST^. A new circuit representation, with thc corresponding vindicated set, will be obtained. For each Cr, perform RMPDF simulation with Tp. In this step, the vindicated set will be updated. The details of each individual step and the order in which they are used has been determined via experimentationto decrease run time and memory complexities. Table 3 summarizes the information obtained and actions taken for the failing and passing test vectors for the circuit in Example 2. The test vcctors applied to the circuit are shown in Column 1. In Column 2, the information obtained by processing this vector is listed. The actions taken when new information is presented are given in Column 3. Since the first vector is a failing test, a suspect set is generated. The second and third vectors are passing robust tests for four paths. Four product terms are eliminated from the suspect set as a result. The fourth vector is a passing test for the RMPDF, P ~ P s P demonstrating that these three paths are not con~, currently faulty. Hencc:, the product term can be eliminated from the suspect set. The final set contains only three product terms.

8 Experimental ]Results
All the proposed procedures have been implemented in C. The combinational pans of three ISCAS89 circuits, namely s208, s510, and s820, hiave been used to conduct experiments. In the following, results are reported only for the larger circuits; the results for the smaller circuits are given in [ 6 ] . Five different scenarios of excessive delays are considered. First four scenarios are selected to represent the type of delay defects which may be introduced during manufacturing processes. The fifth scenario is selected to represent a type of problem that may arise due to mischaracterizationof the delay of a library component. Furthermore, three different test sets

are used in this experiment. Test set 751 is a test set with98% robust path delay fault coverage. Test set TS2 is a compact test set with the same fault coverage. Finally, TS3 is shorter test set which has lower fault coverage (44%). The five different faulty scenarios considered in this experiment are as follows. In the first two scenarios, only the delay of a single circuit component is increased beyond its nominal value. In the first scenario, many paths pass through the faulty component, that is, many paths are potentially affected by the excessive delay of this component. In the second scenario, only few paths pass through the faulty component. In the next two scenarios, two faulty components coexist in the circuit. In the third scenario (calledpurullel), the two faulty components have common transitive fanouts, but neither is in the transitive fanout of the other. On the other hand, in the fourth scenario (called serial), one faulty component is in the transitive fanout of the other. Note that, in this scenario, the magnitude of extra delay at each faulty component is small and by itself cannot increase the circuit delay beyond the clock period, i.e. only the concurrent existence of extra delay of both (faulty) components would create a delay fault. In the fifth scenario, all components of a particular type are assumed to have extra delay. This scenario tries to simulate a mischaracterization of delay of a cell in the library. In order to obtain the error responses for these scenarios, the circuit, including the excessive delay for faulty component(s), has been modeled in Verilog and simulated using the Verilog-XL timing simulator. The results obtained by applying the proposed diagnostic method to s820 are shown in Table 4.The first column shows the five scenarios discussed above. For each scenario, the results are presented for each of the three test sets described above. In the third column, the numbers of failing tests and the total number of tests in the test set are shown. Next, the diagnostic results are shown for two cases (a) using tracing method without using the information obtained from RPDF and RMPDF simulations of the passing vectors, and (b) using tracing method as well as the information obtained from both these simulations. For each case, two characteristics of the suspect sets are shown. The column entitled D.R. (Paths) shows the number of paths in the suspect set that pass through at least one faulty component as well as the total number of paths in the suspect sets. The only exception to above is the fourth scenario (rows entitled Double Faults (Serial)) where only the paths which pass through both faulty components are reported to characterize diagnosticresolution. The column entitled D.R. (Terms) shows the numbers of product terms that contain at least one path that belongs the set described above as well as the total number of product terms. Finally, in the last column, the numbers of untested paths which are eliminated from all suspect sets are shown. Following conclusions can be drawn from the results presented in Tables 4 and 5.

1. The diagnostic resolution is improved significantly by

utilization of the information obtained by the RPDF and

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Vector Failing Test: (Tl,T1, T1, T1, T1) Robust Test: (Tl,T1, S O , S1, SO, SO) Robust Test: (TI, T1, SO, SO, SO, SO) RMPDFTest: (Sl,7'1, S O , T1, S1, Sl)

so,

Information Suspect Set: {Po, P3, A P?I P P7, 4

Action

Result:

PZPaPs, PzPaAo, PsPaPg, p5P8plO) P3 PO, fault free eliminate terms: POand Ps P I ,P fault free 4 eliminate terms: PIP and P P 7 4 7 PSPaps fault free eliminate term: PSPSP g Suspect Set: { P ~ P s P ~ , s P IPSPSPIO} P~P o,

Fault Scenario

Test
Set

Diagnostic Result Failing Tests/ w/o Fault Simulation with Fault Simulation D.R. D.R. D. R. D.R. Total Tests (Paths) (Terms) (Paths) (Terms)

Untested Paths Removed

Fault Scenario

Test
Set

Diagnostic Result Failing Tests/ w/o Fault Simulation with Fault Simulation D.R. D.R. D. R. D. R. Total Tests (Paths) (Terms) (Paths) (Terms)

Untested Paths Removed

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RMPDF simulatilms of the passing tests. In some cases, untested paths are indeed eliminated from all suspect sets. The resolution is the lowest for the test set TS3 which has the lowest RPDF fault coverage. Furthermore, the resolution is lower for compact test set TSz, since tests in this set concurrently detect multiple path delay faults. For all five scenarios, the diagnostic resolution obtained by the proposed methodology is very high, especially for the two test sets with high fault coverage. For example, for TS1, in the first two scenarios, all paths that appear in the suspect sets pass through the fault site. In the third scenario, they all pass through at least one fault site. In the fourth scenario, where neither of the faulty components can individually cause delay fault, all paths in the suspect sets pass through both fault sites.

[7] I. Pomeranz, S . M. Reddy, and P. Uppaluri. NEST A NonenumerativeTestGeneration Method for Path Delay Faults in CombinationalCircuits. IEEE Trans. on CAD, 14(12):1505-1515,December1995. [8] Wuudiann Ke. Delay-Verification and Tynthesis of Delay Verifiable Circuits. Technical report, Ph.D. Dissertation,Universityof Massachusetts, 1994. [9] J. C. Lin and S . Reddy. On Delay Fault Testing in Logic Circuits. IEEETrans. on CAD, 6(5):694-703,September 1987. [IO] S . Venkataraman and W.Fuchs. A DeductiveTechniquefor Diagnosis of Bridging Faults. In Pmceedings IEEE Intemational Conference on Computer-Aided Design, pages 562-569,1997. [ 1I G. L. Smith. Model for Delay Faults Based on Paths. In Proceedings IEEEInter] national Test Conference, pages 342-349,1985.

9 Conclusion
A path-oriented me1hodology for diagnosis of delay failures is presented. The niethodology employs effect-causereasoning and exploits the: knowledge of paths that pass robust tests to improve diagnostic resolution. We have proven [6] that the resulting suspect set contains all possible causes of observed errors. New representations have been developed for suspect sets which make manageable the memory complexity of pathoriented diagnosis. The methodology has been implemented, applied to study various fault scenarios and test sets, and found to provide very high diagnostic resolution. The overall diagnostjc process for delay faults does not end when the results are obltained from the proposed algorithm. Designers or process engineers can usually identify the faulty parts that cause the delay problems by using their intuitions and experience. However, the intuition and experience can also prevent these engineers from locating the real causes of the errors, if the causes perceived by them as being likely are not behind the observed errors. The results from the proposed algorithm can be used to help the designers and engineers to locate the faulty parts by giving them a comprehensive list of potential causes that they might have missed.

References
[I J A. Krstic, K. Cheng, and S. Chakradhar. Identification and Test Generation for PrimitiveFaults. In ProceedingsIEEE International Test Conference,pages 423-

432,1996. [2] M. Abramoviciand M. A. Breuer. Multiple fault diagnosis in combinationalcircuits based on an effect-cauie analysis. IEEE Trans. on Computer. C-29(6):451460,June 1980. [3] M. Abramovici,M. A. Breu,:r, and A. D. Friedman. Digital Sysrems Testing and Testable Design. Computer Science Press, New York, N.Y., 1990. [4] S . Bose, P. Agrawal,and V.D. Agrawal. A Path Delay Fault Simulatorfor Sequential Circuits. In Proc. Sixrh Inter: Con$ on VU1 Design, pages 269-274,1993. [5] P. Girard, C. Landrault, and S . Pravossoudovitch. A Novel Approach to Delay-

IEEE-ACM Design Auromation Conference, Fault Diagnosis. In P mcer:dings pages 357-360,1992. [6] Y.-C. Hsu and S . K. Gupta. A New Path-Oriented Effect-Cause Methodologyto
Diagnose. Delay Failures. Technical report, USC Technical Report CENG 98-07,

1998.

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