SYNTHESIS REPORT:

Release 9.1i - xst J.30

Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
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--> Reading design: aluf.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
===============================================================
*
Synthesis Options Summary
*
===============================================================
---- Source Parameters
Input File Name
: "aluf.prj"
Input Format
: mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name
Output Format
Target Device
---- Source Options
Top Module Name
Automatic FSM Extraction
FSM Encoding Algorithm

: "aluf"
: NGC
: xc3s400-5-tq144
: aluf
: YES
: Auto

Safe Implementation
: No
FSM Style
: lut
RAM Extraction
: Yes
RAM Style
: Auto
ROM Extraction
: Yes
Mux Style
: Auto
Decoder Extraction
: YES
Priority Encoder Extraction
: YES
Shift Register Extraction
: YES
Logical Shifter Extraction
: YES
XOR Collapsing
: YES
ROM Style
: Auto
Mux Extraction
: YES
Resource Sharing
: YES
Asynchronous To Synchronous
: NO
Multiplier Style
: auto
Automatic Register Balancing
: No
---- Target Options
Add IO Buffers
: YES
Global Maximum Fanout
: 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication
: YES
Slice Packing
: YES
Optimize Instantiated Primitives : NO
Use Clock Enable
: Yes
Use Synchronous Set
: Yes
Use Synchronous Reset
: Yes
Pack IO Registers into IOBs
: auto
Equivalent register Removal
: YES
---- General Options
Optimization Goal
Optimization Effort
Library Search Order
Keep Hierarchy
RTL Output
Global Optimization
Read Cores
Write Timing Constraints
Cross Clock Analysis
Hierarchy Separator
Bus Delimiter
Case Specifier
Slice Utilization Ratio
BRAM Utilization Ratio

: Speed
:1
: aluf.lso
: NO
: Yes
: AllClockNets
: YES
: NO
: NO
:/
: <>
: maintain
: 100
: 100

Verilog 2001
: YES
Auto BRAM Packing
: NO
Slice Utilization Ratio Delta : 5
===============================================================
*
HDL Compilation
*
===============================================================
Compiling vhdl file "C:/Xilinx91i/Pavendan/aluf.vhd" in Library work.
Architecture behavioral of Entity aluf is up to date.
===============================================================
*
Design Hierarchy Analysis
*
===============================================================
Analyzing hierarchy for entity <aluf> in library <work> (architecture <behavioral>).
===============================================================
*
HDL Analysis
*
===============================================================
Analyzing Entity <aluf> in library <work> (Architecture <behavioral>).
Entity <aluf> analyzed. Unit <aluf> generated.
===============================================================
*
HDL Synthesis
*
===============================================================
Performing bidirectional port resolution...
Synthesizing Unit <aluf>.
Related source file is "C:/Xilinx91i/Pavendan/aluf.vhd".
Found 3-bit 8-to-1 multiplexer for signal <f>.
Found 3-bit subtractor for signal <f$addsub0000> created at line 45.
Found 3-bit xor2 for signal <f$xor0000> created at line 50.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 3 Multiplexer(s).
Unit <aluf> synthesized.
===============================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
:1
3-bit subtractor
:1
# Multiplexers
:1
3-bit 8-to-1 multiplexer
:1
# Xors
:1

3-bit xor2

:1

===============================================================
===============================================================
*
Advanced HDL Synthesis
*
===============================================================
Loading device for application Rf_Device from file '3s400.nph' in environment
C:\Xilinx91i.
===============================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
:1
3-bit subtractor
:1
# Multiplexers
:1
3-bit 8-to-1 multiplexer
:1
# Xors
:1
3-bit xor2
:1
===============================================================
===============================================================
*
Low Level Synthesis
*
===============================================================
Optimizing unit <aluf> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block aluf, actual ratio is 0.
Final Macro Processing ...
===============================================================
Final Register Report
Found no macro
===============================================================
*
Partition Report
*
===============================================================
Partition Implementation Status
-------------------------------

No Partitions were found in this design.

------------------------------===============================================================
*
Final Report
*
===============================================================
Final Results
RTL Top Level Output File Name : aluf.ngr
Top Level Output File Name
: aluf
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs

: 12

Cell Usage :
# BELS
: 25
# LUT2
:1
# LUT3
: 10
# LUT4
:4
# MUXF5
:7
# MUXF6
:3
# IO Buffers
: 12
# IBUF
:9
# OBUF
:3
===============================================================
Device utilization summary:
--------------------------Selected Device :

3s400tq144-5

Number of Slices:
Number of 4 input LUTs:
Number of IOs:
Number of bonded IOBs:

8 out of 3584 0%
15 out of 7168 0%
12
12 out of 97 12%

--------------------------Partition Resource Summary:

--------------------------No Partitions were found in this design.
---------------------------

===============================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 10.942ns
Timing Detail:
-------------All values displayed in nanoseconds (ns)
===============================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 57 / 3
------------------------------------------------------------------------Delay:
10.942ns (Levels of Logic = 7)
Source:
a<0> (PAD)
Destination:
f<2> (PAD)
Data Path: a<0> to f<2>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
5 0.715 1.078 a_0_IBUF (a_0_IBUF)
LUT2:I0->O
2 0.479 0.745 Msub_f_addsub0000_cy<0>11
(Msub_f_addsub0000_cy<0>)

MUXF5:S->O
1 0.540 0.704 Mmux_f_55_SW0_f5 (N22)
LUT4:I3->O
1 0.479 0.000 Mmux_f_55 (N11)
MUXF5:I1->O
1 0.314 0.000 Mmux_f_4_f5_1 (Mmux_f_4_f52)
MUXF6:I0->O
1 0.298 0.681 Mmux_f_2_f6_1 (f_2_OBUF)
OBUF:I->O
4.909
f_2_OBUF (f<2>)
---------------------------------------Total
10.942ns (7.734ns logic, 3.208ns route)
(70.7% logic, 29.3% route)
===============================================================
CPU : 6.41 / 6.79 s | Elapsed : 6.00 / 6.00 s
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Total memory usage is 141552 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)