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E DEGREE EXAMINATION,MAY/JUNE 2009 First Semester VL-1601 DSP Integreted Circuits

Part-A (10*2=20marks) 1.Differentiate ASIC and DSP chip. 2.Draw two input Cmos Nand Gate Model. 3.State Sampling Theorem. 4.Define Tuddile Factors for Radix-2 FFT. 5.List few applications of multirate systems. 6.Mention few advantages of multirate Operations in DSP Systems. 7.Draw Standard DSP Architecture. 8.What is Complex PE? 9.What are the Advantages of redundant number systems? 10.What is FFT processor?

Part-B (5*16=80marks) 11.a.Explain the Fabrication process of two input nand gate. (or) b.write short notes on the following i.recent trends in CMOS technology ii.ASIC for DSP system. 12.a.find DFT for the following sequences and hence find X(5) i.x(n)=(0.5) ^n n=0,1,2,3,4 =0 n=5,6,7,..15.

ii.x(n)=1 n=0,1,2,3 =0 n=4,5,6,7 =0.5 n=8,..15.

(or) b.Draw the flow chart for FFT radix-2 DIT algorithm. ii.find DCT for the sequence x(n)=(0.5)^n u(n). 13.a.Explain in detail the design procedure for Linear phase FIR filter Design (or) b.For the IIR filter H(z) ,realize in i.Direct form I ii. Direct form II iii.Cascade Form iv.Parallel Form. H(z)=(z+1) /(z+5z+6)(z+0.5)

14.a.Explain the DSP Architecture system and Compare with Conventional p system. (or)

b.i.Discuss the Implementation of Complex PE into Hardware. ii.What are the Benefits of Serial Adder Compound to Parallel Adder system.

15.a.Draw the Structure of Complex Muliplies of(4*4)bit and explain the Working. (or) b.Write Short Notes on i.DCT processor and its applications to DSP system. ii.Number system(redundant)and its Implementation in DSP. VL1601-DSP INTEGRATED CIRCUITS Part-A (10*2=20 marks) 1.What is E-beam Mask? 2.Specify two Standard DSPs used for Communication Purpose. 3.State Sampling Theorem. 4.Draw signal Flow Graph of y(n)=ay(n-1)+x(n). 5.List out the well known techniques for Linear Phase FIR Filter. 6.What is Round off Noise? 7.What s MACD Instructions? 8.Draw the Block Diagram Of Dual Ported Memory? 9. Draw the Block Diagram Of Parallel binary Multiplier? 10.What is the residue Number System? Part-B(5*16=80 marks) 11.a Compare CMOS and Bipolar Technology. (or) b.Explain any one ASIC for digital signal processing in detail with its Architecture. 12.a.The transfer Function of a system is given by H(z)=(1+z^-1)/(1-z^-1)(1-z^-1+z^-2). Realize the system in Cascade and Parallel Structure. (or) b.An 8 Point Sequence is given by x(n)={1,1,1,1,2,2,2,2}.Compute 8 point DFT of x(n) by radix-2 DIT-FFT. 13.a.For Analog T.F of Ha(s)=s+2/s+2s+10 determine H(z) by i) Impulse Invariant Transformation ii) Bilinear Transformation (or) b.Explain the Procedure to Obtain the product quantization noise model of Second Order IIR System. 14.a.Explain in Detail and Compare i) Von Neumann Architecture ii) Hardvard Architecture iii) Modified Hardvard Architecture

(or) b.Write the Steps involved in mapping DSP Algorithm to Hardware 15.a.Draw Layout of FFT Processor and Explain its Operation (or) b.What is DCT Processor?Explain its Algorithm which isFollowed in the Processor.