AVR - Kien Thuc Co Ban

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Thanhtam Ho - www.hocavr.com
Bi 1 - Lm quen AVR
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AVR Studio. M phng vi Proteus.
AVR l mt h vi iu khin do hng Atmel sn xut (Atmel cng l nh sn xut dng vi iu khin 89C51 m c th bn tng nghe n). AVR l chip vi iu khin 8 bits vi cu trc tp lnh n gin ha-RISC(Reduced Instruction Set Computer), mt kiu cu trc ang th hin u th trong cc b x l. Ti sao AVR: so vi cc chip vi iu khin 8 bits khc, AVR c nhiu c tnh hn hn, hn c trong tnh ng dng (d s dng) v c bit l v chc nng:
Gn nh chng ta khng cn mc thm bt k linh kin ph no khi s dng AVR, thm ch khng cn ngun to xung clock cho chip (thng l cc khi thch anh). Thit b lp trnh (mch np) cho AVR rt n gin, c loi mch np ch cn vi in tr l c th lm c. mt s AVR cn h tr lp trnh on chip bng bootloader khng cn mch np Bn cnh lp trnh bng ASM, cu trc AVR c thit k tng thch C. Ngun ti nguyn v source code, ti liu, application notert ln trn internet. Hu ht cc chip AVR c nhng tnh nng (features) sau: C th s dng xung clock ln n 16MHz, hoc s dng xung clock ni ln n 8 MHz (sai s 3%) B nh chng trnh Flash c th lp trnh li rt nhiu ln v dung lng ln, c SRAM (Ram tnh) ln, v c bit c b nh lu tr lp trnh c EEPROM. B nh chng trnh Flash c th lp trnh li rt nhiu ln v dung lng ln, c SRAM (Ram tnh) ln, v c bit c b nh lu tr lp trnh c EEPROM. Nhiu ng vo ra (I/O PORT) 2 hng (bi-directional). 8 bits, 16 bits timer/counter tch hp PWM. Cc b chuyn i Analog Digital phn gii 10 bits, nhiu knh. Chc nng Analog comparator.
Created by QuocHuy Hoang huyhq.fet.hut@gmail.com Page 1
Giao din ni tip USART (tng thch chun ni tip RS-232). Giao din ni tip Two Wire Serial (tng thch chun I2C) Master v Slaver. Giao din ni tip Serial Peripheral Interface (SPI) ...
Mt s chip AVR thng dng:

AT90S1200 AT90S2313 AT90S2323 and AT90S2343 AT90S2333 and AT90S4433 AT90S4414 and AT90S8515 AT90S4434 and AT90S8535 AT90C8534 ATtiny10, ATtiny11 and ATtiny12 ATtiny15 ATtiny22 ATtiny26 ATtiny28 ATmega8/8515/8535 ATmega16 ATmega161 ATmega162 ATmega163 ATmega169 ATmega32 ATmega323 ATmega103 ATmega64/128/2560/2561 AT86RF401. ....
Trong bi vit ny ti s dng chip ATmega8 lm v d, ti chn ATmega8 v y l loi chip thuc dng AVR mi nht, n c y cc tnh nng ca AVR nhng li nh gn (gi PDIP c 28 chn) v low cost nn cc bn c th mua t mnh to ng dng. Ti sao Assembly (ASM): bn c th khng cn bit v cu trc ca AVR vn c th lp trnh cho AVR bng cc phn mm h tr ngn ng cp cao nh BascomAVR (Basic) hay CodevisionAVR (C), tuy nhin khng phi l mc ch ca bi vit ny. hiu thu o v AVR bn phi lp trnh bng chnh ngn ng ca n, ASM. Nh vy lp trnh bng ASM gip bn hiu tng tn v AVR, v tt nhin lp
trnh c bng ASM bn phi hiu v cu trc AVR.Mt l do khc bn m ti khuyn bn nn lp trnh bng ASM l cc trnh dch (compiler) ASM cho AVR l hon ton min ph, v ngun source code cho AVR vit bng ASM l rt ln. Tuy nhin mt khi bn thnh tho AVR v ASM bn c th s dng cc ngn ng cp cao nh C vit ng dng v u im ca ngn ng cp cao l gip bn d dng thc hin cc php ton i s 16 hay 32 bit (vn l vn kh khn khi lp trnh bng ASM). II. Cng c. Trnh bin dch: c rt nhiu trnh bin dch bn c th s dng bin dch code ca bn thnh file intel hex np vo chip, mt s trnh dch quen thuc c th k n nh sau:
AvrStudio: l trnh bin dch ASM chnh thc cung cp bi Atmel, y l trnh bin dch hon ton min ph v tt nhin l tt nht cho lp trnh AVR bng ASM. Phin bn hin ti l 4.18 SP1, bn c th download phn mm AvrStudio ti trang web chnh thc ca Atmel hoc bn 4.623 ti y. Wavrasm: cng c cung cp bi Atmel, n chnh l tin thn ca AvrStudio. Hin ti wavrasm khng cn c s dng nhiu v so vi AvrStudio trnh bin dch ny c nhiu hng ch, nu bn quan tm c th download ti y. WinAVR hay avr-gcc: l b trnh dch c pht trin bi gnu, ngn ng s dng l C v c th c dng tch hp vi AvrStudio (dng Avrstudio lm trnh bin tp editor). c bit b bin dch ny cng min ph v a s ngun source code C c vit bng b ny, v vy n rt l tng cho bn khi vit cc ng dng chuyn nghip. Vic lp trnh bng avrgcc ti s cp trong nhng phn sau. CodeVisionAvr: mt chng trnh bng ngn ng C rt hay cho AVR, h tr nhiu th vin lp trnh. Tuy nhin l chng trnh thng mi. Bn c th download bn demo (y chc nng nhng nhng gii hn dung lng b nh chng trnh 2KB) ti Website hpinfotech ICCAVR: lp trnh C cho avr, download bn demo. BascomAVR: lp trnh cho AVR bng basic, y l trnh bin dch kh hay v d s dng, h tr rt nhiu th vin. Tuy nhin rt kh debug li v khng thch hp cho vic tm hiu AVR. V vy ti khng bn khuyn khch bn s dng trnh dch ny. Bn c th download bn demo (4K limit). V cn rt nhiu trnh bin dch khc cho AVR m ti khng k ra y, nhn chung tt c cc trnh bin dch ny h tr C hoc Basic hoc thm ch Pascal. Vic chn 1 trnh bin dch ty thuc vo mc ch, vo mc ng dng, vo kinh nghim s dng v nhiu l do khc na. V d ti thng dng Avrstudio v avrgcc khi hc s dng AVR v khi vit th vin. Nhng khi cn vit chng trnh ng dng ti thng chn avrgcc v CodeVisionAVR.
Trong bi vit ny ti hng dn bn s dng AvrStudio vit chng trnh cho AVR bng ASM.
Chng trnh np (Chip Programmer): a s cc trnh bin dch (AvrStudio, CodeVisionAVR, Bascom) u tch hp sn 1 chng trnh np chip h tr nhiu loi mch np nn bn khng qu lo lng. Trong trng hp khc, bn c th s dng cc chng trnh np nh Icprog hay Ponyprogl cc chng trnh np min ph cho AVR. Vic chn v s dng chng trnh np s c gii thiu trong cc bi sau. Mch np: tham kho bi vit gii thiu mch np AVR. Chng trnh m phng: avr simulator l trnh m phng v debbug c tch hp sn trong Avrstudio, avr simulator cho php bn quan st trng thi cc thanh ghi bn trong AVR nn rt ph hp bn debug chng trnh. Proteus l chng trnh th hai ti mun ni n, Proteus khng nhng m phng hot ng bn trong chip m cn m phng mch in t. Proteus m phng rt trc quan, n l 1 cng c hu ch khi cc bn cha c iu kin lm cc mch in t. III. V d u tin ca bn. Sau khi download AvrStudio, bn hy ci t phn mm trn my ca bn, qu trnh ci t rt n gin, bn hy theo cc mc nh v nhn next ci t. Trong bi u tin ny chng ta s vit th 1 chng trnh n gin cho AVR sau chy m phng bng Proteus. C th c mt s cu lnh cc bn s khng hiu, nhng ng lo lng qu, trong bi th 2 chng ta s hc v cu trc AVR cc bn s c gii thich r hn. thc hin v d ny, bn hy to mt Project bng AVRStudio, phn hng dn chi tit cho vic to Project trong AVRStudio bn hy tham kho bi hng dn AVRStudio.on code v d trong bi u tin ny c trnh by trong List1. List 1. on code u tin ca bn. 1 .CSEG 2 .INCLUDE "M8DEF.INC" 3 .ORG 0x000 4 RJMP BATDAU 5 6 .ORG 0x020 7 BATDAU: 8 ; KHOI TAO CAC DIEU KIEN DAU 9 LDI R16, HIGH(RAMEND) 10 LDI R17, LOW(RAMEND) 11 OUT SPH, R16 12 OUT SPL, R17 13 LDI R16, 0xFF; 14 OUT DDRB, R16 15 16 ; CHUONG TRINH CHINH
17 MAIN: 18 LDI R16, 0B00000001 19 OUT PORTB, R16 20 RCALL DELAY 21 22 LDI R16, 0B00000010 23 OUT PORTB, R16 24 RCALL DELAY 25 26 LDI R16, 0B00000100 27 OUT PORTB, R16 28 RCALL DELAY 29 30 LDI R16, 0B00001000 31 OUT PORTB, R16 32 RCALL DELAY 33 34 LDI R16, 0B00010000 35 OUT PORTB, R16 36 RCALL DELAY 37 38 LDI R16, 0B00100000 39 OUT PORTB, R16 40 RCALL DELAY 41 42 LDI R16, 0B01000000 43 OUT PORTB, R16 44 RCALL DELAY 45 46 LDI R16, 0B10000000 47 OUT PORTB, R16 48 RCALL DELAY 49 50 RJMP MAIN 51 ; CHUONG TRING CON DELAY 65535 chu ky (khoang 65535us neu xung ;clock cho chip 52 DELAY: 53 LDI R20, 0xFF 54 DELAY0: 55 LDI R21, 0xFF 56 DELAY1: 57 DEC R21 58 BRNE DELAY1 59 DEC R20 60 BRNE DELAY0 61 RET
Trc khi tm hiu ngha on code, hy nhn 1 lt qua on code. Trc ht vic vit HOA hay vit thng l khng quan trng, bn c th vit on code vi bt c hnh thc no min ng c php, t kha l c. Trong on code:
Bn thy 1 s t c mu BLUE (v d LDI, OUT, RJMP, RCALL, RET) l cc INSTRUCTiON, tc l cc cu lnh ca ngn ng ASM, bn c th c ti liu AVR INSTRUCTION tm hiu tt c cc INSTRUCTION. Cc INSTRUCTION sau s c trnh dch dch thnh cc m tng ng. Mt s t bt u bng bng du chm . l cc DIRECTIVE (v d .INCLUDE hay .ORG ) cng l nhng t kha mc nh ca ASM AVR, cc DIRECTIVE khng phi l m lnh m ch l cc ch dn v a ch b nh, khi ng b nh, nh ngha macrov khng c trnh dch dch thnh m. Chi tit v DIRECTIVE c th tm thy trong cc ti liu v ASM AVR, di y ti tm tt cc DIRECTIVE v chc nng ca chng nh sau:
Thng thng 1 INSTRUCTION c theo sau bi 2 ton hng operand (tuy nhin c nhiu trng hp ch c 1 ton hng hoc khng c ton hng), khi ton hng th nht s l cc THANH GHI. ca AVR (nh cp, chng ta s kho st thanh ghi AVR trong cc bi sau), v d : LDI R16, 0xFF; trong ton hng R16 l tn 1 thanh ghi trong AVR, v 0xFF l 1 hng s dng hexadecimal c gi tr tng ng l 255 dng thp phn hay 11111111 nh phn. Cc t theo sau bi du : l cc nhn label (v d MAIN, DELAY), l t do chng ta t t, n thc cht l 1 v tr trong b nh chng trnh, c th s dng nhn nh 1 chng trnh con. Phn i sau du ; gi l gii thch comment, phn ny khng c bin dch, bn c th ghi comment bt c u trong chng trnh vi yu cu phi s dng du ; trc n.
Gii thch on code:c th chia on code trn thnh 4 phn: phn u cha cc DIRECTIVE v lnh RJMP dng xc nh cc a ch b nh chng trnh, phn 2 l khi to mt s iu kin u cho Stack Pointer v PORT, phn 3 l chng trnh chnh, v phn 4 l chng trnh con ( ch y ch l cch b tr ca ring ti, mt khi quen thuc, bn c th b tr chng trnh theo cch ring ca bn).
Phn 1 v phn 2: .CSEG Ch th .CSEG: Code Segment bo cho trnh bin dch rng phn code theo sau l phn chng trnh thc thi, phn ny s c download vo b nh chng trnh ca chip. .INCLUDE "M8DEF.INC" Ch th .INCLUDE bo cho trnh bin dch bt u c 1 file nh km, trong trng hp trn l file M8DEF.INC, y l file cha cc khai bo cho chip Atmega8 nh thanh ghi, ngtcho vic truy xut trong chng trnh ca bn, y l dng bt buc, nu bn lp trnh cho chip khc bn hy i tn file nh km, v d m32def.inc cho chip ATmega32 bn c th tm thy cc file ny trong th mc C:\Program Files\Atmel\AVR Tools\AvrAssembler2\Appnotes. .ORG 0x000 Ch th .ORG: Set Program Origin, set v tr trong b nh s c tc ng n, trong trng hp trn, .ORG 0x000 xc nh phn code theo ngay sau s nm a ch 000, v tr u tin, trong b nh chng trnh. V dng lnh trong v tr u tin l: RJMP BATDAU RJMP: Relative Jump l lnh nhy khng iu kin n 1 v tr trong b nh, trong trng hp trn l nhy n nhn BATDAU, v nhn BATDAU nm v tr 0x020 (s hexadecimal, 0x020 =32 decimal) v n c khai bo ngay sau DIRECTIVE .ORG 0x020. .ORG 0x020 BATDAU Nh th phn b nh chng trnh nm gia 0 v 0x020 khng c s dng trong on code ca chng ta, phn ny c s dng cho mc ch khc, l cc vect ngt ( khng c cp y). Tip theo: ; KHOI TAO CC DIEU KIEN DAU LDI R16, HIGH(RAMEND)
LDI R17, LOW(RAMEND) OUT SPH, R16 OUT SPL, R17 Bn dng code trn khi to cho Stack Pointer, chng ta s tm hiu phn ny trong cc bi v Stack v chng trnh con. Li khuyn: cc bn nn khi ng 1 chng trnh theo cch trn v chng ta s hiu chng r hn sau ny ! LDI R16, 0xFF OUT DDRB, R16 Bn ch 2 dng trn v nhng g ti gii thch sau y, 2 dng ny c tc dng khi ng PORTB ca chip ATmega8 tc dng nh cc ng xut tn hiu (OUTPUT). Trc ht hy quan st chip ATmega8 trong hnh sau
Hnh 1: chip ATmega8. Bn c th thy chip ny gm 28 chn, trng c cc chn c ghi l PB0(chn 14), PB1(chn 15),,PB7(chn 10), l cc chn ca PORTB. PORT l khi nim ch cc ng xut nhp. Trong AVR, PORT c th giao tip theo 2 hng (bi directional), c th dng xut hoc nhn thng tin, mi PORT c 8 chn. Chip Atmega8 c 3 PORT c tn tng ng l PORTB, PORTC v PORTD (mt s chip AVR khc c 4 hoc 6 PORT). PORT c coi l ca ng then cht ca vi iu khin. Trong AVR, mi PORT lin quan n 3 thanh ghi (8 bits) c tn tng ng l DDRx, PINx, v PORTx vi x l tn ca PORT, mi bit trong thanh ghi tng ng vi mi chn ca PORT. Trong trng hp ca Atmega8 x l B, C hoc D. V d chng ta quan tm n PORTB th 3 thanh ghi tng ng c tn l DDRB, PINB v PORTB, trong 2 thanh ghi PORTB v PINB c ni trc tip vi cc chn ca PORTB, DDRB l thanh ghi iu khin hng ( Input hoc Output). Vit gi tr 1 vo mt bit trong thanh ghi DDRB th chn tng
ng ca PORTB s l chn xut (Output), ngc li gi tr 0 xc lp chn tng ng l ng nhp. Sau khi vit gi tr iu khin vo DDRB, vic truy xut PORTB c thc hin thng qua 2 thanh ghi PINB v PORTB. Quay li vi 2 dng code ca chng ta, dng u: LDI R16, 0xFF, vi LDI LoaD Immediately, dng lnh c ngha l load gi tr 0xFF vo thanh ghi R16, R16 l tn 1 thanh ghi trong b nh ca AVR, 0xFF l 1 hng s c dng thp lc phn, k hiu 0x ni ln iu , bn cng c th dng k hiu khc l $ ch 1 s thp lc phn, v d &FF, v 0xFF=255(thp phn)=0B11111111 (nh phn). Nh th sau dng u thanh ghi R16 c gi tr l 11111111 (nh phn). Dng th 2: OUT DDRB, R16 ngha l xut gi tr t thanh ghi R16 ra thanh ghi DDRB, tm li sau 2 dng trn gi tr DDRB nh sau: 1 1 1 1 1 1 1 1
C th bn s hi ti sao chng khng s dng 1 dng duy nht l LDI DDRB, 0xFF hay OUT DDRB, 0xFF, chng ta khng th v lnh LDI ch cho php thc hin trn cc thanh ghi R16,R31 v lnh OUT khng thc hin c vi cc hng s. V v DDRB=11111111 nn trong trng hp ny tt c cc chn ca PORTB sn sng cho vic xut d liu. Lc ny thanh ghi PINB khng c tc dng, thanh ghi PORTB s l thanh ghi xut, ghi gi tr vo thanh ghi ny s tc ng n cc chn ca PORTB.1
Phn 3: Chng trnh chnh MAIN: LDI R16, 0B00000001 OUT PORTB, R16 RCALL DELAY Bn ch cn ch 4 dng trn trong ton b phn chng trnh chnh, trc ht MAIN: ch l 1 nhn do chng ta t t tn, ging nh 1 ct mc trong chng trnh thi. Dng LDI R16, 0B00000001 th bn hiu, ch c 1 khc bit nh l ti s dng hng s dng nh phn cho bn d hiu hn. V dng OUT PORTB, R16 xut gi tr 0B00000001 c sn trong R16 ra thanh ghi PORTB, lc ny chn PB0 ca chip s ln 1 (5V) v cc chn cn li s mc 0 (0V). Dng th 3: RCALL DELAY l lnh gi chng trnh con DELAY, tm hon trc khi thc hin cc dng lnh tip theo: LDI R16, 0B00000010 OUT PORTB, R16 RCALL DELAY
Ba dng lnh ny cng ging ba dng trn, nhng gi tr xut ra lc ny l 0B00000010, chn PB1 s ln 5V v cc chn khc xung mc 0V. V c nh th n on cui: LDI R16, 0B10000000 OUT PORTB, R16 RCALL DELAY RJMP MAIN

Sau khi kt thc 3 dng trn chn PB7 s ln 5V, kt thc 1 vng xoay. Cui cng l quay v u chng trnh chnh bng dng RJMP MAIN By gi chc bn on c chng trnh ca chng ta thc hin vic g, l qut xoay vng cc chn ca PORTB, nu chng ta kt ni cc chn ca PORTB vi cc LED, chng ta s c 1 hiu ng qut LED xoay vng, chng ta thc hin iu ny bng phn mm Proteus. Phn 4: chng trinh con DELAY: on chng trnh ny khng lm g c ngoi vic tr hon 1 khong thi gian, tuy nhin bn cha th hiu n ngay c. y ch l 1 v d n gin, ti c gng thc hin n theo cch d hiu nht cho bn, v th on code c v hi di dng, bn hy thc hin li on chng trnh chnh bng on code ca bn. Phn cui cng l bin dch on code thnh file intel hex vo chip, nhn phm F7 bin dch. Sau khi bin dch bn s c 1 file tn avr1.hex trong thc mc project, chng ta s dng file ny vo chip sau ny.
IV. M phng bng Proteus. Chng ta hy th nghim on chng trnh ca chng ta bng Proteus. Nu bn thc hin ng kt qu s nh minh ha trong hnh 2 Hng dn c th cch v mch in v m phng bng phn mm Proteus bn hy xem bi "M phng Proteus".
Hnh 2. M phng.
Bi 2 - Cu Trc AVR
Ni dung 1. Gii thiu. 2. T chc AVR. 3. Stack. 4. Thanh ghi trng thi. 5. V d. Download v d I. Gii thiu.
Cc bi cn tham kho trc

Lm quen AVR. Assembly cho AVR. AVR Studio. M phng vi Proteus.
Bi ny tip tc bi u tin trong lot bi gii thiu v AVR, nu sau bi "Lm quen AVR" bn phn no bit cch lp trnh cho AVR bng AVRStudio th trong bi ny, chng ta s tm hiu k hn v cu trc ca AVR. Sau bi ny, bn s:

Hiu c cu trc AVR, cu trc b nh v cch thc hot ng ca chip. Hiu v Stack v cch hot ng. Bit c mt s instruction c bn truy xut b nh. Hc cc instruction r nhnh v vng lp. Chng trnh con (Subroutine) v Macro. Ci tin v d trong bi 1. Vit 1 v d minh ha cch s dng b nh v vng lp.
II. T chc ca AVR. AVR c cu trc Harvard, trong ng truyn cho b nh d liu (data memory bus) v ng truyn cho b nh chng trnh (program memory bus) c tch ring. Data memory bus ch c 8 bit v c kt ni vi hu ht cc thit b ngoi vi, vi register file. Trong khi program memory bus c rng 16 bits v ch phc v cho instruction registers. Hnh 1 m t cu trc b nh ca AVR. B nh chng trnh (Program memory): L b nh Flash lp trnh c, trong cc chip AVR c (nh AT90S1200 hay AT90S2313) b nh chng trnh ch gm 1 phn l Application Flash Section nhng trong cc chip AVR mi chng ta c thm phn Boot Flash setion. Boot section s c kho st trong cc phn sau, trong bi ny khi ni v b nh chng trnh, chng ta t hiu l Application section. Thc cht, application section bao gm 2 phn: phn cha cc instruction (m lnh cho hot ng ca chip) v phn cha cc vector ngt (interrupt vectors). Cc vector ngt nm phn u ca application section (t a ch 0x0000) v di n bao nhiu ty thuc
vo loi chip. Phn cha instruction nm lin sau , chng trnh vit cho chip phi c load vo phn ny. Xem li phn u ca v d trong bi 1: .ORG 0x000 RJMP BATDAU .ORG 0x020 Trong v d ny, ngay sau khi set v tr 0x000 bng ch th (DIRECTIVE) .ORG 0x000 chng ta dng instruction RJMP nhy n v tr 0x020, nh th phn b nh chng trnh t 0x00 n 0x01F khng c s dng (v trong v d ny chng ta khng s dng cc vector ngt). Chng trnh chnh c bt u t a ch 0x020, con s 0x020 l do ngi lp trnh chn, tht ra cc vector ngt ca chip ATMEGA8 ch ko di n a ch 0x012, v vy chng trnh chnh c th c bt u t bt c v tr no sau . bit di cc vector ngt ca tng chip bn hy tham kho datasheet ca chip . V chc nng chnh ca b nh chng trnh l cha instruction, chng ta khng c nhiu c hi tc ng ln b nh ny khi lp trnh cho chip, v th i vi ngi lp trnh AVR, b nh ny khng qu quan trng. Tt c cc thanh ghi quan trng cn kho st nm trong b nh d liu ca chip.
Hnh 1. T chc b nh ca AVR. B nh d liu (data memory): y l phn cha cc thanh ghi quan trng nht ca chip, vic lp trnh cho chip phn ln l truy cp b nh ny. B nh d liu trn cc chip AVR c ln khc nhau ty theo mi chip, tuy nhin v c bn phn b nh ny c chia thnh 5 phn: Phn 1: l phn u tin trong b nh d liu, nh m t trong hnh 1, phn ny bao gm 32 thanh ghi c tn gi l register file (RF), hay General Purpose Rgegister GPR, hoc n gin l cc Thanh ghi. Tt c cc thanh ghi ny u l cc thanh ghi 8 bits nh trong hnh 2.
Hnh 2. Thanh ghi 8 bits. Tt c cc chip trong h AVR u bao gm 32 thanh ghi Register File c a ch tuyt i t 0x0000 n 0x001F. Mi thanh ghi c th cha gi tr dng t 0 n 255 hoc cc gi tr c du t -128 n 127 hoc m ASCII ca mt k t no Cc thanh ghi ny c t tn theo th t l R0 n R31. Chng c chia thnh 2 phn, phn 1 bao gm cc thanh ghi t R0 n R15 v phn 2 l cc thanh ghi R16 n R31. Cc thanh ghi ny c cc c im sau:

c truy cp trc tip trong cc instruction. Cc ton t, php ton thc hin trn cc thanh ghi ny ch cn 1 chu k xung clock. Register File c kt ni trc tip vi b x l trung tm CPU ca chip. Chng l ngun cha cc s hng trong cc php ton v cng l ch cha kt qu tr li ca php ton.
minh ha, hy xt v d thc hin php cng 2 thanh ghi bng instruction ADD nh sau: ADD R1, R2 Bn thy trong dng lnh trn, 2 thanh ghi R1 v R2 c s dng trc tip vi tn ca chng, dng lnh trn khi c dch sang opcode download vo chip s c dng: 0000110000010010 trong 00001=1 tc thanh ghi R1 v 00010 = 2 ch thanh ghi R2. Sau php cng, kt qu s c lu vo thanh ghi R1. Tt c cc instruction s dng RF lm ton hng u c th truy nhp tt c cc RF mt cch trc tip trong 1 chu k xung clock, ngoi tr SBCI, SUBI, CPI, ANDI v LDI, cc instruction ny ch c th truy nhp cc thanh ghi t R16 n R31. Thanh ghi R0 l thanh ghi duy nht c s dng trong instruction LPM (Load Program Memory). Cc thanh ghi R26, R27, R28, R29, R30 v R31 ngoi chc nng thng thng cn c s dng nh cc con tr (Pointer register) trong mt s instruction truy xut gin tip. Chng ta s kho st vn con tr sau ny. Hnh 3 m t cc chc nng ph ca cc thanh ghi.
Hnh 3. Register file. Tm li 32 RF ca AVR c xem l 1 phn ca CPU, v th chng c CPU s dng trc tip v nhanh chng, gi cc thanh ghi ny, chng ta khng cn gi a ch m ch cn gi trc tip tn ca chng. RF thng c s dng nh cc ton hng (operand) ca cc php ton trong lc lp trnh. Phn 2: l phn nm ngay sau register file, phn ny bao gm 64 thanh ghi c gi l 64 thanh ghi nhp/xut (64 I/O register) hay cn gi l vng nh I/O (I/O Memory). Vng nh I/O l ca ng giao tip gia CPU v thit b ngoi vi. Tt c cc thanh ghi iu khin, trng thica thit b ngoi vi u nm y. Xem li v d trong bi 1, trong ti c cp v vic iu khin cc PORT ca AVR, mi PORT lin quan n 3 thanh ghi DDRx, PORTx v PINx, tt c 3 thanh ghi ny u nm trong vng nh I/O. Xa hn, nu mun truy xut cc thit b ngoi vi khc nh Timer, chuyn i Analog/Digital, giao tip USARTu thc hin thng qua vic iu khin cc thanh ghi trong vng nh ny. Vng nh I/O c th c truy cp nh SRAM hay nh cc thanh ghi I/O. Nu s dng instruction truy xut SRAM truy xut vng nh ny th a ch ca chng c tnh t 0x0020 n 0x005F. Nhng nu truy xut nh cc thanh ghi I/O th a ch ca chng c tnh t 0x0000 n 0x003F. Xt v d instruction OUT dng xut gi tr ra cc thanh ghi I/O, lnh ny s dng a ch kiu thanh ghi, cu trc ca lnh nh sau: OUT A, Rr, trong A l a ch ca thanh ghi trong vng nh I/O, Rr l thanh ghi RF, lnh OUT xut gi tr t thanh ghi Rr ra thanh ghi I/O c a ch l A. Gi s chng ta mun xut gi tr cha trong R6 ra
thanh ghi iu khin hng ca PORTD, tc thanh ghi DDRD, a ch tnh theo vng I/O ca thanh ghi DDRD l 0x0011, nh th cu lnh ca chng ta s c dng: OUT 0x0011, R6. Tuy nhin trong 1 trng hp khc, nu mun truy xut DDRD theo dng SRAM, v d lnh STS hay LDS, th phi dng a ch tuyt i ca thanh ghi ny, tc gi tr 0x0031, khi lnh OUT trn c vit li l STS 0x0031, R6. thng nht cch s dng t ng, t by gi chng ta dng khi nim a ch I/O cho cc thanh ghi trong vng nh I/O ni n a ch khng tnh phn Register File, khi nim a ch b nh ca thanh ghi l ch a ch tuyt i ca chng trong SRAM. V d thanh ghi DDRD c a ch I/O l 0x0011 v a ch b nh ca n l 0x0031, a ch b nh = a ch I/O + 0x0020. V cc thanh ghi trong vng I/O khng c hiu theo tn gi nh cc Register file, khi lp trnh cho cc thanh ghi ny, ngi lp trnh cn nh a ch ca tng thanh ghi, y l vic tng i kh khn. Tuy nhin, trong hu ht cc phn mm lp trnh cho AVR, a ch ca tt c cc thanh ghi trong vng I/O u c nh ngha trc trong 1 file Definition, bn ch cn nh km file ny vo chng trnh ca bn l c th truy xut cc thanh ghi vi tn gi ca chng. Gi s trong v d bi 1, lp trnh cho chip Atmega8 bng AVRStudio, dng th 2 chng ta s dng INCLUDE "M8DEF.INC" load file nh ngha cho chip ATMega8, file M8DEF.INC. V vy, trong sau ny khi mun s dng thanh ghi DDRD bn ch cn gi tn ca chng, nh: OUT DDRD,R6. Phn 3: RAM tnh, ni (internal SRAM), l vng khng gian cho cha cc bin (tm thi hoc ton cc) trong lc thc thi chng trnh, vng ny tng t cc thanh RAM trong my tnh nhng c dung lng kh nh (khong vi KB, ty thuc vo loi chip). Phn 4: RAM ngoi (external SRAM), cc chip AVR cho php ngi s dng gn thm cc b nh ngoi cha bin, vng ny thc cht ch tn ti khi no ngi s dng gn thm b nh ngoi vo chip. Phn 5: EEPROM (Electrically Ereasable Programmable ROM) l mt phn quan trng ca cc chip AVR mi, v l ROM nn b nh ny khng b xa ngay c khi khng cung cp ngun nui cho chip, rt thch hp cho cc ng dng lu tr d liu. Nh trong hnh 1, phn b nh EEPROM c tch ring v c a ch tnh t 0x0000. Cu hi by gi l AVR hot ng nh th no? Hnh 4 biu din cu trong bn trong ca 1 AVR. Bn thy rng 32 thanh ghi trong Register File c kt ni trc tip vi Arithmetic Logic Unit -ALU (ALU cng c xem l CPU ca AVR) bng 2 line, v th ALU c th truy xut trc tip cng lc 2 thanh ghi RF ch trong 1 chu k xung clock (vng c khoanh trn mu trong hnh 4).
Hnh 4. Cu trc bn trong AVR. Cc instruction c cha trong b nh chng trnh Flash memory di dng cc thanh ghi 16 bit. B nh chng trnh c truy cp trong mi chu k xung clock v 1 instruction cha trong program memory s c load vo trong instruction register, instruction register tc ng v la chn register file cng nh RAM cho ALU thc thi. Trong lc thc thi chng trnh, a ch ca dng lnh ang thc thi c quyt nh bi mt b m chng trnh PC (Program counter). chnh l cch thc hot ng ca AVR. AVR c u im l hu ht cc instruction u c thc thi trong 1 chu k xung clock, v vy c th ngun clock ln nht cho AVR c th nh hn 1 s vi iu khin khc nh PIC nhng thi gian thc thi vn nhanh hn. III. Stack. Stack c hiu nh l 1 thp d liu, d liu c cha vo stack nh thp v d liu cng c ly ra t nh. Kiu truy cp d liu ca stack gi l LIFO (Last In First Out vo sau ra trc). Hnh 5 th hin cch truy cp d liu ca stack.
Hnh 5. Stack. Khi nim v cch thc hot ng ca stack c th c p dng cho AVR, bng cch khai bo mt vng nh trong SRAM l stack ta c th s dng vng nh ny nh mt stack thc th. khai bo mt vng SRAM lm stack chng ta cn xc lp a ch u ca stack bng cch xc lp con tr stack-SP (Stack Pointer). SP l 1 con tr 16 bit bao gm 2 thanh ghi 8 bit SPL v SPH (ch L l LOW ch thanh ghi mang gi tr byte thp ca SP, v H = HIGH), SPL v SPH nm trong vng nh I/O. Gi tr gn cho thanh ghi SP s l a ch khi ng ca stack. Quay li v d bi 1, phn khi to cc iu kin u. ; KHOI TAO CC DIEU KIEN DAU LDI R16, HIGH(RAMEND) LDI R17, LOW(RAMEND) OUT SPH, R16 OUT SPL, R17 Bn dng khai bo trn mc ch l gn gi tr ca RAMEND cho con tr SP, RAMEND (tc End of Ram) l bin cha a ch ln nht ca RAM ni trong AVR, bin ny c nh ngha trong file M8DEF.INC. Nh th sau 4 dng trn, con tr SP cha gi tr cui cng ca SRAM hay ni cch khc vng stack bt u t v tr cui cng ca b nh SRAM. Nhng ti sao l v tr cui cng m khng l 1 gi tr khc. C th gii thch nh sau: stack trong AVR hot ng t trn xung, sau khi d liu c y vo stack, SP s gim gi tr v th khi ng SP v tr cui cng ca SRAM s trnh c vic mt d liu do ghi . Bn c th khi ng stack vi 1 a ch khc, tuy nhin v l do an ton, nn khi ng stack RAMEND. Hai instruction dng cho truy cp stack l PUSH v POP, trong PUSH dng y d liu vo stack v POP dng ly d liu ra khi stack. D liu c y vo v ly ra khi stack ti v tr m con tr SP tr n. V d cho chip ATMega8, RAMEND=0x045F, sau khi khi ng, con tr SP tr n v tr 0x045F trong SRAM, nu ta vit cc cu lnh sau:
LDI R1, 1 PUSH R1 LDI R1, 5 PUSH R1 LDI R1, 8 PUSH R1 Khi ni dung ca stack s nh trong hnh 6.
Hnh 6. Ni dung stack trong v d. Sau mi ln PUSH d liu, SP s gim 1 n v v tr vo v tr tip theo. By gi nu ta dng POP ly d liu t stack, POP R2, th R2 s mang gi tr ca ngn nh 0x045D, tc R2=8. Trc khi instruction POP c thc hin, con tr SP c tng ln 1 n v, sau d liu s c ly ra t v tr m SP tr n trong stack. Stack trong AVR khng phi l v y, ngha l chng ta ch c th PUSH d liu vo stack 1 su nht nh no y (ph thuc vo chip). S dng stack khng ng cch i khi s lm chng trnh thc thi sai hoc tn thi gian thc thi v ch. V th khng nn s dng stack ch lu cc bin thng thng. ng dng ph bin nht ca stack l s dng trong cc chng trnh con (Subroutine), khi chng ta cn nhy t mt v tr trong chng trnh chnh n 1 chng trnh con, sau khi thc hin chng trnh con li mun quay v v tr ban u trong chng trnh chnh th Stack l phng cch ti u dng cha b m chng trnh trong trng hp ny. Xem li v d trong bi 1, trong chng trnh chnh chng ta dng lnh RCALL DELAY nhy n on chng trnh con DELAY, RCALL l lnh nhy n 1 v tr trong b nh chng trnh, trc khi nhy, PC c cng thm 1 v PUSH mt cch t ng vo stack. Cui chng trnh con DELAY, chng ta dng instruction RET, instruction ny POP d liu t stack ra PC mt cch t ng, bng cch ny chng ta c th quay li v tr trc . Chnh v cc lnh RCALL v RET s dng stack mt cch t ng nn ta phi khi ng stack ngay t u, nu khng chng trnh s thc thi sai chc nng. Tm li cn khi ng stack u chng trnh v khng nn s dng stack mt cch ty thch nu cha tht cn thit.
IV. Thanh ghi trng thi - SREG (STATUS REGISTRY). Nm trong vng nh I/O, thanh ghi SREG c a ch I/O l 0x003F v a ch b nh l 0x005F (thng y l v tr cui cng ca vng nh I/O) l mt trong s cc thanh ghi quan trng nht ca AVR, v th m ti dnh phn ny gii thiu v thanh ghi ny. Thanh ghi SREG cha 8 bit c (flag) ch trng thi ca b x l, tt c cc bit ny u b xa sau khi reset, cc bit ny cng c th c c v ghi bi chng trnh. Chc nng ca tng bit c m t nh sau:
Hnh 7. Thanh ghi trng thi.
Bit 0 C (Carry Flag: C nh): l bit nh trong cc php i s hoc logic, v d thanh ghi R1 cha gi tr 200, R2 cha 70, chng ta thc hin php cng c nh: ADC R1, R2, sau php cng, kt qu s c lu li trong thanh ghi R1, trong khi kt qu thc l 270 m thanh ghi R1 li ch c kh nng cha ti a gi tr 255 (v c 8 bit) nn trong trng hp ny, gi tr lu li trong R1 thc cht ch l 14, ng thi c C c set ln 1 (v 270=100001110, trong 8 bit sau 00001110 =14 s c lu li trong R1). Bit 1 Z (Zero Flag: C 0): c ny c set nu kt qu php ton i s hay php Logic bng 0. Bit 2 N (Negative Flag: C m): c ny c set nu kt qu php ton i s hay php Logic l s m. Bit 3 V (Twos complement Overflow Flag: C trn ca b 2): hot ng ca c ny c v s kh hiu cho bn v n lin quan n kin thc s nh phn (phn b), chng ta s cp n khi no thy cn thit. Bit 4 S (Sign Bit: Bit du): Bit S l kt qu php XOR gia 1 c N v V, S=N xor V. Bit 5 H (Half Carry Flag: C nh na): c H l c nh trong 1 vi php ton i s v php Logic, c ny hiu qu i vi cc php ton vi s BCD. Bit 6 T (Bit Copy Storage): c s dng trong 2 Instruction BLD (Bit LoaD) v BST (Bit STorage). Ti s gii thch chc nng Bit T trong phn gii thiu v BLD v BST. Bit 7 I (Global Interrupt Enable) : Cho php ngt ton b): Bit ny phi c set ln 1 nu trong chng trnh c s dng ngt. Sau khi set bit ny, bn mun kch hot loi ngt no cn set cc bit ngt ring ca ngt . Hai instruction dng ring Set v Clear bit I l SEI v CLI.
Ch : tt c cc bit trong thanh ghi SREG u c th c xa thng qua cc instruction khng ton hng CLx v set bi SEx, trong x l tn ca Bit.V d CLT l xa Bit T v SEI l set bit I.
Ti ch gii thch ngn gn chc nng ca cc bit trong thanh ghi SREG, c th chc nng v cch s dng ca tng bit chng ta s tm hiu trong cc trng hp c th sau ny, ngi c c th t tm hiu thm trong cc ti liu v INSTRUCTION cho AVR. Ti cung cp thm 1 bng tm tt s nh hng ca cc php ton i s, logic ln cc Bit trong thanh ghi SREG.
Hnh 8. nh hng ca cc php ton ln SREG. IV. Macro v chng trnh con. Macro l khi nim ch mt on code nh thc hin mt cng vic no , nu c 1 on code no m bn rt hay s dng khi lp trnh th bn nn dng macro trnh vic phi vit i vit li on code . Lp trnh ASM cho AVR cho php bn s dng Macro, to 1 Macro bn s dng DIRECTIVE. .MACRO delay4 NOP NOP NOP NOP .ENDMACRO on Macro trn c tn delay4 thc hin vic delay 4 chu k my bng 4 lnh NOP, nu trong chng trnh bn cn dng Macro ny th ch cn gi delay4 bt k dng no.
[] ; code ca bn Delay4 [] ; code ca bn Mi ln tn ca Macro c gi, trnh bin dch s tm n Macro v copy ton b ni dung Macro vo v tr bn gi. Nh vy thc cht con tr chng trnh khng nhy n Macro, Macro khng lm gim dung lng chong trnh m ch lm cho vic lp trnh nh nhng hn. y chnh l khc bit ln nht ca Macro v Subroutine (chng trnh con). Chng trnh con cng l 1 on code thc hin 1 chc nng c bit no . Tuy nhin khc vi Macro, mi khi gi chng trnh con, con tr chng trnh nhy n chng trnh con thc thi chng trnh con v sau quay v chng trnh chnh. Nh th chng trnh con ch c bin dch 1 ln v c th s dng nhiu ln, n lm gim dung lng chong trnh. y l u im v cng l im khc bit ln nht gia chng trnh con v Macro. Tuy nhin cn ch l vic nhy n chng trnh con v nhy v chng trnh chnh cn vi chu k my, c th lm chm chng trnh, y l nhc im ca chng trnh con so vi macro. Chng trnh con cho AVR lun c bt u bng 1 Label, cng l tn v a ch ca chng trnh con. Chng trnh con thng c kt thc vi cu lnh RET (Return). Chng ta bit v chng trnh con qua v d ca bi 1, trong DELAY l 1 chng trnh con. gi chng trnh con t 1 v tr no trong chng trnh, chng ta c th dng lnh CALL hoc RCALL (Relative CALL) (xem li v d bi 1 v cch s dng RCALL). Mi khi cc lnh ny c gi, b m chng trnh c t ng c PUSH vo stack v khi chng trnh con kt thc bng lnh RET, b m chng trnh c POP tr ra v quay v chng trnh chnh. Lnh CALL c th gi 1 chng trnh con bt k v tr no trong khi RCALL ch gi trong khong b nh 4KB, nhng RCALL cn t chu k xung clock hn khi thc thi. Hai instruction khc c th c dng gi chng trnh con l JMP (Jump) v RJMP (Relative Jump). Khc vi cc lnh call, cc lnh jump khng cho php quay li v khng t ng PUSH b m chng trnh vo Stack, s dng cc lnh ny gi chng trnh con bn cn mt s lnh jump khc cui chng trnh con. Tm li bn nn vit 1 chng trnh con ng chun v dng CALL hoc RCALL gi chng cc chng trnh ny, ch nhng trng hp c bit hoc bn hiu rt r v chng th c th dng cc lnh jump. V. V d minh ha. Nu bn c v hiu n thi im ny th bn c th hiu ht hot ng ca chng trnh v d trong bi 1, tht s v d rt n gin v d hiu. Tuy nhin, bn c th ti u ha v d theo hng lm gim dung lng chng trnh v tt nhin, chng trnh s kh hiu hn cho ngi khc. Cc phn khi ng v tr b nh, stack v chng trnh con DELAY chng ta khng thay i, ch thay i phn chng trnh chnh, 1 trong nhng cch vit chng trnh chnh nh cch sau: ; CHUONG TRINH CHINH , BAI 1, VI DU 1, VERSION 2/////////////////////////////// LDI R16, $1 ;LOAD GIA TRI KHOI DONG CHO R16
MAIN: OUT PORTB, R16 ; XUAT GIA TRI TRONG R16 RA PORTB RCALL DELAY ; GOI CHUONG TRINH CON DELAY ROL R16 ; XOAY THANH GHI R16 SANG TRAI 1 VI TRI RJMP MAIN ; NEU R16 0, NHAY VE MAIN, TIEP TUC QUET ;///////////////////////////////////////////////////////////////////////////////////////// C th khng cn gii thch bn cng c th hiu on code trn, y ch l 1 trong nhng cch c th, bn hy vit li theo cch ca ring bn vi yu cu l chng trnh phi thc hin ng chc nng v ngn gn. By gi chng ta s thc hin mt v d minh ha cho nhng g chng ta hc trong bi 2 ny. Ni dung ca v d th hin trong mch in hnh 9. Hot ng ca mch in t nh sau: 1 chip ATMega8 c s dng nh mt counter, c th dng m ln v m xung, 2 button trong mch in tc ng nh 2 kicker, nhn button 1 m ln v button m xung, gi tr m nm trong khong t 0 n 9. Gi tr m c hin th trn 1 LED 7 on loi anod chung (dng chung), chip 7447 c dng gii m t gi tr BCD xut ra bi ATMega8 sang tn hiu cho LED 7 on anod chung, chng ta cn s dng 7447 v tn hiu xut ra t chip ATMega8 l dng nh phn hoc BCD , tn hiu ny khng th hin th trc tip trn cc LED 7 on, chip 7447 c nhim v chuyn 1 d liu dng digit BCD sang m ph hp cho LED 7 on. thc hin v d, trc ht bn hy v mch in nh trong hnh 9 bng phn mm Proteus (xem cch v mch in bng Proteus), mch in ch c 5 loi linh kin l chip ATMega8 (t kha mega8), 1 LED 7 on anod chung vi tn y trong Proteus l 7SEG-COM-AN-GRN (t kha 7SEG), 1 chip 7447 (t kha 7447), 1 in tr 10 v 2 button (t kha button).
Hnh 9. V d cho bi 2. S dng AVRStudio to 1 project mi vi tn gi avr2 (xem li cch to Project mi trong AVRStudio). Vit li phn code bn di vo vo file avr2.asm List 1. V d cu trc AVR 1 .INCLUDE "M8DEF.INC" 2 .CSEG.
3 .ORG 0x0000 4 RJMP BATDAU 5 .ORG 0x0020 6 BATDAU: 7 ;KHOI DONG STACK POINTER 8 LDI R17, HIGH(RAMEND) 9 LDI R16, LOW(RAMEND) 10 OUT SPL, R16 11 OUT SPH,R17 12 ; KHOI DONG CAC PORT 13 CLR R16 ; XOA R16, R16=0 14 OUT DDRB, R16 ; DDRB=0, PORTB LA NGO NHAP 15 LDI R16, 0xFF ; SET TAT CA CAC BIT CUA R16 LEN 1 16 OUT PORTB,R16 ;DDRB=0, PORTB =0xFF, KEO LEN CAC CHAN PORTB 17 OUT DDRD, R16 ;DDRD=0xFF, PORTD LA NGO XUAT 18 CLR R25 ;XOA R25, R25 LA THANH GHI DUNG CHUA SO DEM 19 SER R20 ; R20 LA THANH GHI TAM CHUA GIA TRI TRUOC DO CUA PINB 20 MAIN: 21 IN R21,PINB ;DOC GIA TRI TU PINB, TUC TU CAC BUTTON 22 RCALL SOSANH ;GOI CHUONG TRINH CON SOSANH 23 OUT PORTD, R25 ;XUAT GIA TRI DEM RA PORTD 24 SBRS R21,0 ;NEU BIT 0 CUA R21 (TUC CHAN PB0) =1 THI BO QUA DONG ; 25 TIEP THEO 26 RCALL TANG ;NHAY DEN CHUONG TRINH CON TANG GIA TRI DEM 27 SBRS R21,1 ;NEU BIT 1 CUA R21 (TUC CHAN PB1) =1 THI BO QUA DONG ; 28 TIEP THEO 29 RCALL GIAM ;NHAY DEN CHUONG TRINH CON GIAM GIA TRI DEM 30 MOV R20,R21 ;LUU LAI TRANG THAI PINB 31 RJMP MAIN 32 ;**********************CHUONG TRINH CON************************ 33 ; **************subroutine kiem tra gioi hang (tu 0 den 9) cua so dem 34 SOSANH: 35 CPI R25, 10 36 BREQ RESET0 ;NEU GIA TRI DEM=10 THI TRA VE 0 37 CPI R25, 255 38 BREQ RESET9 ;NEU GIA TRI DEM =255 THI TRA VE 9 39 RJMP QUAYVE ;NHAY DEN NHAN QUAYVE 40 RESET0: 41 LDI R25,$0 ;TRA GIA TRI DEM VE 0 42 RJMP QUAYVE 43 RESET9: 44 LDI R25,$9 ;GAN 9 CHO GIA TRI DEM 45 QUAYVE: 46 RET 47 ; ************************************************************
48 ; **************subroutine tang so dem 1 don vi neu dieu kien thoa 49 TANG: 50 SBRS R20,0 51 RET 52 INC R25 53 RET 54 ; **************subroutine giam so dem 1 don vi neu dieu kien thoa 55 GIAM: 56 SBRS R20,1 57 RET DEC R25 RET Trong v ny ny, chng ta s dng 2 PORT ca chip ATMega8, PORTD dng xut d liu (s m) ra chip 7447 v sau hin th trn LED 7 on. PORTB dng nh ng nhp, tn hiu t cc button s c chip ATMega8 nhn thng qua 2 chn PB0 v PB1 ca PORTB. Hot ng ca cac PORT v vic xc lp 1 PORT nh cc ng xut chng ta kho st trong bi 1. y chng ta kho st thm v xc lp PORT nh 1 ng nhp, trc ht bn hy quan st mch in tng ng ca 1 chn trong cc PORT xut nhp ca AVR trong hnh 10.
Hnh 10. Cu trc chn trong PORT ca AVR. Trong mch in hnh 10, cc diode v t in ch c chc nng bo v chn PORT, nhng in tr Rpu (R Pull up) ng vai tr quan trng nh l in tr ko ln khi chn ca PORT lm nhim v nhn tn hiu (ng nhp). Tuy nhin trong AVR, in tr ko ln ny khng phi lun kch hot, chng ta bit rng mi PORT ca AVR c 3 thanh ghi: DDRx, PORTx v PINx, nu DDRx=0 th PORT x l ng nhp, lc ny thanh ghi PINx l thanh ghi cha d liu nhn v, c bit thanh ghi PORTx vn c s dng trong mode ny, l thanh ghi xc lp in tr ko ln, nh th nu DDRx=0 v PORTx=0xFF th cc chn PORTx l ng nhp v c ko ln bi 1 in tr trong chip, ngha l cc chn ca PORTx lun mc cao, mun kch thay i trng thi chn ny chng ta cn ni chn trc tip vi GND, y l l do ti
sao cc button trong mch in ca chng ta c 1 u ni vi chn ca chip cn u kia c ni vi GND. y cng l ngha ca khi nim in tr ko ln (Pull up resistor) trong k thut in t. on code trong phn KHOI DONG CAC PORT ca v d ny xc lp PORTD l ng xut (DDRD=0xFF) , PORTB l ng nhp c s dng in tr ko ln (DDRB=0, PORTB=0xFF). Chng ta s gii thch hot ng ca on chng trnh chnh v cc on chng trnh con. Trc ht, trong chng trnh ny, chng ta s dng 3 thanh ghi chnh l R20, R21 v R25, trong R25 l thanh ghi cha s m, gi tr ca thanh ghi R25 s c xut ra PORTD ca chip, thanh ghi R21 cha trng thi ca thanh ghi PINB v cng l trng thi ca cc button, thanh ghi R20 kt hp vi thanh ghi R21 to thnh 1 b m cnh xung ca cc button. hiu thu o hot ng m (cng l hot ng chnh ca v d ny) chng ta xt trng thi chn PB0 nh trong hnh 11.
Hnh 11. Thay i trng thi cc chn I/O. Trong trng thi bnh thng (button khng c nhn), chn PB0 mc cao (do in tr ko ln), b m khng hot ng, gi tr m khng thay i, by gi nu nhn button, chn PB0 c ni trc tip vi GND, chn ny s b ko xung mc thp, bng cch kim tra trng thi chn PB0, nu PB0=0 ta tng gi tr m 1 n v. tng nh th c v hp l, tuy nhin nu p dng th chng trnh s hot ng khng ng chc nng, khi bn nhn 1 ln gi, tr m c th tng n c trm hoc khng kim sot c, hiu ng ny tng t khi bn nhn v gi 1 phm trn bn phm my tnh, l do l v chng ta s dng phng php kim tra mc m, thi gian qut ca chng trnh rt ngn so vi thi gian chng ta gi button. khc phc, chng ta dng phng php kim tra cnh xung, ch khi no pht hin chn PB0 thay i t 1 xung 0 th mi tng gi tr m 1 n v, kt qu l mi ln nhn button th gi tr m ch tng 1 (ngay c khi ta nhn v gi button), thanh ghi R20 c s dng lu trng thi trc ca PINB (cng l trng thi ca cc button). Trong chng trnh, ti s dng 2 istruction mi l SBRC v SBRS kim tra trng thi cc chn ca PORTB (button). SBRC Skip if Bit in Register is Clear, lnh ny s b qua 1 dng lnh ngay sau (ch b qua 1 dng duy nht) nu 1 bit trong thanh ghi mc 0, SBRC Skip if Bit in Register is Set- hot ng tng t SBRC nhng skip s xy ra nu bit trong thanh ghi mc 1. Da vo y chng ta gii thch 4 dng sau: SBRS R21,0 ;NEU BIT 0 CUA R21 (TUC CHAN PB0) =1 THI BO QUA DONG ;TIEP THEO RCALL TANG ;NHAY DEN CHUONG TRINH CON TANG GIA TRI DEM SBRS R21,1 ;NEU BIT 1 CUA R21 (TUC CHAN PB1) =1 THI BO QUA DONG ;TIEP THEO RCALL GIAM ;NHAY DEN CHUONG TRINH CON GIAM GIA TRI DEM Dng 1 dng kim tra trng thi bit 0 trong R21 (ch R21 cha gi tr ca PINB), nu bit ny bng 1 (set), tc chn PB0=1 hay button khng c nhn, th
nhy b qua dng lnh tip theo n dng 3. dng 3 chng trnh kim tra trng thi chn PB1 (button th 2). Quay li dng 1, nu chng trnh kim tra pht hin chn PB0=0 (button th nht c nhn) th dng lnh th 2 c thc thi, kt qu l chng trnh nhy n chng trnh con TANG. TANG: SBRS R20,0 RET INC R25 RET Dng u tin ca chng trnh con TANG l kim tra trng thi trc ca chn PB0 (c lu bit 0 trong thanh ghi R20), nu trng thi ny bng 0, ngha l khng c s chuyn t 1 xung 0 chn PB0, dng 2 (lnh RET) s c thc thi quay v chng trnh chnh. Nhng nu PB0 trc bng 1, ngha l c s thay i t 1->0 chn ny, gi tr m s c tng thm 1 nh INC R25, sau quay v chng trnh chnh. Tm li mun tng gi tr m thm 1 n v cn tha mn 2 iu kin: chn PB0 hin ti =0 (button ang c nhn) v trng thi trc ca PB0 phi l 1 (trnh trng hp tng lin tc). Phng php ny c th p dng cho rt nhiu trng hp m dng m xung. Qu trnh gim gi tr m c hiu tng t, phn cn li ca v d ny bn c hy t gii thch theo nhng gi trn.
Bi 3 - Ngt ngoi
Ni dung 1. Ngt trn AVR. 2. Ngt ngoi. 3. V d ngt ngoi vi C. Download v d
Cc bi cn tham kho trc Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus.
I. Ngt trn AVR. Interrupts, thng c gi l ngt, l mt tn hiu khn cp gi n b x l, yu cu b x l tm ngng tc khc cc hot ng hin ti nhy n mt ni khc thc hin mt nhim v khn cp no , nhim v ny gi l trnh phc v ngt isr (interrupt service routine ). Sau khi kt thc nhim v trong isr, b m chng trnh s c tr v gi tr trc b x l quay v thc hin tip cc nhim v cn dang d. Nh vy, ngt c mc u tin x l cao nht, ngt thng c dng x l cc s kin bt ng nhng khng tn qu nhiu thi gian. Cc tn hiu dn n ngt c th xut pht t cc thit b bn trong chip (ngt bo b m timer/counter trn, ngt bo qu trnh gi d liu bng RS232 kt thc) hay do cc tc nhn bn ngoi (ngt bo c 1 button c nhn, ngt bo c 1 gi d liu c nhn). Ngt l mt trong 2 k thut bt s kin c bn l hi vng (Polling) v ngt. Hy tng tng bn cn thit k mt mch iu khin hon chnh thc hin rt nhiu nhim v bao gm nhn thng tin t ngi dng qua cc button hay keypad (hoc keyboard), nhn tn hiu t cm bin, x l thng tin, xut tn hiu iu khin, hin th thng tin trng thi ln cc LCD(bn hon ton c th lm c vi AVR), r rng trong cc nhim v ny vic nhn thng tin ngi dng (start, stop, setup, change,) rt him xy ra (so vi cc nhim v khc) nhng li rt khn cp, c u tin hng u. Nu dng Polling ngha l bn cn vit 1 on chng trnh chuyn thm d trng thi ca cc button (ti tm gi on chng trnh l Input()) v bn phi chn on chng trnh Input() ny vo rt nhiu v tr trong chng trnh chnh trnh trng hp b st lnh t ngi dng, iu ny tht lng ph thi gian thc thi. Gii php cho vn ny l s dng ngt, bng cch kt ni cc button vi ng ngt ca chip v s dng chng trnh Input() lm trnh phc v ngt - isr ca ngt , bn khng cn phi chn Input() trong lc ang thc thi v v th khng tn thi gian cho n, Input() ch c gi khi ngi dng nhn cc button. l tng s dng ngt.
Hnh 1 minh ha cch t chc ngt thng thng trong cc chip AVR. S lng ngt trn mi dng chip l khc nhau, ng vi mi ngt s c vector ngt, vector ngt l cc thanh ghi c a ch c nh c nh ngha trc nm trong phn u ca b nh chng trnh. V d vector ngt ngoi 0 (external interrupt 0) ca chip atmega8 c a ch l 0x001 (theo datasheet t Atmel). Trong lc chng trnh chnh ang thc thi, nu c mt s thay i dn n ngt xy ra chn INT0 (chn 4), b m chng trnh (Program Counter) nhy n a ch 0x009, gi s ngay ti a ch 0x001 chng ta c t 1 lnh RJMP n mt trnh phc v ngt (IRS1 chng hn), mt ln na b m chng trnh nhy n IRS1 thc thi trnh phc v ngt, kt thc ISR1, b m chng trnh li quay v v tr trc trong chng trnh chnh, qu trnh ngt kt thc. Khng mang tnh bt buc nhng ti khuyn bn nn t chc chng trnh ngt theo cch ny trnh nhng li lin quan n a ch chng trnh.
Hnh 1. Ngt. Bng 1 tm tt cc vector ngt c trn chip atmega8, cho cc chip khc bn hy tham kho datasheet bit thm.
Bng 1 cc vector ngt v Reset trn chip Atmega8.
II. Ngt ngoi (External Interrupt). Phn ny ti dnh gii thiu cc bn cch ci t v s dng ngt ngoi v y l loi ngt duy nht c lp vi cc thit b ca chip, cc ngt khc thng gn vi hot ng ca 1 thit b no nh Timer/Counter, giao tip ni tip USART, chuyn i ADCchng ta s kho st c th khi tm hiu v hot ng ca cc thit b ny. Ngt ngoi l cch rt hiu qu thc hin giao tip gia ngi dng v chip. Trn chip atmega8 c 2 ngt ngoi c tn l INT0 v INT1 tng ng 2 chn s 4 (PD2) v s 5 (PD3). Nh ti cp trong bi AVR2, khi lm vic vi cc thit b ngoi vi ca AVR, hu nh chng ta ch thao tc trn cc thanh ghi chc nng c bit
- SFR (Special Function Registers) trn vng nh IO, mi thit b bao gm mt tp hp cc thanh ghi iu khin, trng thi, ngtkhc nhau, iu ny ng ngha chng ta phi nh tt c cc thanh ghi ca AVR. Lc ny datasheet pht huy tc dng, bn phi nhanh chng download file datasheet ca chip mnh ang s dng, c rt nhiu ni download nh ti www.atmel.com hay trn cc trang web chuyn cung cp IC datasheet min ph (www.alldatasheet.com l 1 v d). Quay v vi ngt ngoi, c 3 thanh ghi lin quan n ngt ngoi l MCUCR, GICR v GIFR. C th cc thanh ghi c trnh by bn di. Thanh ghi iu khin MCU MCUCR (MCU Control Register) l thanh ghi xc lp ch ngt cho ngt ngoi, quan st hnh 2 trc khi tm hiu thanh ghi ny.
Hnh 2. Kt ni ngt ngoi cho atmega8. Gi s chng ta kt ni cc ngt ngoi trn AVR mega8 nh pha tri hnh 2, cc button dng to ra cc ngt. C 4 kh nng (tm gi l cc MODES) c th xy ra khi chng ta nhn v th cc button. Nu khng nhn, trng thi cc chn INT l HIGH do in tr ko ln, khi va nhn 1 button, s c chuyn trng thi t HIGH sang LOW, chng ta gi l cnh xung - Falling Edge, khi button c nhn v gi, trng thi cc chn INT c xc nh l LOW v cui cng khi th cc button, trng thi chuyn t LOW sang HIGH, gi l cnh ln Rising Edge. Trong nhng trng hp c th, 1 trong 4 MODES trn u hu ch, v d trong cc ng dng m xung (m encoder ca servo motor chng hn) th 2 MODE cnh phi c dng. Thanh ghi MCUCR cha cc bits cho php chng ta chn 1 trong 4 MODE trn cho cc ngt ngoi. Di y l cu trc thanh ghi MCUCR c trch ra t datasheet ca chip atmega8.
MCUCR l mt thanh ghi 8 bit nhng i vi hot ng ngt ngoi, chng ta ch quan tm n 4 bit thp ca n (4 bit cao dng cho Power manager v Sleep Mode). Bn bit thp l cc bit Interrupt Sense Control (ISC) trong 2 bit ISC11:ISC10 dng cho INT1 v 2 bit ISC01:ISC00 dng cho INT0. Hy nhn vo bng tm tt bn di
bit chc nng ca cc bit trn, y l bng chn tr ca 2 bit ISC11, ISC10. Bng chn tr cho cc bit ISC01, ISC00 hon ton tng t. Bng 2: INT1 Sense Control
Tht d dng hiu chc nng ca cc bit Sense Control, v d bn mun set cho INT1 l ngt cnh xung (Falling Edge) trong khi INT0 l ngt cnh ln (Rising Edge), hy t dng lnh MCUCR =0x0B (0x0B = 00001011 nh phn) trong chng trnh ca bn. Thanh ghi iu khin ngt chung GICR (General Interrupt Control Register) (ch trn cc chip AVR c, nh cc chip AT90Sxxxx, thanh ghi ny c tn l thanh ghi mt n ngt thng thng GIMSK, bn tham kho thm datasheet ca cc chip ny nu cn s dng n). GICR cng l 1 thanh ghi 8 bit nhng ch c 2 bit cao (bit 6 v bit 7) l c s dng cho iu khin ngt, cu trc thanh ghi nh bn di (trch datasheet).
Bit 7 INT1 gi l bit cho php ngt 1(Interrupt Enable), set bit ny bng 1 ngha bn cho php ngt INT1 hot ng, tng t, bit INT0 iu khin ngt INT0. Thanh ghi c ngt chung GIFR (General Interrupt Flag Register) c 2 bit INTF1 v INTF0 l cc bit trng thi (hay bit c - Flag) ca 2 ngt INT1 v INT0. Nu c 1 s kin ngt ph hp xy ra trn chn INT1, bit INTF1 c t ng set bng 1 (tng t cho trng hp ca INTF0), chng ta c th s dng cc bit ny nhn ra cc ngt, tuy nhin iu ny l khng cn thit nu chng ta cho php ngt t ng, v vy thanh ghi ny thng khng c quan tm khi lp trnh ngt ngoi. Cu trc thanh ghi GIFR c trnh by trong hnh ngay bn di.
Sau khi xc lp cc bit sn sng cho cc ngt ngoi, vic sau cng chng ta cn lm l set bit I, tc bit cho php ngt ton cc, trong thanh ghi trng thi chung ca chip (thanh ghi SREG, xem li bi AVR2). Mt ch khc l v cc chn PD2, PD3 l cc chn ngt nn bn phi set cc chn ny l Input (set thanh ghi DDRD). Qu trnh thit lp ngt ngoi c trnh by trong hnh 10.
Hnh 3. Thit lp ngt ngoi. Ngt ngoi vi ASM: Di y ti trnh by cch vit chng trnh s dng ngt ngoi bng ngn ng ASM, i vi cc ngt khc bn ch cn thm cc DIRECTIVE nh v cc vector ngt tng ng v vit chng trnh phc v ngt tng ng. List 1. Ngt vi ASM. 1 .CSEG 2 .INCLUDE "M8DEF.INC" 3 .ORG 0x000 ; nh v v tr u tin 4 RJMP BATDAU 5 6 .ORG 0x001; nh v vector ngt ngoi 0 - INT0 (xem bng vector) 7 RJMP INT0_ISR ; Nhy n INT0_ISR nu c ngt INT0 xy ra 8 .ORG 0x002 ; nh v vector ngt ngoi 1 INT1 (xem bng vector) 9 RJMP INT1_ISR ; Nhy n INT1_ISR nu c ngt INT1 xy ra 10 11 ;Tng t, nh v cc vector ngt khc y.. 12 ;.. 13 14 .ORG 0x020 ; nh v chng trnh chnh 15 BATDAU:
16 ; khi to Stack 17 LDI R16, HIGH(RAMEND) 18 LDI R17, LOW(RAMEND) 19 OUT SPH, R16 OUT SPL, R17 20 21 22 ; set chn PD2 v PD3 nh cc chn input LDI R16, 0Bxxxx00xx ; x l trng thi do bn t chn, 0 hoc 1 23 OUT DDRD, R16 ; PD2 v PD3 l input 24 LDI R16, 0Bxxxx11xx ; x l trng thi do bn t chn, 0 hoc 1 25 OUT PORTD, R16 ; mc in tr ko ln cho PD2, PD3 26 27 28 29 ; khi ng ngt LDI R16, $0B ; $0B=00001011, INT1: ngt cnh xung, INT0: ngt cnh ln 30 OUT MCUCR, R16 ; xut gi tr iu khin ra thanh ghi MCUCR 31 LDI R16, $C0 ;$C0=11000000: Enable INT1 v INT0 32 OUT GICR, R16 ;xut gi tr iu khin ra thanh ghi GICR 33 SEI ;set bit cho php ngt ton cc 34 35 ; Chng trnh chnh 36 MAIN: 37 ;cc cng vic m chng trnh chnh cn thc hin 38 ;. RJMP MAIN 39 40 41 ;v y l nh ngha trnh phc v ngt INT0_ISR 42 INT0_ISR: 43 ; cc cng vic cn thc hin khi c ngt 44 ;. RETI ; phi dng lnh RETI quay v chng trnh chnh 45 46 ;v y l nh ngha trnh phc v ngt INT1_ISR 47 INT1_ISR: 48 ; cc cng vic cn thc hin khi c ngt ;. RETI ; phi dng lnh RETI quay v chng trnh chnh Bn thy cc cc ngt c nh v nm gia v tr 0x0000, khi mi khi ng, ti v tr 0x000 l lnh RJMP BATDAU, nh th cc lnh RJMP ti cc vector ngt v cc ISR u khng c thc hin, chng ch c thc hin mt cch t ng khi c ngt. Ngt ngoi vi C: Avr-libc h tr mt th vin hm cho ngt kh hon ho, s dng ngt trong chng trnh vit bng C (avr-gcc) bn ch cn include file interrupt.h nm trong th mc con avr l xong. file header interrupt.h cha nh
ngha cc hm v phng thc phc v cho vit trnh phc v ngt, cc vector ngt khng c nh ngha trong file ny m trong file iom8.h (cho atmega8). Nu bn v tnh tm thy 1 chng trnh ngt no khng include file interrupt.h m include file signal.h th bn ng ngc nhin, l cch vit c trong avr-gcc, tht ra bn hon ton c th s dng cch vit c v cc phin bn mi ca avr-libc (i cng vi cc bn WinAVR mi) vn h tr cch vit ny nhng khng khuyn khch bn dng. Trong C, cc trnh phc v ngt c dng l ISR(vector_name). Trong cc phin bn c trnh phc v ngt c tn SIGNAL(vector_name), nhng cng nh file header signal.h, cch vit ny vn c h tr trong phin bn mi nhng khng c khuyn khch. List 2. Ngt vi C. 1 2 3 4 5 6 #include <avr/interrupt.h> ISR (vector_name) { //user code here }
Trong vector_name l tn ca cc vector ngt nh ngha sn avr-libc, ISR l tn bt buc, bn khng c dng cc tn khc ty (nhng c th dng SIGNAL nh trnh by trn). c bit, bn c th t ISR trc hoc sau chng trnh chnh u khng nh hng v tht ra, c kh nhiu cng on c thc hin khi bn gi ISR (nhng bn khng thy v cng khng cn quan tm). ISR lun c trnh bin dch t ngoi vng vector ngt nh cch chng ta thc hin trong ASM, nh th mt chng trnh s dng nhiu loi ngt s phi c s lng trnh ISR tng ng nhng vi vector_name khc nhau, mi khi c ngt xy ra, ty thuc vo gi tr ca vector_name m 1 trong cc trnh ISR c thc thi. i vi cc vector_name, bit c vector_name cho mi loi ngt, bn cn tham kho ti liu avr-libc manual. Bng 10 tm tt cc vector_name ca mt s ngt thng dng trn atmega8, bn ch rng cc vector_name trong avr-libc c nh ngha rt khc nhau cho tng loi chip, bn nht thit phi s dng ti liu avr-libc manual bit chnh xc cc vector_name cho loi chip m bn ang dng. Bng 3: vector_name cho atmega8.
Vector name ADC_vect ANA_COMP_vect EE_RDY_vect INT0_vect INT1_vect Created by QuocHuy Hoang huyhq.fet.hut@gmail.com Page 35 Old vector name SIG_ADC SIG_COMPARATOR SIG_EEPROM_READY SIG_INTERRUPT0 SIG_INTERRUPT1 Description ADC Conversion Complete Analog Comparator EEPROM Ready External Interrupt 0 External Interrupt Request 1
Thanhtam Ho - www.hocavr.com SIG_SPI SIG_SPM_READY SIG_OVERFLOW0 SIG_INPUT_CAPTURE1 Serial Transfer Complete Store Program Memory Ready Timer/Counter0 Overflow Timer/Counter Capture Event
SPI_STC_vect SPM_RDY_vect TIMER0_OVF_vect TIMER1_CAPT_vect TIMER1_COMPA_vect TIMER1_COMPB_vect TIMER1_OVF_vect TIMER2_COMP_vect TIMER2_OVF_vect TWI_vect USART3_UDRE_vect
SIG_OUTPUT_COMPARE1A Timer/Counter1 Compare Match A SIG_OUTPUT_COMPARE1B Timer/Counter1 Compare MatchB SIG_OVERFLOW1 SIG_OUTPUT_COMPARE2 SIG_OVERFLOW2 SIG_2WIRE_SERIAL SIG_USART3_DATA Timer/Counter1 Overflow Timer/Counter2 Compare Match Timer/Counter2 Overflow 2-wire Serial Interface USART3 Data register Empty
III. V d ngt ngoi vi C. thc hin v d s dng ngt ngoi bng C, ti s vit li chng trnh v d ca bi "cu trc AVR" nhng bng ngn ng C v s dng ngt. Trong chng trnh v d ca bi AVR2, chng ta thc hin vic m ln v m xung dng 2 button, chng ta s vn thc hin trn tng ny nhng c cht thay i trong kt ni, trc ht bn v 1 mch in m phng trong Proteus nh hnh 4.
Hnh 4. Mch in m phng ngt. Kt ni button m ln vi ngt INT0, button m xung vi INT1, PORTB c chn lm PORT xut. Hy chy Programmer Notepad, to 1 Project mi tn AVR2INT, type on code bn di vo 1 file new v lu vi tn main.c, add file ny vo Project ca bn, sau to mt Makefile cho Project.
List 3. v d ngt ngoi bng C. 1 #include <avr/io.h> 2 #include <avr/interrupt.h> 3 #include <avr/delay.h> 4 5 volatile int8_t val=0; //khai bo 1 bin val 8 bit, c du v gi tr khi to bng 0. 6 int main(void){ 7 8 DDRD=0x00; //khai bo PORTD l Input s dng 2 chn ngt. 9 PORTD=0xFF; //s dng in tr ni ko ln. 10 DDRB=0xFF; //PORTB l Output xut LED 7 on 11 12 MCUCR|=(1<<ISC11)|(1<<ISC01); //c 2 ngt l ngt cnh xung 13 GICR |=(1<<INT1)|(1<<INT0); //cho php 2 ngt hot ng 14 sei(); //set bit I cho php ngt ton cc 15 16 DDRC=0xFF; //PORTC l Output 17 while (1){ //vng lp v tn 18 PORTC++; //qut PORTC 19 _delay_loop_2(60000); 20 } 21 return 0; 22 } 23 24 //Trnh phc v ngt ca INT0 25 ISR(INT0_vect){ 26 val++; //nu c ngt INT0 xy ra, tng val thm 1 27 if (val>9) val=0; //gii hn khng vt qu 9 28 PORTB=val; 29 } 30 31 //Trnh phc v ngt ca INT1 32 ISR(INT1_vect){ 33 val--; //nu c ngt INT1 xy ra, gim val i 1 34 if (val<0) val=9; //gii hn khng nh hn 0 35 PORTB=val; 36 } C l on code ny kh d hiu nu cc bn theo di t u bi hc, ti ch gii thch nhng nt c bn v mi. tng l chng ta s dng 1 bin tm 8 bit, c du lu gi tr m, tn bin val, mi khi c ngt trn chn INT0, tng val 1 n v v ngc li khi c ngt trn INT1, gim val i 1, l ni dung ca 2 trnh phc v ngt. Trong chng trnh chnh, trc ht chng ta thc hin vic xc lp hot ng cho 2 ngt, sau a chng trnh vo 1 vng lp v tn while(1), PORTC c
dng kim tra rng chng trnh trong vng lp v tn vn ang hot ng. C l phn kh hiu nht trong on code l cch m ti dng khai bo cho 2 thanh ghi iu khin ngt MCUCR v GICR. Nu xem li bng tm tt cc ton t ca C, ton t << c gi l ton t dch tri dng trn dng nh phn ca cc con s, nu bn thy x=5<<3 ngha l dch cc bit nh phn ca 5 sang tri 3 v tr v gn cho x, nh m t nh sau:
Bn thy ton b cc bit ca 5 dch sang tri 3 v tr v gi tr ca s mi thu c l x=40, ch 40=5x8=5x2^3 . Hy nhn cu lnh MCUCR|=(1<<ISC11)|(1<<ISC01), gi th bn hiu (1<<ISC11) ngha l dch s 1 sang tri ISC11 v tr, v (1<<ISC01) l dch s 1 sang tri ISC01 v tr, nhng ISC11 v ISC01 u ra v gi tr ca chng l bao nhiu? Bn ch , khi bn include file io.h th file iom8.h c chn vo, v trong file ny cha khai bo a ch cc thanh ghi ca chip atmega8, cc tn bit cng c khai bo sn trong file ny, nu bn m file iom8.h (thng nm trong th mc ~\WinAVR\avr\include\avr) bng 1 chng trnh text editor nh notepad, dng chc nng find bn s thy cc dng nh ngha nh sau:
/* MCUCR */ #define SE #define SM2 #define SM1 #define SM0 #define ISC11 #define ISC10 #define ISC01 #define ISC00 7 6 5 4 3 2 1 0
y l nh ngha v tr cc bit trong thanh ghi MCUCR, vy l r, ISC11=3, ISC01=1, do : (1<<ISC11) tng ng (1<<3) = 00001000 (Binary) v (1<<ISC01) = 00000010, bn hy tng tng rng bn mang s 1 n cc v tr ca ISC11 v ISC01 trong thanh ghi MCUCR. By gi n lt ton t OR bitwise |. (1<<ISC11) = 00001000 (1<<ISC01) = 00000010 -------------------------------------------------(1<<ISC11)|(1<<ISC01) = 00001010
Gn gi tr ny cho MCUCR, i chiu vi bng cc gi tr ca cc bit ISC (bng 9) bn s thy chng ta ang set cho 2 ngt l falling edge. iu cui cng ca cu lnh set MCUCR l cch rt gn cu lnh MCUCR|=(1<<ISC11)|(1<<ISC01) thc cht l MCUCR= MCUCR| ((1<<ISC11)|(1<<ISC01)), y l cch set mt s bit trong mt thanh ghi m khng mun lm nh hng n cc bit khc (nhng bn phi tht cn thn vi cch lm ny v c th s phn tc dng nu bn khng nm r), bn c th gn trc tip MCUCR=(1<<ISC11)|(1<<ISC01), hay nhanh hn MCUCR=0x0A (0x0A=00001010). Vy l do no khin ti bin 1 cu lnh gn n gin thnh mt bi ton kh hiu, cu tr li chnh l tnh tng qut. Trong cc chip AVR khc nhau, v tr cc bit trong cc thanh ghi l rt khc nhau, cu lnh MCUCR=0x0A ng cho atmega8 nhng khng p dng c cho cc chip khc trong khi cu lnh MCUCR=(1<<ISC11)|(1<<ISC01) th hot ng tt, mt l do khc l cch vit gin tip ny gip ngi khc (hay chnh bn sau ny) khi c code c th d dng hiu c ngi vit Ti ngh bn qu hiu dng lnh tip theo, GICR |=(1<<INT1)|(1<<INT0). Ti dng gii thch on code y v cng dng bi AVR3, bn hy thc tp bng cch vit li on code trn bng ASM.
Bi 4 - Timer - Counter
Ni dung 1. Gii thiu. 2. Tng quan Timer/Counter trn AVR. 3. S dng Timer/Counter. 1. Timer/Counter0 2. Timer/Counter1 Download v d I. Gii thiu. Trong bi 3 ti gii thiu khi qut phng php lp trnh bng ngn ng C cho AVR vi WinAVR v cch s dng ngt trong AVR. Bi 4 ny chng ta s kho st cc ch hot ng ca phng php iu khin cc b nh thi, m (Timer/Counter) trong AVR. Cng c phc v cho bi ny vn l b cng c WinAVR v phn mm m phng Proteus. Ti vn dng chip Atmega8 lm v d. Mt iu khng may mn l khng phi tt c cc b Timer/Counter trn tt c cc dng chip AVR l nh nhau, v th nhng g ti trnh by trong bi ny c th s khng ng vi cc dng AVR khc nh AT90STuy nhin ti cng s c gng ch ra mt s im khc bit c bn cc bn c th t mnh iu khin cc chip khc. Ni dung bi hc ny bao gm:

Cc bi cn tham kho trc Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus.
Nm bt c bn cc b Timer/Counter c trn AVR. S dng cc Timer/Counter nh cc b nh thi. S dng cc Timer/Counter nh cc b m. S dng cc Timer/Counter nh cc b to xung iu rng PWM. Vit mt v d iu khin ng c RC servo bng PWM.
II. Tng quan cc b Timer/Counter trn chip Atmega8. Timer/Counter l cc module c lp vi CPU. Chc nng chnh ca cc b Timer/Counter, nh tn gi ca chng, l nh th (to ra mt khong thi gian, m thi gian) v m s kin. Trn cc chip AVR, cc b Timer/Counter cn c thm chc nng to ra cc xung iu rng PWM (Pulse Width Modulation), mt s dng AVR, mt s Timer/Counter cn c dng nh cc b canh chnh thi gian (calibration) trong cc ng dng thi gian thc. Cc b Timer/Counter c chia theo rng thanh ghi cha gi tr nh thi hay gi tr m ca chng, c th trn chip Atmega8 c 2 b Timer 8 bit (Timer/Counter0 v Timer/Counter2) v 1 b 16 bit (Timer/Counter1). Ch hot ng v phng php iu khin ca tng Timer/Counter cng khng hon ton ging nhau, v d chip Atmega8:
Timer/Counter0: l mt b nh thi, m n gin vi 8 bit. Gi l n gin v b ny ch c 1 ch hot ng (mode) so vi 5 ch ca b Timer/Counter1. Ch hoat ng ca Timer/Counter0 thc cht c th coi nh 2 ch nh (v cng l 2 chc nng c bn) l to ra mt khong thi gian v m s kin. Ch l trn cc chip AVR dng mega sau ny nh Atmega16,32,64chc nng ca Timer/Counter0 c nng ln nh cc b Timer/Counter1 Timer/Counter1: l b nh thi, m a nng 16 bit. B Timer/Counter ny c 5 ch hot ng chnh. Ngoi cc chc nng thng thng, Timer/Counter1 cn c dng to ra xung iu rng PWM dng cho cc mc ch iu khin. C th to 2 tn hiu PWM c lp trn cc chn OC1A (chn 15) v OC1B (chn 16) bng Timer/Counter1. Cc b Timer/Counter kiu ny c tch hp thm kh nhiu trong cc chip AVR sau ny, v d Atmega128 c 2 b, Atmega2561 c 4 b Timer/Counter2: tuy l mt module 8 bit nh Timer/Counter0 nhng Timer/Counter2 c n 4 ch hot ng nh Timer/Counter1, ngoi ra n n cn c s dng nh mt module canh chnh thi gian cho cc ng dng thi gian thc (ch asynchronous). Trong phm vi bi 4 ny, ti ch yu hng dn cch s dng 4 ch hot ng ca cc Timer/Counter. Ch asynchronous ca Timer/Counter2 s c b qua v c th ch ny khng c s dng ph bin. Trc khi kho st hot ng ca cc Timer/Counter, chng ta thng nht cch gi tt tn gi ca cc Timer/Counter l T/C, v d T/C0 ch Timer/Counter0 II. S dng Timer/Counter. C mt s nh ngha quan trng m chng ta cn nm bt trc khi s dng cc T/C trong AVR:

BOTTOM: l gi tr thp nht m mt T/C c th t c, gi tr ny lun l 0. MAX: l gi tr ln nht m mt T/C c th t c, gi tr ny c quy nh bi bi gi tr ln nht m thanh ghi m ca T/C c th cha c. V d vi mt b T/C 8 bit th gi tr MAX lun l 0xFF (tc 255 trong h thp phn), vi b T/C 16 bit th MAX bng 0xFFFF (65535). Nh th MAX l gi tr khng i trong mi T/C. TOP: l gi tr m khi T/C t n n s thay i trng thi, gi tr ny khng nht thit l s ln nht 8 bit hay 16 bit nh MAX, gi tr ca TOP c th thanh i bng cch iu khin cc bit iu khin tng ng hoc c th nhp tr tip thng qua mt s thanh ghi. Chng ta s hiu r v gi tr TOP trong lc kho st T/C1.
1. Timer/Counter0: Thanh ghi: c 4 thanh ghi c thit k ring cho hot ng v iu khin T/C0, l:
TCNT0 (Timer/Counter Register): l 1 thanh ghi 8 bit cha gi tr vn hnh ca T/C0. Thanh ghi ny cho php bn c v ghi gi tr mt cch trc tip.
TCCR0 (Timer/Counter Control Register): l thanh ghi iu khin hot ng ca T/C0. Tuy l thanh ghi 8 bit nhng thc cht ch c 3 bit c tc dng l CS00, CS01 v CS02.
Cc bit CS00, CS01 v CS02 gi l cc chip chn ngun xung nhp cho T/C0 (Clock Select). Chc nng cc bit ny c m t trong bng 1. Bng 1: chc nng cc bit CS0X
TIMSK (Timer/Counter Interrupt Mask Register): l thanh ghi mt n cho ngt ca tt c cc T/C trong Atmega8, trong ch c bit TOIE0 tc bit s 0 (bit u tin) trong thanh ghi ny l lin quan n T/C0, bit ny c tn l bit cho php ngt khi c trn T/C0. Trn (Overflow) l hin tng xy ra khi b gi tr trong thanh ghi TCNT0 t n MAX (255) v li m thm 1 ln na.
Khi bit TOIE0=1, v bit I trong thanh ghi trng thi c set (xem li bi 3 v iu khin ngt), nu mt trn xy ra s dn n ngt trn.
TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c cc b T/C. Trong thanh ghi ny bit s 0, TOV0 l c ch th ngt trn ca T/C0. Khi c ngt trn xy ra, bit ny t ng c set ln 1. Thng thng trong iu khin cc T/C vai tr ca thanh ghi TIFR khng qu quan trng.
Hot ng: T/C0 hot ng rt n gin, hot ng ca T/C c kch bi mt tn hiu (signal), c mi ln xut hin tn hiu kch gi tr ca thanh ghi TCNT0 li tng thm 1 n v, thanh ghi ny tng cho n khi n t mc MAX l 255, tn hiu
kch tip theo s lm thanh ghi TCNT0 tr v 0 (trn), lc ny bit c trn TOV0 s t ng c set bng 1. Vi cch thc hot ng nh th c v T/C0 v dng v c tng t 0 n 255 ri li quay v khng v qu trnh lp li. Tuy nhin, yu t to s khc bit chnh l tnh hiu kch v ngt trn, kt hp 2 yu t ny chng ta c th to ra 1 b nh thi gian hoc 1 b m s kin. Trc ht bn hy nhn li bng 1 v cc bit chn xung nhp cho T/C0. Xung nhp cho T/C0 chnh l tn hiu kch cho T/C0, xung nhp ny c th to bng ngun to dao ng ca chip (thch anh, dao ng ni trong chip). Bng cch t gi tr cho cc bit CS00, CS01 v CS02 ca thanh ghi iu khin TCCR0 chng ta s quyt nh bao lu th s kch T/C0 mt ln. V d mch ng dng ca bn c ngun dao ng clkI/O = 1MHz tc chu k 1 nhp l 1us ( 1 micro giy), bn t TCCR0=5 (SC02=1, CS01=0, CS00=1), cn c theo bng 1 tn hiu kch cho T/C0 s bng clkI/O/1024 ngha l sau 1024us th T/C0 mi c kch 1 ln, ni cch khc gi tr ca TCNT0 tng thm 1 sau 1024us (ch l tn s c chia cho 1024 th chu k s tng 1024 ln). Quan st 2 dng cui cng trong bng 1 bn s thy rng tn hiu kch cho T/C0 c th ly t bn ngoi (External clock source), y chnh l tng cho hot ng ca chc nng m s kin trn T/C0. Bng cch thay i trng thi chn T0 (chn 6 trn chip Atmega8) chng ta s lm tng gi tr thanh ghi TCNT0 hay ni cch khc T/C0 c th dng m s kin xy ra trn chn T0. Di y chng ta s xem xt c th cch iu khin T/C0 theo 1 ch nh thi gian v m. 1.1 B nh thi gian. Chng ta c th to ra 1 b nh th ci t mt khong thi gian no . V d bn mun rng c sau chnh xc 1ms th chn PB0 thay i trng thi 1 ln (nhp nhy), bn li khng mun dng cc lnh delay nh trc nay vn dng v nhc im ca delay l CPU khng lm g c trong lc delay, v th trong nhiu trng hp cc lnh delay rt hn ch c s dng. By gi chng ta dng T/C0 lm vic ny, tng l chng ta cho b m T/C0 hot ng, khi n m 1ms th n s t kch hot ngt trn, trong trnh phc v ngt trn chng tat hay i trng thi chn PB0. Ti minh ha tng nh trong hnh 1.
Hnh 1. So snh 2 cch lm vic. (CPU nop: trong khong thi gian ny CPU khng lm g c)
Mt vn ny sinh lc ny, nh ti trnh by trong phn trc, T/C0 ch m t 0 n 255 ri li quay v 0 (xy ra 1 ngt trn), nh th dng nh chng ta khng th ci t gi tr mong mun bt k cho T/C0? Cu tr li l chng ta c th bng cch gn trc mt gi tr cho thanh ghi TCNT0, khi y T/C0 s m t gi tr m chng ta gn trc v kt thc 255. Tuy nhin do khi trn xy ra, TCNT0 li c t ng tr v 0, do vic gn gi tr khi to cho TCNT0 phi c thc hin lin tc sau mi ln xy ra trn, v tr tt nht l t trong trnh phc v ngt trn. Vic cn li v cng l vic quan trng nht l vic tnh ton gi tr chia (prescaler) cho xung nhp ca T/C0 v vic xc nh gi tr khi u cn gn cho thanh ghi TCNT0 c c 1 khong thi gian nh th chnh xc nh mong mun. Trc ht chng ta s chn prescaler sao cho hp l nht (chn gi tr chia bng cch set 3 bit CS02,CS01,CS00). Gi s ngun xung clock nui chip ca chng ta l clkI/O=1MHz tc l 1 nhp mt 1us, nu chng ta prescaler=1, tc l tn s ca T/C0 (tm gi l fT/C0) cng bng clkI/O=1MHz, c 1us T/C0 c kch v TCNT0 s tng 1 n v. Khi gi tr ln nht m T/C0 c th t c l 256 x 1us=256us, gi tr ny nh hn 1ms m ta mong mun. Nu chn prescaler=8 (xem bng 1) ngha l c sau 8 nhp (8us) th TCNT0 mi tng 1 n v, kh nng ln nht m T/C0 m c l 256 x 8us=2048us, ln hn 1ms, vy ta hon ton c th s dng prescaler=8 to ra mt khong nh th 1ms. Bc tip theo l xc nh gi tr khi u ca TCNT0 T/C0 m ng 1ms (1000us). ng vi prescaler=8 chng ta bit l c 8us th TCNT0 tng 1 n v, d dng tnh c b m cn m 1000/8=125 ln ht 1ms, do gi tr ban u ca TCNT0 phi l 256-125=131. Bn c th quan st hnh 2 hiu thu o hn.
Hnh 2. Qu trnh thc hin. Hy to 1 Project bng Programmer Notepad vi tn gi TIMER0 v vit on code cho Project ny nh trong list 1. List 1. nh th 1ms vi T/C0. 1 #include <avr/io.h> 2 #include <avr/interrupt.h> 3 #include <util/delay.h> 4 5 int main(void){ 6 DDRB=0xFF; //PORTB la output PORT 7 PORTB=0x00; 8
9 TCCR0=(1<<CS01);// CS02=0, CS01=1, CS00=0: chon Prescaler = 8 10 TCNT0=131; //gan gia tri khoi tao cho T/C0 11 TIMSK=(1<<TOIE0);//cho phep ngat khi co tran o T/C0 12 sei(); //set bit I cho phep ngat toan cuc 13 14 while (1){ //vng lp v tn 15 //do nothing 16 } 17 return 0; 18 } 19 20 //trinh phuc vu ngat tran T/C0 21 ISR (TIMER0_OVF_vect ){ 22 PORTB ^=1; //doi trang thai Bit PB0 23 TCNT0=131; //gan gia tri khoi tao cho T/C0 24 } on code rt n gin, bn ch cn ch n 3 dng khai bo cho T/C0 (dng 9, 10, 11). Vi dng 9: TCCR0=(1<<CS01) l 1 cch set bit CS01 trong thanh ghi iu khin TCCR0 ln 1, 2 bit CS02 v CS00 c gi tr 0 (bn xem li bi 3 v cch set cc bit c bit trong cc thanh ghi), tm li dng ny tng ng TCCR0=2, gi tr Prescaler c chn bng 8 (tham kho bng 1). Dng 10 chng ta gn gi tr khi to cho thanh ghi TCNT0. V dng 11 set bit TIOE0 ln 1 cho php ngt xy ra khi c trn T/C0. Trong trnh phc v ngt trn T/C0, chng ta s thc hin i trng thi chn PB0 bng ton t XOR (^), ch n ngha ca ton t XOR: nu XOR mt bit vi s 1 th bit ny s chuyn trng thi (t 0 sang 1 v ngc li). Cui cng v quan trng l chng ta cn gn li gi tr khi to cho T/C0. Bn c th v mt mch in m phng n gin dng 1 Oscilloscope nh trong hnh 3 kim tra hot ng ca on code.
Hnh 3. M phng nh th ca T/C0.

1.2 B m s kin. Nh ti trnh by trong phn hot ng ca T/C0, chng ta c th dng T/C0 nh mt b m (counter) m cc s kin (s thay i trng thi) xy ra trn chn T0. Bng cch t gi tr cho thanh ghi TCCR0 = 6 (CS02=1, CS01=1, CS00=0) cho php m cnh xung trn chn T0, nu TCCR0 = 7 (CS02=1, CS01=1, CS00=1) th cnh ln trn chn T0 s c m. C s dng ngt hay khng ph thuc vo mc ch s dng. Kho st 1 v d n gin gn ging vi v d m trong bi AVR2 nhng s dng T/C0 v ch m 1 chiu tng. Kt ni mch in nh trong hnh 4, mi ln Button 1 c nhn, gi tr m tng thm 1. Button 2 dng reset gi tr m v 0. on code cho v d th 2 ny c trnh by trong List 2.
Hnh 4. m 1 chiu bng T/C0. List 2. m s kin vi T/C0 #include <avr/io.h> 1 #include <avr/interrupt.h> 2 3 int main(void){ 4 DDRB=0xFF; //PORTB la output PORT 5 PORTB=0x00; 6 DDRD=0x00; //khai bao PORTD la input de ket noi Button kich vao chan T0 7 PORTD=0xFF; //su dung dien tro keo len cho PORTD 8 9 TCCR0=(1<<CS02)|(1<<CS01);// CS02=1, CS01=1, CS00=0: xung nhip tu 10 chan T0, down 11 TCNT0=0; 12 13 while (1){ //vng lp v tn 14 if (TCNT0==10) TCNT0=0; 15 PORTB=TCNT0; //xuat gia tri dem ra led 7 doan 16 if (bit_is_clear(PIND,7)) TCNT0=0; //Reset bo dem neu chan PD7=0 17 } 18 return 0; 19 }
Ni dung trong chng trnh chnh l khai bo cc hng giao tip cho cc PORT, PORTB l ouput xut kt qu m ra led 7 on, PORTD c khi bo input v cc button c ni vi PORT ny. T/C0 c khai bo s dng ngun kch ngoi t T0, dng cnh xung thng qua dng TCCR0=(1<<CS02)|(1<<CS01), bn cng c th khai bo tng ng l TCCR0=6 (tham kho bng 1). Gi tr ca b m s c xut ra PORTB kim tra. im ch trong on chng trnh ny l macro bit_is_clear, y l mt macro c nh ngha trong file sfr_defs.h dng kim tra 1 bit trong mt thanh ghi c bit c c xa (bng 0) hay khng, trong trng hp ca on code trn: if(bit_is_clear(PIND,7)) TCNT0=0; ngha l kim tra xem nu chn PD7 c ko xung 0 (button 2 c nhn) th s reset b m v 0. Nh vy vic s dng T/C0 l tng i n gin, bn ch cn khai bo cc gi tr thch hp cho thanh ghi iu khin TCCR0 bng cch tham kho bng 1, sau khi to gi tr cho TCNT0 (nu cn thit), khai bo c s dng ngt hay khng bng cch set hay khng set bit TOIE0 trong thanh ghi TIMSK l hon tt. 2. Timer/Counter1: Timer/Counter1 l b T/C 16 bits, a chc nng. y l b T/C rt l tng cho lp trnh o lng v iu khin v c phn gii cao (16 bits) v c kh nng to xung iu rng PWM (Pulse Width Modulation thng dng iu khin ng c). Thanh ghi: c kh nhiu thanh ghi lin quan n T/C1. V l T/C 16 bits trong khi rng b nh d liu ca AVR l 8 bit (xem li bi 2) nn i khi cn dng nhng cp thanh ghi 8 bits to thnh 1 thanh ghi 16 bit, 2 thanh ghi 8 bits s c tn kt thc bng cc k t L v H trong L l thanh ghi cha 8 bits thp (LOW) v H l thanh ghi cha 8 bits cao (High) ca gi tr 16 bits m chng to thnh.
TCNT1H v TCNT1L (Timer/Counter Register): l 2 thanh ghi 8 bit to thnh thanh ghi 16 bits (TCNT1) cha gi tr vn hnh ca T/C1. C 2 thanh ghi ny cho php bn c v ghi gi tr mt cch trc tip. 2 thanh ghi c kt hp nh sau:
TCCR1A v TCCR1B (Timer/Counter Control Register): l 2 thanh ghi iu khin hot ng ca T/C1. Tt c cc mode hot ng ca T/C1 u c xc nh thng qua cc bit trong 2 thanh ghi ny. Tuy nhin, y khng phi l 2 byte cao v thp ca mt thanh ghi m l 2 thanh ghi hon ton c lp. Cc bit trong 2 thanh ghi ny bao gm cc bit chn mode hay chn dng sng (Waveform Generating Mode WGM), cc bit quy nh dng ng ra (Compare Output Match COM), cc bit chn gi tr chia prescaler cho xung nhp (Clock Select CS)Cu trc ca 2 thanh ghi c trnh by nh bn di.
Nhn chung thuc ht cch phi hp cc bit trong 2 thanh ghi TCCR1A v TCCR1B l tng i phc tp v T/C1 c rt nhiu mode hot ng, chng ta s kho st chng trong phn cc ch hot ng ca T/C1 bn di. y, trong thanh ghi TCCR1B c 3 bit kh quen thuc l CS10, CS11 v CS12. y l cc bit chn xung nhp cho T/C1 nh truong T/C0. Bng 2 s tm tt cc ch xung nhp trong T/C1. Bng 2: chc nng cc bit CS12, CS11 v CS10.
OCR1A v OCR1B (Ouput Compare Register A v B): c mt s khi nim mi m chng ta cn bit khi lm vic vi T/C1, mt trong s l Ouput Compare (sorry, I dont wanna translate it to Vietnamese). Trong lc T/C hot ng, gi tr thanh ghi TCNT1 tng, gi tr ny c lin tc so snh vi cc thanh ghi OCR1A v OCR1B (so snh c lp vi tng thanh ghi), vic so snh ny trn AVR gi l gi l Ouput Compare. Khi gi tr so snh bng nhau th 1 Match xy ra, khi mt ngt hoc 1 s thay i trn chn OC1A (hoc/v chn OC1B) xy ra (y l cch to PWM bi T/C1). Ti sao li c A v B? l v ngi thit k AVR mun m rng kh nng ng dng T/C1 cho bn. A v B i din cho 2 knh (channel) v B. Cng v iu ny m chng ta c th to 2 knh PWM bng T/C1. Tm li, c bn 2 thanh ghi ny cha cc gi tr so snh, chc nng v cc ch hot ng c th ca chng s c kho st trong cc phn sau.
ICR1 (InputCapture Register 1): khi nim mi th 2 ca T/C1 l Input Capture. Khi c 1 s kin trn chn ICP1 (chn 14 trn Atmega8), thanh ghi ICR1s capture gi tr ca thanh ghi m TCNT1. Mt ngt c th xy ra trong trng hp ny, v th Input Capture c th c dng cp nht gi tr TOP ca T/C1. TIMSK (Timer/Counter Interrupt Mask Register): cc b T/C trn AVR dng chung thanh ghi mt n ngt, v th TIMSK cng c dng quy nh ngt cho T/C1. C iu lc ny chng ta ch quan tm n cc bit t 2 n 5 ca TIMSK. C tt c 4 loi ngt trn T/C1 (nh li T/C0 ch c 1 loi ngt trn)
Bit 2 trong TIMSK l TOIE1, bit quy nh ngt trn cho thanh T/C1 (tng t trng hp ca T/C0). Bit 3, OCIE1B l bit cho php ngt khi c 1 Match xy ra trong vic so snh TCNT1 vi OCR1B. Bit 4, OCIE1A l bit cho php ngt khi c 1 Match xy ra trong vic so snh TCNT1 vi OCR1A. Bit 5, TICIE1 l bit cho php ngt trong trng hp Input Capture c dng. Cng vi vic set cc bit trn, bit I trong thanh ghi trng thi phi c set nu mun s dng ngt (xem li bi 3 v iu khin ngt).
TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c cc b T/C. Cc bit t 2 n 5 trong thanh ghi ny l cc c trng thi ca T/C1.
Cc mode hot ng: c tt c 5 ch hot ng chnh trn T/C1. Cc ch hot ng c bn c quy nh bi 4 bit Waveform Generation Mode (WGM13, WGM12, WGM11 WGM10) v mt s bit ph khc. 4 bit Waveform Generation Mode li c b tr nm trong 2 thanh ghi TCCR1A v TCCR1B (WGM13 l bit 4, WGM12 l bit 3 trong TCCR1B trong khi WGM11 l bit 1 v WGM10 l bit 0 trong thanh ghi TCCR1A) v th cn phi hp 2 thanh ghi TCCR1 trong lc iu khin T/C1. Cc ch hot ng ca T/C1 c tm tt trong bng sau 3: Bng 3: cc bit WGM v cc ch hot ng ca T/C1.
2.1 Normal mode (Ch thng). y l ch hot ng n gin nht ca T/C1. Trong ch ny, thanh ghi m TCNT1 c tng gi tr t 0 (BOTTOM) n 65535 hay 0xFFFF (TOP) v quay v 0. Ch ny hon ton ging cch m Timer0 hot ng ch c khc l gi tr m cao nht l 65535 thay v 255 nh trong timer0. Nhn vo bng 3, set T/C1 Normal mode chng ta cn set 4 bit WGM v 0, v 0 l gi tr mc nh ca cc thanh ghi nn thc t chng ta khng cn tc ng n cc bit WGM. Duy nht mt vic quan trng cn lm l set cc bit Clock Select (CS12, SC11, CS10) trong thanh ghi TCCR1B (xem thm bng 2). Bn c th tham kho v d ca Timer0. on code trong list 3 l 1 v d to 1 khong thi gian 10ms bng T/C1, normal mode: List 3. nh th 10ms vi T/C1. 1 #include <avr/io.h> 2 #include <avr/interrupt.h> 3 #include <util/delay.h> 4 5 int main(void){ 6 DDRB=0xFF; //PORTB la output PORT 7 PORTB=0x00; 8
9 TCCR1B=(1<CS10);// CS12=0, CS11=0, CS10=1: chon Prescaler =1 10 // thanh ghi TCCR1B duoc dung thay vi TCCR0 cua Timer0 11 TCNT1=55535; //gan gia tri khoi tao cho T/C1 12 TIMSK=(1<<TOIE1);//cho phep ngat khi co tran o T/C1 13 sei(); //set bit I cho phep ngat toan cuc 14 15 while (1){ //vng lp v tn 16 //do nothing 17 } 18 return 0; 19 } 20 //trinh phuc vu ngat tran T/C1 21 ISR (TIMER1_OVF_vect ){ 22 PORTB ^=1; //doi trang thai Bit PB0 23 TCNT1=55535; //gan gia tri khoi tao cho T/C1 24 } 2.2 Clear Timer on Compare Match (xa timer nu xy ra bng trong so snh)CTC. Mt cch gi tt ca ch hot ng ny l CTC, mt ch hot ng mi trn T/C1. Nhn vo bng 3 bn s thy c 2 mode CTC (mode 4 v mode 12). Ti ly v d mode 4 gii thch hot ng ca CTC. Khi bn set cc bit Waveform Generation Mode tuong ng: WGM13=0, WGM12=1, WGM11=0, WGM10=0 th mode 4 c chn. Trong mode ny, thanh ghi OCR1A cha gi tr TOP (gi tr so snh do ngi dng t), thanh ghi m TCNT1 tng t 0, khi TCNT1 bng gi tr cha trong OCR1A th mt Compare Match xy ra. Khi , mt ngt c th xy ra nu chng ta cho php ngt Compare Match (set bit OCF1A trong thanh ghi TIMSK ln 1). Mode ny cng tng i n gin, mt ng dng c bn ca mode ny l n gin ha vic m cc s kin bn ngoi. V d bn kt ni 1 sensor m s ngi i vo 1 cn phng vi chn T1 (chn counter source ca T/C1), bn mun rng c sau khi m 5 ngi th s thng bo 1 ln. List 4 l on code m t v d ny: List 4. Phi hp CTC vi m s kin. 1 #include <avr/io.h> 2 #include <avr/interrupt.h> 3 #include <util/delay.h> 4 volatile usigned char val=0; //khai bao 1 bien tam val va khoi tao =0 5 int main(void){ 6 DDRB=0xFF; //PORTB la output PORT 7 PORTB=0x00; 8 TCCR1B=(1<<WGM12)|(1<<CS12)|(1<<CS11); //xung nhip tu chan T1, canh xuong 9 OCR1A=4; //gan gia tri can so sanh 10 TIMSK=(1<OCIE1A);//cho phep ngat khi gia tri dem bang 4 11 sei(); //set bit I cho phep ngat toan cuc 12 13 while (1){ //vng lp v tn
14 //do nothing 15 } 16 return 0; 17 } 18 //trinh phuc vu ngat compare match 19 ISR (TIMER1_COMPA_vect){ 20 val++; 21 if (val==10) val=0; //gioi han bien val tu 0 den 9 22 PORTB =val; //xuat gia tri ra PORTB 23 } Ti ch gii thch nhng im mi trong List 4. Th nht l attribute volatile dng trc khai bo bin val, bin val c khai bo l unsigned char (8 bit, khng du) dng cha gi tr tm thi xut ra PORTB khi c ngt xy ra. iu c bit l t kha volatile t trc n, volatile l mt thuc tnh (attribute) ca b bin dch gccavr, n ni vi trnh dch rng bin val s c dng trong chng trnh chnh v c trong cc trnh phc v ngt. Nu bn mun cp nhp gi tr 1 bin ton cc trong cc trnh phc v ngt m bin khng c ch nh thuc tnh volatile trc th qu trnh cp nht tht bi. Mt cch d hiu hn, bn xem trnh ISR trong v d trn, c mi ln c ngt Compare Match xy ra, bin val c tng thm 1 (dng 21) sau kim tra iu kin bng 10 hay khng v cui cng l gn cho PORTB. Nu trong khai bo ca val (dng 4) chng ta khng ch nh volatile th gi tr xut ra PORTB s lun l 1 khi c ngt. Ch l iu ny ch ng it nht l vi phin bn WinAVR thng 12 nm 2007, cc phin bn sau c th khng cn dng volatile (ti s cp nht sau). Dng 8 set cc bit iu khin: TCCR1B=(1<<WGM12)|(1<<CS12)|(1<<CS11); bn thy ti ch set bit WGM12 trong 4 bit WGM v ti mun chn mode CTC 4 (xem bng 3). Hai bit CS12 v CS11 c set bng 1 trong khi CS10 c gi 0 chn xung clock l t bn ngoi, chn T1 (xem bng 2). Trong dng 10, OCR1A=4; l gi tr cn so snh, chng ta bit rng TCNT1 tng ln t 0, v th m 5 s kin th cn t gi tr so snh l 4 (0, 1, 2, 3, 4). Dng 11 set bit cho php ngt khi c Compare match xy ra (dng cho channel A). Mode 12 ca CTC (WGM13=1, WGM12=1, WGM11=0, WGM10=0) cng tng t mode 4 nhng ci khc l gi tr cn so snh c cha trong thanh ghi ICR1 (khng phi OCR1A hay OCR1B). Khi nu mun dng ngt th bn phi dng ngt Input capture. C th dng 8 trong list 4 i thnh: TCCR1B=(1<<WGM13)|( (1<<WGM12)|(1<<CS12)|(1<<CS11); dng 10: ICR1=4 v dng 20: ISR (TIMER1_CAPT_vect ){ Mt kh nng khc ca CTC l xut tn hiu xung vung trn chn OC1A (chn 15 trn Atmega8) bng cch set cc bit Compare Output Mode trong thanh ghi TCCR1A. Tuy nhin vic to cc tn hiu output trong mode CTC khng tht s th v. V vy chng ta s kho st cch to tn hiu output trong 1 ch chuyn nghip v th v hn, ch PWM.
Trc khi bt u lm vic vi cc ch PWM ti ngh cn thit gii thiu th no l PWM v nhc li cc khi nim gi tr m ca Timer1 (hay bt k timer no khc) trn AVR. Trc ht, PWM hay Pulse Width Modulation c hiu theo ngha ting Vit l xung iu rng l khi nim ch tn hiu xung m thng th chu k (Time period) ca n c c nh, duty cycle (thi thi gian tn hiu mc HIGH) ca n c th c thay i. Bn xem 1 v d v PWM trong hnh 5.
Hnh 5. V d v tn hiu PWM. To ra PWM tc l to ra nhng tn hiu xung m ta c th iu khin duty cycle (v c tn s ~ Time period nu cn thit). Timer 1 trsn Atmega8 l 1 module l tng to ra cc tn hiu dng ny. Nhng PWM dng lm g v cch m n c s dng nh th no? Ti ly mt v d nh trong hnh 6: mt ng c DC v mt switch button.
Hnh 6. Motor v switch. Nu nhn button th ng c hot ng, th button th ng c dng. Tuy nhin do tc nhn v th ca con ngi c hn, bn s thy ng c hot ng hi sng (ripple). iu g xy ra nu bn nhn v th button vi vn tc 5000 ln/giy. Cu tr li l tay bn s b gy v button s b hng (^^). 5000 ln/s l iu khng tng, tuy nhin nu bn lm c nh th th tng thi gian cho 1 ln nhn+th l 1:5000=0.0002s = 200us. C s khc bit no khng gia trng hp thi gian nhn = 150us, thi gian th 50us v trng hp thi gian nhn l 50us cn thi gian th l 150us. Bn s d dng tm cu tr li, trong trng hp 1 ng c s quay vi vn tc nhanh hn trng hp 2. l tng c bn s dng PWM iu khin vn tc
ng c (v iu khin nhiu th khc na). bin ci khng tng trn (5000 ln/s) thnh hin thc, chng ta s thay th ci button c kh kia bng 1 cng tc in t (electronics switch). Thng th cc chip MOSFET c dng lm cc kha in t. MOSFET thng c 3 chn G (gate), D (drain) v S (source). V d 1 MOSFET knh N trng thi thng thng 2 chn D v S ko c dng in chy qua, nu in p chn G ln hn chn S khong 3V tr ln th dng in c th chy t D sang S. hy xem cch m t tng ng 1 MOSFET vi 1 button trong hnh 7.
Hnh 7. MOSFET v button. Vic kch cc MOSFET c th thc hin bng cc tn hiu PWM. V th tng iu khin ng c trong hnh 6 c th c thc hin li thng qua PWM nh trong hnh 8.
Hnh 8. M hnh iu khin tc ng c bng PWM n gin. Nh vy l xong phn gii thiu v PWM, by gi chng ta sang cc khi nim s m trong Timer. Hnh 9 minh ha cch b tr cc s m trong Timer1 trn h trc m.
Hnh 9: cc mc gi tr ca T/C1. BOTTOM lun c c nh l 0 (gi tr nh nht), MAX lun l 0xFFFF (65535). TOP l gi tr nh do ngi dng nh ngha, gi tr ca TOP c th c c nh l 0xFF (255), 0x1FF (511), 0x3FF 91023) hoc nh ngha bi cc thanh ghi ICR1 hoc OCR1A. thc cht i vi ng dng PWM th TOP chnh l Time period ca PWM. Do mc ch s dng m c th chn TOP l cc gi tr c nh hay cc thanh ghi, ring vi ti, cho mc ch to tn hiu PWM ti chn TOP nh ngha bi thanh ghi ICR1. Ouput Compare l gi tr so snh ca b Timer. Trong ch PWM th Output Compare quy nh Duty cycle. Vi T/C1, Output Comapre l gi tr trong cc thanh ghi OCR1A v OCR1B. Do c 2 thanh ghi c lp A v B, tng ng chng ta c th to ra 2 tn hiu PWM trn 2 chn OC1A v OC1B bng T/C1. n lc chng ta tm hiu cch to PWM trn AVR. 2.3 Fast PWM (PWM tn s cao). Trong ch Fast PWM, 1 chu k c tnh trong 1 ln m t BOTTOM ln TOP (single-slope), v th m ch ny gi l Fast PWM (PWM nhanh). C tt c 5 mode trong Fast PWM tng ng vi 5 cch chn gi tr TOP khc nhau (tham kho bng 3). Vic xc lp ch hot ng cho Fast PWM thc hin thng qua 4 bit WGM v cc bit chn dng xung ng ra, Compare Output Mode trong thanh ghi TCCR1A, nhn li 2 thanh ghi TCCR1A v TCCR1B.
Ch cc bit COM1A1, COM1A0 v COM1B1, COM1B0 l cc bit chn dng tn hiu ra ca PWM (Compare Output Mode bits). COM1A1, COM1A0 dng cho knh A v COM1B1, COM1B0 dng cho knh B. Hy i chiu bng 4. Bng 4: m t cc bit COM trong ch fast PWM.
Ti s gii thch hot ng ca Fast PWM knh A thng qua 1 trng hp c th, mode 14 (WGM13=1, WGM12=1, WGM11=1, WGM10=0). Trong mode 14, gi tr TOP (cng l chu k ca PWM) c cha trong thanh ghi ICR1, khi hot ng thanh ghi TCNT1 tng gi tr t 0, gi s cc bit ph COM1A=1, COM1A0=0, lc ny trng thi ca chn OC1A (chn 15) l HIGH (5V), khi TCNT1 tng n bng gi tr ca thanh ghi OCR1A th chn OC1A c xa v mc LOW (0V), thanh ghi m TCNT1 vn tip tc tng n khi no n bng gi tr TOP cha trong thanh ghi ICR1 th TCNT1 t ng reset v 0 v chn OC1A tr v trng thi HIGH, ci ny gi l
Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP m bn thy trong hng 4 bng 4. Hnh 10 m t cch to xung PWM trn chn OC1A mode 14.
Hnh 10: Fast PMW mode 14. R rng chng ta c th iu khin c time period v duty cycle ca PWM bng 2 thanh ghi ICR1 v OCR1A. Thng thng gi tr ca ICR1 c tnh ton v gn c nh, gi tr ca OCR1A c thay i thc hin mc ch iu khin (nh thay i vn tc ng c). Ch l nu chng ta set cc bit ph ngc li: COM1A=0, COM1A0=1, th tn hiu PWM trn chn OC1A s c phn LOW t 0 n OCR1A v HIGH t OCR1A n ICR1, y gi l set OC1A/OC1B on Compare Match, clear OC1A/OC1B at TOP (ngc vi tn hiu trn hnh 10). Hot ng ca fast PWM knh B hon ton tng t, trong thanh ghi ICR1 cng cha TOP ca PWM knh B v thanh ghi ICR1B cha duty cycle. Nh vy 2 knh A v B c cng tn s hay Time period v duty cycle c iu khin c lp. Chn xut tn hiu PWM ca knh B l chn OC1B (chn 16 trn Atmega8). Cc mode 5, 6 v 7 ca Fast PWM hot ng hon ton tng t mode 14. im khc nhau c bn l gi tr TOP(Time period). Trong cc mode ny gi tr TOP khng do thanh thi ICR1 nh ngha m l cc hng s khng i. Vi mode 5, tc mode 8 bits, (WGM13=0, WGM12=1, WGM11=0, WGM10=1) gi tr TOP l 1 hng s, TOP = 255 (s 8 bits ln nht). Vi mode 6, tc mode 9 bits, (WGM13=0, WGM12=1, WGM11=1, WGM10=0) gi tr TOP l 1 hng s, TOP = 511 (s 9 bits ln nht). V vi mode 7, tc mode 10 bits, (WGM13=0, WGM12=1, WGM11=1, WGM10=1) TOP =1023 (s 10 bits ln nht). Mode 15 cng l Fast PWM trong TOP do OCR1A quy nh, v th m tn hiu ra knh A hu nh khng phi l 1 xung, n ch thay i trng thi trong 1 clock. Theo ti, s dng Fast PWM bn nn dng mode 14 c gii thch trn. Cc mode 5, 6, 7 cng c th dng nhng khng nn dng mode 15. Chng ta tin hnh vit 1 v d minh ha dng 2 knh ch fast PWM iu khin 2 ng c RC servo (gi tt l Servo). Mch in minh ha nh trong hnh 11.
Hnh 11: iu khin 2 RC servo bng PWM. Hai button c ni vi 2 ng ngt ngoi INT0 v INT1 iu khin gc xoay ca 2 Servo. Tn ca Servo trong phn mm Proteus l MOTOR-PWMSERVO. Trc khi vit code iu khin cc Servo, bn cn bit cch iu khin chng, ti gii thiu ngn gn nh sau: RC servo l mt t hp gm 1 ng c DC cng sut nh, hp gim tc v b iu khin gc quay. C 2 loi chnh l Servo thng v digital Servo, trong v d ny ti gii thiu Servo thng (ph bin). Servo thng c 3 dy, dy mu en l dy GND, dy l dy ngun (thng l 5V) v 1 dy trng hoc vng v dy iu khin (c mt s loi Servo c mu dy khc, bn cn tham kho datasheet ca chng). V cc Servo c sn mch iu khin gc quay bn trong nn chng ta khng cn bt c gii thut g m ch cn cp tn hiu PWM cho dy iu khin l Servo c th xoay n 1 v tr no (ch l Servo thng ch xoay na vng, iu khin servo l iu khin gc xoay ch khng phi iu khin cn tc xoay). Hnh 12 l hnh nh servo v cch iu khin servo.
Hnh 12. Servo v cch iu khin. Bn xem hnh 12b, iu khin servo bn cn cp cho dy iu khin mt tn hiu PWM c Time Period khong 20ms, duty cycle ca PWM s quyt nh gc xoay
ca servo. Vi Duty cycle l 1ms, servo xoay v v tr 0o, khi duty cycle =2ms, gc xoay s l 180o, t bn c th tnh c duty cycle cn thit khi bn mun servo xoay n 1 v tr bt k gia 0o v 180o. Sau khi hiu cch iu khin servo, chng ta c th d dng vit code iu khin chng, ch cn to cc xung PWM bng T/C1. on code cho v d ny c trnh by trong list 5. List 5. iu khin Servo bng PWM. 1 #include <avr/io.h> 2 #include <avr/interrupt.h> 3 4 int main(void){ 5 DDRB=0xFF; //PORTB la output PORT 6 PORTB=0x00; 7 8 MCUCR|=(1<<ISC11)|(1<<ISC01); //ngat canh xuong 9 GICR |=((1<<INT1)|(1<<INT0); //cho php 2 ngat hoat dong 10 11 TCCR1A=(1<<COM1A1)|(1<<COM1B1)|(1<<WGM11); 12 TCCR1B=(1<<WGM13)|(1<<WGM12)|(1<<CS10); 13 OCR1A=1000; //Duty cycle servo1=1000us=1ms (0 degree) 14 OCR1B=1500; //Duty cycle servo2=1500us=1.5ms (90 degree) 15 ICR1=20000; //Time period = 20000us=20ms 16 17 sei(); //set bit I cho phep ngat toan cuc 18 while (1){ //vng lp v tn 19 //do nothing 20 } 21 return 0; 22 } 23 24 //trinh phuc vu ngat ngoai 25 ISR (INT0_vect ){ 26 if (OCR1A==1000) OCR1A=1500; //thay doi goc xoay servo1 den 90 do 27 else OCR1A = 1000; // thay doi goc xoay servo1 den 0 do 28 } 29 ISR (INT1_vect ){ 30 if (OCR1B==1000) OCR1B=1500; //thay doi goc xoay servo1 den 90 do 31 else OCR1B = 1000; // thay doi goc xoay servo1 den 0 do 32 } Vi v d ny ti ch cn gii thch cc dng t 11 n 15 lin quan n vic xc lp ch hot ng Fast PWM mode 14 inverse, phn cn li bn c t i chiu vi cc bi trc. Dng 11 v 12 thc hin set cc bit iu khin Timer1, trc ht l cc bit COM. Bn thy ti ch set 2 bit COM1A1 v COM1B1: (1<<COM1A1)|(1<<COM1B1). Hai bit COM1A0 v COM1B0 khng set tc mc nh bng 0. i chiu vi bng 4 bn thy chng ta s dng Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP cho tt c 2 knh A v B. Chng ta set 3
bit WGM13, WGM12 (thanh ghi TCCR1B, dng 12) v WGM11 (thanh ghi TCCR1A, dng 11) nh th thu c t hp (WGM13=1, WGM12=1, WGM11=1, WGM10=0) tc l mode 14 c chn (bng 3). Cn li chng ta set bit CS10 khai bo rng ngun xung clock cho Timer1 bng clock cho vi iu khin (prescaler=1) tc l 1us trong tng hp f=1Mhz. (nu bn dng cc trnh bin dch khc khng h tr nh ngha tn cc bit th 2 dng 11 v 12 tng ng: TCCR1A=0xA2; TCCR1B=0x19). Dng 15 chng ta khai nhp gi tr cho ICR1 cng l Time period cho PWM, ICR1=20000 chng ta thu c Time period =20000 us = 20ms tha yu cu ca servo. Hai dng 13 v 14 khai bo gi tr ban u ca cc duty cycle ca 2 knh PWM, cc gi tr ny nh v tr gc xoay ca cc servo. Trong 2 trnh phc v ngt, cc gi tr ny c thay i khi cc button c nhn. 2.3 Phase correct PWM (PWM vi pha chnh xc). Phase correct PWM cung cp mt ch to xung PWM c phn gii cao (high resolution) nn c gi l Phase correct PWM. Tng t Fast PWM, cng c 5 mode hot ng thuc Phase correct PWM l cc mode 1, 2, 3, 10 v 11 (xem bng 3). Nm mode ny tng ng cc mode 5, 6, 7, 14 v 15 ca fast PWM. V cch iu khin, Phase correct hu nh ging fast PWM, ngha l nu bn bit cch s dng cc mode ca fast PWM th bn s hon ton iu khin c Phase correct PWM. Khc nhau c bn ca 2 ch ny l trong cch hot ng, nu Fast PWM c chu k hot ng trong 1 single-slope (mt sn) th Phase correct PWM li dual-slope (hai sn). Ly v d mode 10 ca Phase correct PWM tng ng vi mode 14 ca Fast PWM, trong mode ny thanh ghi ICR1 cha TOP v OCR1A (hoc OCR1B i vi knh B) cha gi tr so snh. Khi hot ng, thanh ghi TCNT1 tng t 0, khi TCNT1 bng vi OCR1A th chn OC1A c xa xung mc LOW (ti ang ni trng hp COM1A1=1, COM1A0=0), TCNT1 tip tc tng n TOP, khi TCNT1=TOP th TCNT1 KHNG c t ng reset v 0 nh trng hp Fast PWM m TCNT1 bt u m ngc, tc gim tng gi tr t TOP v 0. Trong lc TCNT1 gim, n 1 lc n s bng gi tr ca OCR1A ln th 2, v ln ny, chn OC1A c set ln mc HIGH, TCNT1 tip tc gim n 0 th 1 chu k hon tt. R rng 1 chu k l qu trnh m trong 2 sn nn ta gi Phase correct PWM l dual-slope. Cng v tnh cht dual-slope m tn hiu PWM trong ch ny c tnh i xng, thch hp cho cc ng dng iu khin ng c. Hnh 13 m t cch m Phase correct PWM hot ng tron mode 10 vi ng ra o (COM1A1=1, COM1A0=0).
Hnh 13. Phase correct PWM mode 10.
Vic vit code cho ch Phase correct PWM gn nh tng t fast PWM, bn ch cn thay i t hp cc bit WGM da theo bng 3 v sau nhp cc gi tr ph hp cho ICR1 v ORC1A, OCR1B l c. 2.3 Phase correct and frequency correct PWM. Ch ny c 2 mode l 8 v 9. V hu ht cc phng din, 2 mode ny ging vi 2 mode 10 v 11 ca Phase correct PWM. Ci khc nhau duy nht l thi im m thanh ghi OCR1A v OCR1B c cp nht d liu nu c s thay i. Vic ny, nhn chung khng nh hng n hu ht ngi dng PWM iu khin. Bn s rt kh thy s khc bit nu bn khng phi ang vit 1 ng dng m sai s trong 1 micro giy l iu t hi. V th ti khng cp chi tit ch ny, bn c c th tham kho datasheet ca chip hiu r hn nu cn thit. Ngoi ra trn chip atmega8 cn c b timer2 8 bits c PWM v asynchronous operation. V mt chc nng timer2 ging nh phin bn 8 bit ca timer1 ( phn gii thp hn nhng c cng ch v phng thc hot ng). im khc bit v cng l im c bit ca Timer2 l kh nng hot ng khng ng b vi chip, n ging nh vic bn tch timer2 ra thnh 1 chip timer ring, v th cn cung cp 1 ngun xung clock khc cho timer ny (1 thch anh khc). Ch ny c th c dng calip (calibrate), canh chnh sai s v b cho ngun xung clock chnh trn chip.
Bi 5 - Giao tip UART

Ni dung 1. Gii thiu. 2. Truyn thng ni tip khng ng b. 3. Truyn thng ni tip khng ng b vi AVR (UART). 1. Thanh ghi. 2. S dng UART. Download v d Cc bi cn tham kho trc Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus.
I. Gii thiu.
Bi ny gip cc bn bit cch s dng cch truyn thng ni tip UART trn AVR. Cng c chnh cng l 2 b phn mm quen thuc WinAVR v Proteus nhng trong bi ny (v cc bi sau na) chng ta s s dng chip Atmega32 lm chip minh ha. V c bn vic thay i chip minh ha khng nh hng ln n tnh mch lc ca lot bi v s khc bit ca hai chip Atmega8 v Atmega32 l khng ng k. Tuy nhin, nu c s khc bit ln phn no ti s k ra cho bn tin so snh. Sau bi ny, ti hy vng bn c th hiu v thc hin c:

Nguyn l truyn thng ni tip ng b v khng ng b. Module truyn thng ni tip USART trn AVR. Truyn thng a x l bng UART.
II. Truyn thng ni tip khng ng b. Thut ng USART trong ting anh l vit tt ca cm t: Universal Synchronous & Asynchronous serial Reveiver and Transmitter, ngha l b truyn nhn ni tip ng b v khng ng b. Cn ch rng khi nim USART (hay UART nu ch ni n b truyn nhn khng ng b) thng ch thit b phn cng (device, hardware), khng phi ch mt chun giao tip. USART hay UART cn phi kt hp vi mt thit b chuyn i mc in p to ra mt chun giao tip no . V d, chun RS232 (hay COM) trn cc my tnh c nhn l s kt hp ca chip UART v chip chuyn i mc in p. Tn hiu t chip UART thng theo mc TTL: mc logic high l 5, mc low l 0V. Trong khi , tn hiu theo chun RS232 trn my tnh c nhn thng l -12V cho mc logic high v +12 cho mc low (tham kho hnh 1). Ch l cc gii thch trong ti liu ny theo mc logic TTL ca USART, khng theo RS232.
Hnh 1. Tn hiu tng ng ca UART v RS232. Truyn thng ni tip: gi s bn ang xy dng mt ng dng phc tp cn s dng nhiu vi iu khin (hoc vi iu khin v my tnh) kt ni vi nhau. Trong qu trnh lm vic cc vi iu khin cn trao i d liu cho nhau, v d tnh hung Master truyn lnh cho Slaver hoc Slaver gi tn hiu thu thp c v Master x lGi s d liu cn trao i l cc m c chiu di 8 bits, bn c th s ngh n cch kt ni n gin nht l kt ni 1 PORT (8 bit) ca mi vi iu khin vi nhau, mi line trn PORT s chu trch nhim truyn/nhn 1 bit d liu. y gi l cch giao tip song song, cch ny l cch n gin nht v d liu c xut v nhn trc tip khng thng qua bt k mt gii thut bin i no v v th tc truyn cng rt nhanh. Tuy nhin, nh bn thy, nhc im ca cch truyn ny l s ng truyn qu nhiu, bn hy tng tng nu d liu ca bn c gi tr cng ln th s ng truyn cng s nhiu thm. H thng truyn thng song song thng rt cng knh v v th km hiu qu. Truyn thng ni tip s gii quyt vn ny, trong tuyn thng ni tip d liu c truyn tng bit trn 1 (hoc mt t) ng truyn. V l do ny, cho d d liu ca bn c ln n u bn cng ch dng rt t ng truyn. Hnh 2 m t s so snh gia 2 cch truyn song song v ni tip trong vic truyn con s 187 thp phn (tc 10111011 nh phn).
Hnh 2. Truyn 8 bit theo phng php song song v ni tip. Mt hn ch rt d nhn thy khi truyn ni tip so vi song song l tc truyn v chnh xc ca d liu khi truyn v nhn. V d liu cn c chia nh thnh tng bit khi truyn/nhn, tc truyn s b gim. Mt khc, m bo tnh chnh xc ca d liu, b truyn v b nhn cn c nhng tha hip hay nhng tiu chun nht nh. Phn tip theo trong chng ny gii thiu cc tiu chun trong truyn thng ni tip khng ng b. Khi nim ng b ch s bo trc trong qu trnh truyn. Ly v d thit b 1 (tb1) kt vi vi thit b 2 (tb2) bi 2 ng, mt ng d liu v 1 ng xung nhp. C mi ln tb1 mun send 1 bit d liu, tb1 iu khin ng xung nhp chuyn t mc thp ln mc cao bo cho tb2 sn sng nhn mt bit. Bng cch bo trc ny tt c cc bit d liu c th truyn/nhn d dng vi t ri ro trong qu trnh truyn. Tuy nhin, cch truyn ny i hi t nht 2 ng truyn cho 1 qu trnh (send or receive). Giao tip gia my tnh v cc bn phm (tr bn phm kt ni theo chun USB) l mt v d ca cch truyn thng ni tip ng b. Khc vi cch truyn ng b, truyn thng khng ng b ch cn mt ng truyn cho mt qu trnh. Khung d liu c chun ha bi cc thit b nn khng cn ng xung nhp bo trc d liu n. V d 2 thit b ang giao tip vi nhau theo phng php ny, chng c tha thun vi nhau rng c 1ms th s c 1 bit d liu truyn n, nh th thit b nhn ch cn kim tra v c ng truyn mi mili-giy c cc bit d liu v sau kt hp chng li thnh d liu c ngha. Truyn thng ni tip khng ng b v th hiu qu hn truyn thng ng b (khng cn nhiu lines truyn). Tuy nhin, qu trnh truyn thnh cng th vic tun th cc tiu chun truyn l ht sc quan trng. Chng ta s bt u tm hiu cc khi nim quan trng trong phng php truyn thng ny. Baud rate (tc Baud): nh trong v d trn v vic truyn 1 bit trong 1ms, bn thy rng vic truyn v nhn khng ng b xy ra thnh cng th cc thit b tham gia phi thng nht nhau v khong thi dnh cho 1 bit truyn, hay ni cch khc tc truyn phi c ci t nh nhau trc, tc ny gi l tc Baud. Theo nh ngha, tc baud l s bit truyn trong 1 giy. V d nu tc baud c t l 19200 th thi gian dnh cho 1 bit truyn l 1/19200 ~ 52.083us. Frame (khung truyn): do truyn thng ni tip m nht l ni tip khng ng b rt d mt hoc sai lch d liu, qu trnh truyn thng theo kiu ny phi tun theo mt s quy cch nht nh. Bn cnh tc baud, khung truyn l mt yu tc quan trng to nn s thnh cng khi truyn v nhn. Khung truyn bao gm cc quy nh v s bit trong mi ln truyn, cc bit bo nh bit Start v bit Stop, cc bit kim tra nh Parity, ngoi ra s lng cc bit trong mt data cng c quy nh bi khung truyn. Hnh 1 l mt v d ca mt khung truyn theo UART, khung truyn ny c bt u bng mt start bit, tip theo l 8 bit data, sau l 1 bit parity dng kim tra d liu v cui cng l 2 bits stop. Start bit: start l bit u tin c truyn trong mt frame truyn, bit ny c chc nng bo cho thit b nhn bit rng c mt gi d liu sp c truyn ti. module USART trong AVR, ng truyn lun trng thi cao khi ngh (Idle), nu mt chip AVR mun thc hin vic truyn d liu n s gi mt bit start bng cch ko
ng truyn xung mc 0. Nh vy, vi AVR bit start l mang gi tr 0 v c gi tr in p 0V (vi chun RS232 gi tr in p ca bit start l ngc li). start l bit bt buc phi c trong khung truyn. Data: data hay d liu cn truyn l thng tin chnh m chng ta cn gi v nhn. Data khng nht thit phi l gi 8 bit, vi AVR bn c th quy nh s lng bit ca data l 5, 6, 7, 8 hoc 9 (tng t cho hu ht cc thit b h tr UART khc). Trong truyn thng ni tip UART, bit c nh hng nh nht (LSB Least Significant Bit, bit bn phi) ca data s c truyn trc v cui cng l bit c nh hng ln nht (MSB Most Significant Bit, bit bn tri). Parity bit: parity l bit dng kim tra d liu truyn ng khng (mt cch tng i). C 2 loi parity l parity chn (even parity) v parity l (odd parity). Parity chn ngha l s lng s 1 trong d liu bao gm bit parity lun l s chn. Ngc li tng s lng cc s 1 trong parity l lun l s l. V d, nu d liu ca bn l 10111011 nh phn, c tt c 6 s 1 trong d liu ny, nu parity chn c dng, bit parity s mang gi tr 0 m bo tng cc s 1 l s chn (6 s 1). Nu parity l c yu cu th gi tr ca parity bit l 1. Hnh 1 m t v d ny vi parity chn c s dng. Parity bit khng phi l bit bt buc v v th chng ta c th loi bit ny khi khung truyn (cc v d trong bi ny ti khng dng bit parity). Stop bits: stop bits l mt hoc cc bit bo cho thit b nhn rng mt gi d liu c gi xong. Sau khi nhn c stop bits, thit b nhn s tin hnh kim tra khung truyn m bo tnh chnh xc ca d liu. Stop bits l cc bits bt buc xut hin trong khung truyn, trong AVR USART c th l 1 hoc 2 bits (Trong cc thit b khc Stop bits c th l 2.5 bits). Trong v d hnh 1, c 2 stop bits c dng cho khung truyn.Gi tr ca stop bit lun l gi tr ngh (Idle) v l ngc vi gi tr ca start bit, gi tr stop bit trong AVR lun l mc cao (5V). (Ch v gi : khung truyn ph bin nht l : start bit+ 8 bit data+1 stop bit) Sau khi nm bt cc khi nim v truyn thng ni tip, phn tip theo chng ta s kho st cch thc hin phng php truyn thng ny trn chip AVR (c th l chip Atmega32). III. Truyn thng ni tip khng ng b vi AVR (UART). Vi iu khin Atmega32 c 1 module truyn thng ni tip USART. C 3 chn chnh lin quan n module ny l chn xung nhp - XCK (chn s 1), chn truyn d liu TxD (Transmitted Data) v chn nhn d liu RxD (Reveived Data). Trong chn XCK ch c s dng nh l chn pht hoc nhn xung gi nhp trong ch truyn ng b. Tuy nhin bi ny chng ta khng kho st ch truyn thng ng b, v th bn ch cn quan tm n 2 chn TxD v RxD. V cc chn truyn/nhn d liu ch m nhim 1 chc nng c lp (hoc l truyn, hoc l nhn), kt ni cc chip AVR vi nhau (hoc kt ni AVR vi thit b h tr UART khc) bn phi u cho 2 chn ny. TxD ca thit b th nht kt ni vi RxD ca thit b 2 v ngc li. Module USART trn chip Atmega32 hot ng song cng (Full Duplex Operation), ngha l qu trnh truyn v nhn d liu c th xy ra ng thi.
1. Thanh ghi: Cng nh cc thit b khc trn AVR, tt c hot ng v trng thi ca module USART c iu khin v quan st thng qua cc thanh ghi trong vng nh I/O. C 5 thanh ghi c thit k ring cho hot ng v iu khin ca USART, l:
UDR: hay thanh ghi d liu, l 1 thanh ghi 8 bit cha gi tr nhn c v pht i ca USART. Thc cht thanh ghi ny c th coi nh 2 thanh ghi TXB (Transmit data Buffer) v RXB (Reveive data Buffer) c chung a ch. c UDR thu c gi tr thanh ghi m d liu nhn, vit gi tr vo UDR tng ng t gi tr vo thanh ghi m pht, chun b gi i. Ch trong cc khung truyn s dng 5, 6 hoc 7 bit d liu, cc bit cao ca thanh ghi UDR s khng c s dng
UCSRA (USART Control and Status Register A): l 1 trong 3 thanh ghi iu khin hot ng ca module USART.
Thanh ghi UCSRA ch yu cha cc bit trng thi nh bit bo qu trnh nhn kt thc (RXC), truyn kt thc (TXC), bo thanh ghi d liu trng (UDRE), khung truyn c li (FE), d liu trn (DOR), kim tra parity c li (PE)Bn ch mt s bit quan trng ca thanh ghi ny: * UDRE (USART Data Register Empty) khi bit by bng 1 ngha l thanh ghi d liu UDR ang trng v sn sng cho mt nhim v truyn hay nhn tip theo. V th nu bn mun truyn d liu u tin bn phi kim tra xem bit UDRE c bng 1 hay khng, sau khi chc chn rng UDRE=1 hy vit d liu vo thanh ghi UDR truyn i. * U2X l bit ch nh gp i tc truyn, khi bit ny c set ln 1, tc truyn so cao gp 2 ln so vi khi bit ny mang gi tr 0. * MPCM l bit chn ch hot ng a x l (multi-processor).
UCSRB (USART Control and Status Register B): y l thanh ghi quan trng iu khin USART. V th chng ta s kho st chi tit tng bit ca thanh ghi ny.
* RXCIE (Receive Complete Interrupt Enable) l bit cho php ngt khi qu trnh nhn kt thc. Vic nhn d liu truyn bng phng php ni tip khng ng b thng c thc hin thng qua ngt, v th bit ny thng c set bng 1 khi USART c dung nhn d liu. * TXCIE (Transmit Complete Interrupt Enable) bit cho php ngt khi qu trnh truyn kt thc. * UDRIE (USART Data Register Empty Interrupt Enable) l bit cho php ngt khi thanh ghi d liu UDR trng. * RXEN (Receiver Enable) l mt bit quan trng iu khin b nhn ca USART, kch hot chc nng nhn d liu bn phi set bit ny ln 1. * TXEN (Transmitter Enable) l bit iu khin b pht. Set bit ny ln 1 bn s khi ng b pht ca USART. * UCSZ2 (Chracter size) bit ny kt hp vi 2 bit khc trong thanh ghi UCSRC quy nh di ca d liu truyn/nhn. Chng ta s kho st chi tit khi tm hiu thanh ghi UCSRC. * RXB8 (Receive Data Bit 8) gi l bit d liu 8. Bn nh li rng USART trong AVR c h tr truyn d liu c di ti a 9 bit, trong khi thanh ghi d liu l thanh ghi 8 bit. Do , khi c gi d liu 9 bit c nhn, 8 bit u s cha trong thanh ghi UDR, cn c 1 bit khc ng vai tr bit th chn, RXD8 l bit th chn ny. Bn ch l cc bit c nh s t 0, v th bit th chn s c ch s l 8, v l m bit ny c tn l RXD8 (khng phi RXD9). * TXB8 (Transmit Data Bit 8), tng t nh bit RXD8, bit TXB8 cng ng vai tr bit th 9 truyn thng, nhng bit ny c dung trong lc truyn d liu.
UCSRC (USART Control and Status Register C): thanh ghi ny ch yu quy nh khung truyn v ch truyn. Tuy nhin, c mt rc ri nho nh l thanh ghi ny li c cng a ch vi thanh ghi UBRRH (thanh ghi cha byte cao dng xc lp tc baud), ni mt cch khc 2 thanh ghi ny l 1. V th bit 7 trong thanh ghi ny, tc bit URSEL l bit chn thanh ghi. Khi URSEL=1, thanh ghi ny c chip AVR hiu l thanh ghi iu khin UCSRC, nhng nu bit URSEL=0 th thanh ghi UBRRH s c s dng.
Cc bit cn li trong thanh ghi UCSRC c m t nh sau: * UMSEL (USART Mode Select) l bit la chn gia 2 ch truyn thng ng b v khng ng b. Nu UMSEL=0, ch khng ng b c chn, ngc li nu UMSEL=1, ch ng b c kch hot. * Hai bit UPM1 v UPM0( Parity Mode) c dng quy nh kim tra pariry. Nu UPM1:0=00, parity khng c s dng (mode ny kh thng dng), UPM1:0=01
khng c s dng, UPM1:0=10 th parity chn c dng, UPM1:0=11 parity l c s dng (xem thm bng 1). Bng 1: chn kim tra parity.
* USBS (Stop bit Select), bit Stop trong khung truyn bng AVR USART c th l 1 hoc 2 bit, nu USBS=0 th Stop bit ch l 1 bit trong khi USBS=1 s c 2 Stop bit c dng. * Hai bit UCSZ1 v UCSZ2 (Character Size) kt hp vi bit UCSZ2 trong thanh ghi UCSRB to thnh 3 bit quy nh di d liu truyn. Bng 2 tm tt cc gi tr c th c ca t hp 3 bit ny v di d liu truyn tng ng. Bng 2: di d liu truyn.
* UCPOL (Clock Pority) l bit ch cc ca xung kch trong ch truyn thng ng b. nu UCPOL=0, d liu s thay i thay i cnh ln ca xung nhp, nu UCPOL=1, d liu thay i cnh xung xung nhp. Nu bn s dng ch truyn thng khng ng b, hy set bit ny bng 0..
UBRRL v UBRRH (USART Baud Rate Register): 2 thanh ghi thp v cao quy nh tc baud.
Nhc li l thanh ghi UBRRH dng chung a ch thanh ghi UCSRC, bn phi set bit ny bng 0 nu mun s dng thanh ghi UBRRH. Nh bn quan st trong hnh trn, ch c 4 bit thp ca UBRRH c dng, 4 bit ny kt hp vi 8 bit trong thanh ghi UBRRL to thnh thanh ghi 12 bit quy nh tc baud. Ch l nu bn vit gi tr vo thanh ghi UBRRL, tc baud s tc th c cp nht, v th bn phi vit gi tr vo thanh ghi UBRRH trc khi vit vo thanh ghi UBRRL.
Gi tr gn cho thanh ghi UBRR khng phi l tc baud, n ch c USART dng tnh tc baud. Bng 3 hng dn cch tnh tc baud da vo gi tr ca thanh ghi UBRR v ngc li, cch tnh gi tr cn thit gn cho thanh ghi UBRR khi bit tc baud. Bng 3: tnh tc baud.
Trong cc cng thc trong bng 3, fOSC l tc tn s xung nhp ca h thng (thch anh hay ngun xung ni). tin cho bn theo di, ti nh km bng v d cch t gi tr cho UBRR theo tc baud mu. Bng 4: mt s tc baud mu.
2. S dng UART:. Thng thng, s dng module USART trn AVR bn phi thc hin 3 vic quan trng, l: ci t tc baud (thanh ghi UBRR), nh dng khung truyn (UCSRB, UCSRC) v cui cng kch hot b truyn, b nhn, ngtNh cp, trong ti liu ny ti ch yu cp n phng php truyn thng khng ng b, vic xc lp cc thng s hot ng ch yu da trn ch ny. Trong hu ht cc ng dng, tc baud v khung truyn thng khng i, trong trng hp ny chng ta c th khi to trc tip USART phn u trong main v sau ch cn truyn hoc nhn d liu m khng cn thay i cc ci t. Tuy nhin, nu trng hp giao tip linh hot v d bn ang ch to mt thit b c kh nng giao tip vi mt thit b u cui khc (nh my tnh chng hn), lc ny bn nn cho php ngi dng thay i tc baud hoc cc thng s khc ph hp vi thit b u cui. i vi nhng ng dng kiu ny bn nn vit 1 chng trnh con khi ng USART v c th gi li nhiu ln khi cn thay i. Phn tip theo chng ta s vit mt s chng trnh v d minh ha cch s dng module truyn thng USART t n gin n phc tp. Cc v d s c thc hin cho chip Atmega32 vi gi s ngun xung nhp h thng l 8MHz. 2.1 Truyn d liu. Trc ht chng ta s thc hin mt v d rt n gin hiu cch khi ng USART v truyn cc gi d liu 8 bit. Mch in m phng trong hnh 3. Gi s chng ta mun nh dng cho khung truyn gm 1 bit start, 8 bit d liu, khng kim tra parity v 1 bit stop. Tc baud 57600 (57.6k). D liu cn truyn l cc gi tr lin tc ca bng m ASCII. on code trong list 1 trnh by cch thc hin v d ny. List 1. Khi ng v truyn d liu khng ng b bng USART
1 #include <avr/io.h> 2 #include <avr/delay.h> 3 4 //chuong trinh con phat du lieu 5 void uart_char_tx(unsigned char chr){ 6 while (bit_is_clear(UCSRA,UDRE)) {}; //cho den khi bit UDRE=1 7 UDR=chr; 8 } 9 10 int main(void){ 11 //set baud, 57.6k ung voi f=8Mhz, xem bang 70 trang 165, Atmega32 datasheet 12 UBRRH=0; 13 UBRRL=8; 14 15 //set khung truyen va kich hoat bo nhan du lieu 16 UCSRA=0x00; 17 UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0); 18 UCSRB=(1<<TXEN); 19 20 while(1){ 21 for (char i=32; i<128; i++){ 22 uart_char_tx(i); //phat du lieu 23 _delay_ms(100); 24 } 25 } 26 } Trc ht ti s gii thch cch khi ng USART trong cc dng code t 12 n 18. Nu bn xem li bng 3 trong trang 9 ca ti liu ny (hoc bng 70, trang 165 datasheet ca chip atmega32), ng vi tn s xung nhp 8Hhz, khng s dng ch nhn i tc (U2X=0), t c tc b baud 57600 th gi tr cn gn cho thanh ghi UBRR l 8 (xem ct 2, bng 3). Hai dng 12 v 13 trong list 1 thc hin gn 8 cho thanh ghi UBRR thng qua 2 thanh ghi UBRRH v UBRRL. Trong dng 16, thanh ghi UCSRA c gn bng 0. Nu bn xem li phn gii thch bn s thy thanh ghi UCSRA ch yu cha cc bit trng thi, ring 2 bit U2X v MPCM l 2 bit iu khin, 2 bit ny bng 0 ngha l chng ta khng s dng ch nhn i tc v khng s dng truyn thng a x l. Phn quan trng nht chnh l t gi tr cho 2 thanh ghi USCRB v UCSRC. Vi thanh ghi UCSRC (dng 17) trc ht chng ta phi set bit URSEL bo rng chng ta khng mun truy cp thanh ghi UBRRH m l thanh ghi UCSRC (2 thanh ghi ny c cng a ch), tip theo chng ta ch set 1 cho 2 bit UCSZ1 v UCSZ0, bn xem li bng 2 thy rng nu UCSZ1=1, UCSZ0=1 cng vi vic bit UCSZ2=0(nm trong thanh ghi UCSRB) th di d liu truyn c chn l 8 bit. Cc bit trong thanh ghi UCSRC khng c set s mc nh mang gi tr 0, bao gm UMSEL = 0 (ch truyn thng khng ng b), UPM1:0=00 ( khng s dng kim tra parity, xem bng 1), USBS=0 (1 bit stop) v UCPOL=0 (bit
ny khng s dng khi truyn khng ng b). Sau cng, trong dng 18, chng ta ch set bit TXEN =1 ngha l ch kch hot b pht d liu, cc thnh phn khc nh b nhn, cc ngtkhng c s dng trong v d ny. Trong cc bi trc ti gii thiu bn v trnh phc v ngt v trong phn ny ti s trnh by cch vit mt chng trnh con bng ngn ng C trong WinAVR, l on chng trnh uart_char_tx dng 5. Chng trnh con l 1 on code bao gm cc cu lnh cng thc hin mt nhim v chung c th no . Trong trng hp ny l nhim v truyn 1 tham s 8 bit ra ng TxD ca USART thng qua thanh ghi UDR. Nh trnh by trong phn m t bit UDRE ca thanh ghi UCSRA, qu trnh truyn ch c bt u khi bit UDRE bng 1, v th dng code 6 lm nhim v kim tra bit UDRE, cu lnh while (bit_is_clear(UCSRA,UDRE)) {}; c hiu l qu trnh lp s ln qun nu bit UDRE bng 0 (bit_is_clear). Khi bit UDRE bng 1 th dng code 7 s xut bin chr ra thanh ghi UDR cng l xut ra chn TxD ca module USART. Trong ngn ng C c 2 cch c bn vit chng trnh con. Vi cch 1 chng trnh con c khai bo v vit trc tip pha trc chng trnh chnh main nh cch m ti thc hin trong v d 1 ny. Cch vit ny hiu v thch hp cho cc on chng trnh con ngn nhng chng c th lm tng quan chng trnh ca bn tr nn rc ri khi c qu nhiu chng trnh con vit trc main. Bn c th khc phc nhc im ny bng cch t cc chng trnh con pha sau main nh cch m chng ta lm vi cc trnh phc v ngt. Nu theo ng quy cch ca ngn ng C, khi t chng trnh con sau main bn phi khai bo tn chng trnh pha trc main, nu bn t chng trnh con uart_char_tx pha sau main th phn trc main bn s t dng khai bo trc: void uart_char_tx(unsigned char chr);. Tuy WinAVR cho php bn b qua khai bo trc ny nhng ti khuyn bn nn vit ng cch to thi quen v cng nh d chuyn chng trnh sang cc trnh bin dch C khc sau ny nu cn thit. Phn cui cng trong on code l gi li chng trnh uart_char_tx truyn cc d liu l cc s t 32 n 127. thc hin m phng bng proteus bn hy v mt mch in n gin nh trong hnh 3. Chip Atmega32 c th c tm vi t kha mega32. Trong mch in m phng c mt thit b u cui o (Virtual Terminal) l mt thit b kt ni v hin th kt qu truyn thng khng ng b, chng ta dng kim tra d liu c truyn bng chip AVR. Bn c th tm thit b ny trong trong danh sch cc d c o (virtual instruments), nhn vo nt cng c v sau chn terminal trong danh sch chn thit b u cui o. Kt ni thit b o vi chip Atmega32 nh trong hnh 3, ch l phi u cho 2 chn TxD v RxD. Bn cnh vic gn chng trnh cho chip AVR, bn phi set thng s cho thit b o trc khi thc hin m phng. Hy m hp thoi edit component ca thit b o (bng cch right click ri left click trn thit b o). Theo mc nh thit b u cui c nh dng khung truyn l 1 bit start+8 bit d liu+1 bit stop tng t nh cch chng ta ci t cho AVR trong v d 1, v th bn ch cn thay i tc baud thnh 57600 trong hp thoi edit component l hon tt (xem hnh 4). Khi chy m phng, thit b u cui o s hin th cc k t ASCII ca cc s t 32 n 127.
Hnh 3. M phng v d 1.
Hnh 4. Ci t thng s cho thit b o. 2.2 Nhn d liu. Qu trnh nhn d liu ch xy ra khi bit RXEN trong thanh ghi UCSRB c set bng 1 v tt nhin chn nhn d liu RxD phi c ni vi mt ngun pht (chn TxD ca mt chip UART khc chng hn). Cc thng s truyn thng nh tc baud v khung truyn trong b nhn phi c ci t nh ca b pht. Nu khng c li
trong qu trnh truyn v nhn d liu, sau khi nhn d liu s c cha trong thanh ghi UDR v bit RXC (Reveice Complete) trong thanh ghi UCSRA s t ng c set ln 1. Sau khi thanh ghi UDR c c, bit RXC li t ng reset v 0 chun b cho qu trnh nhn d liu k tip. Nh th v c bn chng ta c 2 cch c d liu nhn v. Cch th nht l cch hi vng (polling), kim tra nu bit RXC = 1 th c gi tr thanh ghi UDR (v c c bit RXB8 trong thanh ghi UCSRB nu frame truyn 9 bit c dng). Cch th hai l s dng ngt nhn hon tt (Receive Complete Interrupt), bng cch set bit cho php ngt nhn hon tt, tc bit RXCIE trong thanh ghi UCSRB, v bit cho php ngt ton cc (bit I, xem li bi 3) th mt ngt s xy ra khi d liu c nhn v cha trong thanh ghi UDR, chng ta ch cn c gi tr ca thanh ghi UDR trong trnh phc v ngt l xong. Theo kinh nghim, s dng ngt l phng php tt nht cho a s cc trng hp nhn d liu UART, v chng ta khng cn quan tm thi im m d liu gi n, trnh lng ph thi gian dnh cho vic hi vng. V th trong phn tip theo ti s trnh by mt v d minh ha qu trnh nhn d liu bng phng php ngt. phc v cho v d ny, chng ta s kho st mt mch m phng gm 2 chip Atmega32 ni vi nhau qua cc ng TxD v RxD. Chip th l chip pht d liu, nhim v ca chip ny l pht chui d liu t 32 n 127 nh chip Atmega32 trong v d 1. Chn pht TxD ca chip 1 s c ni vi chn nhn RxD ca chip th 2 (chip th 2 c gi l chip nhn d liu). Chip th 2 sau khi nhn d liu s pht d liu ny ra chn TxD ca chnh n c th hin th ln thit b u cui o cho chng qua quan st v so snh kt qu. Bn xem mch in m phng trong hnh 5 hiu r hn. Chng ta s dng on code trong v d 1 cho chip th nht v th ch cn vit on code nhn v pht li d liu cho chip th hai. List 2 trnh by on code cho chip th hai.. List 2. Nhn d liu USART khng ng b bng phng php ngt.
1 #include <avr/io.h> 2 #include <avr/interrupt.h> 3 #include <util/delay.h> 4 //chuong trinh con phat du lieu 5 void uart_char_tx(unsigned char chr){ 6 while (bit_is_clear(UCSRA,UDRE)) {}; //cho den khi bit UDRE=1 7 UDR=chr; 8 } 9 volatile unsigned char u_Data; 10 11 int main(void){ 12 //set baud, 57.6k ung voi f=8Mhz, xem bang 70 trang 165, Atmega32 datasheet 13 UBRRH=0; 14 UBRRL=8; 15 //set khung truyen va kich hoat bo nhan du lieu 16 UCSRA=0x00; 17 UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0); 18 UCSRB=(1<<RXEN)|(1<<TXEN)|(1<<RXCIE);//cho phep ca 2 qua trinh nhan va//truyen
19 phep ngat sau khi nhan xong 20 sei(); //cho phep ngat toan cuc 21 22 while(1){ 23 } 24 } 25 ISR(SIG_UART_RECV){ //trinh phuc vu ngat USART hoan tat nhan 26 u_Data=UDR; 27 uart_char_tx(u_Data); 28 }
on code trong v d nhn v pht d liu khng khc on code trong v d 1 l my. dng th 3 ti include file header interrupt.h v chng ta s s dng ngt nhn d liu. Chng ta khai bo mt bin u_Data dng 8 bit khng du lu d liu nhn c, do bin ny s c truy cp trong trnh phc v ngt nn chng ta t attribute volatile (dng 9). im quan trng khi khi ng UART trong v d ny l dng code 18, nu trong v d 1 chng ta ch khi ng duy nht b pht bng cch set bit TXEN trong thanh ghi UCSRB (UCSRB=(1<<TXEN);) th trong v d ny chng ta set thm 2 bit cho php nhn RXEN v cho php ngt RXCIE trong thanh ghi UCSRB. Bit RXEN khi ng b nhn v bit RXCIE khi ng ch ngt khi d liu nhn trong UDR, tuy nhin c th s dng ngt, chng ta cn set them bit I trong thanh ghi trng thi bng dng code 20 (sei();). Phn quan trng nht trong on code trn l trnh phc ngt nhn d liu ISR. Khi d liu c nhn y trong UDR, trnh ngt ISR(SIG_UART_RECV) s c thc hin, chng ta s c gi tr va nhn c vo bin u_Data (dng 26) v sau pht gi tr ny ra chn TxD hin th ln thit b u cui o bng dng lnh 27. Phn mch in m phng c trnh by trong hnh 5. Chng trnh cho chip TRANSMITTER l chng trnh trong v d 1 v chng trnh cho chip RECEIVER l chng trnh trong on code trn. Bn phi set xung clock cho c 2 chip l 8MHz v set tc baud cho thit b u cui o l 56700. Nu khi chy m phng, thit b u cui hin th cc k t ASCII ca cc s t 32 n 127 nh trong hnh 5 th mi th c thc hin chnh xc.
Hnh 5. Truyn v nhn bng UART.
Bi 6 - Chuyn i ADC
Ni dung 1. Bn s i n u. 2. Chuyn i tn hiu tng t sang tn hiu s (ADC). 3. B chuyn i ADC trn AVR. Download v d Cc bi cn tham kho trc Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus.
I. Bn s i n u.
Bi hc ny, nh tn ca n, s gii thiu cch s dng b chuyn i tng t s (analog to digital converter - ADC). Cng c chnh cng l 2 b phn mm quen thuc WinAVR v Proteus. Sau bi ny, ti hy vng bn c th hiu v thc hin c: Nguyn l chuyn i AD. Chuyn i ADC n knh trn AVR. S dng chuyn i ADC n knh trn AVR, hin th s 4 digit bng LED 7 on. II. Chuyn i d liu tng t (analog) sang d liu s (digital). Trong cc ng dng o lng v iu khin bng vi iu khin b chuyn i tng t-s (ADC) l mt thnh phn rt quan trng. D liu trong th gii ca chng ta l cc d liu tng t (analog). V d nhit khng kh bui sng l 25oC v bui tra l 32oC, gia hai mc gi tr ny c v s cc gi tr lin tc m nhit phi i qua c th t mc 32oC t 25oC, i lng nhit nh th gi l mt i lng analog. Trong khi , r rng vi iu khin l mt thit b s (digital), cc gi tr m mt vi iu khin c th thao tc l cc con s ri rc v thc cht chng c to thnh t s kt hp ca hai mc 0 v 1. V d chng ta mun dng mt thanh ghi 8 bit trong vi iu khin lu li cc gi tr nhit t 0oC n 255 oC, nh chng ta bit, mt thanh ghi 8 bit c th cha ti a 256 (28) gi tr nguyn t 0 n 255, nh th cc mc nhit khng nguyn nh 28.123 oC s khng c ghi li. Ni cch khc, chng ta s ha (digitalize) mt d liu analog thnh mt d liu digital. Qu trnh s ha ny thng c thc hin bi mt thit b gi l b chuyn i tng t - s hay n gin l ADC (Analog to Digital Converter). C rt nhiu phng php chuyn i ADC, ti khng c nh gii thch c th cc nguyn l chuyn i ny trong bi hc v AVR, tuy nhin ti s gii thiu mt
cch chuyn i rt c bn v ph bin cc bn phn no nm c cch m mt b ADC lm vic. Phng php chuyn i m ti ni l phng php chuyn i trc tip (direct converting) hoc flash ADC. Cc b chuyn i ADC theo phng php ny c cu thnh t mt dy cc b so snh (nh opamp), cc b so snh c mc song song v c kt ni trc tip vi tn hiu analog cn chuyn i. Mt in p tham chiu (reference) v mt mch chia p c s dng to ra cc mc in p so snh khc nhau cho mi b so snh. Hnh 1 m t mt b chuyn i flash ADC c 4 b so snh, Vin l tn hiu analog cn chuyn i v gi tr sau chuyn i l cc con s to thnh t s kt hp cc mc nh phn trn cc chn Vo. Trong hnh 1, bn thy rng do anh hng ca mch chia p (cc in tr mc ni tip t in p +15V n ground), in p trn chn m (chn -) ca cc b so snh s khc nhau. Trong lc chuyn i, gi s in p Vin ln hn in p V- ca b so snh 1 (opamp pha thp nht trong mch) nhng li nh hn in p V- ca cc b so snh khc, khi ng Vo1 mc 1 v cc ng Vo khc mc 0, chng ta thu c mt kt qu s. Mt cch tng t, nu tng in p Vin ta thu c cc t hp s khc nhau. Vi mch in c 4 b so snh nh trong hnh 1, s c tt c 5 trng hp c th xy ra, hay ni theo cch khc in p analog Vin c chia thnh 5 mc s khc nhau. Tuy nhin, bn ch l cc ng Vo khng phi l cc bit ca tn hiu s ng ra, chng ch l i din t hp thnh tn hiu s ng ra, d hiu hn chng ta khng s dng c cc bit Vo trc tip m cn mt b gii m (decoder). Trong bng 1 ti trnh by kt qu sau khi gii m ng vi cc t hp ca cc ng Vo.
Hnh 1. Mch flash ADC vi 4 b so snh.
Bng 1 Gi tr s ng ra sau khi gii m.
phn gii (resolution): nh trong v d trn, nu mch in c 4 b so snh, ng ra digital s c 5 mc gi tr. Tng t nu mch in c 7 b so snh th s c 8 mc gi tr c th ng ra digital, khong cch gia cc mc tn hiu trong trng hp 8 mc s nh hn trng hp 4 mc. Ni cch khc, mch chuyn i vi 7 b so snh c gi tr digital ng ra mn hn khi ch c 4 b, mn cng cao tc phn gii (resolution) cng ln. Khi nim phn gii c dng ch s bit cn thit cha ht cc mc gi tr digital ng ra. Trong trng hp c 8 mc gi tr ng ra, chng ta cn 3 bit nh phn m ha ht cc gi tr ny, v th mch chuyn i ADC vi 7 b so snh s c phn gii l 3 bit. Mt cch tng qut, nu mt mch chuyn i ADC c phn gii n bit th s c 2n mc gi tr c th c ng ra digital. to ra mt mch chuyn i flash ADC c phn gii n bit, chng ta cn n 2n-1 b so snh, gi tr ny rt ln khi thit k b chuyn i ADC c phn gii cao, v th cc b chuyn i flash ADC thng c phn gii t hn 8 bit. phn gii lin quan mt thit n cht lng chuyn i ADC, vic la chn phn gii phi ph hp vi chnh xc yu cu v kh nng x l ca b iu khin. Trong 2 m t mt v d s ha mt hm sin analog thnh dng digital.
Hnh 2. Analog v digital ca hm sin.

in p tham chiu (reference voltage): Cng mt b chuyn i ADC nhng c ngi mun dng cho cc mc in p khc nhau, v d ngi A mun chuyn i in p trong khong 0-1V trong khi ngi B mun dng cho in p t 0V n 5V. R rng nu hai ngi ny dng 2 b chuyn i ADC u c kh nng chuyn i n in p 5V th ngi A ang ph phm tnh chnh xc ca thit b. Vn s c gii quyt bng mt i lng gi l in p tham chiu - Vref (reference voltage). in p tham chiu thng l gi tr in p ln nht m b ADC c th chuyn i. Trong cc b ADC, Vref thng l thng s c t bi ngi dng, n l in p ln nht m thit b c th chuyn i. V d, mt b ADC 10 bit ( phn gii) c Vref=3V, nu in p ng vo l 1V th gi tr s thu c sau khi chuyn i s l: 1023x(1/3)=314. Trong 1023 l gi tr ln nht m mt b ADC 10 bit c th to ra (1023=210-1). V in p tham chiu nh hng n chnh xc ca qu trnh chuyn i, chng ta cn tnh ton chn 1 in p tham chiu ph hp, khng c nh hn gi tr ln nht ca input nhng cng ng qu ln. II. Chuyn i ADC trn AVR. Chip AVR ATmega32 ca Atmel c tch hp sn cc b chuyn i ADC vi phn gii 10 bit. C tt c 8 knh n (cc chn ADC0 n ADC7), 16 t hp chuyn i dng so snh, trong c 2 knh so snh c th khuych i. B chuyn i ADC trn AVR khng hot ng theo nguyn l flash ADC m ti cp phn trn, ADC trong AVR l loi chuyn i xp x ln lt (successive approximation ADC). ADC trn AVR cn c nui bng ngun in p ring chn AVCC, gi tr in p cp cho AVCC khng c khc ngun nui chip (VCC) qu +/-0.3V. Nhiu (noise) l vn rt quan trng khi s dng cc b ADC, gim thiu sai s chuyn i do nhiu, ngun cp cho ADC cn phi c lc (filter) k cng. Mt cch n gin to ngun AVCC l dng mt mch LC kt ni t ngun VCC ca chip nh minh ha trong hnh 3, y l cch c gi bi nh sn xut AVR.
Hnh 3. To ngun AVCC t VCC. in p tham chiu cho ADC trn AVR c th c to bi 3 ngun: dng in p tham chiu ni 2.56V (c nh), dng in p AVCC hoc in p ngoi t trn chn VREF. Mt ln na, bn cn ch n noise khi t in p tham chiu, nu dng in p ngoi t trn chn VREF th in p ny phi c lc tht tt, nu dng in p tham chiu ni 2.56V hoc AVCC th chn VREF cn c ni vi mt t in. Vic chn in p tham chiu s c cp chi tit trong phn s dng ADC. Cc chn trn PORTA ca chip ATmega32 c dng cho b ADC, chn PA0 tng ng knh ADC0 v chn PA7 tng ng vi knh ADC7. 1. Thanh ghi. C 4 thanh trong b ADC trn AVR trong c 2 thanh ghi data cha d liu sau khi chuyn i, 2 thanh ghi iu khin v cha trng thi ca ADC.
- ADMUX (ADC Multiplexer Selection Register): l 1 thanh ghi 8 bit iu khin vic chn in p tham chiu, knh v ch hot ng ca ADC. Chc nng ca tng bit trn thanh ghi ny s c trnh by c th nh sau:
Bit 7:6- REFS1:0 (Reference Selection Bits): l cc bit chn in p tham chiu cho ADC, 1 trong 3 ngun in p tham chiu c th c chn l: in p ngoi t chn VREF, in p tham chiu ni 2.56V hoc in p AVCC. Bng 2 tm tt gi tr cc bit v in p tham chiu tng ng.
Bng 2: Chn in p tham chiu
Bit 5-ADLAR (ADC Left Adjust Result): l bit cho php hiu chnh tri kt qu chuyn i. S d c bit ny l v ADC trn AVR c phn gii 10 bit, ngha l kt qu thu c sau chuyn i l 1 s c di 10 bit (ti a 1023), AVR b tr 2 thanh ghi data 8 bit cha gi tr sau chuyn i. Nh th gi tr chuyn i s khng lp y 2 thanh ghi data, trong mt s trng hp ngi dng mun 10 bit kt qu nm lch v pha tri trong khi cng c trng hp ngi dng mun kt qu nm v pha phi. Bit ADLAR s quyt nh v tr ca 10 bit kt qu trong 16 bit ca 2 thanh ghi data. Nu ADLAR=0 kt qu s c hiu chnh v pha phi (thanh ghi ADCL cha trn 8 bit thp v thanh ghi ADCH cha 2 bit cao trong 10 bit kt qu), v nu ADLAR=1 th kt qu c hiu chnh tri (thanh ghi ADCH cha trn 8 bit cao nht, cc bit t 9 n 2, v thanh ADCL cha 2 bit thp nht trong 10 bit kt qu (bn xem hnh cch b tr 2 thanh ghi ADCL v ADCH bn di hiu r hn). Bits 4:0-MUX4:0 (Analog Channel and Gain Selection Bits): l 5 bit cho php chn knh, ch v c h s khuych i cho ADC. Do b ADC trn AVR c nhiu knh v cho php thc hin chuyn i ADC kiu so snh (so snh in p gia 2 chn analog) nn trc khi thc hin chuyn i, chng ta cn set cc bit MUX chn knh v ch cn s dng. Bng 3 tm tt cc ch hot ng ca ADC thng qua cc gi tr ca cc bit MUX. Trong bng ny, ng vi cc gi tr t 00000 n 00111 (nh phn), cc knh ADC c chn ch n knh (tn hiu input ly trc tip t cc chn analog v so snh vi 0V), gi tr t 01000 n 11101 tng ng vi ch chuyn i so snh.
Bng 3: Chn ch chuyn i.
- ADCSRA (ADC Control and Status RegisterA): l thanh ghi chnh iu khin hot ng v cha trng thi ca module ADC.
Tng bit ca thanh ghi ADCSRA c m t nh bn di:
Bit 7 - ADEN(ADC Enable): vit gi tr 1 vo bit ny tc bn cho php module ADC c s dng. Tuy nhin khi ADEN=1 khng c ngha l ADC hot ng ngay, bn cn set mt bit khc ln 1 bt u qu trnh chuyn i, l bit ADSC. Bit 6 - ADSC(ADC Start Conversion): set bit ny ln 1 l bt u khi ng qu trnh chuyn i. Trong sut qu trnh chuyn i, bit ADSC s c gi nguyn gi tr 1, khi qu trnh chuyn i kt thc (t ng), bit ny s c tr v 0. V vy bn khng cn v cng khng nn vit gi tr 0 vo bit ny bt k tnh hung no. thc hin mt chuyn i, thng thng chng ta s set bit ADEN=1 trc v sau set ADSC=1. Bit 4 ADIF(ADC Interrupt Flag): c bo ngt. Khi mt chuyn i kt thc, bit ny t ng c set ln 1, v th ngi dng cn kim tra gi tr bit ny trc khi thc hin c gi tr chuyn i m bo qu trnh chuyn i thc s hon tt. Bit 3 ADIE(ADC Interrupt Enable): bit cho php ngt, nu bit ny c set bng 1 v bit cho php ngt ton cc (bit I trong thanh ghi trng thi ca chip) c set, mt ngt s xy ra khi mt qu trnh chuyn i ADC kt thc v cc gi tr chuyn i c cp nht (cc gi tr chuyn i cha trong 2 thanh ghi ADCL v ADCH). Bit 2:0 ADPS2:0(ADC Prescaler Select Bits): cc bit chn h s chia xung nhp cho ADC. ADC, cng nh tt c cc module khc trn AVR, cn c gi nhp bng mt ngun xung clock. Xung nhp ny c ly t ngun xung chnh ca chip thng qua mt h s chia. Cc bit ADPS cho php ngi dng chn h s chia t ngun clock chnh n ADC. Tham kho bng 4 bit cch chn h s chia.
Bng 4: H s chia xung nhp cho ADC.
- ADCL v ADCH (ADC Data Register): 2 thanh ghi cha gi tr ca qu trnh chuyn i. Do module ADC trn AVR c phn gii ti a 10 bits nn cn 2 thanh ghi cha gi tr chuyn i. Tuy nhin tng s bt ca 2 thanh ghi 8 bit l 16, con s ny nhiu hn 10 bit ca kt qu chuyn i, v th chng ta c php chn cch ghi
10 bit kt qu vo 2 thanh ghi ny. Bit ADLAR trong thanh ghi ADMUX quy nh cch m kt qu c ghi vo. ADLAR=0:
ADLAR=1:
Thng thng, 2 thanh ghi data c sp xp theo nh dng ADLAR=0, ADCL cha 8 bit thp v 2 bit thp ca ADCH cha 2 bit cao nht ca gi tr thu c. Ch th t c gi tr t 2 thanh ghi ny, trnh c sai kt qu, bn cn c thanh ghi ADCL trc v ADCH sau, v sau khi ADCH c c, cc thanh ghi data c th c cp nht gi tr tip theo. - SFIOR(Special FunctionIO Register C): thanh ghi chc nng c bit, 3 bit cao trong thanh ghi ny quy nh ngun kch ADC nu ch Auto Trigger c s dng. l cc bit ADTS2:0 (Auto Trigger Source 2:0). Cc loi ngun kch c trnh by trong bng 5.
Bng 5: Ngun kch ADC trong ch Auto Trigger.
2. S dng ADC- Chuyn i n knh. Khi nim n knh c hiu l i lng cn chuyn i l cc in p t trc tip trn cc chn analog ca chip, gi tr in p ny c so snh vi 0V ca chip, hay ni mt cch khc, in p cn chuyn i v chip AVR c mass chung. Chng ta s minh ha cch s dng ADC trn AVR ch n knh bng v d c v hin th gi tr ADC trn cc LED 7 on. Nh minh ha trong hnh 4, chng ta s dng 4 LED hin th 4 ch s ca kt qu, do chng ta u bit ADC trn AVR c phn gii 10 bit nn kt qu chuyn i ti a l 1023, 4 LED l hin th kt qu ny. 4 chip 7447 c dng iu khin 4 LED, chng ta cn 16 ng xut d liu hin th ln 4 LED v th PORTB v PORTC s c dng cho mc ch ny. 4 bit cao ca PORTC(PC4:7) cha ch s hng nghn ca kt qu, 4 bit thp PC0:3 cha ch s hng trm, 4 bit cao ca PORTB(PB4:7) dng xut ch s hng chc v 4 bit PB0:3 dnh cho ch s hng n v. i lng cn chuyn i l in p trn chn ADC0 (knh 0 ca ADC, chn 0 trong PORTA chip ATmega32), in p c to ra bng mt bin tr RV1. Thay i gi tr bin tr, in p ri trn ADC0 thay i v c cp nht trc tip trn cc LED. Gi tr hin th trn LED khng phi l gi tr in p m l gi tr tng i sau khi chuyn i. Trong v d ny, ti s trnh by dng tng qut, vic c ADC v hin th LED c vit trong cc chng trnh con tng ng. Bng cch ny, cc bn c th d dng sa i v m rng v d sau ny.
Hnh 4. c ADC n knh.
List 1 trnh by on code minh ha c ADC n knh v hin th kt qu trn LED 7 on. List 1. c ADC n knh v hin th bng LED 7 on.
Ti tm thi chia on chng trnh thnh 4 phn, phn 1 l cc nh ngha (dng 4 n 7), phn 2 l chng trnh con c ADC n knh (dng 10 n 14), phn 3 l
chng trnh con hin th mt gi tr 4 ch s ln 4 LED 7 on (t dng 17 n 30) v phn 4 l chng trnh chnh. Chng ta s tm hiu theo tng phn. - Phn 1: ba dng 4, 5 v 6 chng ta nh ngha 3 bin i din tn ca 3 mode in p tham chiu c th dng cho ADC. Xem li bng 2 chng ta bit rng in p tham chiu c chn thng qua 2 bit REFS trong thanh ghi ADMUX, c 3 loi in p c th c chn. Bin AREF_MODE tng ng vi trng hp chng ta mun ly in p trn chn AREF lm in p tham chiu, i chiu bng 2 chng ta cn set 2 bit REFS bng 0, v dng 4 #define AREF_MODE 0 thc hin vic ny. Tng t, bin INT_MODE i din cho trng hp in p tham chiu ni 2.56V v c nh ngha cho php set 1 bit REFS ln 1 #define INT_MODE (1<<REFS1)|(1<<REFS0). Bin AVCC_MODE i din trng hp in p tham chiu ly t chn AVCC. Cui cng, bin ADC_VREF_TYPE c nh ngha l bin chn mode m chng ta thc s mun dng cho ADC, trong v d ny ti chn in p tham chiu ly t chn AVCC v th ti nh ngha #define ADC_VREF_TYPE AVCC_MODE. Bit ADC_VREF_TYPE s c gn cho thanh ghi ADMUX khi khi ng ADC trong chng trnh chnh. - Phn 2-chng trnh con c ADC n knh uint16_t read_adc(unsigned char adc_channel): tn chng trnh l read_adc v adc_channel l tham s cn truyn cho chng trnh con, tham s ny l ch s knh mun c (t knh 0 n knh 7). Gi tr tr v l mt s nguyn khng du 16 bit (kiu unsigned int ca C), tuy nhin trong v d ny ti dng kiu d liu uint16_t thay cho unsigned int, uint16_t l mt cch nh ngha kiu d liu nguyn khng du 16 bit ca ring th vin gcc-avr. Dng u tin ca on chng trnh con (dng 11) l khai bo knh mun c bng cch ghp gi tr knh cho thanh ghi ADMUX ADMUX |=adc_channel;. Xem li cu trc thanh ghi ADMUX, trong thanh ghi ny, ngoi cc bit chn ngun in p tham chiu REFS th 5 bit thp MUX4:0 cho php chn knh ADC cn c. Tham kho them bng 3 chng ta thy rng 8 gi tr u tin ca cc bit MUX4:0 (t 00000 n 00111 nh phn) tng ng vi 8 knh n ADC0:7. Chnh s sp xp ny cho php chng ta ghp trc tip gi tr knh mun c vo thanh ghi ADMUX thng qua dng lnh ADMUX |=adc_channel. Chng ta dng php OR | v chng ta ch mun thay i gi tr c bit MUX m khng mun lm nh hng n gi tr cc bit khc trong thanh ghi ADMUX khi chn knh. Mt ch quan trng l gi tr ca tham s adc_channel ch trong khong t 0 n 7 tng ng vi 8 ch c n knh ADC trong bng 3. Sau khi knh c chn, dng 12 set bit ADCS trong thanh ghi ADCSRA bt u qu trnh chuyn i ADCSRA|=(1<<ADSC);. Nh cp trong khi kho st chc nng ca bit ADIF trong thanh ghi ADCSRA, sau khi qu trnh chuyn i kt thc bit ADIF s c t ng set ln 1, v th dng code 13 c dng ch cho bit ny ln 1, tc ch cho qu trnh chuyn i kt thc. Cu lnh loop_until_bit_is_set(ADCSRA,ADIF); c hiu l lp cho n khi bit ADIF trong thanh ghi ADCSRA c set ln 1, lnh loop_until_bit_is_set ny c nh ngha sn trong th vin gcc-avr. Nu qu trnh chuyn i kt thc, kt qu chuyn i s c cha trong 2 thanh ghi ADCL v ADCH, 2 thanh ghi ny
c t ng gp thnh thanh ghi 16 bit ADCW (ADC WORD), dng 14 return ADCW tr v kt qu chuyn i. - Phn 3-chng trnh con hin th s c 4 ch s ln 4 LED 7 on void LED7_out(uint16_t val) : val l s cn hin th, chng ta khai bo 4 bin tm dvi, chuc, tram, nghin i din cho cc ch s n v, chc, trm v nghn dng 18. ng thi, mt bin tm temp_val c dng lu gi tr tm thi ca s val nh trong dng 19 temp_val=val;, cch lm ny nhm trnh thay i gi tr ca bn thn val trong qu trnh thao tc. Cc dng code t 21 n 26 thc hin qu trnh tch s val ra thnh 4 cc ch s hng n v, chc, trm v nghn. y ch l phng php i s thng thng nn ti s khng gii thch thm cho on ny. Hai dng 28 v 29 xut gi tr ra 4 LED 7 on. Bn LED 7 on c iu khin bi cc IC chuyn m 7447, gi tr input choc cc IC 7447 l cc s BCD 4 bit. V th, xut 4 ch s ra 4 LED thng qua 7447 chng ta cn 4x4=16 bit, trong v d ny ti dng PORTB v PORTC cho nhim v ny. Bn bit cao ca PORTC s cha ch s hng nghn, bn bit thp cha ch s hng trm, bn bit cao ca PORTB cha ch s hng chc v bn bit thp PORTB cha s n v. Dng code 28 PORTB=(chuc<<4)+dvi; xut 2 ch s chc v n v ra PORTB, trong hm chuc<<4 ngha l dch ch s hng chc sang tri 4 v tr a ch s ny ln 4 bit cao ca PORTB, sau cng ch s n v vo 4 bit thp v cui cng l xut ra PORTB. Tng t chng ta c th xut 2 ch s hng nghn v hng trm ra PORTC thng qua dng code 29 PORTC=(nghin<<4)+tram. - Phn 4-chng trnh chnh: do hu ht cc nhim v c thc hin trong cc on chng trnh con nn chng trnh chnh trong v d ny kh n gin. Hai dng code 32 v 33 set cc thng s cho ADC, dng 32 ADCSRA=(1<<ADEN)|(1<<ADPS2)|(1<<ADPS0); set cc bit trong thanh ghi iu khin ADCSRA, ADC c cho php hot ng bi bit ADEN, cc bit ADPS2:0 chn prescaler xung clock (xem li phn m t thanh ghi ADCSRA), trong v d ny ti chn prescaler = 32 (bn c th chn gi tr khc). Dng 33 ADMUX=ADC_VREF_TYPE; cho php chn in p tham chiu bng cch gn bin ADC_VREF_TYPE m chng ta nh ngha trong dng code 7 cho thanh ghi ADMUX. Bn cn ch l sau khi thc hin 2 dng code ny, ADC ch mi t th sn sng nhng vn cha hot ng, ADC s hot ng khi chng ta gi chng trnh con c adc. Trong vng lp while ca chng trnh chnh chng ta ln lt c gi tr ADC knh 0 bng cch gi chng trnh con read_adc(0) dng lnh 39 ADC_val=read_adc(0); sau hin th ra LED 7 on dng 40 LED7_out(ADC_val); v cui cng l delay 1 khong thi gian nh (100ms) trc khi lp li qu trnh c v hin th. M phng v d: To 1 project bng Programmer Notepad v type on code trn vo file source (xem phn to Project vi WinAVR). Bin dch v chy m phng vi mch in trong hnh 4. iu chnh gi tr bin tr RV1 thay i gi tr in p input ca ADC knh 0 v xem gi tr hin th trn cc LED 7 on. Hy thay i gi tr bin ADC_VREF_TYPE trong dng code 7 sang cc mode khc nh INT_MODE,
bin dch v m phng li chng trnh, quan st v so snh s khc nhau gia cc mode in p tham chiu. Bn s d dng nhn thy rng khi chn in p tham chiu ni 2.56V, khi tng bin tr n khong gia th kt qu chuyn i s l 1023(gi tr ln nht ca s 10 bit) v nu tip tc tng bin tr gi tr ny s khng thay i. iu ny c ngha l nu in p input ln hn in p tham chiu th kt qu chuyn i s l 1023. Phn chuyn i ADC ch so snh s c trnh by trong 1 dp khc phn ng dng.
Bi 7 - Giao tip SPI

Ni dung 1. 2. 3. Gii thiu. Chun truyn thng SPI. Truyn thng SPI trn AVR. Cc bi cn tham kho trc Cu trc AVR. AVRStudio. C cho AVR. M phng vi Proteus. Text LCD
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I. Gii thiu.
Bi ny gip cc bn bit cch s dng cch truyn thng ni tip ng b SPI. Cng c chnh cng l 2 b phn mm AVRStudio (+gcc-avr) v Proteus. Thc cht ngn ng lp trnh vn l gcc-avr nhng ti khng dng Programmer Notepad bit code nh thng thng, thay vo ti dng AVRStudio lm trnh bin tp, bn tham kho thm phn Lp trnh C bng AVRStudio trong bi hng dn s dng AVRStudio bit thm cch thc hin. Ti s dng chip ATmega32 lm minh ha. Sau bi ny, ti hy vng bn c th hiu v thc hin c:

Nguyn l truyn thng ni tip SPI. S dng module SPI trong AVR cc ch Master v Slave. II. Chun truyn thng SPI, SPI (Serial Peripheral Bus) l mt chun truyn thng ni tip tc cao do hang Motorola xut. y l kiu truyn thng Master-Slave, trong c 1 chip Master iu phi qu trnh tuyn thng v cc chip Slaves c iu khin bi Master v th truyn thng ch xy ra gia Master v Slave. SPI l mt cch truyn song cng (full duplex) ngha l ti cng mt thi im qu trnh truyn v nhn c th xy ra ng thi. SPI i khi c gi l chun truyn thng 4 dy v c 4 ng giao tip trong chun ny l SCK (Serial Clock), MISO (Master Input Slave Output), MOSI (Master Ouput Slave Input) v SS (Slave Select). Hnh 1 th hin mt kt SPI gia mt chip Master v 3 chip Slave thng qua 4 ng. SCK: Xung gi nhp cho giao tip SPI, v SPI l chun truyn ng b nn cn 1 ng gi nhp, mi nhp trn chn SCK bo 1 bit d liu n hoc i. y l im khc bit vi truyn thng khng ng b m chng ta bit trong chun UART. S
tn ti ca chn SCK gip qu trnh tuyn t b li v v th tc truyn ca SPI c th t rt cao. Xung nhp ch c to ra bi chip Master. MISO Master Input / Slave Output: nu l chip Master th y l ng Input cn nu l chip Slave th MISO li l Output. MISO ca Master v cc Slaves c ni trc tip vi nhau.. MOSI Master Output / Slave Input: nu l chip Master th y l ng Output cn nu l chip Slave th MOSI l Input. MOSI ca Master v cc Slaves c ni trc tip vi nhau. SS Slave Select: SS l ng chn Slave cn giap tip, trn cc chip Slave ng SS s mc cao khi khng lm vic. Nu chip Master ko ng SS ca mt Slave no xung mc thp th vic giao tip s xy ra gia Master v Slave . Ch c 1 ng SS trn mi Slave nhng c th c nhiu ng iu khin SS trn Master, ty thuc vo thit k ca ngi dng.
. Hnh 1. Giao din SPI. Hot ng: mi chip Master hay Slave c mt thanh ghi d liu 8 bits. C mi xung nhp do Master to ra trn ng gi nhp SCK, mt bit trong thanh ghi d liu ca Master c truyn qua Slave trn ng MOSI, ng thi mt bit trong thanh ghi d liu ca chip Slave cng c truyn qua Master trn ng MISO. Do 2 gi d liu trn 2 chip c gi qua li ng thi nn qu trnh truyn d liu ny c
gi l song cng. Hnh 2 m t qu trnh truyn 1 gi d liu thc hin bi module SPI trong AVR, bn tri l chip Master v bn phi l Slave.
Hnh 2. Truyn d liu SPI. Cc ca xung gi nhp, phase v cc ch hot ng: cc ca xung gi nhp (Clock Polarity) c gi tt l CPOL l khi nim dng ch trng thi ca chn SCK trng thi ngh. trng thi ngh (Idle), chn SCK c th c gi mc cao (CPOL=1) hoc thp (CPOL=0). Phase (CPHA) dng ch cch m d liu c ly mu (sample) theo xung gi nhp. D liu c th c ly mu cnh ln ca SCK (CPHA=0) hoc cnh xung (CPHA=1). S kt hp ca SPOL v CPHA lm nn 4 ch hot ng ca SPI. Nhn chung vic chn 1 trong 4 ch ny khng nh hng n cht lng truyn thng m ch ct sao cho c s tng thch gia Master v Slave. III. Truyn thng SPI trn AVR. Module SPI trong cc chip AVR hu nh hon ton ging vi chun SPI m t trong phn trn. V th, nu hiu cch truyn thng SPI th s khng qu kh thc hin vic truyn thng ny vi AVR. Phn bn di ti trnh by mt s im quan trng khi iu khin SPI trn AVR. Cc chn SPI: Cc chn giao tip SPI cng chnh l cc chn PORT thng thng, v th nu mun s dng SPI chng ta cn xc lp hng cho cc chn ny. Trn chip ATmega32, cc chn SPI nh sau: SCK PB7 (chn 8) MISO PB6 (chn 7) MOSI PB5 (chn 6) SS PB4 (chn 5) Khi chip AVR c s dng lm Slave, bn cn set cc chn SCK input, MOSI input, MISO output v SS input. Nu l Master th SCK output, MISO output, MOSI input v khi ny chn SS khng quan trng, chng ta c th dng chn ny iu khin SS ca Slaves hoc bt k chn PORT thng thng no. Thanh ghi: SPI trn AVR c vn hnh bi 3 thanh ghi bao gm thanh ghi iu khin SPCR , thanh ghi trng thi SPSR v thanh ghi d liu SPDR.
SPCR (SPI Control Register): l 1 thanh ghi 8 bit iu khin tt c hot ng ca SPI.
* Bit 7- SPIE (SPI Interrupt Enable) bit cho php ngt SPI. Nu bit ny c set bng 1 v bit I trong thanh ghi trng thi c set bng 1 (sei), 1 ngt s xy ra sau khi mt gi d liu c truyn hoc nhn. Chng ta nn dng ngt (nht l i vi chip Slave) khi truyn nhn d liu vi SPI. * Bit 6 SPE (SPI Enable). set bit ny ln 1 cho php b SPI hot ng. Nu SPIE=0 th module SPI dng hot ng. * Bit 5 DORD (Data Order) bit ny ch nh th t d liu cc bit c truyn v nhn trn cc ng MISO v MOSI,
khi DORD=0 bit c trng s ln nht ca d liu c truyn trc (MSB) ngc li khi DORD=1, bit LSB c truyn trc. Tht ra khi giao tip gia 2 AVR vi nhau, th t ny khng quan trng nhng phi m bo cc bit DORD ging nhau trn c Master v Slaves. bit ny ch nh th t d liu cc bit c truyn v nhn trn cc ng MISO v MOSI, khi DORD=0 bit c trng s ln nht ca d liu c truyn trc (MSB) ngc li khi DORD=1, bit LSB c truyn trc. Tht ra khi giao tip gia 2 AVR vi nhau, th t ny khng quan trng nhng phi m bo cc bit DORD ging nhau trn c Master v Slaves. * Bit 4 MSTR (Master/Slave Select) nu MSTR =1 th chip c nhn din l Master, ngc li MSTR=0 th chip l Slave.. * Bit 3 v 2 CPOL v CPHA y chnh l 2 bit xc lp cc ca xung gi nhp v cnh sample d liu m chng ta kho st trong phn u. S kt hp 2 bit ny to thnh 4 ch hot ng ca SPI. Mt ln na, chn ch no khng quan trng nhng phi m bo Master v Slave cng ch hot ng. V th c th 2 bit ny bng 0 trong tt c cc chip. Hnh 3 trnh by cch sample d liu trong 4 ch ca SPI trn AVR.
CPHA=0.
CPHA=1.
Hnh3 Cc ch hot ng ca SPI. * Bit 1:0 CPR1:0 hai bit ny kt hp vi bit SPI2X trong thanh ghi SPSR cho php chn tc giao tip SPI, tc ny c xc lp da trn tc ngun xung clock chia cho mt h s chia. Bng 1 tm tt cc tc m SPI trong AVR c th t. Thng thng, tc b ny khng c ln hn 1/4 tc xung nhp cho chip.
SPSR (SPI Status Register): l 1 thanh ghi trng thi ca module SPI. Trong thanh ghi ny ch c 3 bit c s dng. Bit 7 SPIF l c bo SPI, khi mt gi d liu c truyn hoc nhn t SPI, bit SPIF s t ng c set len 1. Bit 6 WCOL l bt bo va chm d liu (Write Colision), bit ny c AVR set ln 1 nu chng ta c tnh vit 1 gi d liu mi vo thanh ghi d liu SPDR trong khi qu trnh truyn nhn trc cha kt thc. Bit 0 SPI2X gi l bit nhn i tc truyn, bit ny kt hp vi 2 bit SPR1:0 trong thanh ghi iu khin SPCR xc lp tc cho SPI.
SPDR (SPI Data Register): l thanh ghi d liu ca SPI. Trn chip Master, ghi gi tr vo thanh ghi SPDR s kch qu trnh tuyn thng SPI. Trn chip Slave, d liu nhn c t Master s lu trong thanh ghi SPDR, d liu c lu sn trong SPDR s c truyn cho Master. S dng SPI trn AVR: SPI trn AVR hot ng khng khc nguyn l chung ca chun SPI l my. Vn hnh SPI trn AVR c thc hin da trn vic ghi v c 3 cc thanh ghi SPCR, SPSR v SPDR. Trc khi truyn nhn bng SPI chng ta cn khi ng SPI, qu trnh khi ng thng bao gm chn hng giao tip cho cc chn SPI, chn loi giao tip: Master hay Slave, chn ch SPI (SPOL, SPHA) v chn tc giao tip. Truyn thng SPI lun c khi xng bi chip Master, khi Master mun giao tip vi 1 Slave no , n s ko chn SS ca Slave xung mc thp (gi l chn a ch) v sau vit d liu cn truyn vo thanh ghi d liu SPDR, khi d liu va c vit vo SPDR xung gi nhp s c t ng to ra trn SCK v qu trnh truyn nhn bt u. i vi cc chip Slave, khi chn SS b ko xung n s sn sng cho qu trnh truyn nhn. Khi pht hin xung gi nhp trn SCK, Slave s bt u sample d liu n trn ng MOSI v gi d liu di trn MISO. minh ha cho cch truyn v nhn d liu SPI trn AVR, ti s thc hin mt v d truyn nhn 1 chiu vi 1 chip Master v 3 chip Slaves. Tt c cc chip c dng l ATmega32, chip Master s iu khin cc chip Slaves thng qua 3 ng chn chip PB0, PD1 v PD2. Cng vic thc hin trong v d ny nh sau: Master s ln lt chn 1 trong 3 chip Slaves v gi cc gi d liu tng ng n chng, chip Slave0 s nhn c cc con s t 0 n 80, Slave1 nhn 80 n 160 v Slave2 nhn d liu t 160 n 240. Cc Slave s hin th gi tr m mnh nhn c trn cc Text LCD kt ni vi PORTD mi Slave. S mch in v bng Proteus cho v d ny c trnh by trong hnh 4.
Hnh 4. M phng v d giao tip SPI trn AVR.
Trong bi ny, ti s dng phn mm AVRStudio kt hp vi gcc-avr trong WinAVR lp trnh bng ngn ng C cho AVR. Bn hy tham kho thm bi AVRStudio bit cch to 1 Project lp trnh C cho AVR bng AVRStudio. Hy to 2 Project ring, 1 Project c tn SPI_Master cho chip Master v 1 Project c tn SPI_Slave dng chung cho c 3 Slaves. Copy file myLCD.h dng cho iu khin Text LCD c to trong bi Text LCD vo c 2 th mc cha 2 Projects mi to. Vit on code trong list 0 vo file SPI_Master.c v on code trong list 1 vo file SPI_Slave.c.
List 1. on code cho SPI Master.
Ti s gii thch s lt mt s im chnh trong on code cho chip Master. Cc phn nh ngha t dng th 10 n dng 17 ch c tc dng lm cho chng trnh d c hiu hn v c tnh tng thch cao hn, v d nu bn mun s dng v d ny cho cc chip khc bn ch cn thay i cc nh ngha ny m khng phi thay i trong ni dung cc chng trnh con. Chng ta nh ngha chn PORTB iu khin cc ng chn chip SS ca Slave (gi l cc ng a ch), dng 18 nh ngha Slave(i) l th t chn trn PORT dng cho chip Slave th i. D hiu hn, ng SS trn Slave0 s c kt ni v iu khin bi chn 0 ca PORTB (chn PB0 v tng t cho cc Slaves cn li. Bin wData nh ngha trn dng 20 l mt mng 3 phn t cha cc con s 8 bits s truyn n cc Slaves. Chng trnh con void SPI_MasterInit(void): Chng trnh ny khi ng cho chip Master, vic khi ng trc ht l set hng cho cc chn SPI. i vi Master, cc chn to xung gi nhp SCK v chn truyn d liu MOSI cn c set Output nh trong dng 24, cc chn SPI cn li l input. Dng 25 gip ko in tr ko ln chn nhn d liu MISO ca Master. Dng lnh 26 SPCR=(1<<SPIE)|(1<<SPE)|(1<<MSTR)|(1<<CPHA)|(1<<SPR1)|(1<<SPR0); tht s khi ng SPI vi vic set bit SPIE: cho php ngt SPI=1, bit SPE=1 cho php SPI hot ng, MSTR=1 xc lp chip l chip Master. CPHA=1 tc chn SCK s mc thp khi SPI khng hot ng, trong khi CPOL=0 (khng set CPOL th mc nh l 0) th d liu s c sample (ly mu) cnh xung ca xung SCK. Cui cng c 2 bit SPR1 v SPR0 u c set ln 1, tc SPI s bng tc ngun cung nui chip chia cho 128 (xem bng 1). Dng code 29 set hng Output cho cc chn dng lm chn a ch chn chip Slaves (cc chn PB0, PB1, PB2), sau ko cc chn ny ln mc cao disable tt c cc Slaves (sau ny s kch hot sau). Chng trnh con void SPI_Transmit(uint8_t i, uint8_t data): chng trnh truyn d liu qua SPI ca chip Master, chng trnh c 2 tham s l a ch chip Slave (bin i) v d liu cn truyn (bin data). Trc khi truyn d liu, Master s thc hin vic chn Slave, dng 35 cbi(ADDRESS_PORT, Slave(i)); thc hin vic ny. Thc cht dng ny l ko chn i ca PORTB xung mc thp, cng l ko chn SS ca Slave xung mc thp. Dng 36 gn gi tr cn truyn cho thanh ghi d liu SPDR=data, sau khi gn gi tr cho SPDR, xung clock s t ng c Master to ra trn SCK, qu trnh truyn bt u. Qu trnh truyn kt thc th bit c SPIF trong thanh ghi trng thi SPSR c set ln 1, dng 36 thc hin vic ch bit c SPIF kt thc qu trnh truyn. Khi kt thc truyn 1 byte cho Slave, set chn SS ca Slave ln mc cao v hiu ha SPI, dng 37. Chng trnh chnh: chng trnh chnh cho chip Master SPI tng i n gin, trc ht chng ta cn gi chng trnh con khi ng SPI dng 43. Trong vng lp v tn while, ln lt gi cc gi tr n cc Slaves. Dng 46 gi chng trnh con gi gi tr bin wData[0] n Slave0, dng 50 truyn bin wData[1] cho Slave1 v dng 54 truyn bin wData[2] cho Slave2
List 2.on code cho Slave SPI.
on code trong list 2 l on code cho chip Slaves, ch dng 3 chng ta include file header interrupt.h v vic nhn d liu SPI ca SLave c thc hin bng ngt
SPI. Cc nh ngha bin trong cc dng code t 8 n 15 tng t nh trong chng trnh cho chip Master. Ti s tp trung gii thch cc im khc bit cho Slaves. Chng trnh con void SPI_SlaveInit(void): Chng trnh ny khi ng cho chip Slave, cng ging nh trng hp ca Master, vic khi ng trc ht l set hng cho cc chn SPI. i vi Slave, ch c chn truyn d liu MISO l cn c set Output nh trong dng 19, cc chn SPI cn li l input. Dng 20 gip ko in tr ko ln cc chn nhn d liu MOSI ca Slave, v chn chn Slave SS. Vic tip theo l ci t cc thanh ghi SPI nh trong dng lnh 21, SPCR=(1<<SPIE)|(1<<SPE)|(1<<CPHA)|(1<<SPR1)|(1<<SPR0); , nu quan st dng lnh 26 trong List 1 chop chip Master, dng ny khng khc l my, qu trnh khi ng SPI cho Slave tng t Master vi mt im khc duy nht l bit MSTR, bit ny khng c set ln 1 i vi Slaves. Trnh phc v ngt ISR(SPI_STC_vect): SPI trn AVR ch c duy nht mt s kin gy ra ngt l khi qu trnh truyn-nhn kt thc. Tn vector ngt SPI trong ngn ng lp trnh avr-gcc l SPI_STC_vect. Trong v d ny, khi mt ngt SPI xy ra Slave, chng ta s c thanh ghi SPDR v sau hin th gi tr c c trn LCD. Dng 37, rData=SPDR, gn thanh ghi SPDR cho bin rData. T dng 38 n 42 l cch hin th gi tr c v trn Text LCD bng th vin myLCD (xem bi Text LCD). Dng 39 chng ta khai bo 1 bin tm dng mng ng, dis, lm buffer cha gi tr ascii ca cc k t cn hin th ln LCD. Ch l gi tr nhn v l 1 con s 8 bit, mun hin th gi tr ny ln LCD chng ta khng th hin th trc tip bng lnh putChar_LCD v hm putChar_LCD xem tham s nhp vo l m Ascii, v d chng ta nhn v s rData=65, nu dng hm putChar_LCD(rData) th trn LCD ch thy k t A v 65 l m Ascii ca k t A. LCD hin th 65 chng ta xem 65 l mt chui cc k t, trc ht cn chuyn s 65 thnh cc k t 6 v 5, hm sprintf(dis,"%i",rData) trong dng code 40 thc hin vic nh dng li bin rData thnh chui cc k t v cha trong buffer dis, %i l c nh dng, bo cho hm sprintf xem rData l mt s nguyn. Sau dng 40, v d rData=65, th dis=65. Dng 42 in chui dis ln LCD: print_LCD(dis);. Chng trnh chnh: chng trnh chnh cho chip Slave khng lm nhiu vic v cc vic chnh nh nhn v hin th c thc hin trong trnh phc v ngt SPI. Dng 27 sei() cho php ngt ton cc, iu ny l cn thit ngt SPI c th xy ra, dng 28 gi chng trnh con khi ng SPI cho Slave, sau khi ng LCD dng 29 v kt thc. Khng c vic g cn thc hin trong vng lp while().
Bi 8 - Giao tip TWI - I2C

Ni dung 1. 2. 3. 4. Bn s i n u. Giao din TWI I2C. TWI trn AVR. iu khin AVR TWI. Cc bi cn tham kho trc Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus.
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I. Bn s i n u.
Bi ny gii thiu cch giao tip bng truyn thng ni tip ng b Two-Wire Serial (TWI) tng thch vi chun I2C. Trong bi ny chng ta s kho st 2 mode truyn v nhn trn chip Master cng vi 2 mode truyn v nhn trn chip Slave. Cng c chnh cng l 2 b phn mm WinAVR v Proteus. Vi iu khin ATmega32 s c dng lm minh ha. Sau bi ny, ti hy vng bn c th hiu v thc hin c: Nguyn l truyn thng ni tip TWI v I2C. S dng module TWI trong AVR cc ch Master. S dng module TWI trong AVR cc ch Slave. V d giao tip gia cc AVR bng TWI.
II. Giao din TWI I2C. TWI (Two-Wire Serial Intereafce) l mt module truyn thng ni tip ng b trn cc chip AVR da trn chun truyn thng I2C. I2C l vit tc ca t InterIntegrated Circuit l mt chun truyn thng do hng in t Philips Semiconductor sng lp v xy dng thnh chun nm 1990. Phin bn mi nht ca I2C l V3.0 pht hnh nm 2007. hiu thm v I2C bn c th tham kho cc ti liu I2C Specification t trang web ca NXP- http://www.nxp.com (lp bi Philips). Trong phm vi bi hc ny ti ch gii thiu giao thc TWI c gii thiu trong datasheet ca cc chip AVR t Atmel. Tuy nhin, v c bn TWI trong AVR hon ton tng thch I2C, do tm hiu TWI ca AVR khng ch gip bn giao tip gia cc AVR vi nhau m c th dng TWI iu khin bt k mt thit b no theo chun I2C (cc chip nh, b chuyn i ADC, DCA, ng h thi gian thc). TWI (I2C) l mt truyn thng ni tip a chip ch (tm dch ca cm t multimaster serial computer bus). Khi nim multi-master (ti s dng t ting anh multi-master thay v dng a chip ch) c hiu l trong trn cng mt bus c th
c nhiu hn mt thit b lm Master, ng thi mt Slave c th tr thnh mt Master nu n c kh nng. V d trong mt mng TWI ca nhiu AVR kt ni vi nhau, bt k mt AVR no u c th tr thnh Master mt thi im no . Tuy nhin nu mt mng dng mt AVR iu khin cc chip nh (nh EEPROM AT24C1024 chng hn) th khi nim multi-master khng tn ti v cc chip nh c thit k sn l Slave, khng c kh nng tr thnh master. TWI (I2C) c thc hin trn 2 ng SDA (Serial DATA) v SCL (Serial Clock) trong SDA l ng truyn/nhn d liu v SCL l ng xung nhp. Cn c theo chun I2C, cc ng SDA v SCL trn cc thit b c cu hnh cc gp m (open-drain hoc opencollector, tham kho cc mch s dng transistor hiu thm), ngha l cn c cc in tr ko ln (pull-up resistor) cho cc ng ny. trng thi ngh (Idle), 2 chn SDA v SCL mc cao. Hnh 1 m t mt m hnh mng TWI (I2C) c bn.
Hnh 1. Mng TWI (I2C) vi nhiu thit b v 2 in tr ko ln cho SDA, SCL. Tip theo chng ta tm hiu mt s khi nim v c im ca TWI. Cc khi nim v c im ti cp di y c dng cho c TWI v I2C, nu c s khc bit ti s gii thch thm. Master: l chip khi ng qu trnh truyn nhn, pht i a ch ca thit b cn giao tip v to xung gi nhp trn ng SCL. Slave: l chip c mt a ch c nh, c gi bi Master v phc v yu cu t Master. SDA- Serial Data: l ng d liu ni tip, tt c cc thng tin v a ch hay d liu u c truyn trn ng ny theo th t tng bit mt. Ch l trong chun I2C, bit c trng s ln nht (MSB) c truyn trc nht, c im ny ngc li vi chun UART. SCL Serial Clock: l ng gi nhp ni tip. TWI (I2C) l chun truyn thng ni tip ng b, cn c 1 ng to xung gi nhp cho qu trnh truyn/nhn, c mi xung trn ng gi nhp SCL, mt bit d liu trn ng SDA s c ly mu (sample). D liu ni tip trn ng SDA c ly mu khi ng SCL mc cao trong mt chu k gi nhp, v th ng SDA khng c i trng thi khi SCL mc cao (tr START v STOP condition). Chn SDA c th c i trng thi khi SCL mc thp.
START Condition-iu kin bt u: t trng thi ngh, khi c SDA v SCL mc cao nu Master mun thc hin mt cuc gi, Master s ko chn SDA xung thp trong khi SCL vn cao. Trng thi ny gi l START Condition (chng ta gi tt l S). STOP Condition-iu kin kt thc: sau khi thc hin truyn/nhn d liu, nu Master mun kt thc qu trnh n s to ra mt STOP condition. STOP condition c Master thc hin bng cch ko chn SDA ln cao khi ng SCL ang mc cao. STOP condition ch c to ra sau khi a ch hoc d liu c truyn/nhn. REPEAT START Bt u lp li: khong gia START v STOP condition l khong bn ca ng truyn, cc Master khc khng tc ng c vo ng truyn trong khong ny. Trng hp sau khi kt thc truyn/nhn m Master khng gi STOP condition li gi thm 1 START condition gi l REPEAT START. Kh nng ny thng c dng khi Master mun ly d liu lin tip t cc Slaves. Hnh bn di m t cc Master to ra START, STOP v REPEAT START.
Address Packet Format nh dng gi a ch: trn mng TWI (I2C), tt c cc thit b (chip) u c th l Master hay Slave. Mi thit b c mt a ch c nh gi l Device address. Khi mt Master mun giao tip vi mt Slave no , n trc ht to ra mt START condition v tip theo l gi a ch Device address ca Slave cn giao tip trn ng truyn, v th xut hin khi nim gi a ch (Address Packet). Gi a ch trong TWI (I2C) c nh dng 9 bits trong 7 bit u (gi l SLA, c gi lin sau START condition) cha a ch Slave, mt bit READ/WRITE v mt bit ACK-Ackknowledge (xc nhn). Do bit a ch c di 7 bits nn v mt l thuyt, trn 1 mng TWI (I2C) c th tn ti ti a 27=128 thit b c a ch ring
bit. Tuy nhin, c mt s a ch khng c s dng nh cc a ch c nh dng 1111xxx (tc cc a ch ln hn hoc bng 120 khng c dng). Ring a ch 0 c dng cho cuc gi chung (General call). Bit READ/WRITE (R/W) c truyn tip sau 7 bit a ch l bit bo cho Slave bit Master mun c hay ghi vo Slave. Nu bit ny bng 0 (gi l W) th qu trnh Ghi d liu t Master n Slave c yu cu, nu bit ny bng 1 (gi l R) th Master mun c d liu t Slave v. Tm bits trn (SLA+R/W) c Master pht ra sau khi pht START condition, nu mt Slave trn mng nhn ra rng a ch m Master yu cu trng khp vi Device address ca chnh mnh, n s p tr li Master bng cch pht ra 1 tn hiu xc nhn ACK bng cch ko chn SDA xung thp trong xung th 9. Ngc li, nu khng c Slave p ng li, chn SDA vn mc cao trong xung gi nhp th 9 th gi l tn hiu khng xc nhn NOT ACK, lc ny Master cn c nhng ng x ph hp ty theo mi trng hp c th, v d Master c th gi STOP condition v sau pht li a ch Slave khcNh vy, trong 9 bit ca gi a ch th ch c 8 bit c gi bi Master, bit cn li l do Slave. V d Master mun yu cu c d liu t Slave c a ch 43, n cn pht i mt byte nh sau trn ng truyn: (43<<1)+1, trong (43<<1) l dch s 43 v bn tri 1 v tr v 7 bit a ch nm cc v tr cao trong gi a ch, sau cng gi tr ny vi 1 tc l qu trnh c c yu cu.
General call Cuc gi chung: khi Master pht i gi a ch c dng 0 (thc cht l 0+W) tc n mun thc hin mt cuc gi chung n tt c cc Slave. Tt nhin, cho php hay khng cho php cuc gi chung l do Slave quyt nh. Nu cc Slave c ci t cho php cuc gi chung, chng s p li Master bng ACK. Cuc gi chung thng xy ra khi Master mun gi d liu chung n cc Slaves. Ch l cuc gi chung c dng 0+R l v ngha v khng th c chuyn Master nhn d liu t tt c cc Slave cng thi im. Data Packet Format nh dng gi d liu: sau khi a ch c pht i, Slave p li Master bng ACK th qu trnh truyn/nhn d liu s din ra gia cp Master/Slave ny. Ty vo bit R/W trong gi a ch, d liu c th c truyn theo hng t Master n Slave hay t Slave n Master. D di chuyn theo hng no, gi d liu lun bao gm 9 bits trong 8 bits u l d liu v 1 bit cui l bit ACK. Tm bits d liu do thit b pht gi v bit ACK do thit b nhn to ra. V d khi Master thc hin qu trnh gi d liu n Slave, n s pht ra 8 bits d liu, Slave nhn v pht li ACK (ko SDA xung 0 xung th 9), sau Master s quyt nh gi tip byte d liu khc hay khng. Nu Slave pht tn hiu NOT ACK (khng tc ng SDA xung th 9) sau khi nhn d liu th Master s kt thc qu trnh gi bng
cch pht i STOP condition. Hnh bn di m t nh dng gi d liu trong TWI (I2C).
Phi hp gi a ch v d liu: mt qu trnh truyn/nhn TWI (I2C) thng c bt u t Master, Master pht i mt START condition sau gi gi a ch SLA+R/W trn ng truyn. Tip theo nu c mt Slave p ng li, d liu c th truyn/nhn lin tip trn ng truyn (1 hoc nhiu byte lin tip). Khung truyn thng thng c m t nh hnh bn di.
Multi-Master Bus ng truyn a chip ch: nh trnh by trn, TWI (I2C) l chun truyn thng a chip ch, ngha l ti mt thi im c th c nhiu hn 1 chip lm Master nu cc chip ny pht ra START condition cng lc. Nu cc Master c cng yu cu v thao tc i vi Slave th chng c th cng tn ti v qu trnh truyn/nhn c th thnh cng. Tuy nhin, trong a s trng hp s c mt s Master b tht lc (lost). Mt Master b lost khi n truyn/nhn 1 mc cao trn SDA trong khi cc Master khc truyn/nhn 1 mc thp. Truyn thng a chip ch tng i phc tp v v th ti s khng cp trng hp ny trong lc thc hin v d giao tip trong bi hc ny. Nm c cc khi nim v c im trn ca truyn thng TWI (I2C) l bn sn sng iu khin module TWI trn AVR. Phn tip theo ti s hng dn cch thao tc module TWI trn AVR thng qua mt v d c th. III. TWI trn AVR. 1. Thanh ghi: TWI trn AVR c vn hnh bi 5 thanh ghi bao gm thanh ghi tc gi nhp TWBR, thanh ghi iu khin TWCR , thanh ghi trng thi TWSR, thanh ghi a ch TWAR v thanh ghi d liu TWDR.
- TWBR (TWI Bit Rate Register): l 1 thanh ghi 8 bit quy nh tc pht xung gi nhp trn ng SCL ca chip Master.
Tc pht xung gi nhp c tnh theo cng thc:
Trong CPU Clock frequency l tn s hot ng chnh ca AVR, TWBR l gi tr thanh thi TWBR v TWPS l gi tr ca 2 bits TWPS1 v TWPS0 nm trong thanh thi trng thi TWSR. Hai bits ny c gi l bit prescaler, thng thng ngi ta hay set TWPS1:0 =00 chn Prescaler l 1 (40=1). Bng 1 tm tt tc xung gi nhp to ra trn SCL i vi cc gi tr ca tham s: Bng 1. Tc xung gi nhp tham kho.
- TWCR (TWI Control Register): l thanh ghi 8 bit iu khin hot ng ca TWI.
Bit 7- TWINT (TWI Interrupt Flag): l mt c bo rt quan trng. TWINT c t ng set ln 1 khi TWI kt thc mt qu trnh bt k no (nh pht/nhn START, pht nhn a ch). Ch l bit ny khng t ng c xa bi phn cng nh cc c bo trong cc module khc. V th, khi lp trnh iu khin TWI chng ta lun phi xa TWINT trc khi mun thc hin mt qu trnh no . Mt im quan trng cn lu l bit TWINT c xa khi chng ta vit gi tr 1 vo n. Trong khi lp trnh cho TWI, chng ta thng xa TWINT bng cch vit 1 vo n, sau lin tc kim tra TWINT, nu bit ny c set ln 1 th qu trnh hon thnh. Bit 6 TWEA (TWI Enable Acknowledge Bit): tm hiu l bit kch hot tn hiu xc nhn. i vi chip Slave, nu bit ny c set th tn hiu xc ACK s c gi trong cc trng hp sau: a ch do Master pht ra trng khp vi a ch ca Slave; mt cuc gi chung ang xy ra v Slave ny cho php cuc gi chung; d liu c Slave nhn t Master. Nh th, khi set mt chip ch Slave, chng ta cn set bit ny n c th p ng li Master bt c khi no c gi. i vi chip Master, tn hiu ACK ch c pht trong 1 trng hp duy nht l khi Master nhn d liu t Slave, Master pht ACK bo cho Slave l mnh nhn c v mun tip tc nhn t Slave. Bit 5 TWSTA (TWI START Condition Bit): l bit to START condition. Khi mt chip mun tr thnh Master thc hin 1 cuc gi, bit ny cn c set v mt START condition c to ra trn ng truyn nu ng truyn ang rnh. Nu ng truyn khng rnh, TWI s ch cho n khi n rnh (nhn ra 1 STOP condition) v tip tc gi START condition. Ch l l bit nay cn c xa bi phn mm sau khi START condition c gi (vit 0 vo bit ny xa n). Bit 4 TWSTO (TWI STOP Condition Bit): l bit to STOP condition cho TWI. Khi Master mun kt thc mt cuc gi, n s pht STOP condition bng cch vit gi tr 1 vo bit TWSTO. Slave cng c th tc ng vo bit ny, nu mt cuc gi b li, vit 1 vo TWSTO trn Slave s reset ng truyn v trng thi rnh ban u. Bit 3 TWWC (TWI Write Collision Flag): khi c TWINT ang mc thp tc TWI ang bn, nu chng ta vit d liu vo thanh ghi d liu (TWDR) th mt li xy ra, khi bit TWWC t ng c set ln 1. V th, trong qu trnh truyn d liu, bit TWINT cn c gi mc cao khi ghi d liu vo thanh ghi TWDR v sau xa khi d liu sn sng. Bit 2 TWEN (TWI Enable Bit): bit kch hot TWI trn AVR, khi TWEN c set ln 1, TWI sn sng hot ng. Bit 1 Reserve: khng s dng. Bit 0 TWIE (TWI Interrupt Enable Bit): bit cho php ngt TWI, khi bit nay c set bng 1 ng thi bit I trong thanh ghi trng thi chung c set, mt ngt TWI xy ra khi bit TWINT c set bi phn cng. Ngt TWI c th xy ra sau bt k hot ng no lin quan n TWI. Do cn s dng ngt hp l. Thng thng, ngt ch c s dng cho Slave, i vi Master ngt khng cn thit v Master ch ng khi ng mt cuc gi.
Mt iu cn ch l cc bit trong thanh ghi TWCR khng cn c set cng lc, ty vo tng giai on trong qu trnh giao tip TWI cc bit c th c set ring l. - TWSR (TWI Status Register): l 1 thanh ghi 8 bit trong c 5 bit cha code trng thi ca TWI v 2 bit chn prescaler.
C rt nhiu bc, nhiu tnh hung xy ra khi giao tip bng TWI cho c Master v Slave. ng vi mi trng hp TWI s to ra 1 code trong thanh ghi TWSR . Lp trnh cho TWI cn xt code trong 5 bit cao ca thanh ghi TWSR v a ra cc ng x hp l ng vi tng code. - TWDR (TWI Data Register): l thanh ghi d liu chnh ca TWI. Trong qu trnh nhn, d liu nhn v s c lu trong TWDR. Trong qu trnh gi, d liu cha trong TWDR s c chuyn ra ng SDA. - TWAR (TWI Address Register): l thanh ghi cha device address ca chip Slave. Cu trc thanh ghi c trnh by trong hnh di.
Nh li a ch Slave c to thnh t 7 bits, trn thanh ghi TWAR 7 bits a ch ny nm 7 v tr cao. Trc khi s dng TWI nh Slave, chng ta phi gn a ch cho chip, vic vit a ch thng c thc hin bng lnh TWAR = (Device_address<<1)+TWGCE. Trong TWGCE (TWI General Call Enable) l bit cho php cuc gi chung. Nh ti cp bn trn, Slave co quyn cho php Master thc hin cuc gi chung vi n hay khng. Nu TWGCE=1, Slave s p ng li cuc gi chung nu c, nu TWGCE=0 th Slave s b qua cuc gi chung. 2. Hot ng ca TWI: TWI trn AVR c gi l byte-oriented (tm dch l hng byte) v interruptbased (da trn ngt). Bt k mt s kin no trong qu trnh truyn/nhn TWI cng c th gy ra 1 ngt TWI. TWI trn AVR v th hot ng tng i c lp vi chip. Tuy nhin, cn khai thc ngt trn AVR mt cch hp l. V d, i vi Master, chng ta khng cn s dng ngt v chip ny hon ton ch ng trong vic truyn v nhn. Ring vi Slave, s dng ngt trnh b l cc cuc gi l cn thit. Tt c cc AVR trn mng TWI u c th l Master hay Slave, c Master v Slave u c th truyn v nhn d liu. V th, c tt c 4 mode trong hot ng ca TWI trn AVR. Chng ta s ln lt kho st cc mode ny nh sau: Master Transmitter (chip ch truyn), Master Receiver (Chip ch nhn), Slave Reicever (chip t nhn) v Slave Transmitter (Chip t truyn).
Trc khi kho st cc ch hot ng ca TWI chng ta qui c mt s k hiu thng dng (y cng l cc k hiu dng trong datasheet ca cc chip AVR). S: Rs: R: W: ACK: 9 NACK: Data: P: SLA: START condition iu kin bt u REPEAT START bt u lp li READ Bit, bit ny bng 1 c gi km vi gi a ch WRITE Bit, bit ny mang gi tr 0, gi km gi a ch Ackowledge, bit xc nhn, chn SDA c ko xung 0 xung th Not Acknowledge, khng xc nhn, SDA mc cao bit th 9 8 bits d liu STOP condition iu kin kt thc. Slave address, a ch ca Slave cn giao tip.
A. Master Transmitter mode Master truyn d liu: Trong ch ny, Master truyn 1 hoc mt s byte d liu n mt hoc cc Slave. bt u, Master to ra mt START condition trn ng SDA, nu ng truyn ang rnh, Master s tip tc pht i a ch ca Slave cn giao tip cng vi bit W (ghi) theo nh dng nh sau: SLA+W. Nu Slave p li bng mt ACK trong xung gi nhp th 9, Master s tip tc gi 1 hoc lin tip cc byte d liu trn SDA. C sau mi byte d liu, Master s kim tra ACK t Slave. Nu Slave gi mt NACK hoc Master khng mun gi thm d liu n Slave n s pht i mt STOP condition hoc mt REPEAT START (Rs). Nu STOP c pht, cuc gi kt thc, nu Rs c pht, mt cuc gi mi bt u, sau Rs l a ch ca Slave mi l v mt l thuyt, trn thc t lm sao kim tra mt START condition c c gi cha? lm sao bit c nhn c ACK sau khi pht a ch hoc d liu? Tt c c TWI m ha thnh cc code cha trong thanh ghi TWSR (ch 5 bit cao). Chng ta ch thanh ghi ny v i chiu vi bng code quy nh sn bit trng thi ng truyn v a ra quyt nh tip theo. Hnh 2 m t mt qu trnh Master truyn d liu, cc kh nng c th xy ra v gi tr tng ng ca thanh ghi TWSR. ngha cc code trong thanh ghi TWSR trong lc Master truyn d liu c th tham kho thm datasheet ca chip.
Hnh 2. Master truyn d liu. T hnh 2, chng ta nhn thy khi Master truyn d liu, dy code 0x08 -> 0x18 > 0x28 -> -> 0x28 (-> 0x30) l dy code thnh cng nht. Code 0x08 bo rng START codition c truyn thnh cng, code 0x18 bo a ch truyn thnh cng v c Slave xc nhn bng ACK, code 0x28 tc d liu c Master truyn thnh cng v Slave nhn c, bo ACK li cho Master, code 0x30 tc d liu c truyn nhng Slave khng xc nhn li, lc ny Master c th pht i mt STOP codition sau code 0x30. Ngoi ra cn mt s code khc tng ng vi cc trng hp khc nh gi a ch tht bi (code 0x20), Master b lost (code 0x38)i vi mi loi ng dng, cch hnh x s khc nhau i vi cc trng hp tht bi ny.
Trong bi ny, ti s b qua tt c cc trng hp tht bi, nu mt trong cc code tht bi xy ra chng ta s thot khi cuc gi v a ng truyn v trng thi ngh. B. Master Receiver mode Master nhn d liu: Trong ch ny, Master nhn mt hoc mt s byte d liu t mt Slave. bt u, Master to ra mt START condition trn ng SDA, nu ng truyn ang rnh, Master s tip tc pht i a ch ca Slave cn giao tip cng vi bit R (c) theo nh dng nh sau: SLA+R. Nu Slave p li bng mt ACK trong xung gi nhp th 9, Master s bt u sample d liu trn SDA. C sau mi byte d liu, nu Master mun nhn tip byte khc n phi pht ra 1 ACK xung th 9 bo cho Slave. Khi Master mun kt thc qu trnh nhn n s pht mt NOT ACK sau khi nhn d liu, lin sau Master pht STOP kt thc cuc gi hoc pht i mt REPEAT START nu n mun tip tc gi cc Slaves khc. Hnh 3 m t mt qu trnh Master nhn d liu, cc kh nng c th xy ra v gi tr code tng ng ca thanh ghi TWSR. ngha cc code trong thanh ghi TWSR trong lc Master truyn d liu c th tham kho thm datasheet ca chip.
Hnh 3. Master nhn d liu.

T hnh 3, trong qu trnh Master nhn d liu, dy code 0x08 -> 0x40 -> 0x50 > -> 0x58 l dy code thnh cng nht. Code 0x08 bo rng START codition c truyn thnh cng, code 0x40 bo a ch + R c truyn thnh cng v c Slave xc nhn bng ACK, code 0x50 bo d liu c Master nhn thnh cng v Master cng pht mt ACK bit sau khi nhn, code 0x58 xy ra khi Master nhn d liu thnh cng nhng n khng pht ACK m pht NOT ACK, bo cho Slave rng Master khng mun nhn thm d liu, tip theo Master s pht mt STOP condition hoc mt REPEAT START. Cc trng hp khc chng ta khng kho st. C. Slave Receiver mode Slave nhn d liu: Hnh 4 m t mt qu trnh Slave nhn d liu, cc kh nng c th xy ra v gi tr code tng ng ca thanh ghi TWSR. Ch Slave nhn d liu xy ra khi Master thc hin mt cuc gi pht d liu (SLA+W). Nh quan st trong hnh 4, Slave ch nhn ra cuc gi ny khi a ch ca n trng vi a ch ca Master (Own address mode) hoc khi Master thc hin mt cuc gi chung. Khi , bit TWINT ca Slave s c set ln 1. Nu Slave cho php ngt TWI (bit TWIE trong thanh ghi TWCR c set t lc u) th mt ngt xy ra bo c mt s kin TWI. Nu code trong thanh ghi TWSR l 0x60 th mt cuc gi a ch ring c yu cu v Slave cng p ng li Master bng mt ACK, Slave sau bt u nhn d liu t ng SDA. C sau mt byte d liu Slave phi xc nhn mt ACK nu n cn mun tip tc nhn. Nu v mt l do no m Slave khng th tip tc nhn n c th pht mt NOT ACK sau mt byte d liu. Cuc gi kt thc khi Slave nhn c STOP condition, tng ng code 0xA0. Cuc gi chung cng din ra hon ton tng t cuc gi a ch ring nhng code c gi tr khc. Khi vit chng trnh cho Slave trong ch nhn d liu, chng ta cn xt c 2 trng hp cuc gi a ch ring v cuc gi chung.
Hnh 4. Slave nhn d liu. D. Slave Transmitter mode Slave truyn d liu: y l ch cui cng trong 4 ch ca AVR TWI. Hnh 5 m t mt qu trnh Slave truyn d liu, cc kh nng c th xy ra v gi tr code tng ng ca thanh ghi TWSR. Ch Slave pht d liu xy ra khi Master mun nhn d liu t Slave, Master thc hin mt cuc gi nhn d liu (SLA+R). Nh quan st trong hnh 5, Slave ch nhn ra cuc gi ny khi a ch ca n trng vi a ch ca Master (Own address mode). Khi , bit TWINT ca Slave s c set ln 1. Nu Slave p li bng mt ACK xung nhp th 9, code trong thanh ghi TWSR s l 0xA8, Slave sau bt u pht d liu ln ng SDA. C sau mi byte d liu, Master s xc nhn mt ACK nu n cn mun tip tc nhn, code 0xB8 s xut hin trong trng hp ny. Nu Master khng mun tip tc nhn d liu t Slave, mt NOT ACK s c pht v code 0xC0 xut hin, Slave kt thc qu trnh pht d liu. Mt trng hp
c bit khi bit TWEA (bit ACK) trong thanh ghi TWCR ca Slave c reset v 0 trc khi Slave truyn d liu, trng hp Slave mun bo rng n ht d liu truyn, byte tip theo cng l byte cui cng. Sau khi Master nhn byte ny, n c th xc nhn 1 ACK cho Slave (v tht ra Master khng h bit Slave ang truyn byte cui), code trn Slave trong trng hp ny l 0xC8 v Slave s t ht thc qu trnh truyn m khng cn ch Master. Khi lp trnh cho Slave trong ch pht, cn phi c s tha hip vi Master trc trnh code 0xC8 v code ny khng c nhiu ngha.
Hnh 5. Slave truyn d liu. K thut chnh dng cho Master khi truyn hay nhn cuc gi l hi vng v ch (polling and waiting). ng vi mi code nhn v t thanh ghi TWSR (hay ng vi mi trng thi ca cuc gi) m Master set cc bit tng ng trong thanh ghi iu khin TWCR v sau ch bit TWINT c set (qu trnh kt thc) tip tc c v xt code TWSR. Qu trnh ch v xt ny lp li cho n khi Master kt thc cuc gi bng STOP condition. Tuy nhin Slave th khc, Slave khng ch ng thc hin cuc gi m n phi ch yu cu t Master phc v. V th, nu dng hi vng cho Slave th s tn thi gian ch v ch v i khi cn b l cc cuc gi. i vi Slave, ngt l phng php bt cuc gi ti u nht. Trong bi hc ny, vic truyn v nhn ca Slave s c thc hin trong cc trnh phc v ngt TWI.
IV. iu khin AVR TWI.

Phn ny ti hng dn lp trnh iu khin module TWI AVR bng WinAVR. Cc hnh 2, 3, 4 v 5 cn c tham kho km k v code trong phn ny c pht
trin t cc hnh ny. n gin, chng ta s vit cc hm giao tip TWI trong 1 file ring gi l myTWI.h, y c th coi l th vin cho TWI dng trong trang web ny. Nh trnh by, chun I2C th duy nht nhng cch sp xp d liu ca cc chip I2C th rt a dng. V th, khi mun giao tip vi mt chip I2C no bn nht thit phi c datasheet ca chip hiu nh dng d liu. Cc hm trong th vin myTWI ch phc v giao tip gia cc AVR vi nhau, nu mun s dng chng giao chip vi mt chip EEPROM 24C1004 chng hn, bn phi vit thm cc hm m rng khc da trn cc hm ny. Ni dung file myTWI.h c chia thnh 3 phn, phn u l cc nh ngha bin, tham s chung, phn 2 gm cc hm truyn/nhn cho Master v phn 3 l trnh phc v ngt TWI cho Slave. List 1 trnh by cc nh ngha chung trong file myTWI.h. List 1. nh ngha chung.
Phn ny ch yu nh ngha cc code trng thi trong qu trnh thao tc TWI trn AVR m chng ta bit khi kho st cc ch hot ng ca TWI. Tht ra bn c th tham kho cc hnh 2-5 v cc bng code trong datasheet ca AVR v s dng cc code trng thi trc tip trong lc lp trnh, ti nh ngha nh trn ch tin theo di trong lc lp trnh. Cc dng t 12 n 25 nh ngha cc code trng thi cho Slave (c truyn v nhn). Chng ta cng nh ngha mt s bin ton cc dng cho Slave, bin SLAVE_wData[100] l mt mng 100 phn t dng cha d liu m Slave s truyn, bin Tran_Num l ch s ca phn t trong mng SLAVE_wData s c truyn i. Bin SLAVE_buff[100] l d liu nhn v t TWI v Rec_Num l ch s ca d liu sau cng do TWI nhn v (d liu SLAVE_buff[Rec_Num]). Bin Device_Addr cha a ch m khi l Slave ca chnh AVR chng ta ang lp trnh. Tng t, cc dng t 47 n 57 nh ngha code trng thi cho Master mode. Trc , chng ta cng nh ngha cc gi tr tc pht xung gi nhp s gn cho thanh ghi TWBR (dng 37, 38). Hai bin TWI_R v TWI_W i din cho 2 bit R/W c truyn trong gi a ch (bo cho Slave bit Master mun truyn hay nhn d liu). Mt s macro trong cc dng 42 n 45 bao gm START, STOP condition v xa bit TWINT bng cch gn cc gi tr tng ng cho thanh ghi iu khin TWI. Cui cng l chng trnh con void TWI_Init(void) khi ng TWI. Qu trnh khi ng bao gm set tc xung gi nhp cho Master (dng 61, 62), gn a ch device (dng 63) v xc lp TWI sn sng ch Slave. Xem li thanh ghi TWAR, do 7 bit a ch nm v tr cao nn chng ta cn phi dch tri a ch 1 v tr trc khi gn cho TWAR (Device_Addr <<1), ng thi set bit 0 trong TWAR cho php nhn cuc gi chung khi c yu cu. Dng 64 khi ng TWI vi bit ACK sn sng v cho php xy ra ngt TWI. Nh th, sau khi khi ng TWI sn sng ch Slave. List 2. Code cho Master.
Hm TWI_Master_Send_array(uint8_t Addr, uint8_t Data[], uint8_t len) thc hin truyn 1 dy cc byte d liu trong mode Master. Tham s Addr l a ch ca Slave cn giao tip, Data[] l mng d liu v len l chiu di (s byte) ca d liu cn truyn. Vic u tin khi chng ta vo Master mode l tt ngt TWI bng cch xa bit TWIE (dng 3). Trnh t Master truyn d liu hon ton tng t trnh t trong hnh 2. Dng 5, TWCR=TWI_START, Master bt u pht 1 START condition. Nu xem li nh ngha ca macro TWI_START trong list 1 bn s thy dng TWCR=TWI_START tng ng TWCR=(1<<TWINT)|(1<<TWSTA)|(1<<TWEN) tc chng ta thc hin xa bit TWINT (bit ny phi lun c xa trc khi mun thc hin vic g) bng cch ghi 1 vo TWINT, set bit START (bit TWSTA) v cho php TWI hot ng bng bit TWEN. Dng code 6 ch cho n khi bit TWINT c phn cng set ln 1 (kt thc), sau chng ta kim tra code trong thanh ghi trng thi TWSR. Ch l ch c 5 bit cao trong thanh ghi TWSR cha trng thi nn chng ta cn dng gii thut mt n che cc bit thp li, TWSR & 0xF8 chnh l cch che 3 bit thp ca TWSR. So snh code c c vi code tng ng trong hnh 1, trong trng hp ny chng ta so snh vi _START_Sent, chnh l so snh vi 0x80 (xem li nh ngha ca _START_Sent trong list 1). Nu cc code khng trng nhau, mt li truyn xy ra v chng ta s thot khi chng trnh truyn, gi tr tr v chnh l code c li (xem dng code 7). Cc dng code t 10 n 13 thc hin truyn a ch + W, ch trong lc pht, d liu cn pht phi c ghi sn vao thanh ghi d liu TWDR trc khi xa bit TWINT (dng 10 v 11). Sau khi truyn a ch chng ta truyn mng d liu lin tip v cui cng l pht STOP condition, TWCR=TWI_STOP tng ng TWCR=(1<<TWINT)|(1<<TWSTO)|(1<<TWEN). Cn khi ng li TWI a n v ch Slave trc khi thot khi chng trnh con truyn d liu ca ch Master (dng 24). Hm TWI_Master_Read_array(uint8_t Addr, uint8_t Data[], uint8_t len) thc hin nhn d liu v Master. Cch gii thch cho hm ny khng khc nhiu so vi hm c d liu nn bn c t tm hiu. Mt im cn ch l khi nhn 1 dy byte chng ta nn c n-1 byte u bnh thng, c tr ACK cho Slave v byte cui cng s c nhn ring, tr NOT ACK bo cho Slave rng Master khng mun nhn thm(on code t dng 55 n 59 dng c byte cui cng). List 3. Code cho Slave.
Nh ti trnh by, ton b qu trnh truyn v nhn ca Slave c thc hin trong chng trnh phc v ngt TWI. Khi ngt TWI xy ra, trnh phc v ngt s c v kim tra code trong thanh ghi TWSR thc hin cc cng vic ph hp. Bn c li tham kho thm hnh 4 v hnh 5 cng vi cc code trong nhng case tng ng ca List 3 hiu on chng trnh ny. im lu ln nht m ti mun ni l cc bin c dng cho ch Slave truyn v nhn. Ti dng 2 mng SLAVE_wData v SLAVE_buff cha bin truyn v nhn. Hai bin Tran_Num v Rec_Num l ch s ca byte hin hnh. V th SLAVE_wData[Tran_Num] chnh l byte tip theo s c truyn i nu Slave c yu cu truyn, v SLAVE_buff[Rec_Num] l byte cui cng m Slave nhn v trong ch Slave nhn d liu. Hy khi thc cc bin ny trong cc chng trnh ng dng. minh ha cho cc s dng cc hm trong th vin myTWI, ti thc hin mt mch in m phng mng TWI gm 3 chip ATmega32. Chip th nht l Master, 2 chip cn li l Slaves. Ti to 2 Project, mt cho Master v mt cho 2 Slaves dng chung. PORTD c set input c in tr ko ln. Ti dng 2 chn PD6 v PD7 chn a ch cho 2 Slaves, Slave th nht ti ni chn PD6 xung GND, do chip ny c a ch Device_Addr l PD7:PD6=10=2 (thp phn). Slave cn li ti 2 chn PD6 v PD7 trng nn a ch ca n l PD7:PD6=11=3. Trong chng trnh ca Slave c phn c 2 chn PD6:PD7 v gn cho bin Device_Addr m chng ta khai bo trong List 1, nh vy c th dng cc ny set a ch cho Slaves m chng ta gi l set a ch cng. Trn chip Master, mt swich c ni vi chn PD0 chn Slave cn giao tip, nu switch ng th SLAVE c a ch 2 c chn, nu switch m th SLAVE c a ch 3 c chn giao tip. Mt nt nhn c ni vi ngt INT0 ca chip Master, khi nhn nt ny chng trnh cn c d liu t Slave c gi, ty theo switch ng hay m m Slave tng ng c gi gi d liu cho Master. D liu nhn v s hin th trn 1 Character LCD. Hnh 6 l s mch in m phng bng phn mm Proteus v List 4, List 5 ln lt trnh by on code cho chng trnh chnh ca Master v Slave.
Hnh 6. Demo TWI. List 4. Chng trnh chnh cho Master.
V d ca Master minh ha cch dng 2 hm Master truyn v nhn mng d liu. dng 27 ti dng hm TWI_Master_Send_array gi 40 phn t ca mng Data n Slave c a ch 2, TWI_Master_Send_array(2,Data,40). Tng t, dng 31 gi 50 phn t ca mng Data n Slave c a ch 3. Khi button trn mch m phng c nhn, ngt INT0 xy ra, trong trnh phc v ngt INT0 chng ta dng hm TWI_Master_Read_array c d liu t mt trong 2 Slaves, xem dng code 43: TWI_Master_Read_array(Slave_Addr,rData,1). a ch ca Slave cn c s do switch ni vi chn PD0 quyt nh (xem dng 42). a ch ca Slave ang giao tip s hin th trn dng 1 ca LCD, d liu c hin th trn dng 2. List 5. Chng trnh chnh cho Slaves.
Chng trnh demo ca Slaves minh ha cc ch Slave truyn v nhn d liu. Tuy nhin do cc qu trnh truyn v nhn d liu ca Slave c thc hin trong trnh phc v ngt TWI c vit sn trong file myTWI.h. trong chng trnh chnh ca Slave chng ta khng cn phi gi bt k hm no trong myTWI. Cng vic cn lm trong chng trnh demo cho Slave l khi ng TWI sau gn gi tr cho cc bin ton cc ca Slave (dng 21 gn gi tr cho mng SLAVE_wData). Ti c nh km v d demo cho TWI, ti thc hin 2 Projetc trong 2 th mc: TWI1 cho AMster v TWI2 cho Slave. chy demo, chy file TWI bng Proteus, dng switch SW1 chn Slave cn giao tip, nhn button nhn d liu t Slave. Thay i v tr switch v kim tra kt qu.

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Ni dung 1. Gii thiu. 2. Cng c. 3. V d. 4. M phng. Download v d I. Gii thiu

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Mt s chip AVR thng dng:

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Hnh 7. Thanh ghi trng thi.

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Bng 1 cc vector ngt v Reset trn chip Atmega8.

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