64-Point Pipelined FFT/IFFT

Virtual Components for the Converging World

CS2460

TM

The CS2460 is an online programmable, pipelined architecture 64-Point FFT/IFFT core. This highly integrated application specific core computes the FFT/IFFT based on a radix-4 decimation in frequency (DIF) algorithm. It performs the computations concurrently in three highly pipelined cascaded stages, as illustrated in Figure 1. The CS2460 is capable of processing continuous input data and contains all the necessary circuits to support this continuous processing. It is available in both ASIC and FPGA versions that have been handcrafted by Amphion for maximum performance while minimizing power consumption and silicon area.

Ich_in [11:0] Qch_in [11:0] enable_in QSC[1:0] BSY Input Buffer Stage 1 Radix-4 FFT Stage 2 Radix-4 FFT Stage 3 Radix-4 FFT Output Reordering Buffer

Ich_out [11:0] Qch_out [11:0] DBSO enable_out QOV

Figure 1: Block Diagram of CS2460 Core

FEATURES
On-line programmable FFT/IFFT core 12-bit complex input and output in two's complement format 12-bit twiddle factors generated inside the core 15-bit fixed-point internal arithmetic operation Programmable shift down control Radix-4 based architecture Both input and output in normal order No external memory required Optimized for both ASIC and FPGA technologies with the same functionality Fully synchronous design

APPLICATIONS
OFDM modulation for WLAN IEEE 802.11a and HiperLAN2 Image processing Atmospheric imaging Spectral representation

Amphion continues to expand its family of application-specific cores See http://www.amphion.com for a current list of products

CS2460 64-Point Pipelined FFT/IFFT

FAST FOURIER TRANSFORM
FFT (Fast Fourier Transform) and IFFT (Inverse Fast Fourier Transform) are algorithms computing 2P-point discrete Fourier transform, as defined below:
N1

CS2460 SYMBOL AND PIN DESCRIPTION

Table 1 describes input and output ports (shown graphically in Figure 2) of the CS2460 64-point FFT/IFFT core. Unless otherwise stated, all signals are active high and bit(0) is the least significant bit.
Ich_in [11:0] Qch_out [11:0]

FFT:

Y(k ) =

X( n)W
n=0 N1

n k N

, k = 0, 1, 2...N-1

[1]

IFFT:

1 Y ( k ) = --N

n=0

X ( n ) W N , k = 0, 1, 2...N-1

nk

[2]

Qch_in [11:0] enable_in QSC[1:0]

RST

CS2460 64-Point FFT Function

Qch_out [11:0] enable_out QOV BSY DBSO

Where N=2P and e

j2 N

CLK

The computational complexity of FFT and IFFT is proportional to NlogRN, where R is the radix base on which FFT/IFFT is performed. The higher the radix, the less number of multiplication is required, however the more simultaneous multiple data access is required which causes the circuits to be more complicated. The radix-4 algorithm offers a balance between the computational and circuit complexity and is often used in construction of higher radix FFT computation units when designing high performance FFT/IFFT hardware. Figure 2: CS2460 Symbol

Table 1: CS2460 - 64-Point FFT/IFFT Interface Signal Definitions

Name
Ich_in[11:0] Qch_in[11:0] enable_in QSC[1:0]

I/O
I I I I

Description
12-bit Real input data Ich_in enters the function in natural order. 12-bit Imaginary input data Qch_in enters the function in natural order. Shows the valid section within the input data, when a 64pt block is input, enable_in should remain HIGH for 64 clock cycles. Output Shifting Control determines how the internal 15 bit real and imaginary values are shifted to provide the 12 bit outputs: 00: [14:3] 01: [13:2] 10: [12:1] 11: [11:0] Asynchronous global reset signal, active HIGH. System clock signal, rising edge active. 12-bit transformed Real data Ich_out is output in normal order. The output FFT data in normal order is indicated by enable_out. 12-bit transformed Imaginary data Qch_out is output in normal order. The output FFT data in normal order is indicated by enable_out. Shows the valid section within the output data, when a 64pt block is output, enable_out should remain HIGH for 64 clock cycles. Enable_out goes to HIGH when the first complex data comes out and remains HIGH until the last one is output.

RST CLK Ich_out[11:0] Qch_out[11:0] enable_out

I I O O O

TM

Table 1: CS2460 - 64-Point FFT/IFFT Interface Signal Definitions

Name
QOV

I/O
O

Description
Output overflow signal. Overflow may occur depending on the QSC selection. When overflow occurs the output is saturated. When an overflow occurs QOV remains asserted for the remainder of that block. Output start of block signal, DBSO is asserted HIGH for the first two complex results outputs from the core. Input port status indicator. An input data block can only start when BSY is LOW. It goes to HIGH in the next clock cycle after loading is started and returns to LOW when the last data of the 64-point block is loaded.

DBSO BSY

O O

FUNCTIONAL DESCRIPTION
CS2460 performs decimation in frequency (DIF), radix-4, forward or inverse Fast Fourier Transforms on complex data. Data is loaded into its workspace RAM in normal sequential (natural) order. The transformed data is output from the core in normal order.
Input

enable_in= 1 ? Yes

No

DATA FORMATS
Input and output data is represented by fixed-point real and imaginary components in two's complement format. For IFFT, the real (Ich_in) and imaginary (Qch_in) components are exchanged. The input component wordlength is 12 bits and the output 12 bits. Internal words stored between computation stages are 15 bits including the input to the final output scaling stage from which the required 12 bits are selected under the control of QSC. Twiddle factor (Sine and Cosine values), which are generated by the function internally, has a wordlength of 12 bits.

No Load data into input buffer, then start stage 1 radix-4 computation enable_in= 1 ? Yes

Stage 2 radix-4 computation

Stage 3 radix-4 computation

FFT COMPUTATION
The FFT computation for one data block is scheduled to complete in three highly pipelined stages. In each stage 64 radix-4 operations are performed. The first stage computation starts just after the last data of the 64-point block is loaded. The successive data block can follow the preceding one immediately. Figure 3 shows the flowchart for FFT computations in CS2460.

Output scaling & Re-ordering

Output

Figure 3: FFT Execution Flowchart

DATA LOADING
Before the CS2460 operates, a reset of the circuit should be performed if input port BSY is HIGH. This is done by asserting the input RST for the specified CPLD reset time. Data is clocked in on the clock rising edge in normal order. It is synchronized by signal enable_in, that shows the valid section within the input data. For example, when a 64pt block is input, enable_in should remain HIGH for 64 clock cycles. When loading is started, indicator BSY gets asserted to acknowledge that loading is in progress and computation will be started after loading. When the function is ready to accept the next data block, signal BSY returns to LOW. Figure 4, illustrates the data loading operation in CS2460. 3

CS2460 64-Point Pipelined FFT/IFFT

CLK RST enable_in Ich_in Qch_in BSY
Figure 4: Data Loading Operation
I0 I1 I2 I3 I4 IN-20 IN-19 I63 I0 I1

Q0

Q1

Q2

Q3

Q4

Qn-20

Qn-19

Q63

Q0

Q1

COMPUTATION ACCURACY
The stage 1 and stage 2 radix-4 operations for 64-point transform consist of a radix-4 butterfly followed by a twiddle multiplication. Theoretically the result value may grow by a factor of up to 5.242. In stage 3, the result value may grow by a factor of 4 and the final result value may grow by a factor of up to 81.4 (this occurs when the input data represents a complex square wave). As the output is only 12 bits and fixedpoint arithmetic is employed in the radix-4 processor, it is necessary to be able to scale the result to avoid overflow while still obtaining a good dynamic range. Since the input and

output wordlengths are both 12 bits, a 2 bit unconditional down shift is performed in stage 2 and the remainder of the shifting is performed at the output under the control of input QSC. The internal wordlength for data transferred between stages is 15 bits including 15 bits before output scaling. Figure 5 shows the internal wordlength of CS2460 core. To improve the computation accuracy a rounding technique is employed. Therefore, when the intermediate value is derived from the twiddle multiplication result, or the input to the butterfly is scaled down, rounding is performed to ensure the highest possible accuracy is achieved.

12 bits Data input Stage1

15 bits Stage2

15 bits Stage3

15 bits Scale

12 bits

Data output

QOV 2 bit unconditional down shift

Figure 5: Internal Wordlengths

QSC

LATENCY
The CS2460 function has a fixed latency of 140 clock cycles, as shown in Figure 6. The first transformed data of a 64-point block is 140 clock cycles behind the first data of the corresponding input block. A version of the core with no reorder of the outputs is also available. This has a reduced latency of 89 clock cycles. Signal enable_out gets asserted when the first data of the output block appears on the output port and remains asserted until the last data is outputted. The signal DBSO is asserted for two clock cycles when the first data of each output block appears. 4

OUTPUT DATA ORDER

The transformed data is clocked out in normal order, as illustrated in Figure 6.

TM

140 cycles CLK enable_in Ich_in I block (n+3)

I block n

I block (n+1)

Qch_in enable_out

Q block n

Q block (n+1)

Q block (n+3)

Ich_out Qch_out QOV

0 1 2 3 4 5 0 1 2 3 4 5

62 63 62 63

overflow occurs DBSO 2*CLK

Figure 6: Transformed Data Output Operation

TRANSFORM TIME
When clocked at 50 MHz, for example, with continuous input data, the CS2460 64-point FFT/IFFT core achieves the following transform time: 64 point transform time = 64 x 1/50 x 106 = 1.28s

Table 2: CS2460 Timing Characteristics

Characteristic
Clock Frequency Input setup time Input hold time Signal BSY and QOV output delay Other output delay

Min

Max
60

Units
MHz ns ns

4.5 0 8.8 10

TIMING CHARACTERISTICS
Table 2, represents the timing characteristics of CS2460 64point FFT/IFFT, implemented on a EP20K600EBC652-1X device under the commercial temperature range operating conditions.

ns ns

AVAILABILITY AND IMPLEMENTATION INFORMATION

Amphion offers the CS2460 core in ASIC and programmable logic versions. Consult your local Amphion representative for product specific performance information, current availability of individual products, and lead times on ASIC or different programmable logic core porting. The implementation information provided in Table 3 has been obtained for a stand-alone design on a Altera EP20K600EBC652-1X device. It should be noted that if CS2460 is implemented on different Altera devices, the performance metrics and density might vary accordingly. Table 3: Programmable Logic Cores PRODUCT SILICON PROGRAMMABLE MAXIMUM DEVICE RESOURCES DEVICE RESOURCES ID VENDOR LOGIC PRODUCT FREQUENCY (MHz) USED (LOGIC) USED (MEMORY) CS2460 Altera* Apex20K600E-1 60 5078 LCs 12 ESBs AVAILABILITY Now

* The implementation information on ASIC or Xilinx devices is available upon request.

CS2460 64-Point Pipelined FFT/IFFT

Virtual Components for the Converging World

TM

ABOUT AMPHION
Amphion (formerly Integrated Silicon Systems) is the leading supplier of speech coding, video/ image processing and channel coding application specific silicon cores for system-on-a-chip (SoC) solutions in the broadband, wireless, and mulitmedia markets.

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05/02 Publication #: DS2460 v1.0