Department of Computer & Information Sciences

CS106
Autumn, 2012

Computer Systems and Organisation

Every Week Duration: Semester 1

A Compendium of Exam-Style Questions

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Introduction

1. Transistors and Valves (a) How many terminals does a standard bipolar junction transistor have? What are the standard names given to these terminals? What are their roles in the transistors function? (1 mark) (b) A transistor can function as an amplier or as a simple switch. Explain what distinguishes these uses. (2 marks) (c) In what way are transistors like their predecessors, thermionic valves? In what ways are transistors preferable as components of digital logic circuits? (2 marks)

2. Moores Law and its Implications (a) What did Moores Law predict about the number of transistors on integrated circuits in the twentieth century? In what way did Moores prediction take manufacturing cost into account? Is the same trend continuing in the twenty-rst century? If not, why not? (2 marks) (b) What does Moores Law predict about the clock rate of processors? How did the clock rate of processors evolve in the twentieth century? Is the same trend continuing in the twenty-rst century? If not, why not? (2 marks) (c) In the twenty-rst century, what implications does Moores Law have for the speed of computation? In what way, if any, do changes in chip technology impact on changes in the design of efcient algorithms? (1 mark)

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3. (a) Briey state Moores Law. Does it continue to hold? (1 mark) (b) What are the implications of Moores Law for the amount of RAM computers can readily support? (1 mark) (c) What impact, if any, does Moores Law currently have on clock speed? What other factors affect clock speed? (2 marks) (d) How is Moores Law contributing to faster program execution for some programs? (1 mark)

4. Conceptual Distinctions (a) Explain the distinction between assembly language and machine code. What benets does this distinction bring? (1 mark) (b) Explain the distinction between high-level programming languages and assembly languages. How might changes to the design of a processor affect changes in the design of both sorts of language (for programs to run on that processor)? (2 marks) (c) Explain the distinction between a compiler and an interpreter. Why might you sometimes prefer a compiler to an interpreter? Why might you sometimes prefer an interpreter to a compiler? (2 marks)

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5. A Carefully Assembled Puzzle I have the following software, in the given languages: a BASIC interpreter, in 6502 assembly language a 6502 assembler, in 6502 machine code a 6502 emulator, in C a compiler from C to x86 assembly language, in x86 machine code an x86 assembler, in x86 machine code a nave compiler from Java to BASIC, in BASIC an optimizing compiler from Java to x86 assembly language, in Java I do not have a 6502-based computer. Fortunately, I do have an x86-based computer. Moreover, I can feed the output from one program into another. (a) Explain how, given the above, I can construct a 6502 emulator in x86 machine code. (2 marks) (b) Explain how, given the above, I can run BASIC programs on an x86 machine. (1 marks) (c) Explain how, given the above, I can construct an optimal process compiling from Java to optimized x86 machine code, with both the compilation process and its resulting code running on my x86-based computer. (2 marks)

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Data and Functions

6. Compare and Swap I have functions min :: (Integer, Integer) Integer max :: (Integer, Integer) Integer respectively returning the lesser and greater of a pair of integer inputs. (a) By drawing a diagram or giving an equation, show how to dene cas, for compare and swap, a function which takes a pair of integers and returns those two integers in a pair sorted into increasing order. Remember to include the type of cas. (1 mark) (b) Here is a denition of a sorting function, using cas. sort :: (Integer, Integer, Integer, Integer) -> (Integer, Integer, Integer, Integer) sort-----|---|---|---|--------[cas] | | | | | | | [cas] | | | | | [cas] [cas] | | | | | [cas] | | | | | [cas] | | ---------|---|---|---|--------Trace the evaluation of sort(4, 3, 2, 1) by copying the diagram and labelling the wires with the numbers they carry. (2 marks)

Qu. 6 CONTINUED ON NEXT SHEET

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6. (c) The wcup function uses cas components to rank four inputs by rst comparing in pairs (like the seminals of the World Cup), then comparing the two losers (like the third-fourth playoff in the World Cup) and the two winners (like the World Cup nal). wcup :: (Integer, Integer, Integer, Integer) -> (Integer, Integer, Integer, Integer) wcup-----|---|---|---|--------[cas] [cas] | \ / | | % | | / \ | [cas] [cas] ---------|---|---|---|--------Find an input quadruple which is not correctly sorted by wcup. Show how to x wcup by adding one extra cas component to the circuit. (2 marks)

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7. Translate and Evaluate (a) Here is a wiring diagram representing a function. foo :: (Integer, Integer) -> Integer foo-----------|---|----------/ / / \ / / | [ * ] / | / [ + ] ----------------|------------Dene foo equivalently by giving a suitable type signature and equation. (2 marks) (b) Here is an equational denition of a function. goo :: (Integer, Integer) -> Integer goo (x, y) = x * x + y Dene goo equivalently by giving a suitable type signature and wiring diagram. (2 marks) (c) Evaluate foo(goo(2, 3), 5). Give a trace in which you rewrite one function application or arithmetic operation per step. (1 mark) 8. (a) Express 109 as an 8-bit binary number. (1 mark) (b) Express -76 as a binary number in 8-bit twos complement representation. (c) Add your answers to parts (a) and (b) to give their 8-bit binary sum. Show your working, clearly indicating the carry from each column. (1 mark) (d) What decimal number does your answer to part (c) represent? (1 mark) (e) Explain how to detect overow in twos complement addition and indicate whether overow occurred in part (c). (1 mark) PLEASE TURN OVER Page 7 of 24

9. (a) What are the lowest and highest numbers representable in 8-bit twos complement encoding. Give your answers both in signed decimal notation and in their 8-bit binary encoding. (1 mark) (b) Express the decimal number 105 in 8-bit twos complement binary representation. (1 mark) (c) Express the decimal number -38 in 8-bit twos complement binary representation. (1 mark) (d) Working in binary, compute the sum of your answers to parts (b) and (c), giving your answer in 8-bit binary representation, and in signed decimal representation. (1 mark) (e) Express you answer to part (d) in hexadecimal. (1 mark)

10. Consider the message:

PROPERCOPPERCOFFEEPOT

(a) Use Huffmans method to give a binary coding for each of the letters in the message which will optimally compress it. (3 marks) (b) Calculate the length of the bit sequence which encodes the message. (1 mark) (c) I propose to solve part (a) with the coding P0001, E1001, O101, R11, F000, C100, T10. What is wrong with my proposed solution? (1 mark)

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11. Consider the following message:

APINEAPPLEJELLY
Eric tries to encode this message using Huffmans method, producing the following coding tree, resulting in the codes given on the right: [0] 15 [0] [1] 12 [0] [0] [1] 9 [0] [1] 6 [1] 4 [0] [1] 3 [0] [1] 2 [1] 3 3 3 2 1 1 1 1 P L E A I J N Y 0 10 110 1110 11110 111110 1111110 1111111

(a) Eric claims his coding is prex-free. Explain what he means. Is this claim correct? (1 mark) (b) Eric has not followed Huffmans method correctly. Can you point out his mistake? (1 mark) (c) Construct a correct Huffman coding for this message. (2 marks) (d) Find the length of the encoded message, rst using Erics coding, then using yours. (1 mark)

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12. Jake tries to use Huffmans method to encode this message:

SKIBOODILYBOODILYBOODILYBOO
He draws this coding tree, then reads off his codes, shown to the right: [0] [0] [1] 19 [0] [0] [1] 15 [0] [1] 11 [1] 8 [0] [1] 5 [0] [1] 2 [1] 8 4 4 3 3 3 1 1 O B I D L Y K S 0 10 110 1110 11110 111110 1111110 1111111

27

(a) Jake claims his coding produces a shorter bit sequence for this message than any xed-length encoding of the eight symbols used. Is he right? Explain why. (1 mark) (b) Jake has not followed Huffmans method correctly. Can you point out his mistake? (1 mark) (c) Construct a correct Huffman coding for this message. (2 marks)

(d) Find the length of the encoded message. Give, in lowest terms, the compression ratio your encoding achieves compared to the best possible xed-length encoding. (1 mark)

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Machines Like TINY

13. (a) Can the execution of the TINY halt by executing the HLT instruction if (i) its initial conguration contains no HLT instruction? (1 mark) (ii) its initial conguration contains neither a HLT nor a STA instruction? (1 mark) (b) Copy and complete the following execution trace table for the TINY machine, starting in the given initial conguration, with the input queue initially holding 9A0. The rst step has been done for you. To save time, you need record the contents of memory and registers only when they are updated. You are not required to compute the behaviour of the overow ag, but you should be accurate in your calculation of the carry and zero ags. Registers Main Memory Trace IP LI FR AC 0 1 2 3 4 5 6 7 8 9 A B C D E F Operator Operand Input 0 1 . . . 0 . . . 0 0 . . . 0 9 . . . 6 5 4 3 2 4 8 7 C B A 8 5 8 1 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GET . . . . . . 9 . . . . . .

Output

The TINY machine description has been provided for you in a handout. (3 marks)

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14. (a) Explain how a typical von Neumann architecture allows self-modifying code? (1 mark) (b) The TINY machine has a typical von Neumann architecture. A handout describing the TINY machine has been provided for you. Copy and complete the following execution trace table for the TINY machine, starting in the given initial conguration, with the input queue initially holding 5AA5. The rst step has been done for you. To save time, you need record the contents of memory and registers only when they are updated. You are not required to compute the behaviour of the overow ag, but it is crucial to be accurate in your calculation of the carry and zero ags. Registers Main Memory Trace IP LI FR AC 0 1 2 3 4 5 6 7 8 9 A B C D E F Operator Operand Input 0 1 . . . 0 . . . 0 0 . . . 0 B 6 5 7 6 5 9 4 F 2 F 7 3 1 0 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCF . . . . . . . . . . . .

Output

(4 marks)

15. (a) With reference to its components, explain how a typical von Neumann architecture makes it possible to download a program from the internet and run it. (2 marks) (b) The TINY machine has a typical von Neumann architecture. A handout describing the TINY machine has been provided for you. Copy and complete the following execution trace table for the TINY machine, starting in the given initial conguration, with the input queue initially holding 67B36070. The rst step has been done for you. To save time, record the contents of memory and registers only when they are updated. Registers Main Memory Trace IP LI FR AC 0 1 2 3 4 5 6 7 8 9 A B C D E F Operator Operand Input 0 1 . . . 0 . . . 0 0 . . . 0 6 . . . 6 5 6 6 5 7 1 0 6 5 E 6 5 F 1 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GET . . . . . . 6 . . . . . .

Output

(3 marks)

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16. Consider the following program, written in TINY assembly language. start: SCF loop: GET STA temp GET FLA ADC temp PUT JMP loop temp: 0 A handout describing the TINY machine has been provided. (a) Assemble the above program, with start at location 0. Give the resulting memory conguration as 16 hexadecimal digits, lling unused locations with 0. Show your working. (3 marks) (b) Suppose this program is executed with all registers initially 0, and the input queue BEEF. What is the output? What happens in the end. (2 marks)

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17. Professor Quine has written the following program in TINY assembly language. A handout describing the TINY machine has been provided for you. start: LDA zero loop: STA load+1 load: LDA load+1 PUT LDA load+1 SCF ADC zero JNZ loop HLT zero: 0

(a) By keeping a running total of the instruction sizes, nd the addresses corresponding to the four labels in the Professors program. Start from 0. Give your answers in hexadecimal. (1 mark) (b) Assemble the Professors program, showing how it would be stored in the memory of the TINY machine. Recall that an operand load+1 refers to the memory address one after that labelled by load. Again, use hexadecimal notation. (2 marks) (c) The programs main loop modies the contents of memory address load+1. Suppose this address contains the value n when the three instructions LDA load+1 SCF ADC zero are executed. What value will the accumulator (AC) hold as a result? (1 mark) (d) If the Professors program is executed on the TINY machine, with all registers initially 0, what will be its output? (1 mark)

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18. Master Shrink has written the following program in TINY assembly language. A handout describing the TINY machine has been provided for you. start: GET JZE SCF FLA ADC STA JMP stop: LDA PUT HLT size: F

stop

size size start size

(a) By keeping a running total of the instruction sizes, nd the addresses corresponding to the three labels in the Masters program. Start from 0. Give your answers in hexadecimal. (1 mark) (b) Assemble Master Shrinks program, showing how it would be stored in the memory of the TINY machine. Again, use hexadecimal notation. (2 marks) (c) The programs main loop modies the contents of memory address size. Suppose this address contains the value n and the accumulator (AC) holds the value k when the three instructions SCF FLA ADC size are executed. What value will the accumulator hold as a result? (1 mark) (d) If Master Shrinks program is executed on the TINY machine, with all registers initially 0 and an input queue of 43210, what will be its output? (1 mark)

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Digital Logic

19. (a) According to De Morgans Law, how may we rewrite !(a+b) to move the negation further into the formula? Verify this law by constructing a truth table for both sides of it, with columns for all intermediate formulae involved in the calculation. (2 marks) (b) Explain what it means to say that
NAND

is a universal gate. (1 mark)

(c) There is another universal gate. Identify it, and show how to construct it from gates.

NAND

(2 marks)

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20. A control panel has four switches on it, named S, T , U and V , respectively. Each switch sends a 0 signal when its handle points downward and a 1 signal when its handle points upward. This is the current setting: 1 1 1 / / S T U V \ \ \ \ 0 0 0 1 / / 0

The control panel is wired both to the lock of a safe and to a burglar alarm. The setting on the control panel represents a number in 4-bit twos complement binary notation. (a) Which decimal number is indicated by the above setting? (1 mark) (b) To open the safe, you need to construct a circuit which connects the switches S, T, U, V to the release control R which will set R = 1 if and only if the correct combination is entered. An informant has discovered that the correct combination is 6. (i) Express the correct combination in 4-bit twos complement binary notation. (1 mark) (ii) Draw a diagram showing how to construct your release circuit from NAND gates. Be sure to label the inputs and outputs appropriately. (1 mark) (c) Your informant has also provided you with this circuit diagram for the alarm system: S T U V | | | | | | | | | | | | | | OR | | | | | | OR | | | | | | | | | | | XOR | | | NOT | | AND | A

The alarm will go off if the switch settings ever make A = 1. You can ick only one switch at a time. You need to ick switches in sequence to change from the current setting to the setting with the correct combination. You must not set off the alarm. List the switches you ick in order. At each step, say which signed decimal number the control panel setting represents.

(2 marks)

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21. (a) Explain what makes NAND a universal gate.

(1 mark)

(b) Identify the other universal gate and show how to construct it from NAND gates. (2 marks) (c) The phase counter for a set of trafc lights is a 2-bit binary counter signal, cycling through 0 for red, 1 for red and amber, 2 for green and 3 for amber. Given this signal on two input wires (twos then ones), construct control circuitry for each of the red, amber and green lamps, using at most four NAND gates (and no other gates) in total. (2 marks)

22. (a) Write the truth table for a half adder. (1 mark) (b) Draw a circuit diagram showing how to construct a half adder from standard gates drawn from {AND, OR, NOT, XOR, NAND, NOR}. (1 mark) (c) Show how to construct a full adder from two half adders and one other standard gate. (1 mark) (d) Show how to construct a ripple-carry adder for two 4-bit binary numbers and a carryin from four full adders. (1 mark) (e) Using one 4-bit ripple-carry adder (as in part (d)), a source of logic 0, any amount of wiring, but no other components, show how to construct a circuit which triples a 4-bit number, giving a 5-bit answer. (1 mark)

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23. You have been equipped with a generous supply of AND, XOR and NOT gates, but no other components. You have access to a constant signal of logic 0. (a) Show how to construct a half-adder circuit from the given components. (1 mark)

(b) Show how to construct a full-adder from two half-adders and one more given gate. (1 mark) (c) Show how to construct a circuit which subtracts one 4-bit binary number from another. Hint: construct a ripple-carry adder, then modify it to perform subtraction. (2 marks) (d) Show how to extend your answer to part (c) with an extra output bit which signals 1 exactly when twos complement overow occurs. (1 mark)

Clocks and Memory

24. (a) Write the truth table for a T ip-op. (1 mark) (b) Write the characteristic table for a D ip-op. (1 mark) (c) Write a truth table with inputs T and Q(t) and output D such that sending a D ip-op the D output would deliver the behaviour of a T ip-op for the given input signal and state. (1 mark) (d) Draw a diagram showing how to construct a circuit with the functionality of a T ipop from a D ip-op and additional circuitry build from any number of standard gates AND, OR, NOT, XOR. (2 marks)

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25. Consider the circuit shown to the right. At time t, the input signals X(t) and Y (t) deliver bit t of two binary numbers, counting the ones as bit 0, the twos as bit 1, and so on. The circuit performs one column of calculation in one unit of time. The output signal Z(t) gives bit t of the result. The JK ip-op is used to manage the carry from one column to the next, with Q(0) = 0.

X Y | | | | | | | | | | | | | | | | | | | | | NOT | | NOT | | | | | | | | AND AND XOR | | | | | J K | | | Q | | | | | | XOR | | Z

(a) Give the characteristic table for a JK ip-op. (1 mark) (b) Construct the truth table for controls J(t) and K(t) in terms of inputs X(t) and Y (t). (1 mark) (c) Give the whole circuits truth table, showing how Q(t + 1) and Z(t) are determined. (1 mark) (d) Copy and complete the following time trace, lling in successive states and outputs. t 0 1 2 3 4 5 X(t) Y (t) Q(t) Z(t) 0 1 0 1 1 1 1 1 1 0 1 0 0

(1 mark) (e) What calculation is being performed? With what output? Answer in decimal. (1 mark)

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26. Your task is to nish this adding machine, built from an SR ip-op and four standard gates: X Y | | | | | | | | | | | | | | | | | | | | | g1 ? g2 ? g3 ? | | | | R | S | | | Q | | | | | | g4 ? | | Z The unknown gates g1 , g2 and g3 each receive input signals X and Y . The outputs from g1 and g2 control the ip-op, while g4 combines the ip-ops Q output with g3 s output to give the overall output signal Z. At time t, the input signals X(t) and Y (t) deliver bit t of the two numbers to be added, counting the ones as bit 0, the twos as bit 1, and so on. The output signal Z(t) should give bit t of the sum. The ip-op should be used to store the carry from one column to the next, with Q(0) = 0.

(a) Give the characteristic table for an SR ip-op, writing ? for any undened entries. (1 mark) (b) Give the truth table for a full adder, labelling the input and output columns withX, Y , Q or Z signals expressed in terms of t, thus describing the correct evolution of the adding machine at any given time. (1 mark) (c) Construct a truth table showing how to calculate the control signals S(t) and R(t) from the inputs X(t) and Y (t), so that the system performs carrying correctly. (You may nd it useful to refer to your earlier tables and see how Q changes for each possible X and Y .) Identify which standard logic gates g1 and g2 must be. (2 marks) (d) Choose suitable standard logic gates for each of g3 and g4 to ensure that Z(t) is always correctly computed. (1 mark)

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Coordination and Concurrency

27. Here are three transaction processes, P , Q and R, expressed in terms of assignment and locks. P lock x { lock y { Q lock x { R lock y { x=x+y x=y+x+y y=5 }} } } Note that if one process holds a lock on a variable, other processes must wait to read, write or lock that variable. Variables in expressions are read in left-to-right order. Suppose that, initially, x = 20 and y = 10. (a) Identify all possible outcomes if P and Q execute concurrently. (1 mark) (b) Identify all possible outcomes if Q and R execute sequentially, either way round. (1 mark) (c) Apart from any outcomes identied in part (b), what other outcome is possible if Q and R execute concurrently? How is it possible? (1 mark) (d) In order to exclude part (c)s outcome, programmer Nick modies Q as follows. Q lock y { lock x { x=y+x+y }}

(i) Has Nick excluded part (c)s outcome by replacing Q with Q ? Briey explain. (1 mark) (ii) Has Nick made any outcomes, other than those in part (a), possible if P and Q execute concurrently? (1 mark)

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28. A simple language has assignment, sequencing and lockable variables. The construct lock var {code} will wait until the lock on var becomes available and take the lock, then execute code, then release the lock. Three transactions, P, Q and R, are implemented in this language: P: lock x { lock y { x = x + 5; y = y - 5 } } Q: lock y { lock z { y = y + 10; z = z - 10 } } R: z = z + 15; x = x - 15

In each of the following, assume that initially x=y=z=30. (a) What will the nal values of x, y and z if P, Q and R execute once each, in sequence? (1 mark) (b) Which other outcomes are possible if P, Q and R execute once each, concurrently? (2 marks) (c) Give a modied version of program R which ensures that the outcome from concurrent execution is bound to agree with the sequential outcome. How does your program avoid deadlock? (2 marks)

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29. A simple language has assignment, sequencing and lockable variables. The construct lock var {code} will wait until the lock on var becomes available and take the lock, then execute code, then release the lock. The transactions P and Q are implemented in this language: P: x = x + 20; y = y - 20 Q: x = x - 10; y = y + 10 Alternative locking versions of these transactions are implemented as follows: P: lock x { lock y { x = x + 20; y = y - 20 } } Q: lock y { lock x { x = x - 10; y = y + 10 } } P and Q execute concurrently, accessing the same data store where, initially, x=50 and y=100. One possible sequence of accesses is as follows P Q Q Q reads 50 from x; P writes 70 to x; reads 70 from x; P reads 100 from y; writes 60 to x; P writes 80 to y; reads 80 from y; Q writes 90 to y.

with the outcome that both transactions complete, leaving x=60 and y=90. (a) With different interleavings of access, different outcomes are possible. Find two different (from the above and each other) possible outcomes and specify the access sequences which deliver them. (2 marks) (b) Find an outcome which is possible when P and Q execute concurrently but excluded when P and Q execute concurrently, and give the excluded access sequence. (1 mark) (c) Suppose instead that P and Q execute concurrently. Final all possible results. (2 marks)

END OF PAPER
(Dr Conor McBride)

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