Nanotec Electronic GmbH Tel.

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IMT 902 Microstep Constant Current Driver for 2 Motors

2 stepping motors are controlled by a single driver IC Output voltage 40 V max Output current 1.5 A /phase max Two pairs of built-in 4-bit DACs for micro steps Two pairs of built-in 16-bit shift and latch registers 36-pin power flat package (HSOP36-P-450-0.65) Low On-resistance of Ron = 0.5 (Tj = 25C @ 1.0 A: Typ.) Chopping frequency can be set by external capacitors and resistors. High speed chopping possible at 100 kHz or higher Built-in charge pump circuit (two ext. capacitors)

RECOMMENDED AND MAXIMUM OPERATING CONDITIONS

(Ta = 0 to 85C)
Characteristic Logic Supply Voltage Output Voltage Output Current Logic Input Voltage Clock Frequency Chopping Frequency Reference Voltage Current Detect Pin Voltage Power Dissipation Operating Temp. Storage Temp. Junction Temp. Sym. VDD VM IOut (1) IOut (2) VIN fCLK fchop Vref VRS PD TOPR TSTG TJ Test Condition VDD = 5,0 V Ta = 25 C / Phase (one motor) Ta = 25 C / phase (two motors) VDD = 5,0 V VDD = 5,0 V VM = 24 V, Torque = 100% VDD = 5,0 V VIN 7V or less Measured for IC Min. 4.5 20 GND 1.0 40 2.0 0 Typ. 5.0 24 1.1 1.1 6.25 100 3.0 1.0 Max. 5.5 34 1.3 1.3 VDD 25 150 VDD 1.5 Peak 7.0 40 1.5 1.5 VDD+0.4 4.5 Unit V V A A V MHz KHz V V W C C C

1.4 3.2 - 40 ...+ 85 - 50 ...+ 150 + 150

Note: when using the IC, pay attention to thermal conditions.

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PIN ASSIGNMENT:

(top view)

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Munich - Germany

IMT 902

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PIN DESCRIPTION:
Pin No. 1 2 3 4 5 6 7 8 9 FIN 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FIN 28 29 30 31 32 33 34 35 36 Pin Symbol VM B OUT B RS B PGND OUT B\ LGND Ccp A CR VREF AB VSS (FIN) VREF CD NC Ccp B Ccp C OUT D\ PGND RS D OUT D VM D VM C OUT C\ RS C PGND OUT C STROBE CD CLK CD DATA CD VDD VSS (FIN) RESET\ DATA AB CLK AB STROBE AB OUT A PGND RS A OUT A\ VM A Description Power Supply for output B block Output B pin Channel B current pin Power GND pin Output B\ pin Logic GND pin Capacitor pin for charge pump (Ccp 1) (Capacitor C2, see Pg. 5) External C/R (osc) pin (sets chopping frequency) Vref input pin AB Logic GND pin Vref input pin CD Non conection Capacitor pin for charge pump (Ccp 2) (Capacitor C1, see Pg. 5) Capacitor pin for charge pump (Ccp 3) (Capacitor C1, see Pg. 5) Output D\ pin Power GND pin Channel D current pin Output D pin Power Supply for output D block Power Supply for output C block Output C\ pin Channel C current pin Power GND pin Output C pin CD STROBE (latch) signal input pin CD clock input pin CD serial data signal input pin Power pin for logic block Logic GND pin Output reset signal input pin AB serial data signal input pin AB clock input pin AB STROBE (latch) signal input pin Output A pin Power GND pin Channel A current pin Output A\ pin Power Supply for output A block

Note: All GND pins and FIN pins must be grounded. Since FIN also functions as a heat sink, take the heat dissipation into consideration when designing the board.

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Input equivalent circuit:

1) Logic input circuit (CLK, DATA, STROBE)

2)

Input circuit (RESET\)

Note: The RESET\ pin is pulled down. Do not use this pin open.

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Application example:
(A/B unit only. C/D unit in brackets)

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IMT 902

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Block Diagram:

(A/B unit, C/D unit is the same as A/B unit)

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Calculation of set current:

Determining RS and Vref determines the set current value.

I OUT =

Vref (V ) * HoldCurrent (= 1.0 / 0.85 / 0.7 / 0.5) 5 * RS ()

For example: To input Vref = 5.0 V and hold current = 100 % (= 1.0) and to output Iout = 1A, RS = 1 ( 1 W or more) is required.

Calculation of CR oscillation frequency (Chopping reference frequency):

The CR oscillation frequency and fchop can be calculated by the following formulas:

f CR =

1 [ Hz ] C * (0.523R + 313.8)

f chop =

f CR [ Hz ] 8

For example: When Cosc = 1 nF (=C3) and Rosc = 2200 (= R1) are connected to the CR pin, the oscillation frequency is calculated as 682 kHz. At this time the chopping frequency fchop is fCR/8 = 85.4 kHz.

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IC Power Dissipation:
Power consumed by the Power Transistor (calculated with RDS ON = 0.6 ):

2 P(out ) = 2(Tr ) * I out ( A) * VDS (V ) = 2 * I out * RDSon

Power consumed by the logic block:

Operating mode / unit when VDD is connected to 5V and VM is connected to 24V:

P = 5(V ) * 0.002( A) + 24(V ) * 0.0125( A) = 0.31(W )

Standby mode (RESET\=L) / unit:

P(standby ) = 24(V ) * 0.006( A) + 5(V ) * 0.002( A) = 0.154(W )

PD-Ta (Package power dissipation)

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Signal functions:
Serial data input setting:

Data input to the serial pin are 16-bit data transfered from DATA 0 to DATA 15. Data are input and transfered at the following timings: At clock falling edge: data input At clock rising edge: data transfer After data are transferred, all data are latched on the rising edge of the STROBE signal. As long as STROBE is not rising, the signal can be either low or high during data transfer.

Serial input signals (for A/B, C/D is the same as A/B):

DATA No. 0 LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MSB NAME Hold Current 0 Hold Current 1 Decay Mode B0 Decay Mode B1 Current B0 Current B1 Current B2 Current B3 Phase B Decay Mode A0 Decay Mode A1 Current A0 Current A 1 Current A 2 Current A 3 Phase A HH: 100% LH: 85% HL: 70% LL: 50% 00: Slow Decay 01: Mixed Decay 37.5 % 10: Mixed Decay 75% 11:Fast DEcay Used for setting current. (LLLL = output all off mode) 4-bit current B data (steps can be devidied into 16 by 4-bit data) Phase information: High = OUT B High, OUT B\ Low 00: Slow Decay 01: Mixed Decay 37.5 % 10: Mixed Decay 75% 11:Fast DEcay Used for setting current. (LLLL = output all off mode) 4-bit current A data (steps can be devidied into 16 by 4-bit data) Phase information: High = OUT A High, OUT A\ Low FUNCTIONS DATA No. 0,1:

Hold Current Functions (= current down; DATA No. 0, 1)

Hold Current 0 H L H L Hold Current 1 H H L L Comparator reference voltage ratio 100% 85% 70% 50%

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Decay Mode Functions (DATA No. 2, 3)

Decay Mode X1 Decay Mode X0 L L L H H L H H Function Slow Decay 0% Mixed Decay 37.5% Mixed Decay 75% Fast Decay 100%

Current Ax (Bx) functions (Data No. 4 to 7 and 11 to 14)

STEP 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET ANGLE 90.0 84.4 78.8 73.1 67.5 61.2 56.3 50.6 45.0 39.4 33.8 28.1 22.5 16.9 11.3 5.6 0.0 A3 H H H H H H H H H L L L L L L L L A2 H H H H H L L L L H H H H L L L L A1 H H H L L H H L L H H L L H H L L A0 H H L H L H L H L H L H L H L H L B3 L L L L L L L L H H H H H H H H H B2 L L L L H H H H L L L L H H H H H B1 L L H H L L H H L L H H L L H H H B0 L H L H L H L H L H L H L H L H H

By inputting the above current data, 16-microstep drive is possible.

Phase functions (Data No. 8 and 15)

INPUT H L FUNCTION Positive polarity (A = H, A\ = L) Negative polarity (A = L, A\ = H)

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INPUT CLK STROBE X X X X X X X X DATA X H L X X X RESET\ H H H H L X VDDR Or VMR H H H H X L TSD (1) / ISD(2) L L L L L L

ACTION

No change in shift register H level is input to shift register L level is input to shift register Shift register data are latched Output off, charge pump halted Output off, charge pump halted (only VDDR) Output off, charge pump halted Restored when Reset\ goes from low to high

X: Dont care VDDR: (return voltage VDD and VM) H when the operable range (3V typical) or higher and L when lower.
(1)

TSD:(Thermal shut down circuit): When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal reset circuit is activated switching the outputs of both motors off. When the temperature is set between 130 to 170C (max), the TSD circuit operates. When the TSD circuit is activated, the function data latched at that time are cleared. Output is halted until the reset is released. While the TSD circuit is in operation, the charge pump is halted. Even if the TSD circuit is activated and RESET goes H L H instantaneously, the IC is not reset until the IC junction temperature drops 35C (typ.) below the TSD operating temperature (hysteresis function) ISD: (Overcurrent protection circuit) When current exceeding the specified value flows to the output, the internal reset circuit is activated switching the outputs of both shafts to off. When the ISD circuit is activated, the function data latched at that time are cleared. Until the reset signal is input, the overcurrent protection circuit remains activated. During ISD the charge pump is halted. For failsafe operation be sure to add a fuse to the power supply.

(2)

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Application operation input data:

1/1 Step Hold Hold Current Current 0 1 B0 B1 B2 B3 Phase B A0 Decay A0 Decay A1 A1 A2 A3 Phase A

Decay B0 2 1 1 1 1

Bit 1 2 3 4

0 1 1 1 1

1 1 1 1 1

Decay B1 3 0 0 0 0

4 1 1 1 1

5 1 1 1 1

6 1 1 1 1

7 1 1 1 1

8 1 0 0 1

9 1 1 1 1

10 11 12 13 14 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1

15 1 1 0 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) reqires input of the STROBE signal. Hold Current is set to 100%. Output current waveform of 2-phase excitation sine wave:

1/2 Step Decay B0 Decay B1 Decay A0 Decay A1 Hold Hold Current Current 0 1 B0 B1 B2 B3 Phase B A0 A1 A2 A3 Phase A

Bit 1 2 3 4 5 6 7 8

0 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1

2 1 1 1 1 1 1 1 1

3 0 0 0 0 0 0 0 0

4 1 0 0 0 1 0 0 0

5 1 0 0 0 1 0 0 0

6 1 0 0 0 1 0 0 0

7 1 1 0 1 1 1 0 1

8 1 1 1 0 0 0 0 1

9 1 1 1 1 1 1 1 1

10 11 12 13 14 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1

15 1 1 1 1 0 0 0 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) reqires input of the STROBE signal. Hold Current is set to 100%.

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Output current waveform of 1-2 phase excitation sine wave:

1/4 Step Hold Hold Current Current 0 1 B0 B1 B2 B3 Phase B A0 Decay A0 Decay A1 A1 A2 A3 Phase A

Decay B0

Bit 0 1 2 3 4 5 6 7 8 1 1 1 1 0 1 1 1 1 1 2 1 1 1 0 0 0 1 1 1 3 1 1 1 0 0 0 0 1 1 4 1 1 1 0 0 0 1 0 1 5 1 1 1 0 0 0 0 0 1 6 1 1 1 0 0 0 1 0 0 7 1 1 1 0 0 0 0 1 0 8 1 1 1 0 0 0 1 1 0 9 1 1 1 0 1 1 1 1 0 10 1 1 1 0 0 0 1 1 0 11 1 1 1 0 0 0 0 1 0 12 1 1 1 0 0 0 1 0 0 13 1 1 1 0 0 0 0 0 0 14 1 1 1 0 0 0 1 0 1 15 1 1 1 0 0 0 0 1 1 16 1 1 1 0 0 0 1 1 1 Data are input on the rising edge of CLK. Every input of a the STROBE signal. Hold Current is set to 100%.

Decay B1

9 10 11 12 13 14 15 1 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 1 1 1 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 data string (16-bit) reqires input of

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1/8 Step Hold Hold Current Current 0 1

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Decay B0

Decay B1

Decay A0

Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

5 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

6 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1

7 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1

8 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

10 11 12 13 14 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0

Decay A1

B0 B1 B2 B3 Phase B

A0

A1

A2

A3 Phase A

15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) reqires input of the STROBE signal. Hold Current is set to 100%.

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1/16 Step Hold Hold Current Current 0 1

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Decay B0

Decay B1

Decay A0

Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1

5 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1

6 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0

7 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0

8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

10 11 12 13 14 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 1

Decay A1

B0 B1 B2 B3 Phase B

A0

A1

A2

A3 Phase A

15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

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47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) reqires input of the STROBE signal. Hold Current is set to 100%.

Output current waveform of pseudo sine wave:

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Electrical Characteristics:
CHARACTERISTIC Input Voltage Low VIN (L) Input Current 1 Input Current 2 IIN1 (H) IIN1 (L) IIN2 (H) IIN2 (L) IDD 1 Power Dissipation (VDD pin) IDD 2 SYMBOL TEST CONDITION CLK, RESET\, STROBE, DATA Pins CLK, STROBE, DATA Pins RESET\, (SETUP H) VDD=5V (STROBE, RESET\, DATA = L) logic, output all off Output open, fCLK=6.25MHz Logic active, VDD=5V Charge pump=charged Output open (STROBE, RESET\, DAT = L) Logic, output all off Charge pump = no operation Output open, fCLK = 6.25 MHz, logic active, VDD=5V, VM=24V,output off Charge pump=charged Output open, fCLK = 6.25 MHz, logic active, 100kHz chopping, output open, charge pump=charged, Ccp1=0.22F, Ccp2=0.01F VRS=VM=24V, VOut=0V, RESET\=H, DATA all L VRS=VM=24V, VOut=24V, RESET\=H, DATA all L VRS=VM=Ccp A=VOUT=24V, RESET\ =L Vref=3.0 V, Hold Current=(H.H)=100% Vref=3.0 V, Hold Current =(H.L)=85% Vref=3.0 V, Hold Current =(L.H)=70% Vref=3.0 V, Hold Current =(L.L)=50% MIN 2.0 GND - 0.4 TYP VDD GND 3.0 MAX VDD +0.4 0.8 1.0 1.0 700 700 6.0 mA 4.0 80 A A UNIT V

High VIN (H)

IM 1

5.0

6.0

Power Dissipation (VM pin)

IM 2

12

20

mA

IM 3

30

40

Output Standby Current

Upper

IOH

-400

Output Bias Upper Current Output Leakage Current Lower High Comparator Referece Voltage Ratio Mid High Mid low Low

IOB IOL VRS (H) VRS (MH) VRS (ML) VRS (L)

-200

83 68 48

100 85 70 50

1.0 87 % 72 52

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CHARACTERISTIC Output current differential Output current setting differential RS pin current SYMBOL IOut1 IOut2 IRS RON (D-S) 1 Output transistor drain-source onresistance RON (D-S) 1 RON (D-S) 2 RON (D-S) 2 Vref input voltage Vref input current TSD temperature TSD return temperature difference VDD return voltage VM return voltage Over current protected circuit operation current Vref Iref TjTSD TjTSD VDDR VMR ISD

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TEST CONDITION Differences between output current channels IOut = 1000mA IOut=1000mA VRS=24V, VM=24V, RESET\=L (reset status) IOut=1.0A, VDD=5V, Tj=25C,Drain-Source IOut=1.0A, VDD=5V, Tj=25C,Source-Drain IOut=1.0A, VDD=5V, Tj=105C,Drain-Source IOut=1.0A, VDD=5V, Tj=105C,Source-Drain VM=24V, VDD=5V, RESET\=H output on RESET\=H, output off, VM=24V, VDD=5V Vref=3.0V VM=24V, VDD=5V TjTSD=130 to 170C VM=24V, RESET\=H, STROBE=H VDD=5V, RESET\=H, STROBE=H VDD=5V, VM=24V, fchop=100 kHz set

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MIN -5 TYP MAX 5 UNIT %

-5 2.0

0.5 0.5 0.5 0.5 -

5 10 0.6 0.6 0.75 0.75 VDD 100 170

% A

0 130 2.0 2.0 -

Tj TSD -35 2.6

A C C

4.0 4.0 -

V V A

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AC Characteristics:
CHARACTERISTIC SYMBOL TEST CONDITION Clock frequency fCLK tw(clk) Minimum clock pulse twp(clk) width twn(clk) tSTROBE Minimum STROBE tSTROBE (H) pulse width tSTROBE (L) tsuSINCLK Data setup time tsuST-CLK thSINCLK Data hold time thCLK-ST tr Output load tf 6.8mH/5.7 STROBE (L H) to tpLH (ST) VOut Output transistor Output load switching tpHL (ST) characteristics 6.8mH/5.7 CR to VOut tpLH (CR) Output load tpHL (CR) 6.8mH/5.7 Noise rejection dead Iout=1.0A tBLNK band time Cosc=560pF, CR reference signal fCR oscillation frequency Rosc=3.6k Output active fchop (min) (Iout=1.0A) Chopping frequency Step fixed, fchop (typ) range Ccp1=0.22F, fchop (max) Ccp2=0.01F Output active Chopping frequency fchop (Iout=1.0A) Ccp2=0.22F, Ccp=0.01F Charge pump rise tONG VM=24V, VDD=5V time Reset\ = L H MIN 1.0 40 20 20 40 20 20 20 20 20 20 200 TYP 0.1 0.1 15 10 1.2 2.5 300 736 MAX 25 400 ns kHz s ns UNIT MHz ns

ns

ns

40

100

150

kHz

100

kHz

ms

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Package Dimensions :
Unit: mm HSOP36-P-450-0.65

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