Chapter-1

FIELD PROGRAMMABLE GATE ARRAY (FPGA)

1.1 INTRODUCTION
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturinghence "fieldprogrammable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications. FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together" somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. In addition to digital functions, some FPGAs have analog features. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow. Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed signal FPGAs" have integrated peripheral Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip. Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal 1

programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

1.2 FPGA MANUFACTURERS

There are (at least) 5 companies making FPGAs in the world. The first two (Xilinx and Altera) hold the bulk of the market.

Xilinx invented the FPGA and is the biggest name in the FPGA world. Altera is the second FPGA heavyweight, also a well-known name. Lattice, Actel and SiliconBlue are smaller players.

Xilinx

Xilinx has traditionally been the density and technology leader. Xilinx general philosophy is to provide all the features possible, at the cost of extra complexity.

Biggest and most flexible (feature-full) devices. Complex architecture, powerful devices.

Altera

Altera philosophy is to provide the features that most people want while keeping their devices easy to use.

Lean and efficient devices architecture. Powerful devices. A recent trend has been to take the coarse-grained architectural approach a step

further by combining the logic blocks and interconnects of traditional FPGAs with embedded microprocessors and related peripherals to form a complete "system on a programmable chip". In 2010, an extensible processing platform was introduced for 2

FPGAs that fused features of an ARM high-end microcontroller (hard-core implementations of a 32-bit processor, memory, and I/O) with an FPGA fabric to make FPGAs easier for embedded designers to use. By incorporating the ARM processor-based platform into a 28 nm FPGA family, the extensible processing platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenges they face in designing today's embedded systems, which must meet ever-growing demands to perform highly complex functions. By allowing them to design in a familiar ARM environment, embedded designers can benefit from the time-to-market advantages of an FPGA platform compared to more traditional design cycles associated with ASICs. An alternate approach to using hard-macro processors is to make use of soft processor cores that are implemented within the FPGA logic. MicroBlaze and Nios II are examples of popular softcore processors. As previously mentioned, many modern FPGAs have the ability to be reprogrammed at "run time," and this is leading to the idea of reconfigurable computing or reconfigurable systems CPUs that reconfigure themselves to suit the task at hand. Additionally, new, non-FPGA architectures are beginning to emerge. Softwareconfigurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.

1.3 ARCHITECTURE
The most common FPGA architecture consists of an array of logic blocks (called Configurable Logic Block, CLB, or Logic Array Block, LAB, depending on vendor), I/O pads, and routing channels. Generally, all the routing channels have the same width (number of wires). Multiple I/O pads may fit into the height of one row or the width of one column in the array. An application circuit must be mapped into an FPGA with adequate resources. While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. For example, a crossbar switch requires much more routing than a systolic array with the same gate count. Since unused routing tracks increase the cost 3

(and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of Lookup tables (LUTs) and IOs can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs. In general, a logic block consists of a few logical cells. A typical cell consists of a 4-input LUT, a Full adder (FA) and a D-type flip-flop, as shown below. The LUTs are in this figure split into two 3-input LUTs. In normal mode those are combined into a 4input LUT through the left mux. In arithmetic mode, their outputs are fed to the FA. The selection of mode is programmed into the middle multiplexer. The output can be either synchronous or asynchronous, depending on the programming of the mux to the right, in the figure example. In practice, entire or parts of the FA are put as functions into the LUTs in order to save space.

Figure1.1: Illustration of a logic cell

In recent years, manufacturers have started moving to 6-input LUTs in their high performance parts, claiming increased performance.

1.4 INTERCONNECTION OF LOGIC CELLS

Each logic-cell can be connected to other logic-cells through interconnect resources (wires/multiplexers placed around the logic-cells). Each cell can do little, but with lots of them connected together, complex logic functions can be created.

Figure1.2Interconnectionoflogiccells

Since clock signals (and often other high-fanout signals) are normally routed via specialpurpose dedicated routing networks in commercial FPGAs, they and other signals are separately managed. For this example architecture, the locations of the FPGA logic block pins are shown below.

Figure1.3:Logic Block Pin Locations Each input is accessible from one side of the logic block, while the output pin can connect to routing wires in both the channel to the right and the channel below the logic block. Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it.Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent to it. For example, an I/O pad at the top of the chip can 5

connect to any of the W wires (where W is the channel width) in the horizontal channel immediately below it. Generally, the FPGA routing is unsegmented. That is, each wiring segment spans only one logic block before it terminates in a switch box. By turning on some of the programmable switches within a switch box, longer paths can be constructed. For higher speed interconnect, some FPGA architectures use longer routing lines that span multiple logic blocks. Whenever a vertical and a horizontal channel intersect, there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure below illustrates the connections in a switch box.

Figure1.4: Switch box topology Modern FPGA families expand upon the above capabilities to include higher level functionality fixed into the silicon. Having these common functions embedded into the silicon reduces the area required and gives those functions increased speed compared to building them from primitives. Examples of these include multipliers, generic DSP blocks, embedded processors, high speed IO logic and embedded memories.

FPGAs are also widely used for systems validation including pre-silicon validation, post-silicon validation, and firmware development. This allows chip companies to validate their design before the chip is produced in the factory, reducing the time-to-market. To shrink the size and power consumption of FPGAs, vendors such as Tabula and Xilinx have introduced new 3D or stacked architectures. The technology stacks several (three or four) active FPGA dice side-by-side on a silicon interposer a single piece of silicon that carries passive interconnect.

1.5 FPGA PINS

FPGAs tend to have lots of pins and they are divided into "user pins" and "dedicated pins". User pins The user pins are called "IOs". IO stands for "input-output".

Users have total control over user IOs. They can be programmed to be inputs, outputs, or bi-directional (i.e. with tri-state buffers).

Each IO pin is connected to an "IO cell" inside the FPGA. The "IO cells" are powered by the VCCIO pins (IO power pins) - more details below.

Dedicated pins The "dedicated pins" are hard-coded to a specific function. They fall into the three following sub-categories.

Power pins. Configuration pins: used to "download" the FPGA. Dedicated inputs, or clock pins: these are able to drive large nets inside the FPGA, suitable for clocks or signals with large fan-outs.

The power pins fall into two categories: "core voltage" and "IO voltage".

The core voltage is named "VCC" for Xilinx and "VCCINT" for Altera. It is set by the model of FPGA that is being used. It is used to power the logic gates and flipflops inside the FPGA. The voltage was 5V for older FPGA generations, and is

coming down as new generations come (3.3V, 2.5V, 1.8V, 1.5V, 1.2V and even lower for the latest devices).

The IO voltage is named "VCCO" for Xilinx and "VCCIO" for Altera. It is used to power the I/O blocks (= pins) of the FPGA. That voltage should match what the other devices connected to the FPGA expect.

An FPGA has many VCCIO pins that may be all powered by the same voltage. But new generations of FPGAs have a concept of "user IO banks": the IOs are split into groups, each having its own VCCIO pins. That allows using the FPGA as a voltage translator device, useful for example if one part of your board works with 3.3V logic, and another with 2.5V.

1.6 FPGA CONFIGURATION

An FPGA can be into 2 states: "configuration mode" or "user mode". When the FPGA wakes up after power-up, it is in configuration mode, sitting idle with all its outputs inactive. You need to configure it. Configuring an FPGA means downloading a stream of 0's and 1's into it through some special pins. Once the FPGA is configured, it goes into "user-mode" and becomes active, performing accordingly to your programmed "logic function". There are 3 classical ways to configure your FPGA:

You use a cable from your PC to the FPGA, and run a software on your PC to send data through the cable.

You use a microcontroller on your board, with an adequate firmware to send data to the FPGA.

You use a "boot-PROM" on your board, connected to the FPGA, that configures the FPGA automatically at power-up (FPGA vendors have such special bootPROMs in their catalogs)

During development, the first method is the easiest and quickest. Once your FPGA design works, you probably don't need the PC anymore, so the other 2 methods come in use. Configuration works in a surprisingly identical way between Xilinx and Altera devices. The differences is mostly in the naming (pin names and modes of operation are named differently), but the functionality provided is similar. 8

Most FPGAs can be be configured in multiple ways, using either:

The JTAG interface. The "synchronous serial" interface.

Development boards usually come with a special cable that you can use to configure the FPGA from your PC with no knowledge of the underlying interface.

Chapter-2

BLOCK DIAGRAM

2.1 BLOCK DIAGRAM

Figure2.1: Block diagram of the project FPGA implementation of LCD display consist of 1. FPGA block Micro blaze processor MPMC(multi port memory controller) GPIO

2. DDR-SDRAM 3. LCD display 4. Push Buttons

2.2 FPGA
FPGA block is configured with microblaze processor, multiport memory controller, two general purpose input/outputs and an RS232 UART for examining the program on the desktop.

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2.3 MICRO BLAZE PROCESSOR

The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx Field Programmable Gate Arrays (FPGAs).

Figure2.2: Functional block diagram of MicroBlaze processor

The MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs. In terms of its instruction-set architecture, MicroBlaze is very similar to the RISCbased DLX architecture described in a popular computer architecture book by Patterson and Hennessy. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances. The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, the Core Connect PLB bus, is a traditional system-memory mapped transaction bus with master/slave capability. For 11

access to local-memory (FPGA BRAM), MicroBlaze uses a dedicated LMB bus, which reduces loading on the other buses. User-defined coprocessors are supported through a dedicated FIFO-style connection called FSL (Fast Simplex Link). The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module. Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth (3-stage or 5-stage), embedded peripherals, memory management unit, and bus-interfaces can be customized. This customization enables a developer to make the appropriate design tradeoffs for a specific set of host hardware and application software requirements. With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the Linux kernel. Otherwise it is limited to operating systems with a simplified protection and virtual memory-model: e.g.FreeRTOS or Linux without MMU support. MicroBlaze's overall throughput is substantially less than a comparable hardened CPU-core.

2.3.1 FEATURES
The MicroBlaze soft core processor is highly configurable, allowing you to select a specific set of features required by your design. The fixed feature set of the processor includes: Thirty-two 32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes 32-bit address bus Single issue pipeline In addition to these fixed features, the MicroBlaze processor is parameterized to allow selective enabling of additional functionality.

2.3.2 REGISTERS OF MICROBLAZE PROCESSOR

MicroBlaze has an orthogonal instruction set architecture. It has thirty-two 32-bit general purpose registers and up to eighteen 32-bit special purpose registers, depending on configured options. The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. The register file is reset on bit stream download (reset value is

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0x00000000). Figure 1-3 is a representation of a General Purpose Register and Table 1-1 provides a description of each register and the register reset value (if existing).

31

(R0-R31)

Figure 2.3: General Purpose Registers Table2.1: General Purpose Registers (R0-R31)

2.3.3 PIPELINE ARCHITECTURE

MicroBlaze instruction execution is pipelined. For most instructions, each stage takes one clock cycle to complete. Consequently, the number of clock cycles necessary for a specific instruction to complete is equal to the number of pipeline stages, and one instruction is completed on every cycle. A few instructions require multiple clock cycles in the execute stage to complete. This is achieved by stalling the pipeline. 13

When executing from slower memory, instruction fetches may take multiple cycles. This additional latency directly affects the efficiency of the pipeline. MicroBlaze implements an instruction prefetch buffer that reduces the impact of such multi-cycle instruction memory latency. While the pipeline is stalled by a multi-cycle instruction in the execution stage, the prefetch buffer continues to load sequential instructions. When the pipeline resumes execution, the fetch stage can load new instructions directly from the prefetch buffer instead of waiting for the instruction memory access to complete.

Three Stage Pipeline

When area optimization is enabled, the pipeline is divided into three stages to minimize hardware cost: Fetch, Decode, and Execute.

Table2.2: Three stage pipelining

Five Stage Pipeline

When area optimization is disabled, the pipeline is divided into five stages to maximize performance: Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and Writeback (WB).

Table2.3: Five stage pipelining

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2.3.4MEMORY ARCHITECTURE
MicroBlaze is implemented with a Harvard memory architecture; instruction and data accesses are done in separate address spaces. Each address space has a 32-bit range (that is, handles up to 4-GB of instructions and data memory respectively). The instruction and data memory ranges can be made to overlap by mapping them both to the same physical memory. The latter is useful for software debugging. Both instruction and data interfaces of MicroBlaze are 32 bits wide and use big Endean, bit-reversed format. MicroBlaze supports word, halfword, and byte accesses to data memory. Data accesses must be aligned, unless the processor is configured to support unaligned exceptions. All instruction n accesses must be word aligned. MicroBlaze does not separate data accesses to I/O and memory (it uses memory mapped I/O). The processor has up to three interfaces for memory accesses. The LMB memory address range must not overlap with PLB, OPB or XCL ranges. MicroBlaze has a single cycle latency for accesses to local memory (LMB) and for cache read hits, except with area optimization enabled when data side accesses and data cache read hits require two clock cycles. A data cache write normally has two cycles of latency (more if the posted-write buffer in the memory controller is full). The MicroBlaze instruction and data caches can be configured to use 4 or 8 word cache lines. When using a longer cache line, more bytes are prefetched, which generally improves performance for software with sequential access patterns. However, for software with a more random access pattern the performance can instead decrease for a given cache size. This is caused by a reduced cache hit rate due to fewer available cache lines.

2.4 MULTIPORT MEMORY CONTROLLER

MPMC is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2 memory. MPMC provides access to memory for one to eight ports, where each port can be chosen from a set of Personality Interface Modules (PIMs) that permit connectivity into PowerPC 405 processor and MicroBlaze processors using Core Connect PLBv4.6 and the MPMC Native Port Interface (NPI) structures, and well as a Memory Interface Block (MIB) PIM (PPC440MC) for the PowerPC 440 Processor. MPMC supports the Soft Direct Memory Access (SDMA) controller that provides full15

duplex, high-bandwidth, Local Link interfaces into memory. A Video Frame Buffer Controller (VFBC) PIM is also available. Additionally, MPMC supports optional Error Correcting Code (ECC) and Performance Monitoring (PM).

2.5 DDR-SDRAM
Double data rate synchronous dynamic random-access memory (DDR SDRAM) is a class of memory integrated circuits used in computers. DDR SDRAM (sometimes referred to as DDR1 SDRAM) has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules will not work in DDR equipped motherboards, and vice versa. Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy. The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to lower the clock frequency. One advantage of keeping the clock frequency down is that it reduces the signal integrity requirements on the circuit board connecting the memory to the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a single data rate (SDR) SDRAM running at the same clock frequency, due to this double pumping. With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) 2 (for dual rate) 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s

2.5.1 FEATURES
Soft Direct Memory Access (SDMA) support. Double Data Rate (DDR/DDR2) and Single Data Rate (SDR) SDRAM memory support. DIMM support (registered and unbuffered). 16

Error Correcting Code (ECC) supports. Parameterizable number of ports (1 to 8). Parameterizable number of data bits to memory (8, 16, 32, and 64) and parameterizable configuration of data path FIFOs. Performance Monitoring (PM) support. Memory Interface Generator (MIG)-based PHY v.2.1 support. Static Physical (PHY) interface alternative to the MIG-based PHY. User configuration of arbitration algorithms.

2.6 XPS GENERAL PURPOSE INPUT/OUTPUT

This document describes the specifications for the General Purpose Input/Output (GPIO) core for the Processor Local Bus (PLB). The XPS GPIO is a 32-bitperipheral that attaches to the PLB.

2.6.1 FEATURES
PLB interface is based on PLB v4.6 specification Configurable as single or dual GPIO channel(s) Number of GPIO bits configurable from 1 to 32 bits Each GPIO bit can be dynamically programmed as input or output Can be configured as inputs-only on a per channel basis to reduce resource utilization Independent reset values for each bit of all registers Optional interrupt request generation

2.6.2 FUNCTIONAL DESCRIPTION

The XPS GPIO design provides a general purpose input/output interface to a Processor Local Bus (PLB). The XPS GPIO can be configured as either a single or a dual channel device. The channel widths configurable and when both channels are enabled, the channel width remains the same for both. The XPS GPIO design supports 3-state as well as independent input and output ports. For a port configured as output, the data is driven out through a 3-statebuffer as 17

well as to an output only pin. The ports can be configured dynamically for input or output by enabling or disabling the 3-state buffer. Each channel is individually configurable as input ports only. When a channel is configured as input only, the logic required to implement the output path and three-state controls are removed resulting in reduced resource utilization. The channels may be configured to generate an interrupt when a transition on any of their inputs Occurs. The XPS GPIO core is comprised of modules: PLB Interface Module Interrupt Control GPIO core

Figure2.4:XPS GPIO Block Diagram

2.6.3 PLB INTERFACE MODULE

PLB Interface module provides an interface between the GPIO core and the PLBV4.6 bus standard. The PLB Interface module implements the basic functionality of PLB slave operation and does the necessary protocol and timing translation between the PLB and the IPIC interfaces. The PLB Interface module allows only single beat transactions.

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2.6.4 INTERRUPT CONTROL

Interrupt Controller provides interrupt capture support for the GPIO core. The Interrupt Controller is used to collect interrupts from the GPIO core, by which the GPIO core requests the attention of the microprocessor through the assertion of interrupt signals. The Interrupt Control module comes into the picture only when the C_INTERRUPT_PRESENT generic is set to 1.

2.6.5 GPIO CORE

GPIO core provides an interface between the IPIC interface and the XPS GPIO channels. The GPIO core consists of registers and multiplexers for reading and writing the XPS GPIO channel registers. It also includes the necessary logic to identify an interrupt event when the channel input changes. Figure shows a detailed diagram of the dual channel implementation of the GPIO core.

Figure2.5:GPIO_CORE Channel Implementation

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2.6.6 USAGE
GPIOs are used in:

chips with pin scarcity: IC, SoC, embedded and custom hardware, programmable logic devices (e.g., FPGAs)

multifunction chips: power managers, audio codecs, video cards Embedded applications (i.e. Arduino) make heavy use of GPIO for reading from various environmental sensors (IR, video, temperature, 3-axis orientation, acceleration), and for writing output to dc motors (via PWM), audio, LCD displays, or LEDs for status.

2.6.7 CAPABILITIES
GPIO capabilities include:

direction: GPIO pins can be configured to be input or output enable mask (aka GPIO mask): GPIO pins can be enabled/disabled input values are readable (typically high=1, low=0) output values are writable/readable input values can often be used as IRQs (typically for wakeup events) can use DMA to move large quantities of data efficiently into or out of the device

GPIO peripherals vary quite widely. In some cases, they are very simple, a group of pins that can be switched as a group to either input or output. In others, each pin can be set up flexibly to accept or source different logic voltages, with configurable drive strengths and pull up/downs. The input and output voltages are typically, though not universally limited to the supply voltage of the device with the GPIOs on, and may be damaged by greater voltage. Some GPIOs have 5 V tolerant inputs: even on low supply voltages (2 V), the device can accept 5 V without damage.

2.6.8 PORTS
A GPIO port is a group of GPIO pins (typically 8 GPIO pins) arranged in a group, and treated as a single port.

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2.716 X 2 CHARACTER LCD DISPLAY

LCD (Liquid Crystal Display) screen is an electronic display module and find a wide range of applications. A 16x2 LCD display is very basic module and is very commonly used in various devices and circuits. These modules are preferred over seven segments and other multi segment LEDs. The reasons why LCD is preferred are: LCDs are economical; easily programmable; have no limitation of displaying special & even custom characters animations A 16x2 LCD means it can display 16 characters per line and there are 2 such lines. In this LCD each character is displayed in 5x7 pixel matrix. This LCD has two registers, namely, Command and Data. The command register stores the command instructions given to the LCD. A command is an instruction given to LCD to do a predefined task like initializing it, clearing its screen, setting the cursor position, controlling display etc. The data register stores the data to be displayed on the LCD. The data is the ASCII value of the character to be displayed on the LCD.

2.7.1 FEATURES
5 x 8 dots with cursor (dot size is 0.56x 0.66mm) Built-in controller (KS 0066 or Equivalent) + 5V power supply (Also available for + 3V) N.V. optional for + 3V power supply

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2.7.2 PIN DIAGRAM

Figure2.6: LCD pin diagram

2.7.3 PIN DESCRIPTION

Table2.4: Pin description of LCD

2.7.4 ELECTRICAL SPECIFICATIONS

Table2.5: Electrical specifications

NOTE: VSS = 0 Volt, VDD = 5.0 Volt

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2.7.5 DISPLAY CHARACTER LCD CODE

Figure2.7: LCD character code

2.8 PUSH BUTTON

These are the active-high switches present on the ML405 evaluation board. There are 5 push buttons present on the board each connected to the FPGA through GPIO.

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Chapter-3

HARDWARE

3.1 XILINX VIRTEX-4(ML405) DEVELOPMENT BOARD 3.1.1 INTRODUCTION

The ML405 FX Evaluation Platform provides an ideal entry-level environment for developing high speed serial I/O designs based on the Virtex-4 FX FPGA. The ML405 evaluation platform enables designers to investigate and experiment with features of the Virtex-4 family of FPGAs. This user guide describes features and operation of the ML405 evaluation platform.

3.1.2 FEATURES
Virtex-4 FPGA:

SMA connectors connected to one Rocket IO multi-gigabit transceiver (MGT) Two serial ATA (SATA) host connectors High-performance, low-jitter LVDS clock synthesizer for SMA/SFP MGT clocks 128-MB DDR SDRAM, 32-bit interface running up to 400-MHz data rate One differential clock input pair and differential clock output pair with SMA connectors One 100-MHz clock oscillator (socketed) plus one extra open 3.3V clock oscillator socket General-purpose LEDs and pushbutton switches Expansion header with 32 single-ended I/Os RS-232 serial port 16-character x 2-line LCD display PS/2 mouse and keyboard connectors 24

USB interface chip (Cypress CY7C67300) with host and peripheral ports Xilinx XC95144XL CPLD to allow linear flash chips to be used for FPGA configuration JTAG configuration port for use with PlatformUSB cable Onboard power supplies for all necessary voltages 5V @ 6A AC adapter Power indicator LED

3.1.3 BOARD DESCRIPTION

Figure3.1: Virtex-4 ML405 Evaluation Platform

3.1.4 VIRTEX-4 FPGA

A Xilinx Virtex-4 FPGA, XC4VFX20-FF672-10, is installed on the evaluation platform (the board).

3.1.5 CONFIGURATION
The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master Select MAP, and Slave Select MAP modes. See Configuration Options, page 33 for more information. All the onboard components work with a voltage of 2.5v or 3.3 v. 25

3.2 DDR SDRAM

The board contains 128 MB of DDR SDRAM divided between two InfineonHYB25D512160BT-5 (or compatible) devices. Each device is 16 bits wide and together form a 32-bit data bus capable of running up to 400 MHz. All DDR SDRAM signals are terminated through 47 resistors to a 1.25V VTT reference voltage. The board is designed for matched length traces across all DDR control and data signals except clocks and the DDR loop trace. The board can support up to 256 MB of total DDR SDRAM memory if larger chips are installed. An extra address pin is present on the board to support up to 1-Gb DDR chips.

3.2.1 DDR CLOCK SIGNAL

The DDR clock signal is broadcast from the FPGA as a single differential pair that drives both DDR chips. The delay on the clock trace is designed to match the delay of the other DDR control and data signals. The DDR clock is also fed back to the FPGA to allow for clock deskews using Virtex-4 DCMs. The board is designed so that the DDR clock signal reaches the FPGA clock feedback pin at the same time as it arrives at the DDR chips.

3.2.2 DDR LOOP SIGNAL

The DDR loop signal is a trace that is driven and then received back at the FPGA with a delay equal to the sum of the trace delays of the clock and DQS signals. This looped trace can be used in high-speed memory controllers to help compensate for the physical trace delays between the FPGA and DDR chips.

3.3 USER PUSH BUTTUON SWITCHES (Active-High)

There are five active-High user pushbutton switches available for generalpurpose usage and arranged in a north-east-south-west-center orientation. Table 1-6 summarizes the user pushbutton switch connections

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3.3.1 PUSH BUTTONS SWITCH CONNECTIONS

Table3.1: Push button connections

3.3.2 CPU Reset Pushbutton Switch (Active-Low)

The CPU reset pushbutton switch is active-Low and is used as a system or user reset button. This pushbutton switch is wired only to an FPGA I/O pin so it can also be used as a general-purpose pushbutton switch

3.4 RS-232 SERIAL PORT

The ML405 board contains one male DB-9 RS-232 serial port, allowing the FPGA to communicate serial data with another device. The serial port is wired as a host (DCE) device. Therefore, a null modem cable is normally required to connect the board to the serial port on a PC. The serial port is designed to operate up to 115200 Bd. An interface chip is used to shift the voltage level between FPGA and RS-232 signals. The FPGA is connected only to the TX and RX data pins on the serial port. Therefore, otherRS-232 signals, including hardware flow-control signals, are not used. Flow control should be disabled when communicating with a PC.

3.5 16-Character x 2-Line LCD

The ML405 board has a 16-character x 2-line LCD (Lumex LCMS01602DTR/M) on the board to display text information. Potentiometer R1 adjusts the contrast of the LCD. The data interface to the LCD is connected to the FPGA to support 4-bit mode only. A level translator chip is used to shift the voltage level between the FPGA and the LCD. The LCD is connected to the FPGA Bank 4.

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Table3.2: LCD CONNECTIONS PIN DESCRIPTION LCD Enable LCD Register Select LCD Read/Write LCD Higher Data Bits PIN DESIGNATION LCD_E LCD_RS LCD_RW LCD_DB4 LCD_DB5 LCD_DB6 LCD_DB7 LOCATION AC14 AD14 AD15 AF13 AF14 AF15 AE15

3.6 JTAG CONFIGURATION PORT

The JTAG configuration port (J20) allows for device programming and FPGA debug. The JTAG port supports the Xilinx Parallel Cable III, Parallel Cable IV, or Platform Cable USB products. Third-party configuration products might also be available. The JTAG chain can be extended to an expansion board by setting jumper J26 accordingly.

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CHPTER-4

PROJECT IMPLEMENTATION 4.1 SOFTWARE

The software used for implementing the project is XILINX PLATFORM STUDIO. This software is used for configuring the processor and the peripherals. Then a netlist and a bit stream is generated which is used to place and route the logic cells in the FPGA.

4.1.1Create the Basic Project

Follow these steps to create the basic project: 1. Open XPS. From the dialog box, select Base System Builder wizard and OK.

2. You will be asked to specify which folder to place the project. Click Browse and create a new folder for the project. Click OK.

3. We are given the choice to create a new project or to create one using the template of another project. Tick I would like to create a new design and click Next.

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4. On the Select Board page, select Xilinx as the board vendor. Select Virtex 4 ML405 Evaluation Platform as the board name. Select 1 as the board revision. Click Next.

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5. On the Select Processor page, we normally have a choice between using the PowerPC hard processor, or the Microblaze soft processor. Since the Virtex-4 does not contain any PowerPCs, we can only select Microblaze. Click Next.

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6. On the Configure Microblaze page, select the clock frequency to be 125MHz. For the BRAM local memory, select 64KB. Select No debug and click Next.

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7. In selecting the Additional IO Interfaces, leave RS232_UART_1 and the PUSH BUTTONS ticked and un-tick everything else.

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8. On the Add Internal Peripherals page, click Next.

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9. On the Software Setup page, select RS232_Uart_1 for both STDIN and STDOUT. Leave Peripheral Test ticked and Memory Test. Click Next.

10. Click Generate. 11. Click Finish.

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Now a block diagram is generated with the specified configuration.

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Figure4.1: Internal block diagram of the FPGA

4.1.2 ADDING THE PERIPHERALS

Add the GPIO for the LCD Now we will add a GPIO peripheral to allow the Microblaze to control the LCD. 1. In the IP Catalog tab, open the General Purpose IO tree. 2. Right click on XPS General Purpose IO and select Add IP.

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Figure4.2: Adding the GPIO 3. Connect the instance to the PLB bus by opening the xps_gpio_0 tree and selecting mb_plb for the SPLB bus connection.

Figure4.3: Connecting the GPIO for LCD 4. Double click on the xps_gpio_0 instance. We can modify the instance parameters using this dialog box. Type 7 for the GPIO Data Channel Width and click OK. 38

5. Select the Ports filter and open the xps_gpio_0 tree. 6. The GPIO_IO net should display No Connection. Click on No Connection and type LCD_IO to give the net a name. 7. Click the net again to bring down the drop-down menu and select Make External. The newly created net should now be in the External Ports tree. XPS automatically modifies the system.mhs file to include the new external port. 8. Select the Addresses filter. 9. Click the xps_gpio_0 size drop-down menu and select 64K. Then click Generate Addresses. XPS automatically reconfigures the memory map and gives the GPIO peripheral a base address and a high address. It also automatically modifies the system.mhs file to update the IP address details.

We have now created an instance of the GPIO peripheral in our design. Later, we will modify the constraints file to connect the GPIO peripheral IO port to the LCD.

4.2 MICROPROCESSOR HARDWARE SPECIFICATIONS (MHS)

The Microprocessor Hardware Specifications files include the hardware parameters of the Xilinx Vertex4 ML405 board. These specifications contain the parameters like bus connections, clock settings and the addresses of the peripherals in the block RAMs. The MHS files is as follows: # Created by Base System Builder Wizard for Xilinx EDK 10.1 Build EDK_K.15 # Target Board: Xilinx Virtex 4 ML405 Evaluation Platform Rev 1 # Family: # Device: virtex4 xc4vfx20

# Package: ff672 # Speed Grade: -10 # Processor: microblaze_0

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# System clock frequency: 100.00 MHz # On Chip Memory: 16 KB # Total Off Chip Memory :128 MB # DDR_SDRAM = 128 MB PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O PORT fpga_0_Push_Buttons_Position_GPIO_IO_pin =

fpga_0_Push_Buttons_Position_GPIO_IO, DIR = IO, VEC = [0:4] PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR =O PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0] PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =

fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0] PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin =

fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR =O PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin =

fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O 40

PORT

fpga_0_DDR_SDRAM_DDR_WE_n_pin

fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [3:0] PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [3:0] PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [31:0] PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST PORT LCD_controller_GPIO_IO_pin = LCD_controller_GPIO_IO, DIR = IO, VEC = [0:6]

BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER C_INTERCONNECT = 1 PARAMETER HW_VER = 7.10.a BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb PORT MB_RESET = mb_reset END BEGIN plb_v46 41

PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.02.a PORT PLB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00003fff 42

BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00003fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END BEGIN xps_uartlite PARAMETER INSTANCE = RS232_Uart PARAMETER HW_VER = 1.00.a PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 43

PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000 PARAMETER C_BASEADDR = 0x84000000 PARAMETER C_HIGHADDR = 0x8400ffff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_Uart_RX PORT TX = fpga_0_RS232_Uart_TX END BEGIN xps_gpio PARAMETER INSTANCE = Push_Buttons_Position PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 5 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 1 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO = fpga_0_Push_Buttons_Position_GPIO_IO END BEGIN mpmc 44

PARAMETER INSTANCE = DDR_SDRAM PARAMETER HW_VER = 4.00.a PARAMETER C_NUM_PORTS = 1 PARAMETER C_MEM_PARTNO = HYB25D512160BE-5 PARAMETER C_MEM_DATA_WIDTH = 32 PARAMETER C_MEM_DQS_WIDTH = 4 PARAMETER C_MEM_DM_WIDTH = 4 PARAMETER C_MEM_TYPE = DDR PARAMETER C_NUM_IDELAYCTRL = 2 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2 PARAMETER C_PIM0_BASETYPE = 2 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000 PARAMETER C_MPMC_BASEADDR = 0x88000000 PARAMETER C_MPMC_HIGHADDR = 0x8fffffff BUS_INTERFACE SPLB0 = mb_plb PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n 45

PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n PORT MPMC_Clk0 = sys_clk_s PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s PORT MPMC_Clk_200MHz = clk_200mhz_s PORT MPMC_Rst = sys_periph_reset END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_FREQ = 100000000 PARAMETER C_CLKOUT0_FREQ = 100000000 PARAMETER C_CLKOUT0_BUF = TRUE PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT0_GROUP = DCM0 PARAMETER C_CLKOUT1_FREQ = 100000000 PARAMETER C_CLKOUT1_BUF = TRUE PARAMETER C_CLKOUT1_PHASE = 90 46

PARAMETER C_CLKOUT1_GROUP = DCM0 PARAMETER C_CLKOUT2_FREQ = 200000000 PARAMETER C_CLKOUT2_BUF = TRUE PARAMETER C_CLKOUT2_PHASE = 0 PARAMETER C_CLKOUT2_GROUP = NONE PORT CLKOUT0 = sys_clk_s PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s PORT CLKOUT2 = clk_200mhz_s PORT CLKIN = dcm_clk_s PORT LOCKED = Dcm_all_locked PORT RST = net_gnd END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Slowest_sync_clk = sys_clk_s PORT Dcm_locked = Dcm_all_locked PORT Ext_Reset_In = sys_rst_s PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT Peripheral_Reset = sys_periph_reset 47

END BEGIN xps_gpio PARAMETER INSTANCE = LCD_controller PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 7 PARAMETER C_BASEADDR = 0x81420000 PARAMETER C_HIGHADDR = 0x8142ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO = LCD_controller_GPIO_IO END

4.3 MICROPROCESSOR SOFTWARE SPECIFICATIONS (MSS)

The Microprocessor Software Specifications file (MSS) specify the driver software required to operate the hardware of the board. This also specifies the operating system settings and driver versions of the software. PARAMETER VERSION = 2.2.0 BEGIN OS PARAMETER OS_NAME = standalone PARAMETER OS_VER = 2.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER STDIN = RS232_Uart PARAMETER STDOUT = RS232_Uart END BEGIN PROCESSOR 48

PARAMETER DRIVER_NAME = cpu PARAMETER DRIVER_VER = 1.11.a PARAMETER HW_INSTANCE = microblaze_0 PARAMETER COMPILER = mb-gcc PARAMETER ARCHIVER = mb-ar END BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = dlmb_cntlr END BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ilmb_cntlr END BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = lmb_bram END BEGIN DRIVER 49

PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.12.a PARAMETER HW_INSTANCE = RS232_Uart END BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.11.a PARAMETER HW_INSTANCE = Push_Buttons_Position END BEGIN DRIVER PARAMETER DRIVER_NAME = mpmc PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = DDR_SDRAM END BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = clock_generator_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a 50

PARAMETER HW_INSTANCE = proc_sys_reset_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.11.a PARAMETER HW_INSTANCE = LCD_controller END BEGIN LIBRARY PARAMETER LIBRARY_NAME = xilmfs PARAMETER LIBRARY_VER = 1.00.a PARAMETER PROC_INSTANCE = microblaze_0 END

4.4 USER CONSTRAINTS FILE (UCF)

The pin configurations of all the peripherals together form the USER CONSTRAINTS FILES. This provides the information regarding the pin connections of the peripherals to the FPGA. These pins are directly generated in the microblaze configuration. The added external peripherals are to be added to the FPGA i.e., LCD. The LCD has some specified pins connected to the FPGA for input output operations. These pins should be added to the UCF file to activate the LCD input output operations. The constraints of LCD added to the UCF file are as follows: FPGA user constraints file is as follows: Net sys_clk_pin LOC=AB14; Net sys_clk_pin IOSTANDARD = LVCMOS33; Net sys_rst_pin LOC=M5; 51

Net sys_rst_pin PULLUP; ## System level constraints Net sys_clk_pin TNM_NET = sys_clk_pin; TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; Net sys_rst_pin TIG;

## IO Devices constraints #### Module RS232_Uart constraints Net fpga_0_RS232_Uart_RX_pin LOC=T4; Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; Net fpga_0_RS232_Uart_TX_pin LOC=T8; Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;

#### Module Push_Buttons_Position constraints Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> LOC=D6; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> PULLDOWN; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> SLEW = SLOW; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> DRIVE = 2; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> TIG; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> LOC=K8; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; 52

Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> PULLDOWN; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> SLEW = SLOW; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> DRIVE = 2; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> TIG; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> LOC=L10; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> PULLDOWN; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> SLEW = SLOW; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> DRIVE = 2; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> TIG; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> LOC=M6; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> PULLDOWN; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> SLEW = SLOW; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> DRIVE = 2; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> TIG; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> LOC=G11; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> PULLDOWN; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> SLEW = SLOW; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> DRIVE = 2; Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> TIG; 53

#### Module DDR_SDRAM constraints Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=C18; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=C17; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=E17; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=D16; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=C16; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=B15; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=B16; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=A15; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=F17; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=C21; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I; 54

Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=D18; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=D21; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=E20; Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=E13; Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=C14; Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=B17; Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=J24; Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=H23; Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=A17; Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=D20; Net fpga_0_DDR_SDRAM_DDR_WE_n_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=K20; Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> IOSTANDARD = SSTL2_I; 55

Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=C23; Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> LOC=D23; Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> LOC=E22; Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_DDR_DQS<0> LOC=L23; Net fpga_0_DDR_SDRAM_DDR_DQS<0> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQS<1> LOC=D24; Net fpga_0_DDR_SDRAM_DDR_DQS<1> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQS<2> LOC=C24; Net fpga_0_DDR_SDRAM_DDR_DQS<2> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQS<3> LOC=K22; Net fpga_0_DDR_SDRAM_DDR_DQS<3> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<0> LOC=F23; Net fpga_0_DDR_SDRAM_DDR_DQ<0> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<1> LOC=E21; Net fpga_0_DDR_SDRAM_DDR_DQ<1> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<2> LOC=F20; Net fpga_0_DDR_SDRAM_DDR_DQ<2> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<3> LOC=G20; Net fpga_0_DDR_SDRAM_DDR_DQ<3> IOSTANDARD = SSTL2_II; 56

Net fpga_0_DDR_SDRAM_DDR_DQ<4> LOC=F19; Net fpga_0_DDR_SDRAM_DDR_DQ<4> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<5> LOC=G19; Net fpga_0_DDR_SDRAM_DDR_DQ<5> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<6> LOC=H19; Net fpga_0_DDR_SDRAM_DDR_DQ<6> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<7> LOC=C19; Net fpga_0_DDR_SDRAM_DDR_DQ<7> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<8> LOC=E23; Net fpga_0_DDR_SDRAM_DDR_DQ<8> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<9> LOC=G24; Net fpga_0_DDR_SDRAM_DDR_DQ<9> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<10> LOC=F24; Net fpga_0_DDR_SDRAM_DDR_DQ<10> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<11> LOC=H22; Net fpga_0_DDR_SDRAM_DDR_DQ<11> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<12> LOC=M24; Net fpga_0_DDR_SDRAM_DDR_DQ<12> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<13> LOC=K23; Net fpga_0_DDR_SDRAM_DDR_DQ<13> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<14> LOC=N24; Net fpga_0_DDR_SDRAM_DDR_DQ<14> IOSTANDARD = SSTL2_II; 57

Net fpga_0_DDR_SDRAM_DDR_DQ<15> LOC=L24; Net fpga_0_DDR_SDRAM_DDR_DQ<15> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<16> LOC=F18; Net fpga_0_DDR_SDRAM_DDR_DQ<16> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<17> LOC=N23; Net fpga_0_DDR_SDRAM_DDR_DQ<17> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<18> LOC=J23; Net fpga_0_DDR_SDRAM_DDR_DQ<18> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<19> LOC=N22; Net fpga_0_DDR_SDRAM_DDR_DQ<19> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<20> LOC=H24; Net fpga_0_DDR_SDRAM_DDR_DQ<20> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<21> LOC=L19; Net fpga_0_DDR_SDRAM_DDR_DQ<21> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<22> LOC=G22; Net fpga_0_DDR_SDRAM_DDR_DQ<22> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<23> LOC=F22; Net fpga_0_DDR_SDRAM_DDR_DQ<23> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<24> LOC=J19; Net fpga_0_DDR_SDRAM_DDR_DQ<24> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<25> LOC=L18; Net fpga_0_DDR_SDRAM_DDR_DQ<25> IOSTANDARD = SSTL2_II; 58

Net fpga_0_DDR_SDRAM_DDR_DQ<26> LOC=M22; Net fpga_0_DDR_SDRAM_DDR_DQ<26> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<27> LOC=D19; Net fpga_0_DDR_SDRAM_DDR_DQ<27> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<28> LOC=K18; Net fpga_0_DDR_SDRAM_DDR_DQ<28> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<29> LOC=G21; Net fpga_0_DDR_SDRAM_DDR_DQ<29> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<30> LOC=J21; Net fpga_0_DDR_SDRAM_DDR_DQ<30> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_DQ<31> LOC=K21; Net fpga_0_DDR_SDRAM_DDR_DQ<31> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=C13; Net fpga_0_DDR_SDRAM_DDR_Clk_pin IOSTANDARD = DIFF_SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=C12; Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin IOSTANDARD = DIFF_SSTL2_II;

#### MODULE LCD CONTROLLER CONSTRAINTS#### Net LCD_controller_GPIO_IO_pin<0> LOC=AC14; Net LCD_controller_GPIO_IO_pin<0> IOSTANDARD = LVCMOS33; Net LCD_controller_GPIO_IO_pin<1> LOC=AD14; Net LCD_controller_GPIO_IO_pin<1> IOSTANDARD = LVCMOS33; 59

Net LCD_controller_GPIO_IO_pin<2> LOC=AD15; Net LCD_controller_GPIO_IO_pin<2> IOSTANDARD = LVCMOS33; Net LCD_controller_GPIO_IO_pin<3> LOC=AF13; Net LCD_controller_GPIO_IO_pin<3> IOSTANDARD = LVCMOS33; Net LCD_controller_GPIO_IO_pin<4> LOC=AF14; Net LCD_controller_GPIO_IO_pin<4> IOSTANDARD = LVCMOS33; Net LCD_controller_GPIO_IO_pin<5> LOC=AF15; Net LCD_controller_GPIO_IO_pin<5> IOSTANDARD = LVCMOS33; Net LCD_controller_GPIO_IO_pin<6> LOC=AE15; Net LCD_controller_GPIO_IO_pin<6> IOSTANDARD = LVCMOS33;

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The LOC represents the location of the connection and IOSTANDARD represents the input output standard voltage i.e. 3.3 volts. The LCD is connected to the FPGA through a level shifter circuit which shifts the voltage from 2.5v to 3.3v. The UCF file is then saved. Then the NETLIST AND BITSTREAM files are generated for the specified configuration and the hardware configuration is completed. After the NETLIST and the BITSTREAM are generated, they are dumped into the FPGA through the JTAG. Then the Memory test and the Peripheral test are performed to check for the errors. After the tests, the program is written for the project.

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4.3 C PROGRAM
The software program is added as the application in the project. The software is programmed using C language. The flowchart for the C program to display characters on LCD is as follows:

Figure4.4: Flowchart for C program Initially, the input and output pins of the LCD and the push buttons are initialized. Then the switch function is called corresponding to the signals received from the push buttons to display the message on the LCD screen. The program is compiled and checked for the errors. The bit stream is then updated and dumped into the FPGA. The output of the program is viewed on the HyperTerminal application when the board is connected through the RS232 Uart. After the successful completion of project building, the message corresponding to the push buttons are displayed on the LCD screen.

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OUTPUTS:
1. Output before pressing any key

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2. Output after pressing the key

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Chapter-5

ADVANTAGES AND APPLICATIONS

5.1 ADVANTAGES
There are many advantages of FPGA over the application specific microcontrollers. Some of the advantages are: PerformanceTaking advantage of hardware parallelism, FPGAs exceed the computing power of digital signal processors (DSPs) by breaking the paradigm of sequential execution and accomplishing more per clock cycle. Time to marketFPGA technology offers flexibility and rapid prototyping capabilities in the face of increased time-to-market concerns. You can test an idea or concept and verify it in hardware without going through the long fabrication process of custom ASIC design. The growing availability of high-level software tools decreases the learning curve with layers of abstraction and often offers valuable IP cores (prebuilt functions) for advanced control and signal processing. CostThe nonrecurring engineering (NRE) expense of custom ASIC design far exceeds that of FPGA-based hardware solutions. Because system requirements often change over time, the cost of making incremental changes to FPGA designs is negligible when compared to the large expense of an ASIC. ReliabilityWhile software tools provide the programming environment, FPGA circuitry is truly a hard implementation of program execution. Processor-based systems often involve several layers of abstraction to help schedule tasks and share resources among multiple processes. The driver layer controls hardware resources and the OS manages memory and processor bandwidth. For any given processor core, only one instruction can execute at a time, and processor-based systems are continually at risk of time-critical tasks preempting one another. FPGAs, which do not use OSs, minimize reliability concerns with true parallel execution and deterministic hardware dedicated to every task.

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Long-term maintenanceAs mentioned earlier, FPGA chips are field-upgradable and do not require the time and expense involved with ASIC redesign. Being reconfigurable, FPGA chips can keep up with future modifications that might be necessary. As a product or system matures, you can make functional enhancements without spending time redesigning hardware or modifying the board layout.

5.2 Limitations of FPGA

The FPGA manufacturing process is time consuming. Also the FPGA is slower compared to the microcontrollers. This can be overcome by using proper timers for the applications. For larger applications, placement and wiring becomes more complex.

APPLICATIONS
6.1 Applications of FPGA
The FPGA technology is very advanced technology and can be used in implementing various applications. Some of the applications of the FPGA are: Digital signal processing Software-defined radio Aerospace and defense systems ASIC prototyping Medical imaging Computer vision Speech recognition Cryptography Bioinformatics Computer hardware emulation Radio astronomy Metal detection and a growing range of other areas.

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6.2 Applications of LCD implementations

They are used in a wide range of applications including the computer monitors, telivisions and instrument panels. They are also used in consumer devices such as video games, calculators, gaming devices, clocks and telephones. The LCD application can be integrated with other applications by adding other peripherals and modifying the program.

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CONCLUSION AND FUTURE SCOPE

The project FPGA IMPLEMENTATION OF LCD INTERFACE has been successfully designed and tested. Integrating features of all the hardware components used have developed it. Presence of every module has been reasoned out and placed carefully thus contributing to the best working of the unit. Secondly, using of advanced modules and with the help of growing technology the project has been successfully implemented. FPGAs are implemented mainly in the high end devices for encryption of data and other applications. Through this project we wanted to show that FPGAs can also be implemented for the projects which are implemented only using ASICs till date. This project is proposed to show the implementation of FPGA replacing the ASICs, for displaying message over LCD. The implementation of FPGA is highly efficient and can be easily subjected to improvements in the application without replacing the hardware. Hence we conclude that this technology is very advantageous and can implemented less number of hardware components. Using this technology the power consumption is highly reduced. The process of implementation is considerably easier compared to the Application Specific ICs.

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FUTURE SCOPE
The FPGA implementation can be extended to many other applications like mobiles, televisions etc., to reduce the board size and hardware constraints. They can also be integrated with other processors for high end applications forming an efficient combination of processors with embedded peripheral interfaces. This project can be extended to implement many applications like Automatic Voting Machines(AVM), Calculators, clocks etc. The FPGA can also be used in many other applications where ASICs are implemented, for higher efficiency and less power consumption.

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APPENDIX
C code:
#include"xparameters.h" #include"xbasic_types.h" #include"xgpio.h" #include"xstatus.h" #define lcd_DB4 0x01 #define LCD_DB5 0x02 #define LCD_DB6 0x04 #define LCD_DB7 0x08 #define LCD_RW 0x10 #define LCD_RS 0x20 #define LCD_E 0x40 #define LCD_TEST 0x80

XGpioGpioOutput;

voidgpio_write(Xuint32 c); voidlcd_clk(void); voidlcd_set_test(void); voidlcd_rest_test(void); voidlcd_set_rs(void);

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voidlcd_reset_rs(void); voidlcd_set_rw(void); voidlcd_reset_rw(void); voidlcd_write(Xuint32 c); voidlcd_clear(void); voidlcd_puts(const char *s); voidlcd_putch(Xuint32 c); voidlcd_goto(Xuint32 line,Xuint32 pos); voidlcd_init(void);

int main(void) { Xuint32 status; xil_printf("%c",27); xil_printf("lcd driven by resources"); status=XGpio_Initialize(&GpioOutput,XPAR_LCD_CONTROLLER_DEVICE_ID); if(status!=XST_SUCCESS) { xil_printf("gpio failed to initialize\r\n"); return XST_FAILURE; } XGpio_SetDataDirection(&GpioOutput,1, 0x00); lcd_init(); 71

lcd_puts("windows"); xil_printf("***"); lcd_goto(1,2); lcd_puts("xp1"); xil_printf("**"); while(1) { } }

//write to GPIO outputs voidgpio_write(Xuint32 c) { //write to the GPIOs XGpio_DiscreteWrite(&GpioOutput,1,c&0x0FF); }//read the GPIO output} //clock the LCD(toggles E) voidlcd_clk() { Xuint32 c; gpio_write(c|LCD_E); gpio_write(c &(~LCD_E)); } 72

//assert the rs signal voidlcd_set_rs() { Xuint32 c; //get existing outputs //assert rs gpio_write(c|LCD_RS); } //deassrt the rs signal voidlcd_reset_rs() { Xuint32 c; //get existing outputs //assert RS gpio_write(c&(~LCD_RS)); } //ASSERT THE RW SIGNAL voidlcd_set_rw() { Xuint32 c; //get existing outputs //assert RS gpio_write(c|LCD_RW); 73

} //deassert the RW signal voidlcd_reset_rw() { Xuint32 c; //get existing outputs gpio_write(c&(~LCD_RW)); } //write a byte to LCD(4bit mode) voidlcd_write(Xuint32 c) { Xuint32 temp; //get existing outputs temp=temp & 0xF0; //set the high nibble temp = temp|((c>>4)&0x0F); gpio_write(temp); //clock lcd_clk(); //set the low nibble temp = temp & 0xF0; temp = temp|(c & 0x0F); gpio_write(temp); 74

lcd_clk(); } //clear LCD voidlcd_clear(void) { lcd_reset_rs(); //clear LCD lcd_write(0x01); } //write a string to the LCD voidlcd_puts(const char *s) { int i=0; while(s[i]) { lcd_write(s[i]); i++; } return; } //write charecter to the lcd voidlcd_putch(Xuint32 c) { 75

lcd_set_rs(); lcd_write(c); } //change cursor position //(line=0 or 1,pos=0to15) voidlcd_goto(Xuint32 line,Xuint32 pos) { lcd_reset_rs(); pos = pos& 0x3F; if(line==0) lcd_write(0x80|pos); else lcd_write(0xC0|pos); } //initialize the lcd voidlcd_init(void) { Xuint32 temp; //write mode(always) lcd_reset_rw(); //write controlbytes lcd_reset_rs(); temp = temp|LCD_DB5; 76

gpio_write(temp); lcd_clk(); lcd_clk();

//function set:4bit mode,1/16duty,5*8font,2lines lcd_write(0x28); //display on/off control:ON lcd_write(0x0C); //entry mode set:increment(cursor moves forward) lcd_write(0x06); //clear the display lcd_clear(); }

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