Logic

Synthesis
Pavan Kumar KV

Definition
Synthesis is a translation of a behavioral (RTL) representation of a design into a structural one. Automatic process with user control

Translation

Converts HDL to functional boolean equivalent HDL syntax/rule checks Optimizes HDL Arithmetic function mapping Sequential function mapping Combinational function mapping

RTL level Optimization

Code related processing is first performed when a model is synthesized. Some of the steps are: Expansion - subprograms are in-lie expanded. Constant folding - eg. A + 3 + 2 becomes A + 5 Loop unrolling - loop statements are unrolled to a series of individual statements. Dead code removal - any unused code is discarded. Bit minimization - for example, VHDL state encoding, operator bit width, etc. Different implementations of arithmetic operators have different area and timing characteristics. E.g. + operator can be carry look-forward (fastest), carry look-ahead or ripple carry(smallest). Common sub-expression sharing Operator reordering Resource sharing, etc.

Logic level optimization

All registered elements are fixed, only combinational logic is optimized. Optimization at this level involves restructuring of equations according to the rules of Boolean law. The types of logic optimization include: minimization equation flattening equation factorization

Flattening
The conversion of multiple boolean equations into a two level sum-of-products form (AND/OR) is called flattening. All the intermediate terms are removed. Thus, flattening removes all logic structure from a design. The result of flattening is a two-level, sum-of-products form. Before flattening out = t1.t2 t1 = a + b(c + f) t2 = d + e' After flattening out = ad + bcd + bdf + ae+ bce' + be'f Not all designs can be flattened successfully by the tools. Small designs of 10 inputs or less can always be flattened. Large designs having 20 or more inputs are often impossible to flatten. Designs with many XOR and multiplexer gates, such as adders and ALUs, are generally difficult to flatten. For example An N-bit XOR function produces 2 n-1 terms. A 20-input XOR gate, when flattened, has 219 (524,288) terms.

Factorization/Structuring
The factorization of Boolean equations is a process of adding intermediate terms. This adds implied logic structure which both reduces the size of implied circuit and reduces large fanouts. Adding structure adds levels of logic which tend to make a circuit smaller but it may be slower.

Logic Level Optimization

L = A.B.C Y1=L+A.B.D Y2=A.B+C+D factorize M=A.B L=M.C Y1=L+M.D Y2=M+C+D flatten equations

M=A.B Y1=A.B.C+A.B.D N=C+D Y2=A.B+C+D Y1=M.N factorize Y2=M+N

 In the above eg. Facorization after flattening gave better results. The results may vary from case to case. The tools will choose the optimal optimization tecniques to meet the constraints.

Mapping/Optimization
Maps boolean functions to technology specific primitive functions Modifies mapping to meet design goals Design Rules Timing Area Power

Optimization: Constraint-Driven

Synthesis/Physical Synthesis

Synopsys Design Compiler and the Design Flow

Basic Synthesis Flow

Outline: Set Up

DC Setup Files
Setup files automatically read at DC startup .synopsys_dc.setup Possible locations (read in this order) 1. Root setup: $SYNOPSYS/admin/setup/.synopsys_dc.setup 2. Home setup: $HOME/.synopsys_dc.setup (optional) 3. Local setup: ./.synopsys_dc.setup (optional) Use to customize the work environment

DC Setup Files - example

# TCL-subset .synopsys_dc.setup file must # have the # character on the first line of the file set search_path ". /synopsys/libraries/syn $search_path" set target_library "lsi_10k.db" set synthetic_library "standard.sldb dw_foundation.sldb" set link_library "* $target_library $synthetic_library" set symbol_library "lsi_10k.sdb" define_design_lib MY_WORK -path ./WORK # example: removing high drive inverter set_dont_use lsi_10k/IVP

Library Setup
search_path Allows files to be read in without specifying directory path in the command Directories in which DC will look for library/design .db files during a link target_library Technology cell library files (i.e. lsi_10k.db) Compile chooses inferred cells from target library link_library Used during design linking (pre- and post-compile) All cells in a design must be in one of the link libraries Inferred (chosen during compile based on RTL functionality) Instantiated (specific cell instance placed in design RTL) link_library must always start with "*", indicating loaded designs should be searched first when linking All synthetic and target libraries must be included in link_library synthetic_library Library of DesignWare components dw_foundation.sldb Advanced set of IP components optional to DC Wide variety moderate/high performance arithmetic architectures Fifos, stacks, counters, digital PLL, arbiters, priority encoders, SRAM models, ECC, CRC, debugger, decoders/encoders, more... Macrocells: 8051 microcontroller, 16550 UART, Memory BIST controller, AMBA peripherals(I2C, UART, SSI, APB, AHB, ) define_design_lib Directory where DC places intermediate design files (default is directory in which DC is run) set_dont_use <lib>/<cell> Specifies cells of a target library or implementations of a synthetic library to not use during compile

Setting up libraries for synthesis

Before RTL Design Compiler could synthesize a design, it is necessary to tell the tool which libraries it should use to pick up the cells. There are three types of libraries Technology libraries, Symbol libraries, and DesignWare libraries. The technology libraries, which contain information about the characteristics and functions of each cell, are provided and maintained by the semiconductor vendors and must be in .db format. The symbol libraries contain graphical symbols for each library cells. As with technology libraries, it is also provided and maintained by semiconductor vendors. Design compiler uses it to display symbols for each cell in the design schematic. The DesignWare libraries are composed of pre-implemented circuits for arithmetic operations in your design, and such designware parts are inferred through arithmetic operators in the HDL code, such as "+- <><=>=". The libraries come with two types: the standard DesignWare library and the Foundation DesignWare library.

Outline : Reading the Design

Analyze

Translates HDL to intermediate format Recommended for reading RTL

dc_shell-t> analyze -help Usage: analyze # analyze [-library library_name] (Use this library as the work library) [-work library_name] (Use this library as the work library) -format format string (The format of the hdl files) [-update] (Update analysis from original source) [-schedule] (Analyze the design for scheduling) [-create_update] (Create .update file for use by "analyze -update") [-define macro_names] (list of top-level macros, Verilog only) file_list (Files to read in)

Elaborate
Second step of HDL translation Builds generic technology(GTECH) database
HDL parameters are expanded Registers and latches are inferred Links design

Supports parameter passing/architecture selection Recommended for reading RTL

dc_shell-t> elaborate -help Usage: elaborate # elaborate [-library library_name](Use this library as the work library) [-work library_name] (Use this library as the work library) [-architecture arch_name](Architecture to build) [-parameters param_list](Parameters for the design) [-file_parameters file_list](Files containing parameters for the design) [-update] (Automatically update out-dated files) [-schedule] (Build the design for scheduling) [-gate_clock] (Gate clocks) design name (Name of the design to build)

read_file

read_file performs analysis and elaboration(except link) in one step Parameter passing/architecture selection not supported Recommended for reading mapped netlists
dc_shell-t> read_file help Usage: read_file # read file from disk [-format format_name] (verilog, vhdl, ddc, db) [-single_file file_name] (group all designs into this file) [-define macro_names] (list of top-level macros, Verilog and SystemVerilog only) [-library library_name] (Use this library as the work library, VHDL only) [-work library_name] (Use this library as the work library, VHDL only) [-names_file file_list] (list of files for name changes) [-ilm] (Read from the Milkyway ILM view) [-rtl] (register transfer-level verilog/vhdl format) file_list (list of files to read)

Outline: Defining Design Environment & Set Design Constraint

Define the Design Environment

Defining the operating Conditions set_operating_conditions Sets PVT for timing calculations Process/Voltage/Temperature(PVT) conditions affect timing Technology libraries are characterized at different PVT corners Corner specified in technology library (i.e. worst, typical, best)

Defining Wireload Models (WLM) set_wireload_model, set_wireload_mode Fanout-based statistical model for estimating wire capacitance Needed for non-DCT runs Not as accurate as DCT method Default wireloads provided in technology library generally inaccurate Custom wireload generated from accurate floorplan of the design gives best results DC Topographical (DCT) calculates net parasitics based on physical layout Correlates well to place and route timing Modeling the System Interface Defining drive characteristics for input ports set_driving_cell (or) set_drive (or) set_input_transition Defining loads on input and output ports set_load Defining fanout loads on output ports

Specifying Power Intent

UPF Commands in Synopsys Tools

Defining Design Constraints

Two types of constraints Design Rule Constraints (DRC) Optimization Constraints

Constraint Guidelines
Golden rule #1: set realistic constraints Most critical for timing and DRC constraints Golden rule #2: validate constraints check_design check_timing report_timing_requirements Corollary: Garbage in, garbage out Correlation issues Derate Adjusting constraints to account for unmodeled effects Over-constraining Modifying constraints to drive optimization to desired goal

Optimization Priority
Design goals often conflict Optimization engines must resolve conflict Priority rules DC priority DRC Timing Power Area Can be modified with set_cost_priority

Major Design Compiler Constraints

Design Rule Constraints(DRC)

set_max_transition Largest transition time allowed set_max_fanout Largest fanout allowed set_max[min]_capacitance Largest/smallest capacitance allowed Defaults usually set in technology library Highest optimization priority

Optimization Constraints : Clocks

create_clock Name, source port, period, duty cycle Constrains timing on all register to register paths set_clock_uncertainty Estimated network skew set_clock_latency Estimated source and network delays set_clock_transition Estimated input slew set_ideal_network Disables timing calculation and optimization of clock network On by default Internally generated clocks create_generated_clock Calculates latency from source port to internal pin Post-CTS set_propagated_clock Calculates actual clock tree delays set_dont_touch_network Prevents clock tree optimization Virtual clock Create with create_clock with no clock source port Useful for modeling external clocks Used for input/output delay specification Gated clocks set_clock_gating_checks Delay constraint to prevent clock glitching

Example

Optimization Constraints Derating

set_timing_derate Mechanism to add margin Used to account for unmodeled delay affects Used to adjust for correlation problems Power set_max_dynamic_power set_max_leakage_power set_max_total_power Power constraints are lower priority than timing constraints Optimization engines will not reduce power if it creates negative slack Area set_max_area Constrains design area Area constraints are lower priority than timing constraints Optimization engines will not reduce area if it creates negative slack

Optimization Constraints: Structural

set_fix_multiple_port_nets Buffer all net segments connected to an output port set_dont_touch Prevents optimization Works only for mapped gates set_dont_touch_network Same as set_dont_touch Applies to all combinational logic in fanout set_size_only Prevents all optimizations except sizing

Optimization Constraints: Exceptions

set_false_path Disables timing calculation for a path More cpu intensive than set_disable_timing set_multicycle_path Extend path setup/hold requirement beyond a single clock cycle set_case_analysis Applies logic value to ports/pins for timing analysis only Disables timing arcs through affected logic gates Does not affect functionality Logic value is propagated through combinatorial logic set_disable_timing Disables timing calculation through specified cells, pins, or ports Use instead of set_false_path when possible set_ideal_network Disables timing, optimization, and DRC checking Can be propagated through logic Useful on high-fanout nets which will be fixed in place and route On by default for clocks set_max_delay/set_min_delay Overrides default default setup/hold requirement with point to point requirement

Outline : Compile Strategies

Top-Down Compile
Benefits: Optimization engines work on full design, complete paths Usually get best optimization result No iteration required Simpler constraints Simpler data management Drawbacks: Longer runtime More processing required More memory required

dc_shell-t> current_design TOP dc_shell-t> compile_ultra timing_high_effort_script

Bottom-Up Compile
Benefits: Divide-and-conquer methodology localizes problem areas Budgeting method enables parallelized synthesis effort Less processing required per run Less memory required per run Drawbacks: Optimization works on sub-designs, hierarchical path segments Optimization result not as good as top-down compile Iterations may be required More hierarchies and data to maintain More work for user More error-prone

Meeting Timing Goals

Enable DC-Ultra optimizations and embedded script compile_ultra timing_high_effort_script If runtime excessive compile_ultra compile map_effort_high incr Use critical range and path groups Ungroup hierarchy Register retiming Use fast DesignWare

compile_ultra

Advanced datapath synthesis Optimized arithmetic trees Carry save logic Embedded scripts targeting area/timing Automatic ungrouping Automatic boundary optimization Topographical technology for best timing correlation Library aware structuring and mapping

Setting Critical Range / Group Path

Critical range > 0 reduces TNS and improves overall timing set_critical_range 2 TOP Path groups focus optimization effort Create additional path groups and set a critical range
group_path -from [all_inputs] -name input_paths \ -critical_range 0 group_path -to [all_outputs] -name output_paths \ -critical_range 0 group_path -from clk -to clk -name internal_paths \ -critical_range 2

Group critical paths group_path to top/mem*/data name memory_inputs \

-critical_range 2

Best Practice: Use a reasonable amount for critical range (i.e. 10% of the clock period). The larger the critical range, the longer the compile time.

Ungroup Hierarchy
Optimization works on paths within hierarchical boundaries Removing hierarchical boundaries allows optimization algorithms to work on larger or entire paths Produces better optimization results For best timing results, remove hierarchy on critical paths For best area results, remove as much hierarchy as possible compile_ultra automatically ungroups as needed ungroup allows manual ungrouping

Register Retiming
Moves registers through combinational gates to improve timing/area optimize_registers/set_optimize_registers Use for pipelined designs and aggressive retiming pipeline_design Use to pipeline designs compile_ultra retime Use for non-pipelined designs and less aggressive retiming

Clock Gating
Clock gating not only can save power, it can also help in area savings insert_clock_gating Run before compile_ultra

saves one mux per register, by using only one clock gate per register bank

Outline : Design Analysis

report_design
Operating conditions Wire load model and mode Internal input and output pin delays Disabled timing arcs

report_clock
Clock definition Clock latency Clock skew

check_design
Use check_design to check consistency Consistency means no unintentionally unconnected ports no unintentionally tied ports no cells without input or output pins no mismatch between a cell and its reference no multiple-driver nets no recursive hierarchy

check_timing
Unconstrained timing paths Clock-gating logic

Unmapped cells

report_qor
Timing summary for all path groups Good overall status of design timing

report_constraint
Shows difference between user constraints and actual design values

report_delay_calculation
Shows how report_timing calculates delay of a timing arc (cell or net) Use to understand contributors to Delay calcs

RTL Compiler Synthesis Flow

Inputs and Outputs of the Synthesis Tool

Inputs RTL: Verilog, VHDL, directives, pragmas. Constraints: .sdc or .g Library: .lib or .lbr Physical: LEF (optional) Outputs Optimized netlist LEC .do file ATPG, ScanDEF, and others Constraints: .sdc or .g

.lib .lbr

.g .SDC

Encounter RTL Compiler

Logic Netlist Verification

RTL

.SDC .g

Optimized netlist

Physical Design

Synthesis Features
Encounter RTL Compiler synthesis provides the following features: Large capacity for top-down synthesis Fast linear runtimes Global optimization finds the best overall structure Well balanced structure for congestion and timing closure Support for super-threading Support for multisupply voltage (MSV) design synthesis

Design for Test Features

Design for Testability (DFT) supports the following features: Multiple clock domains Multiple scan chains DFT rule checking Scan chain configuration and connection Shadow logic around untestable logic Scan chain abstraction models Output ScanDEF and ATPG interface files

Low-Power Synthesis Features

Low-power synthesis in the Encounter RTL Compiler supports the following features: Block FF Block MUX Dynamic power optimization Leakage power Optimization en clk Switching activity information from TCF and SAIF Hierarchical clock gating Multi-VT leakage SR TR power optimization State- or path-dependent Cnet Cpin internal power
Instance power Net power

Datapath Synthesis Features

Datapath synthesis in the Encounter RTL Compiler supports the following features: Apply datapath optimization in your flow. Use the datapath operations. Verify operator merging and its typical scenarios. Apply carrysave transformations. Report the datapath components. Use ChipWare Developer.

Synthesis Flow

Basic Design Flow

Set target library set_attr library name / Read HDL files read_hdl ${FILE_LIST} Elaborate the design elaborate Set timing and design constraints Apply optimization directives synthesize -to_generic synthesize -to_mapped and synthesize -incremental Analyze and Report Interface to place and route

Modify optimization directives

Netlist, SDC

Meet constraints?

No

Yes
Place and Route

The Configuration File

The .synth_init file contains commands that are executed upon starting the compiler. These commands do the following: Set the library and HDL search paths. Suppress unwanted warning or information messages Set globally applicable attributes The compiler searches for this file in the installation directory, and in the current directory. In the home directory it searches for .cadence/.synth_init. The compiler loads the file unless you start it with the -n option.

Sample .synth_init file

This file includes useful Tcl procedures that perform any extra functions (e.g. remove_buffer_tree) include load_etc.tcl source ~/my_file.tcl set_attr information_level 9 / set_attr endpoint_slack_opto 1 / suppress_messages { LBR-21 LBR-72 LBR-146 }

Release - 2003.1

55

Navigating the Virtual Directory Structure

The compiler uses UNIX-like commands to navigate the design hierarchy in memory. cd Sets the current directory in design hierarchy. ls <-l > < -a> Lists the objects in the current directory. mv Moves (renames) a design in design hierarchy. mv test2 test3 Renames a design test2 as test3. popd Removes the topmost element of the directory stack, revealing a new top element and changing the directory to the new top element. pushd Pushes the specified new target directory onto the directory stack and changes the current directory to that specified directory. rm Removes an object (like a clock definition) in design hierarchy. rm /des*/test3/timing/clock_domains/domain_1/clock Removes clock object. find Finds an object and passes it to other commands. ls l a [find / wireload *] Reports the wire loads.

Setting Attributes
In the compiler, there are predefined attributes associated with objects in the database. Use the set_attribute or set_attr command to assign values to these attributes. Syntax set_attribute <attribute name> <value> <object> To get information on all the attributes containing the word clock, enter:
set_attr h *clock* *

Examples Root attribute (Notice the fourth argument): set_attribute lp_insert_clock_gating true / Design attribute: set_attr lp_clock_gating_exclude true /des*/top_mod

Querying Attributes
To retrieve the value of an attribute, use: Syntax get_attribute {attribute_name [object]} | {-h object_type [attribute_name]} Works on a single object. Or ls l a (a = attribute, l = long list) Examples get_attr propagated_clocks $pin get_attr load /libraries/slow/INVX1/A ls la / ls l a /designs/dtmf_chip

Finding Design Objects

Purpose Finding all flops and latches Finding all the input ports Command find /des* -instance inst*seq*/* find /des* -port ports_in/*

Finding all the output ports find /des* -port ports_out/* Finding all pins in a hierarchical instance v1 Finding all subdesigns. Finding all hierarchical instances in the design Finding all clocks in the design Finding all available wireload models in a library find /des* -pin find /des* -pin find / -subd * set inst_list [find / -instance *] echo $inst_list find / -clock * [find [find / -library <LibraryName>] wireload *] inst*hier/v1/* v1/*

Setting the Technology Library

The library attribute specifies the target technology for synthesis. To load a single library, enter set_attr library lsi500k.lib / The library attribute is a root attribute. To load multiple libraries, enter set lib_list1 01_wc3.lib mylib1.lib x1.lib set_attr library $lib_list Setting the library attribute loads the specified libraries into the synthesis environment (and populates the /libraries virtual directory). To append the main library database, enter set_attr library {{a.lib b.lib} c.lib {x.lib y.lib}} / In this example, the compiler loads a.lib and appends b.lib to a.lib. Next, it loads c.lib. Then, it loads x.lib and appends y.lib to x.lib.

Setting Up Operating Conditions

Use the operating_condition attribute to set the operation condition. Syntax set_attr operating_condition <name_of_condition> / To find the available operating conditions in the library, use the find command for this. operating_conditions(WORST) {
find /libraries operating_condition *

Specify the operating condition.

set_attr operating_condition WORST /

process : 1 ; temperature : 125 ; voltage : 1.35 ; tree_type : balanced_tree ; } operating_conditions(TYPICAL) { process : 1 ; temperature : 70 ; voltage : 1.35 ; tree_type : balanced_tree ; } operating_conditions(BEST) { process : 1 ; temperature : 0 ; voltage : 1.35 ; tree_type : best_case_tree ; }

Section of the .lib file

Setting the Wire-Load Model

By default, the compiler selects a wire-load model automatically, if: Area based wire-load selection is defined in library. Default wire-load model attribute is set in the library. Use force_wireload attribute to override this condition. Example The specified wire-load model on the design is forced to use the 160K gates wire-load model.
/* wireload.lib file */ /*Units: Capacitance pF, Resistance - Ohm, Length - Micron. */ wire_load_table ("suggested_10k") fanout_length( 1, 6.58 ) ; . . . . . fanout_length( 8, 92.11 ) ; fanout_capacitance( 1, 0.0009 ) ; . . . . . fanout_resistance( 7, 0.37395 ) ; fanout_resistance( 8, 0.43046 ) ; fanout_area( 1, 0.0 ) ; . . . . . fanout_area( 8, 0.0 ) ; } /* End Of Wire Load Model */

wire_load_table ("suggested_160K") fanout_length( 1, 13.5077 ) ; . . . . . . . . . . . . } /* End Of Wire Load Model */

set_attr force_wireload /lib*/mylib/wireload_models/suggested_160K /des*/final

Setting the Wire-Load Mode

Using the wireload_mode attribute Syntax set_attr wireload_mode <mode> / Example set_attr wireload_mode top / Wire-load models are one of these three types: Top Enclosed Segmented
mode=segmented
60x60 40x40

mode=top
60x60 40x40 20x20

60x60

20x20

40x40

20x20

mode=enclosed
60x60 40x40 20x20

wire_load_selection(predcaps){ wire_load_from_area(0, 10000, "10K"); wire_load_from_area(10000, 15000, "20K"); wire_load_from_area(15000, 40000, "40K"); ... } default_wire_load_mode : segmented; default_wire_load_selection : predcaps;

40x40

Physical Layout Estimator (PLE)

PLE is a physical modeling technique that bypasses wireloads for RTL synthesis optimization. In Block A Block B place of wireloads, the compiler Top Block C generates an equation to model Block E Block D the wire delay. PLE uses actual design and physical library information. Dynamically calculates wire delays for different logic LEF/Cap structures in the design. Table In most cases, PLEsynthesized designs correlate better with place-and-route tools. set_attribute lef_library <lef header>
Fanout Load Load 1 Fanout0.0011 1 Fanout0.0013 2 0.0092Load 0.0099 Fanout Load 3 2 1 0.01430.0014 1 0.01580.0016 4 3 2 0.01990.0107 2 0.02120.0111 5 4 3 0.02150.0186 3 0.02670.0207 6 5 4 0.02780.0284 6 5 4 0.03120.0303 7 0.03150.0331 5 0.03860.0399 8 7 6 0.03900.0401 6 0.04670.0495 9 8 7 0.04560.0488 9 8 0.05770.0592 7 0.05780.0590 10 10 9 8 0.06990.0687 0.0685 10 9 0.0811 0.0782 10 0.0879

set_attribute cap_table_file <cap table> set_attribute interconnect_mode ple /

Preventing the Use of Specific Library Cells

Use the avoid attribute to prevent the technology mapper from using the particular cells. Syntax set_attr avoid <true(1)/false(0)> <cell name(s)> Example set_attr avoid 1 { mylib/snl_mux21_prx*} set_attr avoid 1 { /mylib/*nsdel} The set_dont_use Tcl command in Design Compiler (DC) is supported in Encounter RTL Compiler (RC), provided that this command appears inside your SDC file.

Reading Designs
Use the read_hdl or read_netlist commands to parse the HDL source. Syntax read_hdl [-h][-vhdl|-sv][-v1995|-v2001][-netlist] [-define macro=name] file(s)<.gz> -vhdl By default, the compiler reads VHDL-1993. -sv Read System Verilog files -v1995 (Boolean) force Verilog 1995 mode. -v2001 (Boolean) force Verilog 2001 mode. -define Define Verilog macros Examples To read the RTL or mixed source (RTL/gate) design: read_hdl {design1.v subdes1.v subdes2.v} To read the gate-level (structural) netlist: read_netlist design_struc1.v

Elaboration of Designs
The elaborate Command Builds data structures and infers registers in the design. Performs higher level HDL optimization, such as dead code removal. Uses generic gates in elaborated netlist Elaborate is only required for the top-level design and it automatically elaborates all its references. elaborate [-h] [-parameter {} ] [<top_module_name>] Example
elaborate -parameter {12 8 16} TOP When compiling, these parameters will be modified as follows: data_width1 = 12 averg_period = 8 data_width2 = 16
module TOP ( data_in , data_out , averg_per_sel ) ; parameter data_width1 = 12; 3; parameter averg_period = 8; 2; parameter data_width2 = 16; 4; input [data_width1-1:0] data_in ;

Checking for Design Issues

Use check_design to check for design problems such as undriven or multi-driven ports and pins, unloaded sequential elements and ports, unresolved references, constant connected ports and pins, and any assign statements in the design. Syntax check_design [-undriven] [-unloaded] [multidriven] [-unresolved] [-constant] [-assigns] [-all] [<design>] [> file] If you do not specify any options, the check_design command reports a summary in a table format.

Specifying Design Constraints

You can specify the design constraints in either of these two ways: SDC File (recommended) You can read SDC directly into the compiler after elaborating the top-level design. read_sdc <sdcFileName><.gz> Encounter RTL Complier Tcl Constraints

Checking for Missing Constraints

Use report timing -lint to check for missing constraints. Always run this command and review the log file before synthesis.
Here are some examples of missing constraint warnings:

Missing Constraint
Unclocked primary I/Os Unclocked flops

Solution
Define external_delay for these I/Os. Check the fanin cone of these flops using the fanin command. To see which clocks are being propagated to that pin, use the inverting_clocks or non_inverting_clocks attribute of the pin. Use the timing_case_logic_value attribute to propagate only one clock to that pin (set_case_analysis).

Multiple clocks propagating to the same sequential clock pin

Timing exceptions overwriting other timing exceptions, such as setting a false path and multicycle path starting in the same register. Timing exceptions that cannot be satisfied, such as a false path that starts in a flop that was deleted.

Check the log file and remove the redundant ones.

Check the log file.

Setting User Priority and Deleting Constraints

If a timing path satisfies two conflicting timing exceptions, and you want to use one and not the other, set a higher priority on the desired exception by using the user_priority attribute. Example set_attr user_priority 5 $my_multi_cycle set_attr user_priority 4 $other_exception To delete a constraint without exiting the rc shell use the rm command. Example rm $my_multi_cycle

Synthesizing the Design

The goal of synthesis is to provide the smallest possible implementation of the design while meeting timing and power constraints. Use the synthesize command to run synthesis. Syntax synthesize [to_generic] [to_mapped] [-effort <level>] [-incremental] [design|subdesign] -to_generic Optimizes the MUX and datapath and stops before mapping. -to_mapped Maps the specified design(s) to the cells described in the supplied technology library and performs logic optimization. -effort <level> Can be low, medium (default) or high. -incremental/-no_incremental turn incremental synthesis on/off as part of single pass -csa_effort <level> - carry-save effort level addresses equivalency checking limitations By default, the synthesize to_mapped command will run generic optimization, mapping and incremental optimization.

Reporting
report area report datapath report design_rules report gates report hierarchy report instance report memory report messages report power report qor report timing report summary Prints an exhaustive hierarchical area report. Prints a datapath resources report. Prints design rule violations. Reports libcells used, total area and instance count summary. Prints a hierarchy report. Prints an instance report. Prints a memory usage report. Prints a summary of error messages that have been issued. Prints a power report. Prints a quality of results report. Prints a timing report. Prints an area, timing, and design rules report.

Generating Timing Reports

puts " WNS path/timing among all in2out paths" report timing -from [all::all_inps] -to [all::all_outs] puts WNS path/timing among all in2reg paths" report timing -from [all::all_inps] -to

[all::all_seqs]
The all:: commands are Tcl procedures that are part of load_etc.tcl, which is part of your installation hierarchy. Please include load_etc.tcl before using these commands. The .synth_init is a good place to do this.

puts "WNS path/timing among CLK to outputs in domain $clk " report timing -from $clk -to [all::all_outs] puts "WNS path/timing among CLK to D paths in domain $clk" report timing -from $clk -to [all::all_seqs]

puts "WNS path/timing among paths that cross from $clk to $clk2 domains" report timing -from $clk -to $clk2

Fanout and Load: STA Using report timing

======================================== ======================================== G enerated by: RTL Com piler (RC) 5.1 G enerated on: N 05 2004 02:33:19 PM ov M odule: tim ing_example Technology library: cb35os141d_typ 7.1/ 3.3b O perating conditions: N M (balanced_tree) CCO W ireload m ode: segmented ======================================== ======================================== Pin Type Fanout Load Slew D elay A rrival (fF) (ps) (ps) (ps) -------------------------------------------------------------------------------(clock clk) launch 0R stage_y_reg_0/ cp 0 0R 1 1021 41 2051 2051 R 251 stage_y_reg_0/ q dfnrq1 16 101 3741 +4706 251 R 4706 + 2051 251 timing_exam ple/ y[0] < < out port < + 0 4706 R 0 2051 + 251 (ou_del_1) ext delay + 0 4706 R 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk) capture 500 R -------------------------------------------------------------------------------Load exponentially affects delay. Timing slack : - 4206ps ( TI M N V O TI O ) 1551ps I G I LA N 249ps Load exponentially affects delay. Start- point : stage_y_reg_0/ cp Fanout exponentially affects delay. End- point : y[0]

STA Using report timing -exceptions

======================================== ======================================== G enerated by: RTL Compiler (RC) 5.1 G enerated on: N 05 2004 02:04:16 PM ov M odule: add Technology library: tutorial 1.0 O perating conditions: typical_case (balanced_tree) Wire-load mode segmented is W ireload mode: segm ed ent not always recommended. ======================================== ======================================== Pin Type Fanout Load Slew D elay A rrival (fF) (ps) (ps) (ps) -------------------------------------------------------------------------------stage_a_reg_0/ CK < < < 0 0R stage_a_reg_0/ Q fflopd 2 25.7 17 + 148 148 R g82/ A + 0 148 g82/ Y nand2 3 45.9 52 + 130 278 F g81/ A + 0 278 g81/ Y inv1 1 10.5 15 + 84 363 R g66/ B + 0 363 g66/ Y nand2 1 10.5 45 + 121 484 F g62/ B + 0 484 g62/ Y nand2 1 15.5 46 + 120 604 R g59/ A + 0 604 g59/ Y xor2 1 20.5 58 + 146 751 R stage_y_reg_3/ D < < fflopd < + 0 751 stage_y_reg_3/ CK setup 0 + 100 851 R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - path_delay 100 -------------------------------------------------------------------------------Except i on : path_delays/ del_1 100ps Tim slack : - 751ps (TIM G V LA N ing IN IO TIO ) Exceptions are reported here. Start- point : stage_a_reg_0/ CK End- point : stage_y_reg_3/ D

Generating Outputs
Commands for Generating Outputs Use the write_hdl command to generate a gate-level netlist. write_hdl > | >> filename Use write_script command to generate the constraints file. write_script > | >> design_constraints.g Use write_sdc command to export RTL Complier constraints in the SDC Tcl format. write_sdc [design] > | >> [filename]

Use the > symbol to redirect the output to a file or >> to append it to the file.
write_hdl > <path to the output dir>/design.v

Example Script
set_attr information_level 9 / set_attr lib_search_path <UNIX Library Search Path> set_attr hdl_search_path <UNIX HDL Search Path> set_attr library {<library01> <library02> <libraryNN> } read_hdl { <design01>.v <design02>.v <designNN>.v }
Set the diagnostic variables.

Set the library and file search path.

Load all the libraries for the design. Load all the modules of the design. Elaborate the top level module. Set the design and timing constraints. Synthesize and map the design.

elaborate <TopLevel DesignName> read_sdc constraints.sdc synthesize -to_mapped report timing -num_path 10 > timing_10_worst.rpt report area > area.rpt report gates > gates.rpt write_hdl > <NetlistFileName> write_sdc > < file name>

Create reports.

Write netlist and constraints to disk.

Command Help
You can get help on all the commands by entering: man command_name To view man pages from the UNIX shell, set your environment using: setenv MANPATH $CDN_SYNTH_ROOT/share/synth/man When you are unsure of a command, type the first few letters of the command and press the Tab key to display a list of commands that start with those letters. Example path_ This command returns the following: ambiguous "path_": path_adjust path_delay path_disable path_group Entering path_* -h does the same as the previous command and provides help for commands.

Thank You