2009 10th ACIS International Conference on Software Engineering, Artificial Intelligences, Networking and Parallel/Distributed Computing

A HW/SW Co-design Methodology: An Accurate Power Efficiency Model and Design Metrics for Embedded System
Iftikhar, Khan 1, Taikyeong Ted. Jeong 1,*, Gyungleen Park 2, and Anthony P. Ambler 3 Abstract Low-power embedded system design has become extremely important in the most recent years. To fulfill system-level design requirements and time-to-market constraints, a power-driven methodology is essential during embedded system design. The aim of this paper is to introduce accurate and efficient power metrics included in a hardware/software (HW/SW) co-design environment to show the system-level partitioning and design. In order to verify the design effectiveness of hardware/software co-design synthesis, we consider the digital power dissipation methodology and its power reduction techniques. To maximize the performance of system, we developed hierarchical design technique and co-design synthesis for power efficient HW/SW co-design process. In the end, we provided simulation results for single circuit with new design vs. circuit integration with hierarchical power efficiency system (HPES), multiple circuits with new design vs. circuit integration with HPES, new design and no load vs. circuit integration with HPES, new design with load vs. circuit integration with HPES.
Index Terms Embedded systems, hardware/software codesign, low-power, power metrics

I. INTRODUCTION An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions, sometimes with real-time computing constraints. It is usually embedded as part of a complete device, including electrical and mechanical parts, today as they control many of the common devices we use. In general, the typical embedded system architecture consists of hardware, software and peripheral parts. The hardware part consists of one or more general-purpose or
This research was supported by the Korea Science and Eng. Foundation (KOSEF) grant funded by the Korea gov.(MOST) (No.R01-2007-000-205990) and (No.M20809005636-08130900-63610). This research was jointly supported by the MIC, Korea, under the ITRC support program supervised by the IITA (IITA-2008-C1090-0801-0040). Iftikhar Khan was with Dept. of Communications Eng., Myongji Univ., Korea and now with in Pakistan. Taikyeong Ted Jeong., * Corresponding Author, is with Dept. of Communications Eng., Myongji Univ., Korea (e-mail: ttjeong@mju.ac.kr). Gyungleen Park is with Dept. of Computer Statistics, Cheju National University, Korea Anthony P. Ambler is with Dept. of Electrical and Computer Eng. at the University of Texas at Austin. USA.
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dedicated hardware units such as full customized design Application Specific Integrated Circuits (ASICs) [1]. At the same time, the software part consists of specialized software run on a dedicated processor or ASICs. Therefore, to utilize the maximum benefits from submicron Complementary MetalOxideSemiconductor (CMOS) technologies, implementation of maximum possible components of embedded system on a single ASIC is required. A typical co-design process goes through the procedures mentioned below. First of all, define the functional description of the system using concurrent process programming languages. After that, perform HW/SW partitioning using unified representation of data/control flow. Then, perform the interface synthesis of a system using hardware and software synthesis approach. The final step for the HW/SW co-design process is the system-level integration. If there is a requirement for more HW/SW partition for a particular system, then feedback is created to HW/SW interface synthesis step. The co-design approach improves design quality, design cycle time, and cost. Co-design reduces integration and test time and it supports growing complexity of embedded systems. It also takes advantage of advances in design tools and technologies such as processor cores and hardware synthesis capabilities. In Fig. 1, a typical co-design process HW/SW method is shown.

Fig.1: A Typical Co-design Process

978-0-7695-3642-2/09 $25.00 2009 IEEE DOI 10.1109/SNPD.2009.71

The paper is organized as follows: Co-design procedure on real HW and SW, power estimation procedure for the HW and SW part, Customized HW/SW Co-design system is discussed in Section 2. While low power CMOS design case study and hierarchical design approach are addressed in Section 3. Simulation results are also provided in Section 4, to demonstrate the advantages offered by the proposed methodology during the development of control dominated embedded systems. Finally, concluding remarks are drawn in Section 5. II. CO-DESIGN PROCEDURE ON REAL H/W AND S/W Embedded controllers are implemented for real time application as mixed hardware-software systems by most of the designers. Unified framework is used in formal methodology for specifying, modeling, automatically synthesizing, and verifying such systems. After interactive partitioning, co-design on real hardware and software automatically synthesizes the entire design, including hardware-software interfaces. To maintain a finite-state machine model, co-design procedure on real hardware and software preserves the formal properties of the design. A. HW part Power Estimation Procedure Following are inputs for the estimation procedure: Hierarchical VHDL description of the target system architecture is used for the ASIC specification; to implement the basic modules, (such as logic gates, I/O pads, registers, multiplexers, etc). Macro-modules, (such as adders, multipliers, etc), allocation library is used. Frequency, power supply, transition factors are used as the technological parameters inputs. The ASIC primary I/Os are used as the switching activity. The average power of the VHDL descriptions is associated to the physical capacitance and the switching activity of the nets, in an analytical power model. Hierarchical estimation approach is used, which consists of highest and lowest hierarchical level. Ad-hoc analytical power models for each part of the target system architecture are proposed for highest hierarchical level, whereas lowest hierarchical levels are based on a macro-module library, at the lowest hierarchical levels. Weakly pattern-dependent approach is used, to avoid a large amount of input patterns to be simulated. Input probabilities are supplied by the user, which reflects the typical input behavior and the system-level specification. In the proposed single ASIC architecture, the total average power dissipated PAVE is given by

B. SW part Power Estimation Procedure In general, the average power dissipated by a processor while running a program is PSW = IAVE * VDD, where IAVE is the average current and VDD is the supply voltage. The associated energy is given by ESW = PSW * tSW, where tSW is the execution time of the software program, which can be expressed as: tSW = NCLK * CLK. NCLK is the number of clock cycles to execute the program and CLK the clock period [7]. In terms of the energy dissipated by each type of instruction in the instruction set, it is essential to perform some measurements on the energy cost of each instruction to have detailed power information provided by the processor supplier, to compute the average current drawn during the execution of each instruction. For reporting the energy consumption for each instruction in the instruction-set and all possible addressing modes associated with each instruction type, a power table can be derived for each processor [8]. C. Customized HW/SW Co-Design In Fig. 2, Customized HW/SW Co-design method is shown. The nomenclature used here is slightly different from that of Wolf [9] and Axelsson [10]. First of all we have to define the Design Specification, which usually consists of a collection of metrics, both functional and non-functional, which provide a precise description of the top-level system attributes and requirements. Examples of metrics include throughput, latency, unit cost, power consumption, maintainability, productivity and time-to-market.

PAVE

PIO

PCORE

Where PCORE and PIO are the average power dissipated by the core internal nets and the I/O nets, respectively. The power model of core logic is based on the models of the different components of the target system architecture; therefore the PCORE term can be in turn expressed as

Fig. 2. Customized HW/SW co-design

PCORE

PDP

PMEM

PCNTR

PPROC

Where the single terms represent the average power dissipated by the data-path (PDP), the memory, the control logic (PCNTR) and the embedded-core processor (PPROC) [6].
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And then, we have to define the Hardware Architecture, which means describing what hardware components should be used and how they should be connected [10] to support the execution of the processes. Then we have to define Synthesis process which is the implementation of the hardware and

software processes for the selected hardware. After that, we have to go through Integration process which is the recombination and testing of processes and interfaces, after implementation. Next, we have to do the planning and partitioning of the system under consideration which is the action of breaking the system functionality into small domain-independent, concurrent and interacting/communicating processes. Performance requirements for the processes, such as frequency, throughput, and latency should also be defined. At the same time, we have to go through Mapping process which can be defined as the selection of specific hardware components and mapping the processes on to parts of the hardware architecture. This includes mapping processes from the software domain to the processor(s) on which they will be executed. Much consideration should be given to the execution requirements of the processes. Manufacturability should be considered during component selection. Also, we have to go through the Allocation process which can be defined as the action of assigning each process to either the hardware domain or the software domain. Communication bandwidth alternatives/limitations between hardware and software should be considered. For example, two processes exchanging lots of data frequently would likely best exist in the same domain. In the end, we have to perform the Scheduling process in which the assignment of resources to all system processes is done and their execution requirements are satisfied including inter-process communication dependencies. The Proposed Method III. A CASE STUDY: LOW POWER CMOS DESIGN EXAMPLE A. Trade-off between Power and Circuit Delay To trade-off delay and power the remaining three variables under the designers control can be used only.

architecture can be made to cover a large range of operating points, as demonstrated in Fig. 3. Range is from 0.18um CMOS technology to 0.13um technology. Another method for trading off delay and power is to vary the device width W. However, the trade-off is dependent on how large CFIX is with respect to CW. Empirical data shows these capacitances are typically on the order of the same size for transistors with minimum width. As the width is increased above the minimum value, the power increases but the delay is decreased. However, after a short interval of time CW dominates CFIX , and then power scales linearly with width, while the delay remains approximately constant. Thus, there is a delay-power trade-off, but only over a small range of delay values. Scaling the clock frequency is a third approach which is most beneficial if it is coupled with voltage scaling. If the clock frequency is reduced, the delay may be increased (keeping it equal to 1/fCLK ) by reducing the supply voltage and thus saving power. If the voltage is kept constant, then power and throughput reduce linearly with clock frequency [13]. B. Hierarchical Design Method In order to meet the design requirement, we present a new design technique for CMOS design, which is called Hierarchical power efficiency system (HPES) with co-design synthesis, is an efficient way to reduce the dynamic power consumption andit will satisfy the final system design specification. High performance design process is divided into three steps which are as follows: First of all, we have to define Accurate and Power efficient metrics for a particular system under consideration. Then we have to apply digital power dissipation & reduction techniques. In the end, we have to apply the Hierarchal Design Technique & Co-design Synthesis procedure. Fig. 4 shows the necessary steps with a simple block diagram of HPES.

Fig. 3: Comparison of delay vs. power vs. CMOS technology As the voltage is reduced, the delay increases hyperbolically as the supply voltage approaches VT. Meanwhile, the power drops, due to the product of the squared voltage term and the frequency (inverse of the delay) term. Thus, by operating at various values of supply voltage, a given processor
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Fig.4. Overall block diagram of hierarchical design process IV. SIMULATION RESULTS

The simulation results of the HPES design, which is a dynamic logic comparison, is implemented in Fig. 5. It shows waveforms of dynamic circuit simulation result that the two inputs a and b with clock distribution systems are viewed at the top three waveforms in time dependent scale. Moreover, it is a circuit implementation of power reduction methodology for HPES in high performance chips and systems design. Finally, the output of voltage VOUT has a little power saving in the standby mode and higher output while in the active mode [15]. This simulation results can be demonstrated by low power reduction methodology which includes a cascaded logic. It is also included in the logic configurations, measurements, temperature management techniques and power efficiency system. It discusses the re-configurable circuit for the HPES which is a cascaded logic implemented with high speed and low power. In the paper, a high performance circuit will be considered using low power dynamic logic circuit with low-threshold circuits and a clock generation circuits. The high performance circuit contains a latches, adder, shifter, and drivers, so that, sufficient depth of logic circuits can be evaluated for optimizing in high performance chip and systems. This design will provide a way to analysis the speed, power, and leakage of circuits and their scaling techniques. Furthermore, it will discuss about power estimation techniques by using supply voltage reduction in communication chip and systems. Evaluation device can be eliminated and the corresponding circuit family is called delayed-reset domino logic [16]. In the delayed-reset domino logic, the reset clock should be wide enough to cover all the incoming pulses to avoid any unnecessary DC paths from VDD to ground during the precharge period.

circuit design area, HPES has an advantage of higher performance for lower power trade off. Furthermore, the design and management of power dissipation, the thermal engineering that is required for reliable design of high power chips with non-uniform temperature profile. With increasing design complexity and on-chip functions, especially for System-on-Chip (SoC) designs, negligence of temperature effects can lead to serious chip failures in timing. In high performance circuit designs, speed and power are strongly related with circuit designs as well as architectures. V. CONCLUSIONS AND FUTURE STUDY This paper presented an overview to introduce accurate and efficient power metrics included in a hardware/software (HW/SW) co-design environment to guide the system-level integration and partition. This paper also defines power assessment metrics to widely explore the architectural design space at high level of HW/SW co-design environment. In this paper, we have discussed low power CMOS design example. We also presented co-design process on real hardware /software, power estimation for hardware and software part. Also we have discussed a model of customized HW/SW codesign method and synthesis, which is an efficient way to reduce the dynamic power consumption and it will satisfy the final system design specification. After that we have done circuit simulation using software and simulation results with better power efficiency are shown. From the simulation results we conclude that the single circuit with new design scheme and multiple circuits with new design scheme shows better results in terms of circuit delay vs. power dissipation as compared to circuit integration with HPES design scheme. Similarly, from the simulation results of new design scheme with no load vs. circuit integration with HPES design scheme shows that new design scheme with no load is better in terms of circuit delay vs. power dissipation. Also, simulation results of new design scheme with load vs. circuit integration with HPES design scheme shows that new design scheme with load is better in terms of circuit delay vs. power dissipation. However, for the case of new design scheme with load simulation we observe that the circuit delay and power dissipation increases with increasing load. REFERENCE [1] G. De Micheli and M. G. Sami, Eds., Hardware/Software Co-Design, New York: Kluwer Academic, NATO ASI Series, 1996. [2] W. Fornaciari and D.Sciuto,Hw/Sw Codesign of Embedded Systems, Politecnico di Milano, Dipartimento di Elettronica e Informazione, P.zza L. Da Vinci, 32 20133 Milano, Italy. [3] M.Chiodo, P.Glusto, Hardware-Software Co-design of Embedded Systems, University of California, Berkely, Politecnio di Torino, IEEE Micro, August 1994. [4] F. Najm, Transition Density: A new measure of activity in digital circuits, in IEEE Trans. On CAD, Vol. 12, No. 2, pp. 310-323, February 1995.
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Fig.5. Dynamic circuit implementation result In order to reduce the system power consumption, we need to consider new scheme, which is HPES with co-design syntheses method. Modern computer architectures dedicate a significant fraction of the chip to system hierarchies. In digital

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