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Control Unit Implementation


Control Unit of a CPU is responsible for generating all the timing and control signals required both by internal and external units of the CPU for proper execution of instructions. There are two popular methods available to design the CU. Hard wired control unit (Hardware approach) Micro program control unit (Software approach)

Hard wired control unit


The hardwired approach has the advantage that it is possible to devise faster CPUs if typical CPU speeds are faster than typical memory speeds (a situation that has been true for quite some time). The drawback to hardwired logic is that it is difficult to design CPUs with large and complex instruction sets using this approach.
Instruction Register (IR) 8 bit OPCODE

OPERAND

Instruction Decoder
Master clock
T1 T2 T3 T4 Tn 0 1 2 3 64 255

Timing Generator

Control M atrix
Sequenced control signals

RESET

Condition codes

The timing generator generates pulses at corresponding time slots as shown below
Master clock T1

t t t

T2

T3

Similarly all the timing signals are generated up to again from T 1. Same thing repeats in a cyclic manner.

Tn. Then start

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Now consider the fetch cycle. Control signals to activate are listed below according to the order T1 (PC)outA T2 (MAR)inA T3 (MAR)out T4 Read T5 (MBR)in (MBR)outD T6 (IR)inD T7 (PC)inc T8 The above control signals are activated in the given order. In order to do that timing generator outputs are hard wired to an array of AND gates.

Selected Line corresponding to the OPcode 1


(PC)outA
T1

(MAR)inA
T2

Instruction decoder select a line out of 255 according to the Opcode part (64 th line for LOAD A OPcode ). Each and every line is connected to a set of AND gates. Required control signals are activated at the proper order as the timing pulses are applied to gate inputs This continues for the execution cycle as well. Now consider the execution cycle of LOAD A instruction

(MAR)out
T3

Read
T4 T5

(MBR)in (MBR)outD

T6 T7

(IR)inD (PC)inc

T8

Selected Line corresponding to the OPcode 1


(IR)outA
T9

(MAR)inA
T10 T11

(MAR)out Read

T12 T13

(MBR)in (MBR)outD

The RESET control signal initializes the timing generator. In the above execution cycle, the timing generator is reset with T 16 (with 16 th clock pulse). Therefore with the following clock pulse the timing generator will activate T 1 there by starting the fetch cycle of the next instruction. Since the length of the execution cycle can vary from instruction to instruction timing generator will be initilized during different time slots(not always with T 16 )

T14 T15

(ACC)inD RESET

T16

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Draw the AND gate band diagram for the FETCH & EXECUTION cycles of the ADD A,(address) instruction

(Complete your self)

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Draw the AND gate band diagram for the FETCH & EXECUTION cycles of the STORE A,(address) instruction

(Complete your self)

Draw the AND gate band diagram for the FETCH & EXECUTION cycles of the JUMP (address) instruction

(Complete your self)

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Now it is clear that each machine code instruction (OPcode) requires a separate AND gate band inside the control matrix in the CU. As the number of instruction increases gate count also increases. This limits the instruction set to a small number. A particular control signal (e.g. (MAR)out) will have to be activated during different intervals for different instructions. Therefore the similar control signals from the AND gate bands must be combined using a band of OR gates to derive a final control signal output.
STORE A, (address)

T11
FETCH cycle T3

(MAR)out (MAR)in A

Further it is possible to carry out some operations in parallel without affecting the other. E.g. put ACC to Bus D & IR to Bus A. So that time taken to complete the execution of an instruction can be reduced. Consider the execution cycle of STORE A,(address) instruction.

1
(IR)outA / (ACC)outD
T9 T10 T11 T12 T13 The disadvantage of hard wired CU is that it makes the instruction set fixed and no modifications or enhancements to the instruction set is possible after it is manufactured. However hard wired control units can be operated at high clock rates and more suitable for high speed CPUs.

(MAR)inA / (MBR)inD (MAR)out / (MBR)out Write RESET

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Micro Program Control Unit


(IR) OPCODE OPERAND

Starting Address Selection (Instruction Counter Source Selector) LOAD RESET

CCR

-PC - Program memory


(Control memory) Instruction Decoder

- IR

Control signals

The instruction counter source selector (ICSS) provides the starting address of the microinstruction fragment corresponding with the current machine code instruction. The micro program counter starts counting from this starting address. The microinstruction currently being executed, is held in the microinstruction register, and is decoded by the instruction decoder for final control outputs. At he end of each fetch cycle micro instruction program counter is loaded by the output of the ICSS.at the end of each execution cycle the -PC is reset, initiating the next fetch cycle.

The control memory is divided in to number of micro instruction segments. Each segment contains number of micro instructions. There is a micro instruction fragment corresponding to fetch cycle. usually the first one, fragnent1. Similarly there is a micro instruction fragment corresponding for each execution cycle , of the machine code instruction cycle.

-ins1

Fragment 1

-ins2

-insN

Fragment 2 Fragment 3

Micro program CU can be implemented in three different ways. 1. Horizontal microprogramming 2. Vertical microprogramming 3. Combined microprogramming Control Unit Implementation 28

Horizontal microprogramming

(MAR)in

(MBR)in (MAR)out (MBR)out

Micro instruction format

LOAD RESET

In horizontal micro programming a unique bit position in the microinstruction format is reserved for each control Each microinstruction is responsible for the activation of a single control signal. Let us consider the fetch cycle. The control sequence for the fetch cycle is given here

(PC)outA (MAR)inA (MAR)out Read (MBR)in (MBR)outD (IR)inD (PC)inc

(MAR)out

(MBR)out

D
(MBR)out

(MAR)in

(MBR)in

(PC)inc

WRITE

(PC)out

1 2 3 4 5 6 7 8 9

0 1 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0

0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0

1 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0

LOAD

0 0 0 0 0 0 0 0 1

In horizontal micro programming an instruction decoder is not necessary inside the control unit. Control signals are straight away derived from the microinstruction register. Each out put of microinstruction register corresponds to a control signal output. In horizontal microprogramming the length of the microinstruction is relatively large (If there are 200 control signals to be generated, each micro instruction will be 200 bit long). This is considered as major disadvantage of the horizontal microprogramming. However this technique supports the parallel operation of controls. If parallel operation of controls are provided, a microinstruction can contain more than a single one 1. Further advantage of this technique is that it does not require an instruction decoder Draw the control memory for the execution cycle of ADD A,(address) instruction Control Unit Implementation 29

RESET

READ

(IR)in

Clock cycle

(MBR)in

0 0 0 0 0 0 0 0 0

(Complete Your self)

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Draw the control memory for the execution cycle of STORE A,(address) instruction

(Complete Your self)

Vertical microprogramming This technique is an effort to reduce the microinstruction length. There by reducing the complexity of micro IR and the control memory. Ex. Lets assume that there are 256 controls and each microinstruction activates a single control out of the 256 controls. Since 256 = 28, an 8 bit coded microinstruction can be used. This technique is known as Vertical microprogramming and an instruction decoder is required to get the final control outputs. The advantages of vertical micro programming are the reduced micro instruction length & control memory size. The major disadvantage is the inability to perform Parallel operation of controls. Further an additional instruction decoder is required. Due to the additional instruction decoder the speed of the control unit can be slower compared to horizontal micro programming.

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Combined microprogramming This is a hybrid version of horizontal and vertical micro programming. This technique tries to reduce the microinstruction length, while allowing parallel operation of controls. In this technique the control signals are grouped in such a way that parallel operation of controls is not required within a group. E.g. Group1 Group2 Group3 Bus D controls (ACC)out D (R0)out D (TEMP)out D) Bus D out put controls (ACC)in D (R0)in D ALU controls.

Group1

Group2

Group3

Fully encoded bit pattern


Each group require separate decoder unit. Group1 Group2 Group3

Decoder 1

Decoder 2

Decoder 3

Decoder 4

Control signals

Control signals

Control signals

Within each group a fully encoded bit pattern can be used so that only a single control within a group can be activated at a time. However control signals from different groups can be activated at the same time. An additional bit pattern within each group is required to keep all the control signals disabled, each other pattern would corresponds to the activation of a single control within the group. A micro program control unit can be slower than a hardwired control unit however the advantage of a micro programmed control unit over a hard wired one is the flexibility to change the available instruction set and EPROM (Erasable Programmable Read Only Memory) can be used for the control memory of micro program CU, allowing the micro instruction fragments to be re-programmed Control Unit Implementation 32

Exercise 1. Draw the internal architecture of a typical microprocessor. 2. Explain the functions of Control unit and ALU 3. Briefly mention about special purpose registers and general-purpose registers. 4. Determine the number of control signals required to operate the above microprocessor. 5. Draw the micro operation and control signal sequences for the following processes. i) Instruction fetch cycle ii) Execution cycle of LOAD A,(address) instruction iii) Execution cycle of ADD A(address) instruction iv) Execution cycle of PUSH A instruction v) Execution cycle of POP A instruction 6. Explain the operation of a micro programmed control unit. Draw the micro program segment (Horizontal technique) corresponding to above processes. 7. Explain the operation of the following assembly language program segment. PUSH A PUSH R0 LOAD A,(2A0001H) ADD A,(2A0002H) STORE A,(2A0003H) POP R0 POP (010000H) 8. This program is supposed to run on the above microprocessor. Write down the micro operations for the fetch cycle and execution cycle of the first instruction (PUSH A,) with corresponding control signals to be activated. 9. Draw the AND gate array diagram to generate the above control signals at proper time slots. 10.Identify the addressing mode used in the following instruction and explain its operation. LOAD A,(R1) 11.What does pipelining mean?. 12.Name the six segment registers of the 80386 and above. 13.Explain the difference between the AH, the AL. the AX. and the EAX registers. 14. (a) What is a flag. (b) What two purposes are flags used for. 15.What are the two types of information stored in memory? 16.What is meant by the term 32 bit microprocessor

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