Bit and Byte

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Bit and Byte

A signal the state of which is exclusively defined by two values, is a binary signal and is called a BIT = BINARY DIGIT . A BIT stands for a unit of a binary signal and represents the smallest unit of information technologic units with two unequivocal signal states, defined "0" or"1". 4 Bit make a half-byte or a nybble. 2 nybbles/half-byte make a byte. 8 Bit are combined in one Byte . One Byte expressed binary could represent the values 0 to 255 or the values -127 to +127 . Two coherent bytes (2Byte = 16 Bit) make a digital word (WORD). 1 word = 2 Byte = 16 Bit. Two coherent words make a digital double word (DWORD). 1 double word = 2 words = 4 Byte = 32 Bit. The terms bit , byte and double word known from information technology and data processing are also used for programmable locic controls. Within one byte every bit is allocated a digit - the bit address.Via these bit addresses the single bits are recognised and also activated. The addressing of the 8 bits within one byte is carried out from right to left, far right there is bit 0 and far left there is bit 7. Bit address

Representation of the bit address 0 to 7 Byte address Every single byte again contains a number, the byte address. In addition the operand is defined. IB1 stands for input byte 1 or QB2 for output byte 2. A single bit is addressed unequivocally by the combination of bit- and byte address. The bit address in this procedure is separated by a point from the byte address. Left from the point there is the byte address and right from the point there is the bit address. Thus the output Q2.3 is the third bit within the second byte of an output component. Diagram of a byte address

Representation of the byte address Word address By numbering of words the word addresses are made. The word addresses when using input words IW, output words QW and memory words MW is always the smaller byte address of the two bytes in the word. The same goes for double words, here it is the smaller word address which is the address of the double word. Diagram of a word address

Representation of word address Specifics of the addressing From the above illustration the following can be derived: Output Word QW0 consists of output byte QB0 and output byte QB1 Output byte QB0 consists of output bytes Q0.0 to Q0.7 Output byte QB1 consists of output bytes Q1.0 to Q1.7 Output word QW2 consists of output byte QB2 and output byte QB3 Output byte QB2 consists of output bytes Q2.0 to Q2.7 Output byte QB3 consists of output bytes Q3.0 to Q3.7 Output word QW1 consists of output byte QB1 and output byte QB2 Output byte QB1 consists of output bytes Q1.0 to Q1.7 Output byte QB2 consists of output bytes Q2.0 to Q2.7 The same goes for addressings of double words. Addressings here are also to be treated with special care. If an output double is to be addressed according to the example of word addresses above then this output double word QDW0 consists of the following addresses:

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Bit and Byte

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output double word QDW0 consists of output word QW0 and output word QW2 output word QW0 consists of output byte QB0 and output byte QB1 output word QW2 consists of output byte QB2 and output byte QB3 output byte QB0 consists of output bytes Q0.0 to Q0.7 output byte QB1 consists of output bytes Q1.0 to Q1.7 output byte QB2 consists of output bytes Q2.0 to Q2.7 output byte QB3 consists of output bytes Q3.0 to Q3.7

Rules for addressing Note: In tis example the output word QW1 dropped for the output double word QDW0 cannot be activated because in this case it would result in an overlapping of the address field. That means that for an addressing of an output double word QDW0 the next possibly addressable output double word would be the output double word QDW4. This goes for all addressings when inputs, outputs, and memory are made as well as for the address allocation of Integers (INT, DINT) and Floating Point Numbers (REAL). Home | Contact | Privacy | About us | Sitemap | PLC-Pages

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12/01/2013