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VHDL/FPGA Applications in Signal Processing and Communications

By: Robert Patterson and Ismail Jouny

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Overview of Presentation
Description of an FPGA n Description of VHDL n Applications
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Error Control Coding CDMA Communications Master/Slave And Token Ring Networks Pattern Classification With A Hopfield Neural Net
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Design Options
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TTL logic chips


Difficult for large designs Customized board Limited by power consumption and time delay Custom masks required for wiring Expensive Long turnaround time
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PLD

ASIC/MPGA

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What is an FPGA?
Field Programmable Gate Array n Consists of:
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n An

array of configurable logic blocks n Programmable I/O blocks n Programmable interconnects

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Benefits of Using an FPGA


Programmed by users at their site using programming hardware n Can implement tens of thousands of gates of logic on a single IC n Can be programmed many times n Short development time n Low cost
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What is VHDL?
VHSIC Hardware Definition Language n Common Language for Designers (> 50%) n High-Level Language n Simulation and Synthesis Tools are Available
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Error Control System Overview

A/D converter

Introduction of Error

D/A converter

Encoder
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Decoder
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Error Control Coding Overview


By adding redundancy in the signal, errors can be detected and corrected n Signals are broken up into blocks of data n Parity calculations add extra bits to signal n Receiver tries to detect and correct the error through the use of the parity bits
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(7,4) Hamming Code


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4 data bits => 7-bit code word n Minimum distance between codes is 3 n All single bit errors can be corrected - or n All single and double bit errors can be detected A B
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What is CDMA?
Code Division Multiple Access n Multiple users can use a wide slice of the bandwidth n A unique code accesses the users information n Codes are made orthogonal as much as possible to reduce cross correlation
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CDMA Design Overview


Pn1 Encoder Pn1 Decoder

Encoder Pn2
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Decoder Pn2
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Spectrum Spreading
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Data signal PN-code Coded signal


(M1Pn1 + M2Pn2)Pn1 M1Pn1Pn1 + M2Pn1Pn2 M1 + M2Pn1Pn2 M1
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Received signal at Decoder #1 = = = =


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Master/Slave Network Overview

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Token Ring Network Overview

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Hopfield Neural Net


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An artificial network that is capable of recalling certain stored patterns from a set of inputs

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Hopfield Neural Net (cont.)


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The weight matrix is formed from exemplars

t ij

x x , i j = 0 , i = j , 0 i , j N - 1
M -1 s i s j s=0
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Problems Encountered
VHDL Synthesis/Implementation n Memory in FPGA n Speed of computer in the synthesis of design
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Conclusions
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VHDL/FPGA combination is a very powerful design tool


Versatile Adaptable Efficient Economic

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