SMU MCA Assignments

July 2011 Master of Computer Science (MSCCS) Semester 1 MC0062 Digital Systems, Computer Organizations 4 Credits (Book ID:
D: B0680 & B0684) Assignment Set 1 (60 Marks)

Answer all Questions Q.1) Each question carries Ten Marks Book ID: B0680 Convert the following binary numbers to decimal a. 11.001 (2)
b. c. d. Q.2)
1100 (2) 1111 (2) 1011.101 (2)
Use Boolean algebra to simplify the logic function and realize the given function and minimized function using discrete gates.
f = ab( c + bd ) + ab f = ab( c + bd ) + ab
Answer 2) direct realization of the function
ii) Simplified realization of the function
f = ab( c + bd ) + ab
b a c
Q.3) Simplify the given logic expressions with the given three inputs.
f 1 = ( 0,1,2,5,6,7 )
m
and
f 2 = ( 2 ,4,5,6)
m
Answer:
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July 2011 Master of Computer Science (MSCCS) Semester 1 MC0062 Digital Systems, Computer Organizations 4 Credits (Book ID: B0680 & B0684) Assignment Set 1 (60 Marks)
Or
Case I.) Output is Case II.) Output is Case II) has a common term Case I ) Output is
with with . Therefore realization requires lesser number of gates with
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Case ii) Output is with
Book ID: B0684 Q.4) Explain the following for Instructions: a. Data processing b. Data storage c. Data movement d. Control
Answer: 4 (a) DATA processing is the most fundamental type of machine instruction. The DATA transfer must specify
1. the location of the source and destination each location can be memory, register or top of stack 2. the length of the DATA to be transferred 3. The mode of addressing for each operand If both the operands are CPU registers, then the CPU simply causes DATA to be transferred from one register to another. This operation is internal to the CPU. If one or both operands are in memory, then the CPU must perform some or all of the following actions: Calculate the memory address, based on the address mode. If the address refers to virtual memory, translate from virtual to actual memory address. Determine whether addressed item is in cache. If not issue command to memory module. For example: Move, Store, Load (Fetch), Exchange, Clear (Reset), set, Push, Pop Arithmetic: Most machines provide BASIC arithmetic functions like Add, Subtract, Multiply, Divide. They are invariably provided for signed integer numbers. Often they are also provided for floating point and packed decimal numbers. Also some operations include only a single operand like Absolute that takes only absolute value of the operand, Negate that takes the compliment of the operands, Increment that increments the value of operand by 1, Decrement that decrements the value of operand by 1. Logical: Machines also provide a variety of operations for manipulating individual bits of a word often referred to as bit twiddling. They are based on Boolean operations like AND, OR, NOT, XOR, Test, Compare, Shift, Rotate, Set control avalchandas. Answer: 4) (b) DATA storage Computer DATA storage, often called storage or memory, refers to computer components and recording media that retain digital DATA used for computing for some interval of time. Computer DATA storage provides one of the core functions of the modern computer, that of information retention. It is one of the fundamental components of all modern computers, and coupled with a central processing unit (CPU, a processor), implements the BASIC computer model used since the 1940s.
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Primary storage (or main memory or internal memory), often referred to simply as memory, is the only one directly accessible to the CPU. The CPU continuously reads instructions stored there and executes them as required. Any DATA actively operated on is also stored there in uniform manner. Secondary storage (also known as external memory or auxiliary storage), differs from primary storage in that it is not directly accessible by the CPU. The computer usually uses its input/output channels to access secondary storage and transfers the desired DATA using intermediate area in primary storage. Secondary storage does not lose the DATA when the device is powered downit is non-volatile. Per unit, it is typically also two orders of magnitude less expensive than primary storage. Consequently, modern computer systems typically have two orders of magnitude more secondary storage than primary storage and DATA is kept for a longer time there. Tertiary storage or tertiary memory provides a third level of storage. Typically it involves a robotic mechanism which will mount (insert) and dismount removable mass storage media into a storage device according to the system's demands; this DATA is often copied to secondary storage before use. It is primarily used for archiving rarely accessed information since it is much slower than secondary storage (e.g. 560 seconds vs. 1-10 milliseconds). This is primarily useful for extraordinarily large DATA stores, accessed without human operators. Typical examples include tape libraries and optical jukeboxes. Answer: 4(C) DATA movement Instructions to copy DATA and perform arithmetic operations on the MSP=430 reference two operands. The first called the "source" (abbreviated as src) describes an operand (avalchanda) from which DATA is only
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obtained, and the second operand, called the destination (dst or dest) describes a avalchanda to whom the operation is applied. By default, two-operand instructions operate on words (2-bytes=16 bits) at a time. This default option can be explicitly specified by a ".w" suffix. To operate on bytes, a ".b" suffix can be specified instead. For example, mov.b&0x1000, &1002 ; move 1 byte from 0x1000 to 0x1002 Is a "byte move" instruction, which implements an assignment operator (=). This instruction copies one byte from (source) address 0x1000 to the (destination) address 0x1002. The ampersand (&) is required. Listing of two-operand instructions opcode 4 5 6 7 subc sub dest -= (src + C) with carry all mnemonic mov add addc meaning move dest = src dest += src add with dest += src + C carry flags affected** none all all
sub*
subtract dest -= src compare (like sub; dest - src decimal adjust bit test (AND, but result not stored) bit dst&= ~src bit dst |= src dst ^= src dst&= src set clear (OR)
all
9 0xa=10 0xb=11 0xc=12 0xd=13 0xe=14 0xf=15
cmp* dadd bit bic bis xor and
result
not
saved) all ZCN N,Z; C= !Z; V=0 none none arcane** Z, C=!Z; V=0 N
Answer: 4(d) Control The control unit is the part of a computer that controls the computer's operation. Basically, each part of the computer requires control signals to arrive at particular times for each instruction of the computer's software. The control unit provides those control signals The control system's function is as followsnotes that this is a simplified description, and some of these steps may be performed concurrently or in a different order depending on the type of CPU: 1. Read the code for the next instruction from the cell indicated by the program counter.
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2. Decode the numerical code for the instruction into a set of commands or signals for each of the other systems. 3. Increment the program counter so it points to the next instruction. 4. Read whatever DATA the instruction requires from cells in memory (or perhaps from an input device). The location of this required DATA is typically stored within the instruction code. 5. Provide the necessary DATA to an ALU or register. 6. If the instruction requires an ALU or specialized hardware to complete, instruct the hardware to perform the requested operation. 7. Write the result from the ALU back to a memory location or to a register or perhaps an output device. 8. Jump back to step (1). Q.5) Explain the Virtual address translation method with neat diagram.
Answer: 5) Virtual address translation method A virtual address translation method based on the concept of fixed length pages is shown in Figure given below. Each virtual address generated by the processor is interpreted as a page number followed by a word number. Information about the disk or the main memory is kept in a page table in the main memory.
The starting address of this table is kept in a page table base register. By adding the page number to the contents of this register, the address of corresponding entry in the page table is obtained. The content of this location gives the starting address of the page if that page currently resides in the main memory. Otherwise they indicate the location where the page is to be found in the secondary storage. In this case the entry in the table usually points to an area in the main memory where the secondary storage address of the page is held. Each entry also includes some control bits to describe the status of the page while it is in the main memory. One control bit indicates whether the page has been modified when it was in the main memory.
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If the page table is stored in the main memory unit, then the two main memory accesses must be made for every main memory access requested by the program. This may result in a degradation of speed by a factor of two. However a specialized cache memory is used in most of the systems to speed up the translation process by storing recently used virtual to physical address translation. Virtual memory increases the effective size of the main memory. Only the active space of the virtual address space is mapped onto locations in the physical main memory, whereas the remaining virtual addresses are mapped onto the bulk storage devices used. During a memory cycle the addressing spacing mechanism (hardware or software) determines whether the addressed information is in the physical main memory unit. If it is, the proper information is accessed and the execution proceeds. If it is not, a contiguous block of words containing the desired information are transferred from the bulk storage to main memory displacing some block that is currently inactive. Q.6) Explain the addition of a two floating point numbers with examples.
Answers: 6) Two floating numbers can be added as per the steps given below: 1. The exponents of the two floating point numbers to be added are compared to find the number with the smallest magnitude. 2. The significand of the number with the smaller magnitude is shifted so that the exponents of the two numbers agree. 3. The significands are added. 4. The result of the addition is normalized. 5. Checks are made to see if any floating point exceptions occurred during the addition, such as overflow or underflow. 6. Rounding occurs. Floating Point Addition Example: Example: s= x + y Numbers to be added are x = 1234.00 and y = -567.8 These are represented in decimal notation with mantissa (significand) of four digits. Six stages (A-F) are required to complete the addition. Step A B C D E F X 0.1234E4 0.12340E4 Y 0.05678E3 0.05678E4 S 0.066620E4 0.06662E3 0.6662E3 0.6662E3 Biased exponents and the assumed 1.0 before the magnitude are thrown out. And all numbers are decimal numbers and no compliment is done. Time for addition Each stage of the addition takes t time units and each floating point addition takes 6t time units. Time t 2t 3t 4t 5t 6t 7t 8t Step A x1 + y1 x2 + y2 B x1 + y1 x2 + y2 C x1 + y1 D x1 + y1 E x1 + y1 F x1 + y1
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Q.1) Each question carries Ten Marks Book ID: B0680 Implement the following SOP expressions with discrete gates a) f = (0,2,4,6,8,10,12,14) b) f = (1,3,5,7,9,11,13,15) What do you mean by latch? Explain the working of NAND gate based latch operation. Answer:2) The latch is a bi-stable device. The term bi-stable refers with respect to the output of the device that can reside in either of two states and a feedback mechanism is used. These are similar to the flip-flops in that even flip-flops are bi-stable devices. The difference between the two is in the method used for changing their output state. Active Low S-R Latch (NAND Gate S-R Latch) A NAND gate active high S-R latch can be constructed and is shown in figure 1 which has two cross connected or coupled NAND gate circuitry. Answer all Questions
Q.2)
Figure 1: active LOW S-R Latch Inputs Output S R 0 0 0 1 1 0 1 1 ? 1 0 ? 0 1 Comments Invalid SET RESET No change
Table 1: Truth table of S-R Latch The operation of the active-LOW NAND latch can be summarized as follows 1. SET = 0 and RESET = 0: the condition tries to set and reset the output of the latch at the same time or output is unpredictable. This state is referred as invalid state.
2. SET = 0 and RESET = 1: always sets the output

3. SET = 1 and RE
= 1 and
=0
4. SET = 0: always resets the output = 0 and = 1

5. SET = 1 and RESET = 1: has no effect on the output state from its previous state. Active HIGH NAND latch can be implemented whose circuit diagram is shown in figure 2 and its truth table is shown in table 2
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Figure 2: active HIGH S-R Latch Inputs Output S R 0 0 0 1 1 0 1 1 0 1 ? 1 0 ? Comments No change RESET SET Invalid
Table 2: Truth table of S-R Latch Q.3) How does a synchronous counter differ from an asynchronous counter? Explain the working of 4-bit binary synchronous counter. Answer:3) Asynchronous counter V/S Synchronous Counter In an asynchronous counter, an external event is used to directly SET or CLEAR a flip-flop when it occurs. In a synchronous counter however, the external event is used to produce a pulse that is synchronized with the internal clock. An example of an asynchronous counter is a ripple counter. Each flip-flop in the ripple counter is clocked by the output from the previous flip-flop. Only the first flip-flop is clocked by an external clock A synchronous counter has the same sequence of counting as in an asynchronous or ripple counter. Flip-flops changes state when a synchronous counter is incremented on the positive or negative edge of a clock pulse. Where as in the asynchronous counters the flip-flop changes state for the positive or the negative edge of the preceding flip-flops output. Thus all the flip-flops are connected to a same clock signal and changes state at the same time. A Four-bit Synchronous Binary Up-counter Figure 1 shows a four-bit binary up counter and Figure 2 gives its timing diagram. The reasoning behind the J and K input control for the first three flip-flops is the same as presented previously for the three stage counter. For the fourth stage, FFD, changes only twice in the sequence. And notice that during both of these transitions occur following the times, QA, QB and QC are all HIGH. This condition is denoted by a three input AND gate. For all other times inputs J and K of FFD are LOW, and it is in a no-change condition.
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Figure 1: A Four bit synchronous up counter.
Figure 2: Timing diagram for the four bit synchronous up counter. Book ID: B0684 Q.4) Write notes on: I/O commands I/O instructions Answer: 4) (a) I/O commands To execute an I/O related instruction, the CPU issues an address, specifying the particular I/O module and external device and an I/O command. Four types of I/O commands can be received by the I/O module when it is addressed by the CPU. They are A control command: is used to activate a peripheral and tell what to do. o Example: a magnetic tape may be directed to rewind or move forward a record.
A test command: is used to test various status conditions associated with a 110 module and its peripherals. The CPU wants to know the interested peripheral for use. It also wants to know the most recent I/O operation is completed and if any errors have occurred. A read command: it causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer. The CPU then gets the data items by requesting I/O module to place it on the data bus. A write command: it causes the I/O module to take an item of data from the data bus and subsequently transmit the data item to the peripheral
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Figure: Input of block of data using programmed I/O Answer: 4) (a) I/O instructions Addressing I/O Devices Under programmed I/O data transfer is very like memory access (CPU viewpoint) Each device given unique identifier CPU commands contain identifier (address) I/O Mapping When the CPU, main memory, and I/O module share a common bus two modes of addressing are possible. 1. Memory mapped I/O Devices and memory share an address space I/O looks just like memory read/write No special commands for I/O Large selection of memory access commands available 2. Isolated l/O Separate address spaces Need I/O or memory select lines Special commands for I/O Limited Set What are the functional requirements of a CPU? Discuss the significance of Data Path and Control Signal. Functional Requirements The functional requirements of control unit are those functions that the control unit must perform. And these are the basis for the design and implementation of the control unit. A three step process that lead to the characterization of the Control unit:
Q.5)
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Define the BASIC elements of the processor Describe the micro-operations that the processor performs Determine the functions that the control unit must perform to cause the micro-operations to be performed.
BASIC Elements of Processor The following are the BASIC functional elements of a CPU: o ALU: is the functional essence of the computer. o Registers: are used to store DATA internal to the CPU. As discussed earlier, Some register also contain status information needed to manage instruction sequencing ex: program status word. Some register contain DATA for transfer between ALU, memory, I/O modules. o Internal DATA paths: are used to move DATA between the registers and ALU o External DATA paths: are used to link registers and I/O modules, often by a system bus. o Control Unit: The control unit causes operations to happen within the CPU.
Types of Micro-operation The execution of a program as seen earlier consists of operations involving these CPU elements. These operations consist of a sequence of micro operations. All micro instructions fall into one of the following categories: o Transfer DATA between registers o Transfer DATA from register to external o Transfer DATA from external to register o Perform arithmetic or logical ops All micro operations need to perform one instruction cycle.
Functions of Control Unit Now we define more explicitly the function of control unit. The control unit perform two tasks: o Sequencing: The control unit causes the CPU to step through a series of micro-operations in proper sequence based on the program being executed. o Execution: The control unit causes each micro-operation to be performed. These tasks are accomplished using Control Signals Control Signals For the control unit to perform its function, it must have inputs that allow it to determine the state of the system and outputs that allow it to control the behavior of the system. These are the external specifications of the control unit. Internally, the control unit must have the logic required to perform sequencing and execution functions. Let us take a close look on the general model of the control unit given in figure 1. The model is indicated with all of its inputs and outputs. As from earlier section we know that the function of control unit is sequencing and then execution of instruction. Hence the control unit organization can be considered as shown in fig 2.
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Figure 1:
Figure 2: Control Unit Organization Control unit Inputs The possible inputs for the control units are: Clock: The control unit uses clock to maintain the timings. The control unit causes one micro-instruction (or set of parallel micro-instructions) per clock cycle. This is sometimes referred to as the processor clock time or the clock cycle time. Instruction register: Op-code of the current instruction is used to determine which micro-instructions to be performed during the execution cycle. Flags: These are needed by the control unit to determine the status of the CPU and outcome of previous ALU operations. Example: As seen earlier the instruction ISZ, which is increment and skip if zero, the control unit will increment the PC if the zero flag is set. Control signals from control bus: the control bus portion of the system bus provides signals to the control unit, such as interrupt signals and acknowledgements. Control Signals output The following are the control signals which are output of the control unit: Control signals within CPU: There are two types 1. Signals that cause DATA to be moved from one register to another. 2. Signals that activate specific ALU functions Control signals to control bus: There are two types 1. signals to memory 2. signals to I/O modules DATA paths and control signals To illustrate the DATA paths and control signals we will consider an example as shown in figure 3. This is a simple machine whose CPU has a single accumulator. The control unit receives inputs from the clock, the IR, and the flags. With each clock cycle, the control unit reads all of its inputs and emits a set of control signals. Control signals go to three separate destinations. ALU: the control unit controls the operation of ALU by a set of control signals. This signal activates the various logic devices and gates within the ALU. DATA paths: the control unit controls the internal flow of DATA. For each DATA path to be controlled there is a gate indicated by a circle in figure 3. A control signal temporarily opens the gate to let DATA pass.
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Figure 3: DATA paths and control signals Table 1: Micro-Operations and Control Signals Micro-Operations Timing Active Control Signals t1: MAR < PC t2: memor< MAR C2 Fetch: t3: MBR < memory C5 , CR t4: IR <- MBR C4 t5: PC <- PC +1 t1: MAR <- (IRaddress) C8 Indirect: t2: MBR <- (Memory) C5 , CR t3: IR(address)<- (MBRaddress) C4 t1: MBR <- (PC) t2: MAR <- save-address C1 Interrupt: PC <- routine-address C12 , CW t3: memory <- (MBR) Where CR = Read control signal to system bus CW = Write control signal to system bus
Example: In the instruction fetch, as shown in table 1 the contents of MBR are transferred to the IR. And this transfer is activated by the control signal C4 given in table 1 and shown in figure 3. Thus control unit controls everything with few control signals sent to registers or modules (ALU) which are within the CPU and few control signals sent to the system bus. Q.6) write short note on: i) Super scalar processors. ii) RISC iii) CISC Answers 6) (a) A superscalar CPU can execute more than one instruction per clock cycle. Because processing speeds are measured in clock cycles per second (megahertz), a superscalar processor will be faster than a scalar processor rated at the same megahertz. A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock
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rate. A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier. In the Flynn Taxonomy, a superscalar processor is classified as a MIMD processor (Multiple Instructions, Multiple Data). While a superscalar CPU is typically also pipelined, pipelining and superscalar architecture are considered different performance enhancement techniques. The superscalar technique is traditionally associated with several identifying characteristics (within a given CPU core): Instructions are issued from a sequential instruction stream CPU hardware dynamically checks for data dependencies between instructions at run time (versus software checking at compile time) The CPU accepts multiple instructions per clock cycle A superscalar architecture includes parallel execution units, which can execute instructions simultaneously. This parallel architecture was first implemented in RISC processors, which use short and simple instructions to perform calculations. Because of their superscalar capabilities, RISC processors have typically performed better than CISC processors running at the same megahertz. However, most CISC-based processors (such as the Intel Pentium) now include some RISC architecture as well, which enables them to execute instructions in parallel. Nearly all processors developed after 1998 are superscalar. Answers 6) (b) RISC: Stands for "Reduced Instruction Set Computing, and is pronounced "risk." It is arguably the fastest and most efficient microprocessor technology available today. RISC is a microprocessor that is designed to perform a smaller number of types of computer instructions so that it can operate at a higher speed (perform more millions of instructions per second, or MIPS). Since each instruction type that a computer must perform requires additional transistors and circuitry, a larger list or set of computer instructions tends to make the microprocessor more complicated and slower in operation. John Cocke of IBM Research in Yorktown, New York, originated the RISC concept in 1974 by proving that about 20% of the instructions in a computer did 80% of the work. The first computer to benefit from this discovery was IBM's PC/XT in 1980. The concept was used in Sun Microsystems' SPARC microprocessors and led to the founding of what is now MIPS Technologies, part of Silicon Graphics. A number of current microchips now use the RISC concept. The RISC concept has led to a more thoughtful design of the microprocessor. Among design considerations are how well an instruction can be mapped to the clock speed of the microprocessor (ideally, an instruction can be performed in one clock cycle); how "simple" an architecture is required; and how much work can be done by the microchip itself without resorting to software help. Besides performance improvement, some advantages of RISC and related design improvements are: A new microprocessor can be developed and tested more quickly if one of its aims is to be less complicated. Operating system and application programmers who use the microprocessor's instructions will find it easier to develop code with a smaller instruction set. The simplicity of RISC allows more freedom to choose how to use the space on a microprocessor. Higher-level language compilers produce more efficient code than formerly because they have always tended to use the smaller set of instructions to be found in a RISC computer.
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Answers 6) (c) CISC: Stands for "Complex Instruction Set Computing." This is a type of microprocessor design. The CISC architecture contains a large set of computer instructions that range from very simple to very complex and specialized. Though the design was intended to compute complex instructions in the most efficient way, it was later found that many small, short instructions could compute complex instructions more efficiently. This led to a design called Reduced Instruction Set Computing (RISC), which is now the other major kind of microprocessor architecture. Intel Pentium processors are mainly CISC-based, with some RISC facilities built into them, whereas the PowerPC processors are completely RISC-based. The PowerPC microprocessor, used in IBM's RISC System/6000 workstation and Macintosh computers, is a RISC microprocessor. Intel's Pentium microprocessors are CISC microprocessors. RISC takes each of the longer, more complex instructions from a CISC design and reduces it to multiple instructions that are shorter and faster to process.
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July 2011 Master of Computer Science (MSCCS) Semester 1 MC0062 Digital Systems, Computer Organizations 4 Credits (Book ID:

D: B0680 & B0684) Assignment Set 1 (60 Marks)

1100 (2) 1111 (2) 1011.101 (2)

Answer 2) direct realization of the function

ii) Simplified realization of the function

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with with . Therefore realization requires lesser number of gates with

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9 0xa=10 0xb=11 0xc=12 0xd=13 0xe=14 0xf=15

cmp* dadd bit bic bis xor and

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2. SET = 0 and RESET = 1: always sets the output

4. SET = 0: always resets the output = 0 and = 1

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Figure 1: A Four bit synchronous up counter.

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