IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO.

11, NOVEMBER 2007

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Design of On-Chip Transformer With Various Coil Widths to Achieve Minimal Metal Resistance
Heng-Ming Hsu, Member, IEEE, and Chien-Wen Tseng
AbstractA layout design algorithm of a variable-width transformer is proposed to minimize metal resistance in this letter. The proposed algorithm can rapidly design metal widths in each coil of a planar transformer for a given chip area. Two on-chip transformers with identical self-inductance are fabricated to verify the proposed algorithm in 90-nm CMOS technology. Measurement results demonstrate the improvement of metal resistance approximates to the value of 11.6%. Results of this study provide an effective algorithm to design a minimal-loss transformer for radio frequency integrated circuit applications. Index TermsAnalytical algorithm, minimum resistance, on-chip transformer, variable metal width.

II. M ETAL R ESISTANCE OF A P LANAR T RANSFORMER The layout of a planar transformer with 4 : 4 coil ratios is illustrated in Fig. 1(a), where the parameters rit and rot represent the inner and outer radii, respectively. We concentrate on the 4 : 4 coil ratios of a rectangular transformer, as shown in Fig. 1(a), where the dark and light colors of coils express the primary and secondary terminals, respectively. By checking the layout in detail, the transformer can be separated into two individual inductors during the characterization of metal resistance. Accordingly, the metal loss of a transformer can be characterized by focusing on one inductor. The metal resistance of a rectangular inductor is expressed as N 1 1 (1) 8 Rspiral = ro (m) t 1 m=1
ri (m)

I. I NTRODUCTION

N-CHIP transformer is an important component in a circuit operation, which is needed to achieve impedance transformation, signal coupling, and dc isolation, among others [1], [2]. Accordingly, the low-loss characteristic is essential during the implementation of a transformer into RF circuits [3], [4]. The variable-width inductor is proposed to improve the Q value by suppressing eddy current losses in the inner turns, as reported in literature [5]. However, the use of a variable metal width introduces further variables (such as the metal width of each turn) and complicates the design of layout. An algorithm to design inductor coils by using a numerical approach is reported in a previous study [6]. Nevertheless, the numerical approach applies at a specic dimension range and consumes computer resource during layout optimization. Therefore, an analytical method to design a transformer coil for achieving a minimal metal resistance is proposed in this letter. This algorithm spirit is to nd a specic ratio of transformer coil in a given chip area. After acquiring the specic ratio, it is used to design the metal width in each coil to minimize the metal resistance. The advantage of the method is that it rapidly designs a transformer coil by using an analytical approach in a given chip area. By incorporating the prediction of a selfinductance formula [7], one specic layout with given chip area and self-inductance can have a minimal metal resistance, as demonstrated in this study.

where t, , and N represent metal thickness, conductivity, and turn number, respectively. ro (m) and ri (m) express the outer and inner radii at specic mth coil, respectively. After a lengthy manipulation, the minimum resistance of a spiral inductor is derived as Rmin = 1 1 8 t 1 m=1
N

(2)

where = (rot /rit )1/N is the metal width ratio of each coil. By combining two inductors to construct a planar transformer, as shown in Fig. 1(a), the transformer can be symmetric with respect to a diagonal line, as depicted by a dot line in this graph. Thus, there are two metal ratios 1 and 2 corresponding to primary and secondary coils used for achieving minimum resistance in a layout design. The resulting metal resistance of a transformer can be generalized from (2) in the following expression: Rmin = 4 t
N

m=1

1 1 1

+
m=1

1 2 1

(3)

Manuscript received June 27, 2007; revised August 16, 2007. This work was supported in part by the National Science Council of Taiwan, R.O.C., under Grant NSC 96-2220-E-005-002 and in part by the Ministry of Education of Taiwan, R.O.C., under the ATU plan. The review of this letter was arranged by Editor A. Wang. The authors are with the Department of Electrical Engineering, National Chung Hsing University, Taichung 402-27, Taiwan, R.O.C. (e-mail: hmhsu@nchu.edu.tw). Color versions of one or more of the gures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/LED.2007.906934

The denition of 1 and 2 is given by 1 = ro,1 (m)/ ri,1 (m) and 2 = ro,2 (m)/ri,2 (m), where m is the mth coil of a transformer layout, as shown in Fig. 1(a). The physical meaning of represents the width ratio between two neighbor coils that maintains the uniform current distribution from one coil to the next coil . The cross section and relationship between the inner and outer radii of each coil and the equation derivations are depicted in Fig. 1(b). Two equations with the variables 1 and 2 with N = 4 case are also depicted in Fig. 1(b).

0741-3106/$25.00 2007 IEEE

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IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 11, NOVEMBER 2007

Fig. 1. (a) Layout and parameter description of a planar transformer. (b) Cross section and radii relationship of a planar transformer.

By using an inductive approach, the equations of an N -coil transformer can be derived in the following formulas:
N N 1 2 1 +

N N N 1 2 rit +S n=1 n1 n 1 2 +

N 1 n n 1 2 rot = 0 n=1

S rit

N n n1 1 2 + n=1

N 1 n n 1 2 n=1

rot 2

rit

=0 (4)

(5) where rot , rit , S, and N are the given values corresponding to outer, inner radii, metal spacing, and coil number.

HSU AND TSENG: DESIGN OF ON-CHIP TRANSFORMER WITH VARIOUS COIL WIDTHS

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TABLE I LAYOUT DIMENSIONS AND SELF-INDUCTANCE AND MUTUAL INDUCTANCE OF TRANSFORMERS

Fig. 2. Kelvin measurement of metal resistances of TRA and TRB devices and die photo of TRA device.

III. E XPERIMENT R ESULTS This experiment is implemented with two transformers, due to the limited area in 90-nm technology, one is the proposed device (i.e., TRA ) and the counterpart (i.e., TRB ) is the standard device. The layouts of these two devices are carefully designed with an identical self-inductance. The analytical approach for calculating self-inductance, which has been published in [7], is incorporated with the proposed approach in layout parameter design. The self-inductances are designed with 4 nH in these two devices. Moreover, the metal spacing and turn ratio are 3 m and 4 : 4 in these two devices, respectively. Because previous parameters are xed in this layout design, the inner radius and metal widths are adjusted to maintain an identical selfinductance based on an analytical method [7]. By substituting the following parameters: rit = 52 m, rot = 142 m, and S = 3 m into (3) and (4), the metal ratios: 1 = 1.13 and 2 = 1.06 are found by numerical approach. Therefore, the metal widths in primary and secondary terminals can be calculated, as listed in Table I. Since the magnetic strongly concentrates in inner coils, the width of counterpart takes the average value of most two inner coils of primary and secondary terminals and is calculated to be approximately 7 m, as listed in Table I. Furthermore, the inner and outer radii of counterpart are adjusted to 49 and 118 m in order to keep the 4-nH selfinductance. These two transformers were fabricated using the foundry 90-nm CMOS process. All devices were deposited on the metal-9 layer with a thickness of 3-m copper lm, and the substrate has low-resistivity ( = 8 12 cm) silicon material. The die photo of the proposed transformer is depicted in the inset of Fig. 2. In order to verify the proposed algorithm, the metal resistance is measured using a four-point probe method [8]. Since the metal resistance in this device is small, the probe contact resistance can be removed by using this approach. The metal resistances of devices TRA and TRB are shown in Fig. 2, sweeping the force voltage from 0.05 to 1 V. The average values are depicted in the inset of Fig. 2, the values are 2.86 and 3.22 for TRA and TRB devices, respectively. Furthermore, substituting 1 = 1.13 and 2 = 1.06 and adopting

Fig. 3. Measurement of self-inductances and Q values of TRA and TRB transformers.

= 5.813 107 (S/m) and t = 3 m into (3) and counting the underpass metal resistances, the calculated resistances are 2.85 and 3.19 for TRA and TRB devices, respectively. The results consist of the measurement shown in Fig. 2 and express the feasibility of the proposed approach. The improvement of the metal resistance of TRA device approximates to 11.6% in this experiment. This result demonstrates that the proposed method for minimizing the metal resistance is achievable in a planar transformer design. Moreover, the RF measurement adopts the Agilent E8362B network analyzer and a Suss probe station. The S parameters were obtained by de-embedding procedure to remove the undesired pad parasitics [9]. The left axis of Fig. 3 depicts the self-inductances of TRA and TRB versus frequency. The inductances of TRA and TRB are 3.96 and 3.93 nH at 100 MHz. The results verify that the maintenance of constant inductances is achieved in the experiment. Furthermore, the right axis of Fig. 3 depicts the Q value of TRA and TRB devices versus frequency. The low frequency is dominated by the metal resistance due to the identical self-inductance in

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IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 11, NOVEMBER 2007

this experiment. The low metal resistance expresses the highQ performance of TRA device at low frequency. Additionally, the high frequency behavior is determined by substrate loss factor and self-resonance factor [10]. The peak Q values are 9.86 and 8.53 for TRA and TRB devices, and these occurred at 4 GHz, as shown in this graph. The variablewidth structure improves the Q value at high frequency, this mechanism is explained by suppressing the eddy current in the inner turn [11]. Moreover, the self-resonance frequencies fSR are 9.2 and 10.4 GHz for TRA and TRB devices, respectively. The high fSR value of standard device is due to the small chip area, the small chip area results in low parasitic capacitance and increases the fSR value in this experiment. IV. C ONCLUSION An analytical algorithm to minimize metal resistance of a variable-width transformer is derived in this letter. The metal widths of each coil are determined by the proposed approach to minimize metal resistance. Two planar transformers are fabricated to verify the proposed method in foundry 90-nm technology. Measurement results express the 11.6% improvement of a metal resistance in a variable-width layout. Therefore, the proposed algorithm can be applied to the design variablewidth transformer with a low metal loss for radio frequency integrated circuit applications.

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