On Single-Electron Technology Full Adders

Mawahib H. Sulieman1, Member, IEEE, and Valeriu Beiu2, Senior Member, IEEE
1

College of Engineering and 2 College of Information Technology United Arab Emirates University, Al-Ain, P.O. Box 17555, UAE mawahib.sulieman@uaeu.ac.ae and vbeiu@uaeu.ac.ae

Abstract This paper reviews several full adder (FA) designs in single electron technology (SET). In addition to the structure and size (i.e. number of devices), this paper tries to provide a quantitative and qualitative comparison in terms of delay, sensitivity to (process) variations, and complexity of the design. This will allow for a better understanding of the advantages and disadvantages of each solution. An optimization of a SET FA (combining one of the SET FAs with a static buffer), together with a new SET FA design (based on capacitive SET threshold logic gates), will also be described and compared with the other SET FAs. Index Terms Full adders, sensitivity to variations, single electron technology, threshold logic.

I. INTRODUCTION
The scaling of Complementary Metal Oxide Semiconductor (CMOS) transistors has so far provided lower cost and higher performance circuits. However, further progress of integration scale will be hindered by a variety of physical effects. The most important effects are the increase in power consumption and the decrease in reliability . These problems have motivated an active search in quest for both short- and long-term solutions. The former include non-

M. Sulieman and V. Beiu: SET FAs

classical CMOS (e.g., FinFET and vertical MOSFET , as well as SOI ), while the latter include several emerging technologies (see , ). Single-electron-technology (SET) is one of these new technologies, distinguished by a very small device size and ultra-low power dissipation. While promising for helping solve the power consumption challenge, SET is expected to be sensitive to variations (like many other nanodevices , ), and to background charge . Such problems might be tackled by using fault-tolerant designs , but a closer understanding of SETs sensitivity to variations is clearly needed. Still, room temperature SET devices have been demonstrated , while the low gain of SET devices suggest that they should be combined with CMOS , , or even with resonant tunneling devices (RTDs), and might lead to hybrids like SET-CMOS, SET-RTD, or even SET-CMOS-RTD. That is why, a better understanding of the SET (e.g., by including sensitivity to variations) is considered both timely and useful. One of the SET logic circuits which has recently been presented in several studies is the classical full adder (FA) . By reviewing these articles it was apparent that SET FA structures differ both in their mode of operation, and in the number of elementary components. However, delays were reported for only two (out of the four) designs, while sensitivity to variations was not investigated. The importance of such performance measures have strongly motivated this work which provides both qualitative and quantitative comparison of the reported SET FAs. Further, a modified SET FA (combining one of the SET FAs already reported with a static buffer), and a new SET FA design are also presented. The first approach modifies the SET FA introduced in , by using a static buffer. [Why a static buffer is needed] The use of a static buffer was suggested in , where it was used only for implementing Boolean gates. The same static buffer was recently used in for implementing latches and flip-flops, but the threshold logic gates (TLGs) used are different from the ones used in the SET FA introduced in . We have determined

M. Sulieman and V. Beiu: SET FAs

the optimal capacitors values for the SET FA from when using a static buffer, and the results are reported in this paper. Finally, another (novel) SET FA design augments the one presented in in a way that simplifies its structure and reduces the total number of components. To obtain quantitative measures of performance, all the SET FAs were simulated under identical conditions using SIMON , a widely used Monte Carlo simulator for single electron devices and circuits that takes cotunneling into account. The simulation results, together with the SET FA structures, were used to compare all these SET FAs in terms of:

The number of junctions and capacitors, which could affect an important characteristic of

future nanoelectronics, their overall reliability , , . The delay. The design complexity, estimated in terms of control and voltage supply

requirements. The sensitivity to variations.

The remainder of the paper is organized as follows. Section II presents the background material about FAs and threshold logic gates (TLGs). The different types of SET FAs are described in Section III. The simulation procedure for characterizing the SET FAs is described in Section IV, with Section V providing both quantitative and qualitative comparisons of the SET FAs. Concluding remarks are provided in Section VI.

II. FULL ADDERS

AND

THRESHOLD LOGIC

M. Sulieman and V. Beiu: SET FAs

The FA is a basic arithmetic block which has three inputs: the addend a (1-bit precision), the augend b (1-bit precision), and the carry-in ci; and two outputs: the sum s, and the carry-out co. An established method for computing s and co is s = (a b ci), co = (a b) (a ci) (b ci), where we have used the following notation: for logic while x will represent the complement of a signal x. The classical FA designs are based on transmission gates, complementary pass-transistor logic and static CMOS (see for an in-depth review of many CMOS FAs). However, most of the SET FA solutions are based on TLGs. A TLG is the simplest artificial neuron which computes the weighted sum of its inputs (wixi), and compares this sum with a threshold value . If the sum is larger than the threshold , the TLG outputs a one, otherwise the output will be zero. Mathematically, a TLG implements a linearly separable function
n f ( x ,, xn ) = sign wi xi , 1 i= 1

(1) (2)
AND,

for logic

OR,

and for logic

XOR,

(3)

where wi is the weight associated with xi, the threshold, and n the fan-in . In practice, the (integer) threshold is reduced by 0.5 as the simplest method to improve on the noise margins, but more evolved methods are possible (see ). In the remainder of this paper, a TLG will be represented by its series of weights and practical threshold (w1,,wn; 0.5). A particular TLG having all the weights equal, w1 = w2 = = wn = 1, for n = 2k + 1 (for any integer k 1) is known as a majority gate (MAJ).

M. Sulieman and V. Beiu: SET FAs

To implement FAs using only TLGs, the sum and carry-out functions have to be represented as linearly separable functions. The carry-out co does satisfy this condition, and can be written as co = sign (a + b + ci 1.5), (4)

which is a MAJ function (w1 = w2 = w3 = 1, and = 1.5). On the other hand, the sum function s as expressed in (1) is not a linearly separable function. However, it can be represented in a linearly separable form by writing it in terms of both the carry-in (ci) and carry-out (co) s = (a b ci) [co (a b ci)], which can be written as s = sign (a + b + ci 2co 0.5), (6) (5)

or equivalently (1,1,1,2; 0.5). By simple algebra, any negative weight can be changed to a positive weight (by inverting the associated input and modifying the threshold ), hence the function can be written as s = sign (a + b + ci + 2co 2.5). (7)

This (1,1,1,2; 0.5) solution was presented in , used later in , and rediscovered in . One way to obtain the threshold equations (6) and (7) from the Boolean equation (5) is as follows: Equation (5) is written in a simplified sum-of-product form:

s = (a b ci) (co a) (co b) o ci). (c If a, b, ci are assigned a weight of 1, co should be assigned a weight of 2 to make all the

product terms equally weighted. This weight can be negative (using co) or positive (using co). Hence the threshold equation becomes either s = sign (a + b + ci 2co 1), or s = sign (a + b + ci + 2co 2).

M. Sulieman and V. Beiu: SET FAs

To determine the thresholds 1 and 2, two weight maps, in addition to the Karnaugh map,

are created (see Fig. 1). o In the Karnaugh map (Fig. 1(a)), dont care () symbols are assigned to all the

unfeasible combinations of a, b, ci, and co. o The weight map in Fig. 1(b) shows the weighted sum-of-inputs using a negative

weight for co: a + b + ci 2co. o The weight map in Fig. 1(c) shows the weighted sum-of-inputs using a positive

weight for co: a + b + ci + 2co. Comparing each of these two weight maps with the Karnaugh map, it is clear that: o In Fig. 1(b) logic 0 corresponds to 0, and logic 1 corresponds to 1, hence the

threshold is 1 = 0.5. o In Fig. 1(c) logic 0 corresponds to 2, while logic 1 corresponds to 3, hence the

threshold is 2 = 2.5. Having all the weights and thresholds completes the specification of the threshold equations (6) and (7). In practice, it is normally necessary to obtain either one of these equations, and the other one can be obtained by simple algebra. Using this procedure for both of them here is only for illustration purposes.

III. TYPES

OF

SINGLE-ELECTRON TECHNOLOGY FULL ADDERS

The first two types of the SET FAs proposed are based on MAJ gates , , but differ in the way the MAJ gates are implemented. The third SET FA is based on pass-transistor logic (PTL) , and the fourth one is based on TLGs . The fourth one will be modified by matching the TLG gate detailed in with a static buffer, and optimizing the capacitor values. The new SET FA we
M. Sulieman and V. Beiu: SET FAs 6

present in this article is also TLG based . The different types of SET FAs are described in the following subsections. The description will be accompanied by simulation results to verify the functionality of each SET FA. All the simulations were done using SIMON . The input signals used in these simulations cover all the eight possible combinations of the inputs a, b, and ci, as shown in Fig. 2, where the voltage levels (0 mV and 6.5 mV) correspond to the SET FA introduced in . [We need to explain a bit how each FA functions 1-2 paragraphs each ?!] A. Single-Electron Transistor Majority Full Adder In 1998, Iwamura et al. introduced a SET FA based on MAJ gates (MAJ-SET). This SET FA consists of three MAJ gates and two inverters (Fig. 3(a)). One MAJ and an inverter produce the carry-out co, while the combination of all the gates produces the sum s. The MAJ gate configuration (Fig. 3(b)) is based on the SET inverter proposed by Tucker , and produces the complement of the MAJ function. However, it will still be referred to as MAJ for simplicity. Starting from the inverter configuration proposed by Tucker , the input capacitance is divided into three equal capacitances, which are connected to three inputs to create a MAJ gate (see Fig. 3(b)). The MAJ consists of an input capacitor array (six input capacitors C = 1 aF) for input summation and an inverter (four tunnel junctions Cj1 = Cj4 = 1 aF, Cj2 = Cj3 = 2 aF; two bias capacitors Cb1 = Cb2 = 9 aF; and a load CL = 24 aF) for threshold operation. This SET FA is quite simple, using only one voltage supply (VDD = 6.5 mV), and does not require any external controls (i.e., other voltages or clock signals). The complete circuit comprises 20 tunneling junctions and 37 input and bias capacitors. The sum output s of this SET FA is shown in Fig. 4. The waveform is regular, and the output swing is comparable to the input swing (Vi = 6.5 mV). The original paper reports a mean delay of about 0.3ns, and mentions that for achieving small errors the FA

M. Sulieman and V. Beiu: SET FAs

must be operated at very low temperatures: below 0.2 K for no errors in 100 trials, while the FA will make about 1 error at 0.5 K and about 10 errors at 1 K (in 100 trials).

B. Single-Electron Box Majority Full Adder The MAJ implementation has been revisited in 2003 by Oya et al. . In this design, the MAJ has been implemented as an irreversible single-electron box (SEB) leading to a MAJ-SEB FA design. The SEB has a simple structure and comprises a smaller number of devices than a SET inverter. However, it requires additional control at the circuit level because it is bidirectional. Figure 5(a) shows the MAJ-SEB FA. It consists of three MAJ gates, which correspond to the three MAJs in Fig. 3(a). The other gates act as delay and/or fan-out buffers. Figure 5(b) shows a three-input MAJ gate based on a double-junction SEB. It consists of two tunneling junctions connected in series (Cj = 20 aF, Rj = 200 K), a bias capacitor Cb = 2 aF, an output capacitor CL = 2 aF, three input capacitors C = 2 aF, and a bias voltage i. Three input voltages V1, V2, and V3 are applied through the input capacitors C to the internal node int. The input capacitors form a voltage summing network, and produce the weighted sum of their inputs on the internal node int. The SEB produces the complementary MAJ output on the same node. Using SEB, instead of SET inverter, reduces the number of tunneling junctions from 20 (MAJ-SET) to 14 (MAJ-SEB), and the number of capacitors from 37 (MAJ-SET) to 29 (MAJ-SEB). Since the proposed MAJ-SEB gate is bidirectional, the signal flow has to be controlled. A three-phase clock has been used for this. The circuit is divided into three layers, each layer being excited in turn by one of the three clock phases 1, 2, 3 (Fig. 5(a) and Fig. 6(a)). The clock is a two-step pulse which is first set to an excitation voltage of 60 mV, and then to a holding voltage of 40 mV (see Fig. 6(a) and ). The three clock phases should overlap, so that the output of one

M. Sulieman and V. Beiu: SET FAs

stage will be evaluated while the preceding stage is still holding its outputs. The inputs are return-to-zero signals with logic 1 encoded as 4 mV and logic 0 as 4 mV (Fig. 6(b)). The inputs are received while 3 is in the excitation period. The carry-output co is produced when 2 goes high, and is retrieved by the output buffer while 2 is in the holding period. The sum output s is produced when 3 goes high again. The carry-out delay is two-thirds of a clock period, and the sum delay is one clock period. The sum output s of this SET FA is shown in Fig. 7. It has a large voltage swing, and the waveform is a return-to-zero two-step pulse, borrowing the shape of the clock two-step pulses. Unlike the MAJ-SET, the simulation results are shown up to 90 ns because of the one-clock-period delay explained above. The original paper reports simulations results at 0 K using SIMON, and estimates the excitation period to be 3.7 ns (assuming zero temperature) for an error probability of 1010. The paper also mentions that for a holding duration of 1 ns and 1010 error probability the gates should be operated below 5.1 K.

C. Pass Transistor Logic Full Adder The third SET FA design is based on pass transistor logic (PTL-SET), and was introduced by Ono et al. . In this design, multi-input SETs are used as pass transistors. Figure 8(a) shows a two-input SET that implements the
XOR

function of two inputs. Given that each of the two input

capacitances is equal to C = 1 aF (Cj = 1 aF, Rj = 100 k) and the voltage amplitude is VDD = e/2C = 80 mV, the SET is ON only when one of the inputs is high, and it is OFF when neither or both inputs are high. The sum circuit is shown in Fig. 8(b). It consists of two multi-input transistors. The control voltage Vcon = 0.8 V is used to change the type of SET from n-type to p-type. This is achieved by applying a constant DC voltage of Vcon = e/2Ccon, (Ccon = 0.1 aF) which shifts the drain current

M. Sulieman and V. Beiu: SET FAs

versus input voltage characteristics by 180. The two-input transistor on the left-hand side implements (a b) ci, while the right-hand-side two-input transistor produces (a b) ci. Hence, the result is a b ci, which is the sum s of the three input bits. Contrary to all the previous solutions, which implement the carry-out co as a simple MAJ gate, this solution has a relatively complex circuit to produce the carry-out co (see Fig. 8(c)). It consists of two subcircuits each having two multiple input SET transistors. The lower subcircuit implements (b VDD + b GND), which is obviously equal to b. The upper subcircuit implements (a b) ci + (a b) b, which can be simplified to a ci + b ci + a b, giving the carry-out co. An inter-SET-node capacitance CM has been used as a parameter. The optimum value is CM = 25100 aF, while the load used was COUT = 2.5 fF. Fig. 9 shows the sum output of this SET FA for an input swing of Vi = 80 mV. Unlike MAJ-SET and MAJ-SEB, this SET FA has a smaller output voltage swing of about 25 mV at T = 0 K, and about 21 mV at T = 30 K (which is the temperature reported in the paper). The original paper reports 10 mV, and a delay of 6.68 ns and 10.8 ns for pull-down and pull-up at T = 30 K. Our simulations have shown that by reducing both the inte-SET-node capacitance and the output node capacitance the speed can be improved.

D. Single-Electron Junction Threshold Logic Full Adder The fourth SET FA design was proposed by Lageweg et al. , and is based on TLGs implemented using single electron junctions (TLG-SEJ). This SET FA consists of two TLGs and a buffer for each of the TLGs (Fig. 10(a)). The sum function s is implemented by a (1,1,1, 2; 0.5) TLG, and the carry-out co is implemented by a MAJ. Figure 10(b) shows the (1,1,1, 2; 0.5) SEJ TLG. It consists of one SEJ, and five input and bias capacitors. The input signals V1, V2, V3 are weighted by their corresponding capacitors C = 0.5 aF, and added to the voltage across

M. Sulieman and V. Beiu: SET FAs

10

the junction. The input signals V4 is weighted by 2C = 1 aF and subtracted from the voltage across the junction (i.e. implementing a negative weight). The bias voltage Vb, weighted by the capacitor Cb = 1.18 aF is used to adjust the threshold. The advantage of this approach is the ability to directly implement negative weights. The disadvantage is that each TLG should be augmented with a buffer in order to prevent bidirectional effects. The SET FA described in uses dynamic buffers like the one in Fig. 10(c). This type of buffers needs a reset phase before any data can be processed. The TLG-SEJ original solution requires four different voltages: V(TLG) = 240 mV, V(BUF) = 48 mV, V(reset) = 53 mV, Vi = 16 mV, and the original paper reports simulations done with SIMON at 0 K. A solution for solving some of the problems due to dynamic buffers was presented in , where a static buffer was proposed (see Fig. 10(d)). The static buffer, which is Tuckers inverter , simplifies the TLG-SEJ as it does not need a reset phase anymore, and also reduces the number of different voltages required. The design of static buffered NAND and NOR gates is detailed in , where it is shown that they operate correctly for a fan-out of 4 (simulations are done with SIMON at 0 K), but a redesigned TLG-SEJ FA with static buffers is not presented. The SEJ TLGs using the same static buffer have very recently been used in the design of various SET flip-flop/latches . This paper presents many buffered SEJ TLGs: AND, NAND, OR, NOR, (1, 1; 0), (1,1; 0.5), (1,1,1; 0.5), (1,1,2; 0.5), and (1,1,2; 1.5). Still, the (1,1,1,2; 2.5) TLG required by the original TLG-SEJ FA from is not presented. That is why, we have redesigned the original TLG-SEJ from using static buffers. The approach we have taken for optimizing the buffered SEJ TLGs is original as based on our own MATLAB modules linked to SIMON . Using these modules, has allowed us to obtained a range of valid values for the TLGs bias capacitors: between 11.1 aF and 11.6 aF. The values used for simulations are Cb = 11.25 aF for both TLGs,

M. Sulieman and V. Beiu: SET FAs

11

and Cb = 4.23 aF for the buffers. The other parameter are C = 0.5 aF, Cj1 = Cj4 = 0.1 aF, Cj2 = Cj3 = 0.5 aF, Rj = 100k, CL = 9 aF, and VDD = 16 mV. This SET FA structure (including the two static buffers) uses 10 tunneling junctions and 21 capacitors. The s output is shown in Fig. 11. The output is a full swing signal (16 mV), though the 0 and 1 voltages are slightly shifted (by 0.8 mV) above GND and VDD.

E. Single-Electron Transistor Threshold Logic Full Adder In this section, a new TLG-based FA (TLG-SET) is presented and analyzed (also detailed in ). This SET FA is a generalization of the MAJ-SET (presented in Section III-A), where TLGs are used instead of MAJs. By using TLGs, the circuit is reduced from three MAJs and two inverters (Fig. 3(a)), to only two TLGs (Fig. 12(a)). The sum function s is implemented by a (1,1,1,2; 2.5) TLG, and the carry-out co by a MAJ. Being a TLG-based solution, it uses the same basic TLG structure as TLG-SEJ (compare Fig. 12(a) to Fig. 10(a)), but the implementation is different as it does not require the additional buffers, and the TLGs are implemented using SETs (as in and ) instead of SEJs (as in , , ). The implementation of the elementary TLG is based on Tuckers inverter. Figure 12(b) shows the (1,1,1,2; 2.5) TLG which is used to produce the sum. The carry-out co is produced by a MAJ (see Fig. 3(b)). Both TLGs have several parameters in common, namely: Cb1 = Cb2 = 9.0 aF, CL = 24 aF, VDD = 6.5 mV . To design a TLG, the weight ratios and the threshold are used to calculate the values of the input capacitors. The design of the (1,1,1,2; 2.5) TLG is detailed below. The capacitors are calculated according to the weights, threshold and the sum-of-input capacitances. This sum is determined as part of the inverter parameters which produce a step function. Using the parameters given in , the sum-of-input capacitor is 3 aF. To map the weights

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12

to the input capacitors, we first define C as the unit capacitance corresponding to a weight of 1. Since the threshold is 2.5, three capacitor units should be larger than 1.5 aF, and two capacitor units less than this value. Mathematically: 3C > 1.5 aF and 2C < 1.5 aF, hence

0.5 aF < C < 0.75 aF. The 3 aF sum-of-input condition, mandates that C 0.6 aF. Any value in the range 0.5 aF < C 0.6 aF can be used in the design, and a bias capacitor should be used to complete the sum-of-input to 3 aF. Fortunately, 0.6 aF satisfies all the conditions without a need for a bias capacitor, hence 0.6 aF was used for this design, i.e., C1 = C2 = C3 = 0.6 aF and C4 = 1.2 aF. This choice of capacitor values seems like a direct division of the 3 aF according to the ratio of weights. This is true only for this particular TLG because the threshold ( = 2.5) is half of the sum-of-weights (1+1+1+2=5). If the threshold were 1.5, for instance, a direct division would not produce the proper capacitor values. As indicated above, using TLGs instead of MAJs reduces the total number of components. The number of tunneling junctions is reduced from 20 (MAJ-SET) to 8 (TLG-SET), and the number of capacitors from 37 (MAJ-SET) to 20 (TLGSET). Figure 13 shows the s output of this SET FA for an input swing of Vi = 6.5 mV. The output signal is regular and has a large voltage swing, similar to that of the MAJ-SET FA .

IV. CHARACTERIZATION

OF

SINGLE-ELECTRON TECHNOLOGY FULL ADDERS

After the initial simulations verifying the functionality of the SET FAs (presented in Figs. 3, 6, 8, 10 and 12), a second set of simulations was carried out to analyze the delay of all these SET FAs. The simulations were run with the same input signals: b = 1, ci = 0, and a switching between 0 and 1 every 10 ns (i.e., at a 100 MHz switching frequency). All the simulations were done at 0 K, as in the original articles , , , , . A higher operating temperature is theoretically

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13

estimated in two of the papers, namely 1 K in , and 5.1 K in . The only paper reporting simulations at T = 30 K is . The circuit parameters used are the ones reported in the corresponding article for each SET FA.

For MAJ-SET: C = 1 aF; Cj1 = Cj4 = 1 aF, Cj2 = Cj3 = 2 aF, Rj = 100 K; Cb1 = Cb2 = 9 aF; CL = 24 aF; VDD = 6.5 mV.

For MAJ-SEB: C = 2 aF; Cj = 20 aF, Rj = 200 K; Cb = 2 aF, CL = 2 aF; an excitation voltage of 60 mV, and a holding voltage of 40 mV.

Considering the PTL-SET FA: C = 1 aF; Cj = 1 aF, Rj = 100 k; CCON = 0.1 aF; CM = 25100 aF; CL = 2.5 fF; VDD = 80 mV; Vdd = 10 mV; VCON = 0.8 V. Higher speeds can be achieved by reducing the load capacitor (the value is rather large as compared to the other SET FAs, and did not produce the correct logic results when run at comparable speeds). In the PTL-SET FA, all subcircuits were implemented as two-input SETs. When a single input was needed (as in the carry-out co case), one of the inputs was grounded as reported in .

With regard to the modified TLG-SEJ the circuit parameters are the ones detailed in Sections III-D: C = 0.5 aF, Cj = 0.1 aF, Rj = 100 K, Cb = 11.25 aF, and CL = 9 aF for the carry; C = 0.5 aF, Cj1 = Cj4 = 0.1 aF, Cj2 = Cj3 = 0.5 aF, Rj = 100 K, Cb1 = Cb2 = 4.23 aF, and CL = 9 aF for the static buffer; C = 0.5 aF and C = 1.0 aF, Cj = 0.1 aF, Rj = 100 K, Cb = 11.25 aF, and CL = 9 aF for the sum; and VDD = 16 mV).

For the new TLG-SET, the circuit parameters have been determined in Section III-E as: C = 1 aF, Cj1 = Cj4 = 1 aF, Cj2 = Cj3 = 2 aF, Rj = 100 K, Cb1 = Cb2 = 9 aF, CL = 24 aF for

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14

the carry; C = 0.6 aF and C = 1.2 aF, Cj1 = Cj4 = 1 aF, Cj2 = Cj3 = 2 aF, Rj = 100 K, Cb1 = Cb2 = 9 aF, CL = 24 aF for the sum; and VDD = 6.5 mV. Fig. 14 shows the schematics of all the SET FA circuits in SIMON. Concerning delay it is usual practice for single electron circuits to represent the operation speed by the mean of the operation delay time . That is why the results we report here are the average delays of the sum output, i.e., from a to s. The MAJ-SEB FA is a special case in the delay analysis. As mentioned in Section III-B, the sum delay is one clock period. Therefore, in the case of MAJ-SEB FA the average delay was estimated as the inverse of the maximum clock frequency that still gives the correct outputs. Finally, another set of simulations was performed for studying the sensitivity to variations of all these SET FAs. These simulations have been done using both SIMON and MATLAB . Random errors were injected into all the capacitors and tunneling junctions that comprise these SET FAs. A modified capacitor value was generated as C = C + v U(1,1), where C is the original value, v is the maximum allowed variation, and U(1,1) is a random number uniformly distributed between 1 and 1. The process of varying the selected values, and running SIMON, was repeated 1000 times in a loop in MATLAB, while data was collected. The SET FA circuit under test was considered to err if any of its outputs were wrong for any input combinations, in any of the 1000 runs/iterations. Figure 15 illustrates the effects of variations on the sum outputs s of all these SET FAs [Remark: The same outputs without variations for all SET FAs are shown in Figs. 3, 6, 8, 10, and 12]. In Fig. 15, the 1000 results of the 1000 runs for each SET FA are plotted (on top of each other). This was done on purpose, and explains why sometimes the lines appear thicker, as in fact being the results of 1000 simulations plotted on top of each other. The simulations have been run such as errors can be observed. The variations for each SET FA were

M. Sulieman and V. Beiu: SET FAs

15

chosen such as to force the SET FA to make a few errors (out of the 1000 runs). These have also been plotted on top of the correct ones (thicker lines). As can be seen from Fig. 17, the detection of errors is quite straightforward for MAJ-SET, MAJ-SEB, enhanced TLG-SEJ, and TLG-SET. For these SET FAs, the voltage values for logic 1 and 0 are almost constant, and the errors manifest themselves as a flip of the output (i.e., the output becomes the inverse of the correct logic value). This is in contrast to the PTL-SET FA, where there are variations in the output voltage (see Fig. 16(c)). To detect the errors in the PTL-SET FA case, the ideal output voltage (Vo) was divided into three regions. Logic 1 was defined as any voltage larger than 2/3 Vo, and logic 0 as any voltage less than 1/3 Vo. The two horizontal lines bordering the light (yellow) rectangle in Fig. 17(c), mark the lower limit of logic 1 (2/3 Vo), and the upper limit of logic 0 (1/3 Vo) for the PTL-SET FA.

V. COMPARISON
All the simulation results reported above are summarized in a compact form in Table I, which provides a quantitative and a qualitative comparison of all these SET FAs. The second column gives the average delay from a to s. The third column shows the amplitude of the input voltage Vi and the load capacitance CL of each SET FA design, in addition to the output voltage Vo obtained from simulations. The ratio between the output and the input voltage amplitudes (Vo / Vi) is given in the fourth column. Following this is the number of tunneling junctions Cj and input and bias capacitors C. The sixth column shows the maximum variation that can be tolerated by each SET FA (when randomly varying all the capacitors and junctions without any correlation). The last column shows the design complexity in terms of control and voltage supply requirements of each SET FA.

M. Sulieman and V. Beiu: SET FAs

16

The table shows that the TLG-SET adder has the smallest number of components (28), while MAJ-SET has the largest number (57). It is clear all the SET FAs have fewer SET transistors than classical CMOS FAs. Since each SET transistor consists of two junctions, the number of SET transistors is #Cj/2. SET FAs comprise 410 SET transistors, as opposed to 18 32 MOS transistors in CMOS FAs . However, a fair comparison between SET and CMOS FAs should include not only the active devices (i.e., transistors) but also the passive ones (i.e., capacitors for SET FAs). This shows that the total number of components of SET FAs (2857) is comparable to that of CMOS FAs (1832). It is also obvious that the PTL-SET FA can achieve a very small delay if load capacitances can be reduced (to aF). It also exhibits a large tolerance to variations (10%), and can operate at higher temperatures. However, PTL-SET has the smallest Vo / Vi ratio (the output swing is about 25 mV for an input signal Vi of 80 mV). This is a well-known disadvantage of pass-transistor designs in general, which also affects PTL-SET, and suggests that buffers to recover the signal are needed (which will add to the delay). The MAJ-SEB FA has the largest delay. In addition, this SET FA is the most complex design when compared to all the other SET FAs. First, it requires a three-phase clock, which has two voltage levels (60 mV, 40 mV), and secondly, the input signal should be a return-to-zero signal (logic 1 encoded as 4 mV and 0 as 4 mV). The output swing is large (> 97%) but variable, taking a two-step shape like the three clock phases (see Fig. 7). This SET FA also requires both the inputs and their complements (see Fig. 5(a)), suggesting that additional buffering might be needed.

M. Sulieman and V. Beiu: SET FAs

17

The enhanced TLG-SEJ FA has a full output swing. However, this SET FA requires a buffer for each TLG to prevent bidirectional effects. This solution is quite fast and simple (no controls and only one voltage supply), but seems to be sensitive to variations. The MAJ-SET FA has an average delay. However, it comprises the largest number of components (57) compared to all the other SET FA designs. In spite of these, it is quite robust to variations. This can be explained only in part by the simple design (no controls and only one voltage supply), but more due to the fact that the sum-of-weights of the gates used by this SET FA is the smallest: MAJ gates with 3 inputs being simpler than a (1,1,1,2: 2.5) TLG. Finally, the TLG-SET FA introduced in this article has the smallest number of components (28 like the PTL-SET), and a very simple design (single supply, the same values for both the input and supply voltage, and no control signals). The delay and output swing compare favorably to the other SET FAs. However, it seems to be quite sensitive to variations. A simple solution for enhancing the robustness to variations is high matching, which is used in CMOS analog circuit designs , . It has been used for CMOS TLGs , and advocated recently for SET in , . It consists of implementing the capacitors as several (identical smaller) capacitors. This has similarities with designs using several islands like e.g., the single electron trap, the single electron turnstile, and the single electron pump , or the use of an array of islands for one SET transistor (which have shown that a five-junction SET allows for a threefold increase of the operating temperature). The question we want to raise here with high matching is if we could use such ideas to improve on the tolerance to variations. The results are preliminary, and many more investigations are needed, but we have decided to report them as showing one possible approach. We have used the high matching technique for the TLG-SET FA, by dividing only the bias capacitor of each TLG into smaller identical capacitors. The selection of the bias

M. Sulieman and V. Beiu: SET FAs

18

capacitors only is based on recent results which have shown that SET TLGs are more sensitive to variations in the bias capacitors than in the input capacitors . Our simulation results for the SETTLG FA show that using this low-level technique the variations the circuit can tolerate increase from 0.6% to 1.1%, when nine 1 aF parallel bias capacitors are used instead of a single 9 aF one. This matching-inspired technique can be applied to all the MAJ-SET FAs, and also to the static buffers (inverters) of the enhanced TLG-SEJ FA. The tolerances increase from 1.5% to 3.2% for the MAJ-SET FA, and from 0.7% to 1.0% for the TLG-SEJ FA. Still, this technique can not be directly applied to either the MAJ-SEB or the PTL-SET FA.

M. Sulieman and V. Beiu: SET FAs

19

TABLE I COMPARISON OF SET FULL ADDERS Components (#Cj Variations ( + #C %) ) Cj : 20 C: 37 Total = 57 Cj : 14 C: 29 Total = 43 Cj : 12 C: 16 Total = 28 Cj : 10 C: 21 Total = 31 Cj : 8 C: 20 Total = 28 1.5 3.2 (variation enhanced) Design Complexity Multiple Control supp lies No None

Delay (ns)

Vin, Vo, CL (mV, aF) 6.5 mV 5.8 mV 24 aF 4.0 mV 3.9 mV 1 aF 80.0 mV 24.6 mV 1 aF 16.0 mV 16.0 mV 10 aF 6.5 mV 5.8 mV 24 aF

Vo / Vi (%)

MAJ-SET 1998

0.260

89

MAJ-SEB 2003

8.000

> 97

1.0

Two-step clocks Three-phase clock Input clock Two voltage supplies Input VDD

PTL-SET 2002 (Runs at up to 30 K) TLG-SEJ 2002 (original) Modified in this paper TLG-SET 2004 This paper

0.04

31

10.0

None

0.100

100

0.7 1.0 (variation enhanced) 0.6 1.1 (variation enhanced)

No

None

0.200

89

No

None

20

VI. CONCLUSIONS
Recent SET FA designs have been reviewed, while an enhanced SET FA together with a new SET FA design have been presented. These SET FAs differ significantly in their mode of operation: from pass transistor logic to TLG, including MAJ. The SET FAs were simulated under similar conditions to obtain quantitative estimates of their delays, and sensitivity to variations. This has allowed for a better understanding of the advantages and disadvantages of each solution. The example of MAJ logic design shows an interesting tradeoff between simplifying the gate and simplifying the circuit. The TLG-SET FA we have introduced has the smallest number of components, and a very simple design (single supply, the same values for both the input and supply voltage, and no control signals). The sensitivity analysis of the SET FAs presented in this paper is still crude, but suggests that the variations-reliability relation does not depend on the number of components, but more on the principle of operation of the gates, pointing to the fact that, for being most effective, redundancy should be considered at the lowest possible level, i.e. the device level. A solution inspired from the high matching techniques used in analog CMOS circuits has been advocated, but unfortunately it can not be directly applied to all SET FAs. Many more investigations are needed to characterize SET sensitivity to variations, and better unified modeling of failures in devices, gates, and interconnectsbased on different probabilistic models that include correlationshave to be developed.

21

REFERENCES
[1] The International Technology Roadmap for Semiconductors (ITRS), 2004. Available: http://public.itrs.net/ [2] R. Compa, L. Molenkamp, and D.J. Paul (Eds.), Technology Roadmap for Nanoelectronics, European Commission, IST Programme, Future and Emerging Technologies, Microelectronics Advanced Research Initiative MELARI NANO, 2000. Available: http://www.cordis.lu/esprit/src/melna-rm.htm [3] D. J. Frank, Power constrained CMOS scaling limits, IBM J. Res. & Dev., vol. 46, 2002, pp. 235244. [4] V. Beiu, U. Rckert, S. Roy, and J. Nyathi, On nanoelectronic architectural challenges and solutions, Proc. IEEE Conf. Nanotech. IEEE-NANO04, Aug. 2004, pp. 628631. [5] E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C. Chuang, K. Bernstein, and R. Puri, Turning silicon on its edge, IEEE Circ. & Dev. Mag., vol. 20, Jan./Feb. 2004, pp. 2031. [6] A. Marshall, and S. Natarajan, SOI Design: Analog, Memory, and Digital Techniques, Kluwer Academic Publishers, Boston, 2002. [7] K. K. Likharev, Electronics below 10 nm, in J. Greer, A. Korkin and J. Labanowsky (Eds.): Nano and Giga Challenges in Microelectronics, Elsevier, Amsterdam, 2003. [8] S. Roy, and V. Beiu, Majority multiplexingEconomical redundant fault-tolerant design for nano architectures, IEEE Trans. Nanotech., vol. 4, Jul. 2005, in press. [9] K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, and K. Seki, Room-temperature single-electron memory, IEEE Trans. Electron Devices, vol. 41, Sep. 1994, pp. 1628 1638.

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[10] Y. Pashkin, Y. Nakamura, and J. Tsai, Room-temperature Al single-electron transistor made by electron beam lithography, Appl. Phys. Lett., vol. 76, May 2000, pp. 22562258. [11] K. Uchida, J. Koga, R. Ohba, and A. Toriumi, Room-temperature operation of multifunctional single-electron transistor logic, IEDM Tech. Dig., Dec. 2000, pp. 863 865. [12] J. Koga, R. Ohba, K. Uchida, and A. Toriumi, Silicon single-electron memory and logic devices for room temperature operation, IEDM Tech. Dig., Dec. 2001, pp. 711714. [13] T. Kim, D. Choo, J. Shim, and S. Kang, Single-electron transistors operating at room temperature, fabricated utilizing nanocrystals created by focused-ion beam, Appl. Phys. Lett., vol. 80, Mar. 2002, pp. 21682170. [14] Y. Tan, T. Kamiya, Z. Durrani, and H. Ahmed, Room temperature nanocrystalline silicon single-electron transistor, J. Appl. Phys., vol. 94, Jul. 2003, pp. 633637. [15] K. Uchida, J. Koga, R. Ohba, and A. Toriumi, Programmable single-electron transistor logic for future low-power intelligent LSI: Proposal and room-temperature operation, IEEE Trans. Electron Devices, vol. 50, Jul. 2003, pp. 16231630. [16] S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. Tringe, Y. Leblebici, M. Declercq, K. Banerjee, and A. Ionescu, SETMOS: A novel true hybrid SET-MOS high current Coulomb blockade cell for future nanoscale analog ICs, IEDM Tech. Dig., Dec. 2003, pp. 14. [17] K.-W. Song, G. Baek, S.-H. Lee, D. H. Kim, K. R. Kim, D.-S. Woo, J. S. Sim, J. D. Lee, and B.-G. Park, Realistic single-electron transistor modeling and novel CMOS/SET hybrid circuits, Proc. IEEE Conf. Nanotech. IEEE NANO03, Aug. 2003, pp. 119121.

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[18] V. Beiu, A novel highly reliable low-power nano architecture: When von Neumann augments Kolmogorov, Proc. IEEE Intl. Conf. App.-specific Sys., Arch. and Processors ASAP04, Galveston, USA, Sep. 2004, pp. 167177. [19] H. Iwamura, M. Akazawa, and Y. Amemiya, Single-electron majority logic circuits, IEICE Trans. Electron., vol. E81-C, Jan. 1998, pp. 4248. [20] T. Oya, T. Asai, T. Fukui, and Y. Amemiya, A majority logic device using an irreversible single-electron box, IEEE Trans. Nanotech., vol. 2, Mar. 2003, pp. 1522. [21] Y. Ono, H. Inokawa, and Y. Takahashi, Binary adders of multi-gate single-electron transistor: Specific design using pass-transistor logic, IEEE Trans. Nanotech., vol. 1, Jun. 2002, pp. 9399. [22] C. Lageweg, S. D. Coofan, and S. Vassiliadis, A full adder implementation using SET based linear threshold gates, Proc. Intl. Conf. Electronics, Circ. and Sys., ICECS02, Sep. 2002, pp. 665668. [23] M. Sulieman, Design and Analysis of Single-Electron Technology Neural-Inspired Gates and Arithmetic Circuits, PhD dissertation, School of EECS, Washington State University, USA, Aug. 2004. Available: http://www.eecs.wsu.edu/~vbeiu/Theses/M_Sulieman.pdf. [24] C. Lageweg, S. D. Coofan, and S. Vassiliadis, Static buffered SET based logic gates, Proc. IEEE Conf. Nanotech. IEEE-NANO02, Jul. 2002, pp. 491494. [25] C. Lageweg, S. D. Coofan, and S. Vassiliadis, Single electron encoded latches and flip flops, IEEE Trans. Nanotech., vol. 3, Jun. 2004, pp. 237248. [26] C. Wasshuber, H. Kosina, and S. Selberherr, SIMON: A simulator for single-electron tunnel devices and circuits, IEEE Trans. Computer-Aided Design, vol. 16, Sep. 1997, pp. 937944.

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[27] A. Shams, T. Darwish, and M. Bayoumi, Performance analysis of low-power 1-bit CMOS full adder cells, IEEE Trans. VLSI Syst., vol. 10, Feb. 2002, pp. 2029.
[28]

S. Muroga, Threshold Logic and Its Applications, NewYork: John Wiley & Sons, 1971.

[29] V. Beiu, High-speed noise robust threshold gates, Intl. Semicond. Conf. CAS00, Sinaia, Romania, Oct. 2000, pp. 7982. [30] V. Beiu, Noise tolerant conductance-based logic gate and methods of operation and manufacturing thereof, U.S. Patent 6 430 585, Aug. 6, 2002. [31] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, Threshold network synthesis and optimization and its application to nanotechnologies, IEEE Trans. CAD of IC and Sys., vol. 24, Jan. 2005, 107118 [preliminary version as Synthesis and optimization of threshold logic networks with application to nanotechnologies, Proc. Design, Autom. & Test in Europe DATE04, Paris, France, Feb. 2004, vol. 2, pp. 904909].
[32] [33]

R. Betts, Majority logic binary adder, U.S. Patent 3 440 413, Apr. 22, 1969. S. D. Coofan, and S. Vassisliadis, Low weight and fan-in neural networks for basic arithmetic operations, Proc. IMACS World Congress Sci. Comp., Modeling & Appl. Maths., vol. 4, Aug. 1997, pp. 227232.

[34]

J. F. Ramos, and A. G. Bohrquez, Two operand binary adders with threshold logic, IEEE Trans. Comput., vol. 48, Dec. 1999, pp. 13241337.

[35] J. R. Tucker, Complementary digital logic based on the Coulomb blockade, J. Appl. Phys., vol. 72, Nov. 1992, pp. 43994413. [36] M. Sulieman, and V. Beiu, Design and analysis of SET circuits: Using MATLAB modules and SIMON, Proc. IEEE Conf. Nanotech. IEEE-NANO04, Aug. 2004, pp. 618621.

25

[37] M. Lan, A. Tammineedi, and R. Geiger, A new current mirror layout technique for improved matching characteristics, Proc. IEEE Midwest Symp. Circ. and Sys. MWSCAS99, Aug. 1999, vol. 2, pp. 11261129. [38] M. Lan, and R. Geiger, Gradient sensitivity reduction in current mirrors with nonrectangular layout structures, Proc. IEEE Intl. Symp. Circ. and Sys. ISCAS00, May 2000, vol. 1, pp. 687690. [39] Tatapudi, and V. Beiu, Split-precharge differential noise immune threshold logic gate (SPD-NTL), in J. Mira, and J. R. lvarez (Eds.): Artificial Neural Nets Problem Solving Methods (Proc. Intl. Work-Conf. Artif. Neural Nets. IWANN03, Menorca, Spain), Springer, LNCS 2687, 2003, pp. 4956. [40] K.K. Likharev, Single-electron devices and their applications, Proc. IEEE, vol. 87, Apr. 1999, pp. 606632.

26

Valeriu Beiu (S92M95SM96) received the M.Sc. degree in computer engineering from the Politehnica University of Bucharest, Romania, in 1980, and the Ph.D. degree (summa cum laude) in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 1994. Upon graduation, for two years he was involved with high-speed CPUs and FPUs with the Research Institute for Computer Techniques, Bucharest, Romania, prior to rejoining the Politehnica University of Bucharest. He was a founder and Chief Technical Officer (CTO) of RN2R (1998-2001), and an Associate Professor with the School of Electrical Engineering and Computer Science, Washington State University (2001-2005). Since 2005 he is a Visiting Professor with the School of Computing and Intelligent Systems, University of Ulster, UK, and Chair of Computer System Engineering, College of Information Technology, United Arab Emirates University, Al-Ain, UAE. He was the principal investigator of 34 research contracts. He holds 11 patents. He has received 32 grants, given over 100 invited talks, and authored over 130 papers in refereed journals and international conferences. He authored a chapter on digital integrated circuit implementations of neural networks in the Handbook of Neural Computation (New York: Oxford Univ. Press, 1997), and two forthcoming books: one on the VLSI complexity of discrete neural networks, and another one on emerging brain-inspired nanoarchitectures. His main research interests are VLSI-efficient designs (i.e., ultrahigh speed, very low power, and highly reliable), and emerging nanoarchitectures (massively parallel, adaptive/reconfigurable, regular, fault-tolerant, and neural inspired) as well as their optimized designs inspired by cellular and systolic arrays, artificial neural networks, or combinations of these.

27

Dr. Beiu is a member of the International Neural Network Society (INNS), the European Neural Network Society (ENNS), the Association for Computing Machinery (ACM), and the Marie Curie Fellowship Association (MCFA). He has organized 15 conferences and 32 conference sessions. He was the Program Chairman of the IEEE Los Alamos Section (1997). He was the recipient of five Best Paper Awards. He was also the recipient of five fellowships: Fulbright (1991), Human Capital and Mobility (19941996) with Kings College London (Programmable Neural Arrays project), Directors Funded Postdoc (19961998) with Los Alamos National Laboratory (Field Programmable Neural Arrays project, under the Deployable Adaptive Processing Systems initiative), and Fellow of Rose Research (19992001).

FIGURE CAPTIONS
Fig. 1. Fig. 1. Mapping of a Boolean function to a threshold function. (a) Karnaugh map of the Boolean function s = (a b ci) [co (a b ci)]. (b) Weight map showing the sum-of-weights a + b + ci 2co. ai + bi + ci + 2co. Fig. 2. The sequence a, b, ci, used for all SET FAs (the voltage levels are those used in ). Fig. 3. (a) MAJ based SET FA (MAJ-SET). (b) A MAJ gate based on SET inverter. Fig. 4. Sum output of the MAJ-SET FA. Fig. 5. (a) MAJ based SET FA (MAJ-SEB). (b) A MAJ gate based on SEB. Fig. 6. Control and input signals for MAJ-SEB FA. (a) Three phase clock for controlling the MAJ-SEB FA. (b) Input signal for the MAJ-SEB FA (return-to-zero signal). Fig. 7. Sum output of the MAJ-SEB FA. (c) Weight map showing the sum-of-weights

28

Fig. 8. PTL SET FA. (a) SET XOR gate. (b) PTL Sum gate. (c) PTL Carry gate. Fig. 9. Sum output s of the PTL SET FA. The output swing is about 25 mV (for an input swing of 80 mV). Fig. 10. (a) Threshold logic FA (TLG-SEJ). (b) A TLG based on SEJ. (c) SET dynamic (active) buffer. (d) SET static buffer (inverter). Fig. 11. Sum output s of the enhanced TLG-SEJ FA using static buffers. Fig. 12. (a) Threshold logic full adder (TLG-SET). (b) A TLG based on SET inverter. Fig. 13. Sum output s of the TLG-SET FA. Fig. 14. SIMON schematics for: (a) MAJ-SET (see also Fig. 2 in ); (b) MAJ-SEB (see also Fig. 8 in ); (c) PTL-SET (see also Fig. 3 in ); (d) TLG-SEJ with static buffer; and (e) TLGSET (see Fig. 12). Fig. 15. Errors caused by random variations in all the capacitors and junctions. (a) MAJ-SET. (b) MAJ-SEB. (c) PTL-SET. (d) TLG-SEJ. (e) TLG-SET.

29

ci co ab 00 01 11 10

00 0 1 1

01 0

11 0 1 0

10 1

ci co ab 00 01 11 10

00 0 1 2 1

01 2 1 0 1

11 1 0 1 0

10 1 2 3 2

ci co ab 00 01 11 10

00 2 3 4 3

01 0 1 2 1

11 1 2 3 2

10 3 4 5 4

(a)

(b)

(c)

Fig. 1. Mapping of a Boolean function to a threshold function. (a) Karnaugh map of the Boolean function s = (a b ci) [co (a b ci)]. (b) Weight map showing the sum-ofweights a + b + ci 2co. (c) Weight map showing the sum-of-weights ai + bi + ci + 2co.

30

Fig. 2. The sequence a, b, ci, used for all SET FAs (the voltage levels are those used in ).

31

V1

C C C C C C

VDD Cb1

a b ci
(a)

V2

s co

V3 V1 V2 V3

Cb2 VDD

CL

(b)

Fig. 3. (a) MAJ based SET FA (MAJ-SET). (b) A MAJ gate based on SET inverter.

32

Fig. 4. Sum output of the MAJ-SET FA.

33

a a

3
C V1 C

Cb

b b

V2 C V3

int

CL

c c

co

(a)

(b)

Fig. 5. (a) MAJ based SET FA (MAJ-SEB). (b) A MAJ gate based on SEB.

34

(a)

(b)

Fig. 6. Control and input signals for MAJ-SEB FA. (a) Three phase clock for controlling the MAJ-SEB FA. (b) Input signal for the MAJ-SEB FA (return-to-zero signal).

35

Fig. 7. Sum output of the MAJ-SEB FA.

36

drain
C C

source
C

co
C

CL

v1 v2 (a)
s
C

a b
C

Ccon C CM

ci
C Ccon
C C Ccon Vcon

a b
C

C Vcon

ci
(b)

ci

VDD (c)

Fig. 8. PTL SET FA. (a) SET XOR gate. (b) PTL Sum gate. (c) PTL Carry gate.

37

Fig. 9. Sum output s of the PTL SET FA. The output swing is about 25 mV (for an input swing of 80 mV).

38

Vb

Cb C

a b ci

co s
(a)

V1 C V2 C V3 2C V4 CL Vo

(b)
VDD Cb1

Vb Cin Vin

Vo CL

Vi

Vo

Cb2

CL

VDD

(c)

(d)

Fig. 10. (a) Threshold logic FA (TLG-SEJ). (b) A TLG based on SEJ. (c) SET dynamic (active) buffer. (d) SET static buffer (inverter).

39

Fig. 11. Sum output s of the enhanced TLG-SEJ FA using static buffers.

40

C V1 C V2 C V3

VDD Cb1

a b ci

co s

2C V4 C V1 C V2 C V3 2C V4 VDD Cb2 CL

(a)

(b)

Fig. 12. (a) Threshold logic full adder (TLG-SET). (b) A TLG based on SET inverter.

41

Fig. 13. Sum output s of the TLG-SET FA.

42

(a)

(b)

(c)

(d)

(e) Figure 14. SIMON schematics for: (a) MAJ-SET (see also Fig. 2 in ); (b) MAJ-SEB (see also Fig. 8 in ); (c) PTL-SET (see also Fig. 3 in ); (d) TLG-SEJ with static buffer; and (e) TLG-SET (see Fig. 12). 43

Title: C:\Program Files\SIMON2.0\maj_var.eps Creator: MATLAB, The Mathworks, Inc. Preview: This EPS picture was not saved with a preview included in it. Comment: This EPS picture will print to a PostScript printer, but not to other types of printers.

Title: C:\Program Files\SIMON2.0\Box_var.eps Creator: MATLAB, The Mathworks, Inc. Preview: This EPS picture was not saved with a preview included in it. Comment: This EPS picture will print to a PostScript printer, but not to other types of printers.

(a)
Title: C:\Program Files\SIMON2.0\TLG1_16mV_var.eps Creator: MATLAB, The Mathworks, Inc. Preview: This EPS picture was not saved with a preview included in it. Comment: This EPS picture will print to a PostScript printer, but not to other types of printers.

(b)

(c)
Title: C:\Program Files\SIMON2.0\TLG2_var.eps Creator: MATLAB, The Mathworks, Inc. Preview: This EPS picture was not saved with a preview included in it. Comment: This EPS picture will print to a PostScript printer, but not to other types of printers.

(d)

(e) Fig. 15. Errors caused by random variations in all the capacitors and junctions. (a) MAJ-SET. (b) MAJ-SEB. (c) PTL-SET. (d) TLG-SEJ. (e) TLG-SET.

44

Valeriu Beiu

45