IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO.

9, SEPTEMBER 2011

2225

A Novel Method for Synthesizing an Automatic Matching Network and Its Control Unit
F. Chan Wai Po, Member, IEEE, E. de Foucauld, D. Morche, P. Vincent, and E. Kerherv, Senior Member, IEEE
AbstractWe present a novel method simplifying matching network synthesis and design based on a tunable low-pass matching network topology. This method exploits the Smith chart in a novel way. Analytic expressions for calculating the optimal matching network for automatically adapting the load to the source impedance are derived. This work is applied to a new antenna tuning unit concept able to calibrate the system in a single iteration process reducing strongly both the speed and the overall consumption of the antenna calibration module. The obtained matching network nodal and load quality factors are analyzed and the matching network efciency is evaluated to highlight the impact of the imperfection in the design. The simulation and experimental results are presented to validate the proposed method and to evaluate the obtained matching efciency. We perform reection coefcients less than 30 dB, high efciency matching networks with only 258 s to calculate the proper state of the tunable matching network under a processor delivering 40 MIPS of performance. Index TermsAntenna tuning units (ATU), impedance transformers, matching network, control unit.

Fig. 1. Architecture of the automatic matching system.

I. INTRODUCTION

ADIOCOMMUNICATION modules are widely integrated into handheld or portable devices to exchange data like in mobile phones or in biomedical implants. The antennas used in such modules are typically narrow bandwidth miniaturized high-Q antennas [1] easily detuned by unpredictable near eld environmental factors [2][4]. Mismatch of the antenna impedance signicantly degraded the power efciency of the radio link. Automatic matching networks are therefore developed to match any change in antenna impedance to power source impedance in many RF applications. Most of adaptive antenna impedance tuning units were developed operating iteratively [5][14] to match source and load impedances. This approach matching time, approximately equal to several hundred milliseconds, is strongly affected by the iterative process and is not well suited to low power applications and is also an obstacle to
Manuscript received July 02, 2010; revised November 19, 2010; accepted January 04, 2011. Date of publication March 10, 2011; date of current version September 14, 2011. This work was supported by ELA Medical Sorin Group. This paper was recommended by Associate Editor Y. Massoud. F. Chan Wai Po was with CEA LETI MINATEC, 38054 Grenoble, France. He is now with ISEP, 75006 Paris, France (e-mail: francis.chan-wai-po@isep.fr). E. de Foucauld, D. Morche and P. Vincent are with CEA LETI MINATEC, 38054 Grenoble, France (e-mail: emeric.defoucauld@cea.fr, Dominique.morche@cea.fr, Pierre.vincent@cea.fr). E. Kerherv is with the IMS Laboratory, 33405 Talence, France (e-mail: eric. kerherve@ims-bordeaux.fr). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TCSI.2011.2112830

the high speed recongurability consideration for future radio developments [15]. A fast and accurate way to automatically match a system in a single step was developed in [16], [17]. The architecture of the single step automatic matching network is illustrated in Fig. 1 and its interest on an application was presented in [16]. A generic detector made of capacitor is inserted between the power module and the tunable matching network. The sensed and are attenuated for linearity, down converted signals to a lower intermediate frequency and analyzed by a processor. The benet of the proposed architecture in Fig. 1 is that the different modules used for the design of the antenna impedance tuning units, in particular the down conversion module and the baseband processor, are already included into common radio transceiver architecture. Only minor extra hardware is therefore required. In addition, the power consumption of radio communication modules is dominated by the power consumption of the power amplier during the transmitting path and by the power consumption of the low noise amplier during the receiving path. The extra power consumptions from the computing unit and the extra hardware are very small compared to the power consumption of the power amplier. Since the antenna impedance calibration is done during the transmitting mode as described in Fig. 1, to achieve low power antenna impedance tuning units, we reduce strongly the time required for the calibration. We achieve therefore so fast calibration that the extra power consumption from the extra modules is completely neglected. At the end of the calibration, the extra modules are switched to the idle mode. As described by the ow chart in Fig. 2, the processor exploits the magnitude and the phase of the sensed signals to rst and/or located in the left and the calculate the impedance right port of the detector, respectively. Finally, the extraction of

1549-8328/$26.00 2011 IEEE

2226

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

Fig. 3. Matching network with complex source and load impedances.

Fig. 2. Flow chart of the antenna impedance tuning processor.

the antenna input impedance exploits the well known deembedfrom or . The obtained ding techniques to calculate antenna input impedance value is used to directly calculate the parameters of the matching network to reach the proper state of the system at a selected frequency. The success of the optimization or the calibration with arbitrary source and load impedances is achieved with a single iteration. Since iteration is avoided, matching time is strongly reduced by more than several hundred times compared to common iterative optimization method [5][14] to achieve high speed recongurable system and low power consumption. This concept is obviously well adapted for the evolution of wireless communications towards cognitive or software dened radio where the parameters, in particularly the carrier frequency at a time, are dynamically chosen and controlled by a exible baseband processor [18]. However, the calculation of the parameters of the optimal conguration of the network that matches the extracted antenna input impedance to the optimal source impedance is difcult. Indeed, classical methods based on the study of the transfer function of the matching network were rst investigated but lead to heavy calculations that contribute to increase the processing time limiting the reduction of the calibration speed and the overall power consumption. To optimize the process, it was necessary to develop a novel method for synthesizing an automatic matching network quickly and easily. Here, we propose a new approach to achieve the process with simple analytical expressions. By reducing the complexity of the algorithm, the number of instructions and the required time to calculate the optimal conguration of the tunable matching network strongly decrease when the algorithm is implemented in a common embedded synchronous DSP, ASIC, or FPGA with memory. This approach also lowers the required memory size for the algorithm implementation into synchronous or asynchronous control units. Since the goal of the automatic matching network design is to optimize the power efciency of the radio transceiver, we also propose in this paper to study the power efciency of the designed lossy network. Indeed, a well matched network can contribute to generate high insertion loss in many RF applications. It is therefore very important to highlight the parameters of the

matching network that impact on its power efciency in order to discuss how to improve our design. Based on the study of the quality factors, the efciency range of the automatic matching network is therefore presented to evaluate the performance of the obtained matching topology. So, in this paper, we present the analysis of the automatic matching network and its design method in Section II. The quality factor and the efciency of the automatic matching network are then evaluated in Section III. In Section IV, the analytical results are discussed and compared to the simulations. The experimental results highlighting the achieved performance of the algorithm and its application to adaptive antenna impedance tuning unit demonstrator are presented and discussed in Section V. II. AUTOMATIC MATCHING NETWORK We present in this section a new design method for automatic matching network. This new method is meant to optimize the overall performance of the control unit of the single step automatic matching network presented previously in [16]. Our study uses a low-pass tunable matching network to approach the design. The design includes a network transformation, the choice of the inductance value and the matching network design method. A. Topology In ATU applications, a tunable matching network is needed for its ability to adapt a great number of load impedances or any change of load impedance to the source impedance. The generic low-pass tunable matching network shown in Fig. 3 is chosen as the starting point of our study. As in many impedance transformers or ATU applications operating from 400 MHz to 2.4 GHz frequency band, the inductor is not tunable. The tuning ability of the matching network is provided by variable capacitors made of diode varactors or banks of switched capacitors. B. Matching Network Transformation In RF applications, source and load impedances to be matched are usually complex. The rst step in the proposed method is to transform the complex source and load impedances into real source and load impedances. The rationale behind such transformation from complex to real impedances results in the fact that the best and the worst cases that affect the system can not be identied easily while exploiting the range variation of the complex load impedances. This analysis becomes evident with transformed real load impedance range where the minimum and the maximum real load impedances are identied. Thus, such transformation simplies strongly the design of the optimum values of the matching network, the

CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT

2227

Fig. 4. Transformed matching network with real source and load impedances.

analysis of its quality factor and the study of its power transfer efciency. The transformed matching network topology is illustrated in Fig. 4. The transformation consists of three steps: i) extraction of series-leg quality factors; ii) extraction of the transformed source and load; iii) analysis of the equivalent shunt variable capacitors. and of We can dene the series-leg quality factors source and load respectively by (1) (2) The transformed source is a resistance capacitor in parallel with

Fig. 5. Dynamic range of the impedance tuner at 2.4 GHz depending on the inductance. (a) L = 2:5 nH. (b) L = 1:7 nH.

(3) (4) Similarly, the transformed load is a resistance with a capacitor in parallel

(5) (6)

area can be matched to the source impedance; whereas it is impossible to match to the source impedance any normalized complex conjugate load impedance located in the forbidden region. To avoid this type of scenario, it is necessary to correctly set the value of the inductance in order to obtain the conguration illustrated in Fig. 5(b) where the complete normalized complex conjugate load impedance variation range is included into the impedance tuner dynamic range. For our study, we rst apply a matching network transformation as described previously to achieve the matching network topology illustrated in Fig. 4. It becomes therefore evident to identify the maximum and the minimum load impedance that affect our system. The range of the transformed and normalized which varies between and real load impedance is illustrated in Fig. 5 by the bold lines. In general, at a given angular frequency and neglecting the self-resonant frequency of the elements, the forbidden circle where load impedance can not be matched depends on the inductance value and its diameter is given by (9)

The equivalent shunt capacitances as follows:

and

are expressed The inductance value should be set carefully in order to match any value that could affect the load impedance. Indeed, the forbidden circle diameter should be smaller than (10) Thus, for our single-end matching network topology, in order to have the ability to match the load variation, the value of the chosen inductance should be smaller than the inductance maxwhich expression is derived from (9) and (10) imum value as

(7) (8)

C. Choice of the Inductance Value The dotted area located in the Smith charts in Fig. 5(a) and (b) illustrates the dynamic range of the impedance tuner in Fig. 3 simulated at 2.4 GHz frequency with 50 source impedance using respectively an inductance value of 2.5 nH and 1.7 nH. The capacitors values vary from 0.2 pF to 10 pF with a 0.2 pF resolution. Let us consider an example of normalized complex conjugate load impedance variation range represented in the Smith charts in Fig. 5(a) by the semicircular shape. Any normalized load impedance whose complex conjugate is located in the dotted

(11) where , the transformed source real impedance, is constant. , the transformed load real impedance, can reach a value and max . between min

2228

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

expressions of the curve 2 in the impedance domain are in the admittance domain

and

(14) (15) Step 3: The node belongs to the curve 2. Moreover, the is equal to the real part of the real part of the admittance of . As a result, we obtain admittance of the normalized load the following equation: (16) When the inductance quality factor is high can be neglected and (16) is reduced to the following second-order equation: (17) D. Matching Network Design Method We present a novel method strongly reducing the complexity of the matching network design, providing a quick and easy calculation. It exploits and approaches the Smith chart shown in Fig. 6 in a novel way. We simplify the analysis by using the transformed matching network shown in Fig. 4, where source and load impedance values are real. The impedances are normalized assuming the dened in (3). The goal is to characteristic impedance to be match the normalized impedance to the normalized source equal to 1 and localized at the center of the Smith chart. to the source The steps for matching the normalized load are as follows: Since is in shunt with the load , the normalized moves in the clockwise direction real load impedance on the admittance Smith chart until . in The next element is a serial inductance . We rotate the clockwise direction on the impedance Smith chart until . is designed to reach the Finally, the shunted capacitor located at the center of the Smith nal matching goal chart. The steps and the analytical expressions to calculate the optimum element values of the tunable matching network are presented below: is on the curve 1. In general, we can Step 1: The node . Therefore, consider the capacitor quality factor is high is neglected, the the parasitic resistance of the capacitor analytical expressions of this curve in the admittance domain and in the impedance domain are given by Step 4: In general, the quadratic equation (17) has two roots: and (18) (19) The solutions depend on the normalized real load impedance , on the normalized inductance value and on the angular frequency . Since (19) can lead to negative optimum values of the variable capacitors and shown in Fig. 3, only (18) is selected as the unique solution. and are obtained Step 5: The admittance of the node from (12), (15), and (18) as (20) (21) Step 6: The values of the capacitance and are given until and in the admittance domain by the move from from until , respectively (22) (23) and Step 7: Using (7), (8), (22), and (23), the capacitances , giving the optimal conguration of the matching network, are calculated (24) (12) (13) Step 2: If inductance and is the normalized expression of the is its normalized parasitic resistance, the (25) Finally, after transforming the matching network and choosing the inductance value matching the desired load range to the source, the matching network design algorithm can be

Fig. 6. Transformation diagram of the impedances of the matching network.

CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT

2229

Fig. 7. Multistage variable matching network.

implemented using only the analytical formulas given by (18), (20), (21), (24), and (25). These formulas can also be used to and calculate the necessary variation range of the capacitors suitable to adapt a variation range of load impedances to the source.

Thus, we get the intermediate real impedances of each stage by exploiting the following equation:

E. Multistage Matching Network Design A multistage matching network is sometimes preferred to a single stage topology for efciency consideration, especially between when the impedance transformation ratio the load and the source impedances is strong. It is demonstrated in [19] that the optimum number of stage is equal or greater than two for a resistance transformation ratio greater than nine. Having nontunable stages before the tunable one in the multistage scheme presents the advantage to make the impedance transformation process in several steps reducing the impedance transformation ratio of each stage contributing therefore to improve the matching network load quality factor and its overall efciency that will be studied in Section III. To design a tunable multistage matching network scheme, we propose to insert rst nontunable stages before the tunable matching network as illustrated in Fig. 7. The nontunable stages transform the optimal source impedance to an intermediate as shown in Fig. 7, reducing real source impedance therefore the resistance transformation ratio of each stage. The tunable matching network topology, which is a low pass structure as described previously in Fig. 3, is next designed to match the variable load impedance range to the intermediate exploiting the matching network real source impedance design methodology developed previously. Such methodology is used to convert the complex load to real load impedance (5), to set the inductance value of the tunable matching network (11) and to nd its proper state conguration (24), (25). For stages network, the values of the intermediate impedances are obtained by choosing the transformation quality facof all stages as follows: tors (27) Similarly, as , we can write

(28) And the intermediate impedances are obtained from (27) and (28) are given as follows: (29) (30)

III. QUALITY FACTOR AND EFFICIENCY ANALYSIS We analyze in this section the quality factors and the power efciency of the designed matching network. The goals of this work are to evaluate the lossy network performance and to highlight the parameters that contribute to degrade its power efciency in order to discuss how to improve our design. A. Nodal and Load Quality Factors Let us start with the matching node . At each node , the equivalent impedance can be expressed in terms of a normalized series impedance or admittance (31) (32)

(26)

where and are the transformed real source and load impedances, respectively.

2230

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

Fig. 8. Low pass  matching network with parasitic resistances divided into two sections: (a) a low pass L section and (b) a high pass L section. (c) demonstrates the Smith chart with impedance transformation.

The nodal quality factor can be found as the ratio of the absolute value of the normalized reactance to the cor[20] responding normalized resistance (33) Similarly, can be calculated as the ratio of the absolute to the normalized convalue of the normalized susceptance ductance (34) By denition, the matching network load quality factor is given by the maximum nodal quality factor. For efciency consideration, it is better to keep the load quality factor of a matching network as small as possible. Considering the and as illustrated in matching topology with two nodes Fig. 6, we can write the matching network load quality factor as follows: (35) and where respectively. are the nodal quality factors of and ,

Consider the low pass L section shown in Fig. 8(a). The exand , entering the matching netpression of the powers work from the left and from the right, respectively, are given by

(36) (37) If the right port is connected to the load, the impedance of shown in Fig. 8(a) is obtained from in addition the node with the impedance of the series inductance (38) The nodal quality factor lated from (33) and (38) of the node is easily calcu-

(39) If the left port is connected to the source, the admittance of the node illustrated in Fig. 8(a) can be expressed as the admitminus the admittance of the shunted capacitance tance

B. Matching Network Efciency In order to evaluate the losses in the matching network, the initial network is divided into a low pass L section and a high pass L section networks as illustrated in Fig. 8. The high pass into L matching network transforms the impedance with a nodal quality factor . The low pass L section transto with a nodal quality factor . The parasitic forms resistances are included in Fig. 8(a) and (b). The normalized and , matching source and load impedances and impedance transformation are represented in node the Smith chart in Fig. 8(c).

(40) From (34) and (40), the nodal quality factor is also given by to the node associated

(41)

CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT

2231

The parasitic resistances of the lossy components, like inductors or capacitors, used to design the matching network contribute to generate the insertion loss. The losses that affect the low pass L section represented in Fig. 8(a) are the loss in the inductor and the loss in the capacitor

With no approximation and no simplication, the expression of the low pass matching network efciency is

(47) (42)

(43)

The initial matching network is divided into two L sections where the inductors have exactly the same ratio between their reactance and their parasitic resistance, consequently they . Also, the have the same quality factor nodal quality factors are most of the time small compared to the quality factors of the matching components to avoid high insertion loss. In this condition and for simplicity, we can transform (47) into

where lated from

is (39),

calcu-

(48)

is obtained from (41), and . If the left port is connected to the source and the right port is connected to the load, we can write (44) From (42), (43), and (44), we obtain therefore the expression of the low pass L section matching network power efciency as the ratio between the output power and the input power as follows:

For the case of high efciency, when , we can simplify (48) as (49) It is well known that the quality factor of capacitors is strong compared to the quality factor of inductors. For and , the capacitor loss can be neglected and the only loss to be considered is the inductor loss. In this case, (49) can be approximated as (50) When the entire inductor quality factors are identical and given by , the multistage matching network in Fig. 7 achieves an overall efciency approximated by

(45)

Similarly, we calculate the expression of the power efciency expression of the high pass L matching network illustrated in Fig. 8(b). If the left port is connected to the source and the right port is connected to the load, the ratio between the output power and the input power is given by

(46)

(51) where to are the quality factors of L section nontunare the nodal quality able matching networks and factors of the tunable matching network. IV. CALCULATION AND SIMULATION RESULTS The previous sections presented the design method of the automatic matching network and its efciency analysis. In this

Finally, from Fig. 8 and (45) and (46), the low pass matching network efciency expression, with the left port connected to the source and the right port connected to the load, is given as function of the network nodal and of the quality factors quality factors of the network lossy components.

2232

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

TABLE I CALCULATED PARAMETERS OF THE OPTIMAL MATCHING NETWORK

Fig. 10. Simulated reection coefcient. Fig. 9. Flow chart of the matching network design algorithm.

section, we apply the analysis in order to match the load to the source impedance. The calculations and the simulations are done using the matching network topology illustrated in Fig. 3. The results are compared and the efciency of the designed matching network is nally veried by calculations and simulations. A. Automatic Matching Network Design Results Below, we elaborate three scenarios where complex load impedance values of and need to be matched to the source impedance values of at 400 MHz, at 900 MHz and 100 at 2.4 GHz, respectively, using the automatic matching network in Fig. 3. The matching network design algorithm whose ow chart is illustrated in Fig. 9 is executed by simulation and calculation to set the optimum values of the network. and real load The transformed real source impedance values are calculated using (3) and (5) respecimpedance tively. The maximum inductance Lmax is calculated from (11). equal to 32.8 nH, 14.4 nH, and 6.63 nH are calculated for a chosen minimum value of the transformed load impedance of 100 at 400 MHz, 50 at 900 MHz, and 100 at 2.4 GHz, respectively. The chosen inductance values should be smaller than Lmax as demonstrated in Section II. Thus, we select L equal to 30 nH, 10 nH, and 5 nH, respectively for the rst, the second and the third scenario. The values of are given by (18), by (20), and by (21). The optimal values of the and , allowing maximum power transfer from capacitors the source to the load, are nally extracted using (24) and (25), respectively. The numerical results are summarized in Table I.

The designed matching networks are simulated with advanced design system (ADS) tool in S-domain and the obtained reection coefcients are shown in Fig. 10. The simulations show excellent results. In all cases, reection coefcient values dB. are less than B. Evaluation of the Matching Network Efciency The matching network efciency developed in Section III is mainly used to estimate the losses of our design, but can be also very useful to decide on the topology of the automatic matching network, in particular its number of stages, to achieve a reasonable load quality factor Q (35) for efciency. Typically, the efciency of a matching network is function of its nodal quality factors (33), (34) and the quality factor of the components used for its design. For high efciency low-pass networks, where the quality factor of the components are high compared to the nodal quality factors of the network, the efciency of the automatic matching network is estimated from (49). In addition, assuming the quality factors of the selected matching network capacitances are high compared to the inductor quality factors ; the formula (50) is preferred. The design results obtained previously and summarized in Table I are used below. The normalized nodal admittances and are used to evaluate the nodal quality factors and exploiting (34). The simulations and the calculations are done using inductances quality factors of and . As illustrated in Table II, the nodal quality and are small compared to the quality factor factors of the inductors. The matching network efciencies can be therefore evaluated from (50). However, it is important to mention that the practicability of (50) is limited for high efciency matching network. In the case where the nodal quality factors

CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT

2233

TABLE II COMPARISON OF CALCULATED AND SIMULATED MATCHING NETWORK EFFICIENCY

Fig. 12. Two stage matching network with real source and load impedances.

Fig. 11. Efciency range of the automatic matching network versus Re(Z and Im(Z ).

are not small enough compared to the quality factors of the components, it is better to exploit the formula (47). Finally, as expected, the computed efciency results for and are in good agreement with the simulations as summarized in Table II. The maximum efciency is 98% and the minimum is 86%. Next, for a given complex load impedance range to match to a source impedance using a tunable matching network, we can obviously predict the efciency range of the well-matched network. Exploiting the design methodology developed in Section II, we evaluate rst the node impedances or admittances (20), (21) range of the network followed by the extraction of the nodal quality factors range from (33) or (34). For high efciency network, the efciency range is obtained applying the nodal quality factors range in (50) for a given inductance quality factor. We use this method to match a complex load to impedance range, whose real part can vary from 60 260 and imaginary part from 100 to 100 , to 100 source impedance at 2.4 GHz using the low-pass automatic matching network in Fig. 3. The efciency results calculated are represented in for an inductance quality factor of Fig. 11. We show that the automatic matching network reaches efciency values ranging from 90% up to 98%. The efciency of a high impedance transformation ratio scenario has also been calculated and simulated using respectively a single-stage matching network shown in Fig. 3 and a two stage network illustrated in Fig. 12 to match the

load impedances to the source impedance as summarized in Table III. In a single-stage topology, applying the design method nH developed in Section II gives a chosen inductance and the nodal quality factors and . , we achieve a simulated efciency of 82.5% For , and a calculated efciency from (50) of 80%. For we obtained in both case a efciency approximately equal to 94%. The two stage matching network illustrated in Fig. 12 aims to reduce the load quality factor (35) of the network in order to improve its power efciency. As illustrated in Fig. 12, the load impedance is rst matched to a desired intermediated , calculated from (30), using a tunable matching impedance network. The obtained impedance is next matched to the source with a nontunable matching network. impedance and Two nodal quality factors are derived from the tunable matching network. The nodal quality factor of the non tunable low pass L section matching . For , the simulated network is given by matching efciency is 90.5% and the calculated efciency from the efciency is approximately (51) is 88.5%. For equal to 97%. Compared to the single stage network, we reduce the load quality factor (35) from 11.523 to 3.594, and we improve the efciency of our design by more than 8% and 2% and , respectively. In general, in single for and two stage networks, the calculation and simulation t well. The difference is due to the approximation made in (50) and (51) to calculate the efciency. V. EXPERIMENTAL RESULTS The simplied block diagram of the automatic antenna-impedance tuning unit presented in our previous work [16] is illustrated in Fig. 13. The detector module allows the system to extract phase/magnitude information. The data are down converted to a low intermediate frequency and analyzed by the control unit. As shown in the ow chart of the control unit in Fig. 2, the processor analyses the information to extract

2234

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

TABLE III COMPARISON OF THE ESTIMATED AND SIMULATED EFFICIENCY OF A SINGLE STAGE AND MULTISTAGE MATCHING NETWORK

Fig. 13. Automatic antenna impedance tuning unit (AATU) simplied block diagram. Fig. 16. Measured reection coefcient: (a) before the calibration routine and (b) after single iteration calibration process.

Fig. 14. AATU prototype including the matching control unit.

Fig. 17. Postcalibration measured reection coefcient obtained for different load scenarios.

Fig. 15. Simplied structure of the varactor.

the load complex impedance. The matching design algorithm shown in Fig. 9 is executed to match the load impedance to the source impedance applying the developed matching network design method in Section II. A rst prototype of the automatic antenna tuning unit that operates only at the MICS 402405 MHz frequency band is shown in Fig. 14. The control unit has been implemented as an Analog Devices microcontroller ADUC7026. The microcontroller core is an ARM7TDMI, 16/32 bits RISC processor, offering up to 40 MIPS peak performance. The tunable matching network consists of a low pass matching network in Fig. 3 with an inductance and two variable capacitors made of varactors [21] which simplied structure as shown in Fig. 15. 12-bit DACs control the DC voltage of the varactors with a resolution of 750 V LSB. Fig. 16 shows two experimental reection coefcient measurements. The rst one shown in Fig. 16(a) was done before the calibration process in the presence of a detuned tunable low-pass

matching network. With knowledge of the load impedance and source optimal impedance, the developed matching network design algorithm in Fig. 9 is executed to set the proper state of the network. As illustrated in Fig. 16(b), we achieve a postcaldB at the desired freibration reection coefcient up to quency of 403 MHz. Experimental postcalibration reection coefcient has been also measured for different load impedances dB at as illustrated in Fig. 17. We obtained a S11 up to 403 MHz. Moreover, the synchronous processor spends no more than 258 s to compute the matching network design algorithm under a processor speed of 40 MIPS as illustrated in Fig. 18 and requires only 2512 bytes of memory size for its implementation. The algorithm was implemented under Keil embedded development tools. It was coded in C language; compiled and downloaded into Flash EEPROM memory using JTAG interface. VI. DISCUSSION The study and results presented so far have left a few questions unanswered, while also opening up new avenues of research. We address these points in this section.

CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT

2235

application. The implemented matching network design algorithm takes 258 s to calculate the optimal network and requires 2512 bytes Flash EEPROM memory space in the ADUC7026 microcontroller from Analog Devices. ACKNOWLEDGMENT The authors would like to thank ELA Medical (Sorin Group) for supporting this work. The authors would also like to thank E. Isa for contributing to improve the quality level of this paper. REFERENCES
Fig. 18. Time to calculate the optimal network conguration. [1] H. A. Wheeler, Small antennas, IEEE Trans. Microw. Theory Tech., vol. AP-23, no. 4, pp. 462469, Jul. 1975. [2] K. Boyle, The performance of GSM 900 antenna in the presence of people and phantoms, in Proc. IEEE Int. Conf. Antennas Propag., Mar. 2003, vol. 1, pp. 3538. [3] R. A. Sadeghzadeh and N. J. McEwan, Prediction of head proximity effect on anetnna impedance using spherical waves expansions, Electron. Lett., vol. 30, pp. 844847, Aug. 1994. [4] E. L. Firrao, A. J. Ennema, and B. Nauta, Antenna behaviour in the presence of human body, in Proc. 15th Annu. Workshop Circuits, Syst. Signal Process. (ProRISC), Nov. 2526, 2004, pp. 487490. [5] H. Song, B. Bakkaloglu, and J. T. Aberle, A CMOS adaptative antenna-impedance-tuning IC operating in the 850 MHz-to-2 GHz band, in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 384386. [6] J. de Mingo, A. Valdovinos, A. Crespo, D. Navarro, and P. Garcia, An RF electronically controlled impedance tuning network design and its application to an antenna input impedance matching system, IEEE Trans. Microw. Theory Tech., vol. 52, no. 2, pp. 489497, Feb. 2004. [7] P. Sjblom and H. Sjland, An adaptive impedance tuning CMOS circuit for ISM 2.4 GHz band, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 6, pp. 11151124, Jun. 2005. [8] A. van Bezooijen, M. A. de Jongh, C. Chanlo, L. C. H. Ruijs, F. van Straten, R. Mahmoudi, and A. H. M. van Roermund, A GSM/EDGE/WCDMA adaptive series LC matching network using RF-MEMS switches, IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 22592268, Oct. 2008. [9] E. L. Firrao, A. J. Annema, and B. Nauta, An automatic antenna tuning system using only RF-Signal amplitudes, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 9, pp. 833837, Sep. 2008. [10] H. Song, S. H. Oh, J. T. Aberle, B. Bakkaloglu, and C. Chakrabarti, Automatic antenna tuning unit for software-dened and cognitive radio, in Proc. IEEE Int. Symp. Antennas Propag., Jun. 2007, pp. 8588. [11] A. van Bezooijen, M. A. de Jongh, F. van Straten, R. Mahmoudi, and A. H. M. van Roermund, Adaptive impedance-matching techniques for controlling L networks, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 2, pp. 495505, Feb. 2010. [12] J. Fu and A. Mortazawi, Improving power amplier efciency and linearity using a dynamically controlled tunable matching network, IEEE. Trans. Microw. Theory Tech., vol. 56, no. 12, pp. 32393244, Dec. 2008. [13] E. W. C. Neo, Y. Lin, X. Liu, L. C. N. de Vreede, L. E. Larson, M. Spirito, M. J. Pelk, K. Buisman, A. Akhnoekh, A. de Graauw, and L. K. Nanver, Adaptive multi-band multi-mode power amplier using integrated varactor-based tunable matching networks, IEEE J. SolidState Circuits, vol. 41, no. 9, pp. 21662176, Sep. 2006. [14] A. Van Bezooijen, M. de Jongh, C. Chanlo, L. Ruijs, H. J. ten Dolle, P. Lok, F. van Straaten, J. Sneep, R. Mahmoudi, and A. H. M. van Roermund, RF-MEMS based adaptive antenna matching module, in Proc. IEEE RF-IC Symp., 2007, pp. 573576. [15] D. Morche, M. Belleville, C. Delaveaud, D. Ktenas, S. Mayrargue, and F. Chan Wai Po, Future needs in RF reconguration from a system point of view, in Proc. IEEE Bipolar BiCMOS Circuits Technol. Meet., Oct. 2009, pp. 3338, Invited Paper. [16] F. Chan Wai Po, E. de Foucauld, P. Vincent, F. Hameau, D. Morche, C. Delavaud, R. D. Molin, P. Pons, R. Pierquin, and E. Kerherv, A fast and accurate automatic matching network designed for ultra low power medical applications, in Proc. IEEE Int. Symp. Circuits Syst., May 2009, pp. 673676. [17] F. Chan Wai Po, E. de Foucauld, C. Delavaud, P. Ciais, and E. Kerherv, A vector automatic matching network designed for wireless medical telemetry, in Proc. IEEE NEWCAS-TAISA Joint Conf., Jun. 2008, pp. 8992.

We have shown a method that strongly reduces the automatic matching network design. It is extremely efcient to match any load impedance to the source using the matching topology in Fig. 3. The impedance transformations are performed, the choice of the inductance is discussed, and matching network design is achieved with simple analytical expressions. The expressions are exploited to implement the matching network design algorithm of a novel ATU control unit [16] whose ow chart is illustrated in Fig. 9. The resulting algorithm complexity is low and hence reduces the tuning time. Matching the system in a single step but with an algorithm of high complexity has little interest. Therefore, this approach simplifying the matching process can be considered as a key point of the single step adaptive load impedance tuning units. This contributes to reduce the matching time, the power consumption and the required memory for its implementation. The load impedance can be well matched to the source, but the matching network can be also strongly affected by losses. Thus, we developed the analytical expressions of the power transfer efciency to identify the impacts of the matching network parameters, as nodal quality factors and the quality factors of the inductors and capacitors. Even if design techniques such as multistage network design are helpful for increasing matching network efciency, it is clear that investigation should be lead in the development of inductors with high quality factor. Indeed, to improve the fully integration of ATU, the quality factor of integrated inductors should increase. Moreover, the variability of inductors is limited today. The use of variable inductors should be investigated in the future to demonstrate its ability to improve automatic matching network nodal quality factors and increase the overall matching efciency. The inductor variability should be not necessary continuous but can be also discrete. VII. CONCLUSION This paper presents a method for automatic matching network design and its synthesis. The method is developed to reduce the matching design complexity. The analytic expressions to achieve the optimal conguration of the automatic matching network are derived and its efciency is evaluated. Both simulation and measured results are presented to validate the method. The experimental results show that a reection coefcient up to dB is reached with the presented method applied to an ATU

2236

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

[18] E. Hossain, D. Niyato, and Z. Han, Dynamic Spectrum Access and Management in Cognitive Radio Networks. Cambridge, U.K.: Cambridge University Press. [19] Y. Han and D. J. Perreault, Analysis and design of high efciency matching networks, IEEE Trans. Power Electron., vol. 21, no. 5, pp. 14851491, Sep. 2006. [20] R. Ludwig and G. Bogdanov, RF Circuit Design: Theory and Applications, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 2000. [21] H. M. Nemati, C. Fager, U. Gustavsson, R. Jos, and H. Zirath, Design of varactor-based tunable matching networks for dynamic load modulation of high power ampliers, IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp. 11101118, 2009.

Dominique Morche received the Engineer diploma from the Ecole Nationale Suprieure dElectricit et de Radioelectricit de Bordeaux (ENSERB), France, in 1990 and the Ph.D. degree in electronics from the Institut National Polytechnique de Grenoble (INPG), France, in 1994. His Ph.D. mainly focuses on sigmadelta ADC. From 1994 to 2001 he was employed by France Telecom as a research engineer. He has been involved in architecture and design of analog circuits for telecom application. He is currently working at CEA-LETI, Grenoble. His current eld of research is in the specication and design of RF architecture for UWB and 4G systems.

Francis Chan Wai Po (M10) received the Engineering diploma from Ecole Nationale Suprieure dElectronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB), France, and the Ph.D. degree in microelectronics from the University of Bordeaux 1, France, in 2004 and 2010, respectively. His Ph.D. work was carried out at CEA LETI in collaboration with ELA Medical and the IMS Laboratory and was mainly focused on the design of a low power RF front-end transceiver with automatic power efciency optimization for biomedical implants. He has since joined the MINARC research team at Institut Suprieur dElectronique de Paris (ISEP), France, where he is currently an Assistant Professor in Microelectronics. His current eld of research is the design of analog and radiofrequency integrated circuits for biomedical applications. Dr. Chan Wai Po is a member of the IEEE Cicuits and Systems Society.

Pierre Vincent received the M.Sc. degree in microelectronic engineering from the University of Montpellier (ISIM), France. In 1990 he worked as an Analog RF development engineer and technical group leader in Thomson CSF semiconductor for space, military, and avionic applications. In 2000 he joined Inneon Technologies Echirolles France at its start-up. He was responsible for setting up the Analog IC development for 40 Gbps high-speed optical network applications. He joined the CEA-LETI, Grenoble, France, in 2003 as a design manager and responsible for RF architecture and the RF IC design lab. He is involved in millimeter wave and RF MEMS cointegration design.

Emeric de Foucauld received the Ph.D. degree from IRCOM-University of Limoges, France, in 2001. This study was focused on radio-frequency voltage-controlled oscillators for TETRA-TETRAPOL application of EADS-Telecom. He joined the Wireless Division of STMicroelectronics in 2001, and worked on the Frequency Synthesizer IP team as RFIC design engineer. In 2003, he joined the RF design team of CEA-LETI, Grenoble, France, and he is currently involved in analog integrated circuit design for wireless systems.

Eric Kerherv (M96SM09) received the Ph.D. degree in electrical engineering from University of Bordeaux, France, in 1994. He joined IPB ENSEIRB-MATMECA and the IMS Laboratory in 1996, where he is currently a Professor in Microelectronics and Microwave Applications. His main areas of research are the design of RF, microwave and millimeter-wave circuits (power ampliers and lters) in silicon, and BAW technologies. He is or was involved in European projects, such as MEDEA+ UPPERMOST, FP6 MOBILIS, MEDEA+QSTREAM, CATRENE PANAMA, and ENIAC MIRANDELA to develop silicon power ampliers and BAW duplexer. He has authored or coauthored more than 190 technical papers in this eld, and was awarded 17 patents. Prof. Kerherv has organized six workshops on advanced silicon technologies for radiofrequency and millimeter-wave applications. He is involved in the technical program committees of various international conferences (ICECS, IMOC, NEWCAS, EuMIC, SBCCI) and he was the chair of the international IEEE ICECS2006 conference. Since 2010, he has been an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART II: EXPRESS BRIEFS.